Piezoelectric Memory

Abstract

An exemplary nonvolatile memory device includes a first hydrogen storage portion that is conductive; a hydrogen charge trapped within the first hydrogen storage portion; a dielectric layer having a first surface adjacent to the first hydrogen storage portion and a second surface facing the first hydrogen storage portion; a second hydrogen storage portion that is conductive and adjacent to the second surface of the dielectric layer, and has a surface facing the dielectric layer; and a piezoelectric layer that is adjacent to the surface of the second hydrogen storage portion and has a surface facing the second hydrogen storage portion.

Description

[Technical Field]

[0001] The present invention relates to the electrical, electronic and computer fields, and more particularly to non-volatile memory devices. [Background technology]

[0002] Computing memory devices are classified as volatile or non-volatile. Volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM). Volatile memory devices do not retain data when power is not applied. In particular, SRAM requires a continuous voltage supply to keep its flip-flop registers locked, while DRAM requires frequent refreshing of its capacitors. Non-volatile memory devices include NAND gates (flash), magnetoresistive (MRAM), ferroelectric (FeRAM), resistive (RRAM), and phase-change (PCM) technologies. Non-volatile memory retains data even during periods when power is not applied. Summary of the Invention

[0003] The principles of the present invention provide a technique for piezoelectric memory.

[0004] In one aspect, an exemplary nonvolatile memory device includes a first hydrogen storage portion that is conductive; a hydrogen charge trapped within the first hydrogen storage portion; a dielectric layer having a first surface adjacent to the first hydrogen storage portion and a second surface facing the first hydrogen storage portion; a second hydrogen storage portion that is conductive and adjacent to the second surface of the dielectric layer, and has a surface facing the dielectric layer; and a piezoelectric layer that is adjacent to the surface of the second hydrogen storage portion and has a surface facing the second hydrogen storage portion.

[0005] Another aspect provides a method for operating a nonvolatile memory device. The device includes first and second hydrogen storage portions, a dielectric layer separating the first and second hydrogen storage portions, a piezoelectric layer adjacent to the second hydrogen storage portion, and a neutral layer on a surface of the piezoelectric layer facing the second hydrogen storage portion. The method includes setting a high-order bit for the memory device by inducing a strain in the piezoelectric layer; inducing the strain includes transferring hydrogen from the first hydrogen storage portion to the second hydrogen storage portion through the dielectric layer. Transferring the hydrogen includes applying an electric field between the first and second hydrogen storage portions.

[0006] According to another aspect, a piezoelectric memory device includes a piezoelectric layer; programmable means for placing and removing strain in the piezoelectric layer; and readout circuitry connected to the programmable means.

[0007] In view of the above, the techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments may provide one or more of the following:

[0008] A memory element that is electrically isolated from its readout device.

[0009] Very low energy consumption for reading the memory.

[0010] Use of well-known materials that are compatible with semiconductor fabrication processes.

[0011] Multilevel (analog) memory element.

[0012] Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required in all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1]1A and 1B show schematic diagrams of planar configurations of piezoelectric memory elements, according to exemplary embodiments;

[0014] [Figure 2] 1A and 1B are schematic diagrams illustrating cylindrical configurations of piezoelectric memory elements, according to exemplary embodiments.

[0015] [Figure 3] The programming of the piezoelectric memory element shown in FIG. 1 is shown in a schematic diagram.

[0016] [Figure 4] 1A and 1B show schematic diagrams of symmetrical planar piezoelectric memory elements according to exemplary embodiments;

[0017] [Figure 5] A memory circuit including the symmetrical planar piezoelectric memory element shown in FIG. 4 is shown in a schematic diagram.

[0018] [Figure 6] Another memory circuit including the symmetrical planar piezoelectric memory element shown in FIG. 4 is shown in a schematic diagram.

[0019] [Figure 7] 1 is a schematic diagram showing a hydrogen activated memory element according to the prior art; DETAILED DESCRIPTION OF THE INVENTION

[0020] 1 shows a schematic cross-sectional view of a piezoelectric memory element 100 having a generally planar configuration according to an exemplary embodiment. The memory element 100 includes a piezoelectric layer 102 having a first hydrogen storage portion 104 adjacent to the upper surface of the piezoelectric layer and a neutral layer 106 adjacent to the lower surface of the piezoelectric layer. A dielectric 108, which is permeable to hydrogen, is located on the upper surface of the first hydrogen storage portion, and a second hydrogen storage portion 110 is located on the upper surface of the dielectric. Read terminals 1 and 2 are connected between the first hydrogen storage portion 104 and the neutral layer 106. Programming terminals 3 and 4 are connected between the first and second hydrogen storage portions 104 and 110.

[0021] The hydrogen storage portion and the neutral layer include a conductive material, such as a metal. In one or more embodiments, each of the first and second hydrogen storage portions includes the same metal. In one or more embodiments, each of the first and second hydrogen storage portions includes a metal selected from the list consisting of palladium, platinum, vanadium, tungsten, hafnium, zirconium, niobium, tantalum, and titanium.

[0022] Dielectrics, as will be appreciated by those skilled in the art, are permeable to hydrogen but are good electrical insulators (blocking the flow of electrons but not H + (allowing for the transport of protons). Phosphosilicate glass is one non-limiting example of a suitable dielectric. Other similar materials may be used.

[0023] The piezoelectric material in one or more embodiments is selected to be compatible with semiconductor fabrication processes. For example, the piezoelectric material may be any of lead zirconate titanate, lithium niobate, and ferroelectric hafnium oxide. Undoped, properly annealed (orthorhombic) hafnium oxide may be used, or in one or more embodiments, the hafnium oxide may be doped to stabilize its ferroelectric phase, for example, with one of zirconium, silicon, aluminum, lanthanum, yttrium, or nitrogen. Lead zirconate titanate, commonly abbreviated as PZT and also called lead zirconate titanate, has the chemical formula Pb[Zr x Ti 1-x Note also that it is an inorganic compound with ]O3 (0≦x≦1).

[0024] In operation of memory element 100, as shown in FIG. 3, a positive voltage applied from terminal 4 to terminal 3 causes hydrogen charges H +The configuration 100A causes the volume of the first hydrogen storage section 104 to decrease, resulting in a compressive (contraction) strain on the piezoelectric layer 102. The dynamic contraction of the piezoelectric layer 102 generates a charge that can be read as either a low (zero) bit or a high (one) bit in the manner described below. Meanwhile, a positive voltage applied from terminal 3 to terminal 4 decreases the hydrogen charge H + The second hydrogen storage portion 110 moves hydrogen from the second hydrogen storage portion 110 to the first hydrogen storage portion 104. This configuration 100B increases the volume of the first hydrogen storage portion, causing a tensile strain on the piezoelectric layer 102. The dynamic expansion of the piezoelectric layer 102 generates a charge that can be read as either a high (one) bit or a low (zero) bit in the manner described below.

[0025] Depending on the piezoelectric material used and the thickness of the piezoelectric layer, the memory element 100 can retain a charge (delay) for a few seconds, a few hours, or even days. In one or more embodiments, the piezoelectric layer 102 is on the order of about 10 nm to about 50 nm thick, while the area of ​​a (square) piezoelectric layer is on the order of about 2500 nm. 2 In other embodiments, the piezoelectric layer may be non-square, such as circular or rectangular, having a length of about 50 nm and an aspect ratio of 2:1 or even 5:1 (length:width).

[0026] FIG. 2 shows a schematic cross-section of a piezoelectric memory element 200 having a generally cylindrical configuration according to an exemplary embodiment. The memory element 200 includes a piezoelectric layer 202 having a first hydrogen storage portion 204 adjacent to the top or outer surface of the piezoelectric layer and a neutral layer 206 adjacent to the inner or lower surface of the piezoelectric layer. A dielectric 208, which is permeable to hydrogen, is located on the outer surface of the first hydrogen storage portion, and a second hydrogen storage portion 210 is located on the outer surface of the dielectric. Readout and programming terminals are not shown in FIG. 2 but are connected equivalently to terminals 1, 2, 3, and 4 shown in FIG. 1. The principles of operation of the cylindrical configuration are essentially the same as those for the planar configuration. In one or more embodiments, the cylindrical shape may more effectively concentrate strain in the first hydrogen storage portion onto the piezoelectric layer.

[0027] FIG. 3 shows a schematic diagram of programming the piezoelectric memory element shown in FIG. 1 already described above. In configuration 100A, the voltage between terminals 1 and 2 (V L ) is lower than ground. In configuration 100B, the voltage between terminals 1 and 2 (V H ) is higher than ground. Thus, the voltage will change polarity according to the direction of the stress placed on the piezoelectric layer.

[0028] FIG. 4 is a schematic diagram illustrating a symmetrical planar piezoelectric memory element 400 according to an exemplary embodiment. The memory element 400 includes a first piezoelectric layer 402 having a first hydrogen storage portion 404 adjacent to the upper surface of the piezoelectric layer and a first neutral layer 406 adjacent to the lower surface of the piezoelectric layer. A dielectric 408, which is permeable to hydrogen, is located on the upper surface of the first hydrogen storage portion, and a second hydrogen storage portion 410 is located on the upper surface of the dielectric. A second piezoelectric layer 412 is located on the upper surface of the second hydrogen storage portion 410, and a second neutral layer 414 is located on the upper surface of the second piezoelectric layer 412. The neutral layer is connected to electrical ground. Readout terminals 1 and 2 are connected between the first hydrogen storage portion 404 and the first neutral layer 406; readout terminals 3 and 4 are connected between the second hydrogen storage portion 410 and the second neutral layer 414; and programming terminals 5 and 6 are connected between the first and second hydrogen storage portions. By providing a voltage to the programming terminal that moves hydrogen charges from the second hydrogen storage portion to the first hydrogen storage portion, a contractile strain is generated on the second piezoelectric layer and a tensile strain is generated on the first piezoelectric layer. By providing a voltage to the programming terminal that moves hydrogen charges from the first hydrogen storage portion to the second hydrogen storage portion, a contractile strain is generated on the first piezoelectric layer and a tensile strain is generated on the second piezoelectric layer. Such a situation results in the voltages shown in Figures 5 and 6, and V H is V L is farther from the ground than

[0029] 5 shows a schematic diagram of a memory circuit 500 including the symmetrical planar piezoelectric memory element 400 shown in FIG. 4 and a readout circuit 502 connected between readout terminals 2, 3. The readout circuit 502 includes three operational amplifiers (opamps) A1, A2, A3 connected with resistors R1, R2, R3, R4 as shown to amplify the voltage difference between the two piezoelectric layers 402, 412 of the memory element 400. Opamps A1 and A2 are connected in a voltage follower and act as input buffers to the inputs of opamp A3, which functions as a differential amplifier.

[0030] FIG. 6 is a schematic diagram illustrating another memory circuit 600 including the symmetrical flat piezoelectric memory element 400 shown in FIG. 4. The memory circuit 600 also includes a latching sense amplifier 602 as a read circuit. Those skilled in the art are familiar with circuits for implementing latching sense amplifiers. In the circuit 602, transistors M1, M3, M2, and M4 are connected to provide two cross-coupled inverters for the true complementary bit lines BL and BLB. When the signal sen is not provided to transistors M5, M6, and M7, the inverters latch the voltage difference between BL and BLB. When the signal sen is provided, the inverters amplify the voltage difference to a full swing voltage between the outputs OUT and OUTB.

[0031] 7 shows a schematic diagram of a prior art hydrogen activated memory element 700. Applying a high (1) bit to the gate terminal G causes hydrogen charge H + moves from the first hydrogen reservoir 702 (Pd layer) through the dielectric 704 (PSG) to the channel layer 706 made of tungsten oxide (WO3). The channel 706 is normally highly resistive. When hydrogen is introduced into the layer 706, it transforms the WO3 into WO2-OH+e (where e is a free electron), effectively "doping" the layer 706 and allowing current to pass from the source terminal S to the drain terminal D. By applying a high (one) bit to the source terminal S while applying a low (zero) bit to the gate terminal G, the hydrogen charge H +The hydrogen returns to the first hydrogen reservoir, making the channel 706 non-conductive again. The first hydrogen reservoir is a conductive material, preferably a noble metal such as palladium. The second hydrogen reservoir is a metal oxide such as tungsten oxide (WO). The dielectric 704 is permeable to hydrogen; phosphosilicate glass is an exemplary suitable material for the dielectric. Those skilled in the art will appreciate that the memory element 700 uses hydrogen to change the chemical structure of the layer 706 so that it can conduct current, resulting in an operating mechanism that is completely different from the piezoelectric operation of the memory elements 100, 200, and 400.

[0032] The present invention has been described with respect to a binary memory that holds a logic "1" or a logic "0". However, it is also possible to use the memory as a multi-level memory by varying the amount of hydrogen transferred between hydrogen reservoirs. This allows for control of the amount of compressive / tensile strain achieved on the piezoelectric layer. This in turn leads to intermediate output voltages that can be used to create additional memory levels.

[0033] Thus, in view of the foregoing, in general terms, the exemplary non-volatile memory devices 100, 200, 400 comprise a first hydrogen reservoir 110, 210, 410 that is electrically conductive; a hydrogen charge H trapped within the first hydrogen reservoir; + It will be understood that the dielectric layer 108, 208, 408 has a first surface adjacent to the first hydrogen storage portion and a second surface facing the first hydrogen storage portion; a second hydrogen storage portion 104, 204, 404 adjacent to the second surface of the dielectric layer, is conductive, and has a surface facing the dielectric layer; and a piezoelectric layer 102, 202, 402 adjacent to the surface of the second hydrogen storage portion and has a surface facing the second hydrogen storage portion.

[0034] In one or more embodiments, each of the first and second hydrogen storage units includes a metal. In some embodiments, each of the first and second hydrogen storage units includes the same metal. For example, each of the first and second hydrogen storage units includes a metal selected from the list of palladium, platinum, vanadium, tungsten, hafnium, zirconium, niobium, tantalum, and titanium.

[0035] In one or more embodiments, the dielectric layer comprises a phosphosilicate glass.

[0036] In one or more embodiments, the nonvolatile memory device also includes a first programming contact 5 electrically connected to the first hydrogen storage portion; a second programming contact 6 electrically connected to the second hydrogen storage portion; a conductive neutral layer 406 adjacent to the side of the piezoelectric layer facing the second hydrogen storage portion; and a readout circuit 502, 602 electrically connected to at least one of the first and second hydrogen storage portions.

[0037] In one or more embodiments, a readout circuit is connected between the first and second hydrogen storage portions. In one or more embodiments, a readout circuit is connected between the second hydrogen storage portion and the neutral layer.

[0038] In one or more embodiments, the readout circuit includes an operational amplifier. In one or more embodiments, the readout circuit includes a sense amplifier. In one or more embodiments, the readout circuit includes a latch circuit.

[0039] In one or more embodiments, each of the first and second hydrogen reservoirs comprises a metal film between about 10 nm and about 50 nm thick, with the longest dimension of each reservoir being from about 50 nm to about 100 nm.

[0040] In one or more embodiments, the piezoelectric layer comprises a material selected from the list consisting of lead zirconate titanate, barium niobate, and ferroelectric hafnium oxide.

[0041] Another aspect provides a method of operating a nonvolatile memory device. The device includes first and second hydrogen storage sections 104, 110, a dielectric layer 108 separating the hydrogen storage sections, a piezoelectric layer 102 adjacent to the second hydrogen storage section, and a neutral layer 106 on a surface of the piezoelectric layer facing the second hydrogen storage section. The method includes setting a high-order bit for the memory device by inducing strain in the piezoelectric layer; inducing strain includes transferring hydrogen from the first hydrogen storage section to the second hydrogen storage section through the dielectric layer. Transferring hydrogen includes applying an electric field between the first and second hydrogen storage sections.

[0042] In one or more embodiments, the method also includes reading a high-order bit from the memory device by connecting a read circuit to at least one of the hydrogen storage portions. In one or more embodiments, connecting the read circuit includes connecting the read circuit between the first and second hydrogen storage portions. In one or more embodiments, connecting the read circuit includes connecting the read circuit between the second hydrogen storage portion and the neutral layer. In one or more embodiments, connecting the read circuit includes connecting a pair of operational amplifiers between the first and second hydrogen storage portions, such that the pair of operational amplifiers form part of a high-input impedance amplifier.

[0043] According to another embodiment, the piezoelectric memory device 100, 200, 400 comprises a piezoelectric layer 102, 202, 402; a programmable means 104, 108, 110, 204, 208, 210, 404, 408, 410, 3, 4, 5, 6 for placing and removing strain in the piezoelectric layer; and a readout circuit 502, 602 connected to the programmable means.

[0044] The fabrication of semiconductor devices involves various stages of a device patterning process. For example, the fabrication of a semiconductor chip may begin with, for example, multiple CAD (computer-aided design) generated device patterns, followed by replicating these device patterns into a substrate. The replication process may involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing procedures.

[0045] Materials such as palladium, lead zirconate titanate, and other metal compounds can be deposited by, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plating, thermal or electron beam evaporation, or sputtering. These various deposition methods often provide excellent control of layer thickness and structure.

[0046] While the overall fabrication method and structures formed thereby are novel, certain individual processing steps required to implement this method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tools. Given the teachings herein, these techniques and tools will already be familiar to those of ordinary skill in the art. Furthermore, one or more of the processing steps and tools used to fabricate semiconductor devices are also described in several readily available publications, including, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001, and P.H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, both of which are incorporated herein by reference. It is emphasized that while several individual processing steps are described herein, they are exemplary only, and one of ordinary skill in the art will be familiar with several equally suitable alternative steps that may also be applicable.

[0047] The description of various embodiments of the present invention is presented for illustrative purposes but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein. Terms such as "first," "second," etc. may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed herein could be referred to as a second element without departing from the scope of the present concepts.

Claims

1. a first hydrogen reservoir, wherein said first hydrogen reservoir is electrically conductive; a hydrogen charge captured within the first hydrogen storage portion; a dielectric layer having a first surface adjacent to the first hydrogen storage portion and a second surface facing the first hydrogen storage portion; a second hydrogen storage portion adjacent to the second surface of the dielectric layer, wherein the second hydrogen storage portion is electrically conductive and has a surface facing the dielectric layer; and a piezoelectric layer adjacent to the surface of the second hydrogen storage portion and having a surface facing the second hydrogen storage portion; A non-volatile memory device comprising:

2. The apparatus of claim 1 , wherein each of the first and second hydrogen reservoirs comprises a metal.

3. The apparatus of claim 2 , wherein each of the first and second hydrogen reservoirs comprises the same metal.

4. 3. The apparatus of claim 2, wherein each of the first and second hydrogen reservoirs comprises a metal selected from the group consisting of palladium, platinum, vanadium, tungsten, hafnium, zirconium, niobium, tantalum, and titanium.

5. The device of claim 1 , wherein the dielectric layer comprises a phosphosilicate glass.

6. a first programming contact electrically connected to the first hydrogen reservoir; a second programming contact electrically connected to the second hydrogen reservoir; a conductive neutral layer adjacent the surface of the piezoelectric layer facing the second hydrogen storage portion; and a readout circuit electrically connected to at least one of the first and second hydrogen storage portions; The apparatus of claim 1 further comprising:

7. The apparatus of claim 6 , wherein the readout circuitry is connected between the first and second hydrogen reservoirs.

8. The device of claim 6 , wherein the readout circuit is connected between the second hydrogen reservoir and the neutral layer.

9. The apparatus of claim 6 , wherein the readout circuitry comprises an operational amplifier.

10. The apparatus of claim 9 , wherein the read circuitry comprises a sense amplifier.

11. The apparatus of claim 10 , wherein the readout circuitry comprises a latch circuit.

12. 10. The device of claim 1, wherein each of the first and second hydrogen reservoirs comprises a metal film having a thickness between about 10 nm and about 50 nm, wherein the longest dimension of each reservoir is from about 50 nm to about 100 nm.

13. 10. The device of claim 1, wherein the piezoelectric layer comprises a material selected from the group consisting of lead zirconate titanate, barium niobate, and ferroelectric hafnium oxide.

14. 1. A method of operating a nonvolatile memory device including first and second hydrogen storage portions, a dielectric layer separating the first and second hydrogen storage portions, a piezoelectric layer adjacent to the second hydrogen storage portion, and a neutral layer on a surface of the piezoelectric layer facing the second hydrogen storage portion, comprising: setting a high order bit for the memory device by inducing a strain in the piezoelectric layer, wherein the inducing a strain comprises: transferring hydrogen from the first hydrogen storage portion to the second hydrogen storage portion through the dielectric layer; Including, Here, the hydrogen transfer is applying an electric field between the first and second hydrogen storage portions; Including, A method comprising:

15. reading the high order bits from the memory device by connecting a read circuit to at least one of the hydrogen reservoirs; The method of claim 14 further comprising:

16. The method of claim 15 , wherein connecting the readout circuitry comprises connecting the readout circuitry between the first and second hydrogen reservoirs.

17. The method of claim 15 , wherein connecting the readout circuitry includes connecting the readout circuitry between the second hydrogen storage portion and the neutral layer.

18. 16. The method of claim 15, wherein connecting the readout circuitry includes connecting a pair of operational amplifiers between the first and second hydrogen reservoirs, wherein the pair of operational amplifiers form part of a high input impedance amplifier.

19. a piezoelectric layer; programmable means for placing and removing strain in the piezoelectric layer; and a read circuit connected to said programmable means; A piezoelectric memory device comprising:

20. 20. The device of claim 19, wherein the programmable means comprises a dielectric layer, a first hydrogen storage portion disposed on a first surface of the dielectric layer, a second hydrogen storage portion disposed on a second surface of the dielectric layer opposite the first hydrogen storage portion and between the dielectric layer and the piezoelectric layer, and a hydrogen charge in at least one of the first and second hydrogen storage portions.

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