Verification method and system for artificial neural network arrays

Abstract

Numerous examples of verification circuits and related methods in artificial neural networks are disclosed. In one example, a system includes a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, each capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks for receiving currents from respective columns of the vector x matrix multiplication array, generating voltages during verification operations of the vector x matrix multiplication, and generating digital outputs during read operations of the vector x matrix multiplication array.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. patent application Ser. No. 18 / 080,545, filed December 13, 2022, entitled "Verification Method and System in Artificial Neural Network Array," and U.S. provisional patent application Ser. No. 63 / 409,142, filed September 22, 2022, entitled "Verification Method and System in Artificial Neural Network Array."

[0002] FIELD OF THE INVENTION Numerous examples of verification circuits and related methods in artificial neural networks are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that can depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] Figure 1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons and an output layer of neurons that provide the neural network's output. Neurons at each level make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. Indeed, practical neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency, compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, the synapses of most CMOS implementations are too large given the large number of neurons and synapses.

[0006] Applicant previously disclosed in U.S. Patent Application Publication No. 2017 / 0337466 A1, which is incorporated by reference, an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as synapses. The non-volatile memory array operates as an analog neural memory and includes non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed insulated above a first portion of the channel region, and a non-floating gate disposed insulated above a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to the number of electrons in the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight value to generate the first plurality of outputs.

[0007] <Nonvolatile memory cell> Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by source side injection (SSI) of hot electrons (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0016] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are accomplished by electrons flowing from the source region 14 toward the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable), and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in the above artificial neural network, two modifications are made. First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is essentially analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), making every memory cell in the memory array very precisely and individually tunable and making memory arrays ideal for storage and for fine-tuning adjustments to the synaptic weights of neural networks.

[0021] <Neural network using nonvolatile memory cell array> 6 conceptually illustrates a non-limiting example of a neural network utilizing the present example non-volatile memory array. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after summing the outputs of the multiplications, determines a single output value, which is applied by the first synapse of CB1 to generate one pixel of layer C1's feature map. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all of layer C1's feature maps have been calculated.

[0023] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for this purpose. A vector-by-matrix multiplication (VMM) array 32 contains nonvolatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of nonvolatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and sums them for each output line (source line or bit line) to produce an output that becomes the input to the next layer or the input to the last layer. Having the non-volatile memory cell array 33 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also more power efficient due to in-memory computation.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a difference adder (such as a summing op-amp or a summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The difference adder 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the difference adder 38 are then provided to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving inputs from a previous layer of neurons or from an input layer such as an image database), and the summing operational amplifiers 38 and the activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or current. The first layer's input D / A conversion can be performed by using a function or LUT (look up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that a system may alternatively include more than two hidden layers and more than two fully connected layers.

[0033] <Vector × Matrix Multiplication (VMM) Array> 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, row-oriented reference array 902 is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Here, inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all the currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, i.e., memory cells 310 of VMM array 900, may be configured to optionally operate in the sub-threshold region.

[0036] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion (subthreshold region) as follows: Ids=Io×e (Vg-Vth) / nVt =w×Io×e (Vg) / nVt , In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n×Vt×log[Ids / wp×Io] where wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector x matrix multiplier VMM array with current inputs, the output current is: Iout=wa×Io×e (Vg) / nVt , i.e. Iout=(wa / wp)×Iin=W×Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: Vth=Vth0+γ(SQRT|Vsb-2×φF)-SQRT|2×φF|) where Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and γ is the body effect parameter.

[0039] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta×(Vgs-Vth)×Vds, beta=u×Cox×Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0042] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2×beta×(Vgs-Vth) 2 , beta=u×Cox×Wt / L Wα(Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0044] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0046] 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0048] Memory array 1003 serves two purposes. First, it stores the weights used by VMM array 1000 in each memory cell. Second, memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert to input voltages provided to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic circuitry and is also power efficient. Here, voltage inputs are applied to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current on each of the bit lines BL0-BLN performs the function of summing the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines extend vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each of the multiplexers 1212 includes a respective multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on the respective bit lines (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation, in which the reference cells are tuned to a target reference level.

[0053] Memory array 1203 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1200. Second, memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)) and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current on each bit line performs the function of summing all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 performs one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (causing the wrong value to be stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] FIG. 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 or first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0 through BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited to the memory cells 210 shown in FIG. 2 and that is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2200, the input INPUT 0. , ... , INPUT N are the bit lines BL0, ..., BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 shows a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUTM are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are the bit lines BL0, ..., BL N , 2701-(N-1) and 2701-N, which are coupled to the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] 28 shows a neuron VMM array 2800 that is particularly suited for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i.

[0067] <Long and short-term memory> Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any predetermined period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] 14 shows an example LSTM 1400. In this example, the LSTM 1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1402 receives an input vector x1, an output vector (hidden state) h0 from cell 1401, and 、 Cell 1403 receives input vector x2, output vector (hidden state) h2 from cell 1402, and cell state c1 from cell 1402, and generates output vector h2 and cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and generates output vector h3. Additional cells can be used; an LSTM with four cells is merely an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows LSTM cell 1600, an example implementation of LSTM cell 1500. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. VMM arrays, therefore, prove particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508 and summation device 1509 are implemented in digital or analog fashion. Activation function block 1602 can be implemented in digital or analog fashion.

[0072] An alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an addition device 1708 for adding two vectors, a tanh device 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from sigmoid function block 1702, a register 1704 for storing the value f(t) × c(t−1) when that value is output from multiplier device 1703 via multiplexer 1710, a register 1705 for storing the value i(t) × u(t) when that value is output from multiplier device 1703 via multiplexer 1710, a register 1706 for storing the value o(t) × ĉ(t) when that value is output from multiplier device 1703 via multiplexer 1710, and a multiplexer 1709.

[0073] While LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 requires one-quarter the space for the VMMs and activation function blocks compared to LSTM cell 1600, so LSTM cell 1700 requires less space than LSTM 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the example described below reduces the circuitry required outside the VMM array itself.

[0075] <Gated Recurrent Unit> Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are the gating mechanism within recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 shows an exemplary GRU 1800. GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used; a GRU with four cells is merely an example.

[0077] FIG. 19 shows an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate the output.

[0078] FIG. 20 shows GRU cell 2000, which is an example of an implementation of GRU cell 1900. For the convenience of the reader, the same numbering scheme as GRU cell 1900 is used in GRU cell 2000. As can be seen from FIG. 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that VMM arrays are particularly used in GRU cells used in specific neural network systems. Multiplier devices 1904, 1905, and 1906, summation device 1907, and complementary device 1908 are implemented in a digital or analog manner. Activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an addition device 2105 for adding the two vectors, a complementation device 2109 for subtracting an input from one to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)×r(t) as it is output from multiplier device 2103 via multiplexer 2104, a register 2107 for holding the value h(t-1)×z(t) as it is output from multiplier device 2103 via multiplexer 2104, and a register 2108 for holding the value h^(t)×(1-z(t)) as it is output from multiplier device 2103 via multiplexer 2104.

[0080] While GRU cell 2000 includes multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires one-third the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in which case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] Typically, for each memory cell in the VMM array, each weight W can be provided by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of differential cells, two memory cells are required to provide the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to provide the weight W as the average of the two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some examples, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that will store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that provide a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 3101 and 3102, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells of every pair of (W+, W−) lines. Although described above with respect to W- lines interspersed alternately among W+ lines, in other examples, the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another example: In a VMM system 3210, positive weights W+ are provided in a first array 3211 and negative weights W− are provided in a second array 3212 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 3213.

[0086] Figure 33 shows a VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). VMM system 3300 includes array 3301 and array 3302. Half of the bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connecting to memory cells that provide a negative weight W-. W- lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W- lines. The outputs on the W+ and W- lines from each array 3301, 3302 are combined together, respectively, to effectively give W = W+ - W- for each pair of (W+, W-) cells on every pair of (W+, W-) lines. Additionally, the W values ​​from each array 3301 and 3302 may be further combined via adder circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from adder circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge, or number of electrons, in its floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] It is important to be able to accurately verify programming operations after they have been performed. Summary of the Invention

[0089] Numerous examples of verification circuits and related methods in artificial neural networks are disclosed.

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[0139] [Brief explanation of the drawings]

[0140] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a VMM system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 9] 1 shows another example of a VMM system. [Figure 10] 1 shows another example of a VMM system. [Figure 11] 1 shows another example of a VMM system. [Figure 12] 1 shows another example of a VMM system. [Figure 13] 1 shows another example of a VMM system. [Figure 14] 1 shows a prior art long-term memory system. [Figure 15] An exemplary cell for use in a long-term memory system is shown. [Figure 16] 16 illustrates an exemplary implementation of the cell of FIG. 15. [Figure 17] 16 illustrates another exemplary implementation of the cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19]1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an exemplary implementation of the cell of FIG. 19. [Figure 21] 20 illustrates another exemplary implementation of the cell of FIG. 19. [Figure 22] 1 shows another example of a VMM system. [Figure 23] 1 shows another example of a VMM system. [Figure 24] 1 shows another example of a VMM system. [Figure 25] 1 shows another example of a VMM system. [Figure 26] 1 shows another example of a VMM system. [Figure 27] 1 shows another example of a VMM system. [Figure 28] 1 shows another example of a VMM system. [Figure 29] 1 shows another example of a VMM system. [Figure 30] 1 shows another example of a VMM system. [Figure 31] 1 shows another example of a VMM system. [Figure 32] 1 shows another example of a VMM system. [Figure 33] 1 shows another example of a VMM system. [Figure 34] 1 shows another example of a VMM system. [Figure 35A] Shows how to program. [Figure 35B] Shows how to program. [Figure 36] The search and execution method is shown. [Figure 37] A precision programming method is presented. [Figure 38] A precision programming method is presented. [Figure 39] 1 shows an adaptive calibration method. [Figure 40] 1 shows a calibration circuit. [Figure 41] 1 shows an adaptive calibration method. [Figure 42] Absolute calibration method is shown. [Figure 43] A VMM system including a verification circuit is shown. [Figure 44A] An exemplary verification circuit is shown. [Figure 44B] An exemplary comparator circuit with offset compensation is shown. [Figure 45] A reference voltage generator is shown. [Figure 46] A physical array including a plurality of reference arrays is shown. [Figure 47] A physical array including a plurality of reference arrays is shown. [Figure 48] A physical array including a VMM array and another physical array including a reference array are shown. [Figure 49] A reference array including a plurality of reference sub-arrays is shown. [Figure 50] A reference array including a plurality of reference sub-arrays is shown.

Best Mode for Carrying Out the Invention

[0141] <Structure of the VMM System> 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high voltage decoder 3403, a column decoder 3404, a bit line driver 3405, an input circuit 3406, an output circuit 3407, control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high voltage level generator 3413. The VMM system 3400 further comprises an algorithm controller 3414 (for program / erase or weight adjustment), analog circuitry 3415, a control engine 3416 (which may include specialized functions such as, but not limited to, arithmetic functions, startup functions, embedded microcontroller logic, etc.), test control logic 3417, and a static random access memory (SRAM) block 3418 for storing intermediate data such as input circuitry (e.g., activation data) or output circuitry (neuron output data), or data input for programming (such as data input for an entire row or multiple rows).

[0142] The input circuit 3406 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of a normalization, a linear or nonlinear up / downscaling function, or an arithmetic function. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as a ReLU or a sigmoid. The input circuit 3406 may store digital activation data that is applied as an input signal or combined with an input signal during a program or read operation. The digital activation data may be stored in a register. The input circuits 3406 may include circuitry for driving the array terminals, such as the CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. DACs can be used to convert digital activation data into analog input voltages that are applied to the array.

[0143] The output circuit 3407 may include circuits such as an ITV (current-to-voltage circuit), an ADC (analog-to-digital converter for converting the analog output of the neuron into digital bits), an AAC (analog-to-analog converter such as a current-to-voltage converter or a logarithmic converter), an APC (analog-to-pulse converter), or any other type of converter. The output circuit 3407 can convert the array output into activation data. The output circuit 3407 may implement activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement one or more of statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, log) of the neuron output. The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as the bit line output) to keep the power consumption of the array approximately constant over temperature changes, or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over temperature changes. The output circuit 3407 may also include registers to store the output data.

[0144] FIG. 35A illustrates a programming method 3500. Initially, the method begins, typically in response to a received program command (step 3501). Next, a mass program operation programs all cells to a "0" state (step 3502). A soft erase operation then erases all cells to a weak erase level (step 3503), such that each cell draws, for example, approximately 1-5 μA of current during a read operation. This contrasts with a deeply erased level, where each cell draws, for example, approximately 20-30 μA of current during a read operation. A hard program operation is then performed (step 3504) on all unselected cells, adding electrons to the floating gates of the cells to a very deep programmed state, ensuring that those cells are truly "off," i.e., they draw negligible amounts of current during a read operation.

[0145] A coarse programming operation is then performed to program the selected cells to a level much closer to the target, for example, 2X to 100X of the target. A coarse programming operation is performed on the selected cells (step 3505), followed by a fine programming operation on the selected cells (step 3506) to program the desired precise value into each selected cell.

[0146] The coarse programming operation (3505) may consist of multiple coarse verify / program cycles. In each coarse verify / program cycle, a verify operation is performed to verify whether the cell output meets the coarse target. If not, a programming operation is performed on that cell again. The verify / program cycles are repeated until the cell outputs of all target cells meet the coarse target.

[0147] The precision programming operation (3506) may consist of multiple precision verify / program verify / program cycles. In each precision verify / program cycle, a verify operation is performed to verify whether the cell output meets the precision target. If not, a programming operation is performed on that cell again. The verify / program cycles are repeated until the cell outputs of all target cells meet the precision target.

[0148] FIG. 35B illustrates another programming method 3510 similar to programming method 3500. However, after the method begins (step 3501), instead of a program operation that programs all cells to a "0" state as in step 3502 of FIG. 35A, an erase operation is used to erase all cells to a "1" state (step 3512). A soft program operation (step 3513) is then used to program all cells to a weakly programmed state, such that each cell draws, for example, approximately 3-5 μA of current during a read operation. A hard program operation is then performed on all unselected cells to a very deep programmed state (step 3504), followed by coarse and fine programming (3505-3506) as in FIG. 35A. A variation of the example of FIG. 35B eliminates the soft programming method (step 3513) entirely.

[0149] 36 illustrates a first example of a coarse programming operation 3505, which is a lookup and execution method 3600. First, a lookup table lookup is performed to find the coarse target current value (I CT ) based on the value intended to be stored in the selected cell (step 3601). This table may be generated, for example, by silicon characterization or from wafer test calibration. The selected cell may be programmed to store one of N possible values ​​(e.g., without limitation, 128, 64, 32, etc.). Each of the N values ​​represents a different desired current value (I) to be drawn by the selected cell during a read operation. DIn one example, the lookup table may correspond to a coarse target current value I for a cell selected during the search and execution method 3600. CT , where M is an integer less than N. For example, if N is 8, then M may be 4, meaning there are 8 possible values ​​that the selected cell can store, and one of the four coarse target current values ​​will be selected as the coarse target for the search and execute method 3600. That is, the search and execute method 3600 (which, as shown above, is an example of the coarse programming method 3505) programs the selected cell to store a desired value (I D ) somewhat close to the value (I CT ) and then the precision programming method 3506 programs the desired value (I D ) is intended to program selected cells more precisely.

[0150] Examples of cell values, desired current values, and coarse target current values ​​are shown in Tables 9 and 10 for a simple example with N=8 and M=4. Table 9: Example of N desired current values ​​for N=8 [Table 9] Table 10: Example of M target current values ​​when M=4 [Table 10] Offset value I CTOFFSETx is used to prevent overshooting the desired current value during coarse adjustment.

[0151] Rough target current value I CTOnce selected, the selected cell is programmed (step 3602) by applying a voltage v to the appropriate terminal of the selected cell based on the cell architecture type of the selected cell (e.g., memory cell 210, 310, 410, or 510). If the selected cell is of the type of memory cell 310 of FIG. 3, a voltage v is applied to control gate terminal 28, and v is the coarse target current value I CT The value of v0 can be 5 to 7 V depending on the coarse target current value I CT The voltage can be determined from a voltage lookup table that stores values ​​of v0 corresponding to

[0152] The selected cell is then connected to the i =v i-1 +v increment where i starts at 1 and increments each time this step is repeated, and v increment is a small, weak voltage that causes programming to a degree commensurate with the granularity of the desired change (step 3603). Thus, the first time step 3603 is performed at i=1, and v is equal to v increment Next, a verify operation is performed (step 3604), where a read operation is performed on the selected cell to measure the current drawn through the selected cell (I cell ) is the rough target threshold I CT Compared to I cell I CT If so, the search and execute method 3600 is complete and the precision programming method 3506 can begin. cell I CT If not, i is incremented and step 3603 is repeated.

[0153] In this way, at the point where the coarse programming method 3505 ends and the fine programming method 3506 begins, the voltage v i is the final voltage used to program the selected cell, and the selected cell is programmed to the coarse target current value I CT (Note that Icell I CT The fine programming method 3506 performs a read operation on the selected cell by applying a current I D The current is programmed to the pull point (allowing for an acceptable amount of deviation, such as + / - 30% or less, e.g., + / - 50 pA), this current being the desired current value associated with the value intended to be stored in the selected cell.

[0154] 37 shows examples of different voltage progressions that may be applied to the control gates of selected memory cells during a coarse programming operation 3505 and / or a fine programming operation 3506, which consists of multiple verify / program cycles.

[0155] Under the first approach, to program a selected memory cell, an increasing voltage is applied to the control gate, starting at v i , which is the last voltage applied during the coarse programming method 3505 during the fine programming operation 3506. p1 is applied to v1, and then the voltage v1+v p1 is used to program the selected cell (indicated by the second pulse from the left in progression 3701). p1 is v increment (the voltage increment used during the coarse programming method 3505). After each programming voltage is applied, Icell PT1 A verify operation (similar to step 3404) is performed in which a determination is made whether I is less than or equal to (the first precision target current value, here the second threshold value). PT1 =I D +I PT1OFFSET and I PT1OFFSET is an offset value added to prevent program overshoot. If the decision is false, another increment v p1 is added to the previously applied programming voltage and the process is repeated. cell I PT1This portion of the programming sequence stops at some point below: PT1 I D or with sufficient accuracy, i.e., within + / - an acceptable deviation, D If the value is approximately equal to , the selected memory cell has been successfully programmed.

[0156] I PT1 I D is not close enough to I, i.e., with sufficient accuracy D If it is not approximately equal to V, then further programming with a finer granularity is performed. Here, progression 3702 is used. The starting point of progression 3702 is the last voltage used for programming under progression 3701. p2 (v p1 (less than I) is applied to that voltage, and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, I cell I PT2 A verify operation (similar to step 3404) is performed in which a determination is made whether I is less than or equal to (a second precision target current value, here a third threshold value), where I PT2 =ID+I PT2OFFSET and I PT2OFFSET is an offset value added to prevent program overshoot. If the decision is false, another increment V p2 is added to the previously applied programming voltage and the process is repeated. cell I PT2 At this point, this portion of the programming sequence stops because the target value has now been achieved with sufficient accuracy. PT2 I D or until programming stops. D It is assumed that the .times. ...

[0157] The second approach is shown in progression 3703 of Figure 37 and progression 3803 of Figure 38. Instead of increasing the voltage applied during programming of a selected memory cell, the same voltage is applied for increasing periods of time duration. That is, each applied pulse is applied with a voltage greater than the previously applied pulse. p1 time t p1 An additional increment of time is added to the programming pulse. After each programming pulse is applied, the same verify operation as described above for progression 3701 is performed. Optionally, additional progressions can be applied, where the additional time increment added to the programming pulse is of shorter duration than the previous progression used. Although only one temporal progression is shown, one skilled in the art will understand that any number of different temporal progressions can be applied.

[0158] Further details are now provided for three examples of the coarse programming method 3505.

[0159] 39 shows another example of the coarse programming method 3505, which is an adaptive calibration method 3900. The adaptive calibration method begins (step 3901). The cell is programmed with a default starting value, v0 (step 3902). Unlike the search and execute method 3600, here v0 is not obtained from a lookup table but instead can be a relatively small initial value. The control gate voltage of the cell is measured at a first current value, IR1 (e.g., 100 nA) and a second current value, IR2 (e.g., 10 nA), and a sub-threshold slope is determined (e.g., 360 mV / dec) based on those measurements and stored (step 3903).

[0160] new voltage v i The first time this step is performed, i=1, and v1 is determined based on the stored subthreshold slope values ​​and current target and offset values ​​using a subthreshold equation as follows: v i =v i-1 +vincrement In the formula, v increment is the slope v g is proportional to v g =n * v t * log[Ids / wa * Io] Here, wa is the w of the memory cell, and Ids is the target current plus the offset value.

[0161] If the stored slope value is relatively steep, a relatively small current offset value can be used. If the stored slope value is relatively flat, a relatively high current offset value can be used. Thus, determining the slope information allows a current offset value to be selected that is customized for the particular cell in question. This ultimately makes the programming process shorter. As this step is repeated, i is incremented and v is increased. i =v i-1 +v increment Then the cell is i Programmed using v increment corresponds to the target current value, v increment The value of .times. ...

[0162] A verify operation is then performed and a read operation is performed on the selected cell, drawing a current (I cell ) is the rough target threshold I CT (Step 3905). cell I CT Below, I CT I D +I CTOFFSET and I CTOFFSET If I is the offset value added to prevent program overshoot, the adaptive calibration method 3900 is complete and the fine programming operation 3506 can begin. cell I CTIf not, steps 3904-3905 are repeated and i is incremented. Then, the fine programming method 3506 begins, and the voltage v i is the final voltage used to program the selected cell.

[0163] 40 illustrates aspects of an adaptive calibration operation 3900. During step 3903, a current source 4001 applies exemplary current values ​​IR1 and IR2 to a selected cell (here, memory cell 4002), and then the voltage at the control gate of memory cell 4002 (CGR1 with respect to IR1 and CGR2 with respect to IR2) is measured. The slope is determined as (CGR2-CGR1) / dec of current, which is the slope of VCG versus LOG(I).

[0164] 41 shows another example of a coarse programming operation 3505, an adaptive calibration method 4100. The adaptive calibration method begins (step 4101). A cell is programmed with a default starting value, v0 (step 4102). The value v0 is obtained from a lookup table, such as one created from silicon characterization, and the table value is offset so as not to overshoot the target program value.

[0165] In the next step 4103, an IV slope parameter is generated that is used to predict the next programming voltage, V CGR1 is applied to the selected cell and the resulting cell current IR1 is measured. Then, a second control gate read voltage V CGR2 is applied to the selected cell and the resulting cell current IR2 is measured. The slope is determined and stored based on those measurements, for example, according to the following equation in the sub-threshold region (cells operating at sub-threshold): Slope=(V CGR1 -V CGR2 ) / (LOG(IR1)-LOG(IR2)) (Step 4103). V CGR1 and V CGR2 Example values ​​for are 1.5V and 1.3V, respectively.

[0166] Determining the slope information is customized to the particular cell in question. increment This allows values ​​to be selected, which ultimately makes the programming process shorter.

[0167] Step 4104 is repeated, incrementing i to obtain the new desired programming voltage V i is determined based on the stored slope value and the current target and offset values ​​using the following equation: v i =v i-1 +v increment , where for i-1, v increment =α * Incline * (LOG(IR1)-LOG(I CT ))、 where I CT is the target current, and α is a predetermined constant less than 1 (the programming offset value), e.g., 0.9, to prevent overshoot. For example, V i is VSLP or VCGP, i.e., source line or control gate programming voltage.

[0168] The cell then V i (step 4104).

[0169] A verify operation is then performed and a read operation is performed on the selected cell, drawing a current (I cell ) but I CT (Step 4106). cell I CT (here the coarse target threshold) CT =I D +I CTOFFSET and I CTOFFSET is an offset value added to prevent program overshoot), the process proceeds to step 4107. Otherwise, the process returns to step 4104 and i is incremented.

[0170] In step 4107, I cell I CT Less than threshold I CT2 The purpose is to check if an overshoot has occurred. cell I CT It is to be less than cell I CT If it is much lower than I, then overshoot has occurred and the stored value may actually correspond to an incorrect value. cell I CT2 If it is not, then no overshoot has occurred and the adaptive calibration method 4100 is complete, at which point the process proceeds to the fine programming operation 3506. cell I CT2 If it is less than or equal to 1, then an overshoot has occurred. In that case, the selected cell is erased (step 4108) and the programming process restarts at step 4102 by resetting i to 0. Optionally, if step 4108 is performed more than a predetermined number of times, the selected cell may be considered a bad cell that should not be used.

[0171] A fine program operation 3506 consists of multiple verify and program (V / P) cycles in which the program voltage is incremented by a constant fine voltage with a fixed pulse width, or the program voltage is fixed and the program pulse width is varied.

[0172] Optionally, the step of determining whether the current passing through the selected non-volatile memory cell during the read or verify operation is less than or equal to the coarse target threshold may be performed by applying a fixed bias to the terminals of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate a digital output bit, and comparing the digital output bit to a digital bit representing the first threshold current.

[0173] Optionally, the step of determining whether the current passing through the selected non-volatile memory cell during the read or verify operation is less than or equal to the coarse target threshold may be performed by applying a fixed bias to the terminals of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate a digital output bit, and comparing the digital output bit to a digital bit representing the first threshold current.

[0174] Optionally, the step of determining whether the current through the selected non-volatile memory cell during the read or verify operation is less than or equal to the coarse target threshold may be performed by applying an input to a terminal of the non-volatile memory cell, modulating the current drawn by the selected non-volatile memory cell with an output pulse to generate a modulated output, digitizing the modulated output to generate a digital output bit, and comparing the digital output bit to a digital bit representing the first threshold current.

[0175] 42 shows a third example of a coarse programming operation 3505, which is an absolute calibration method 4200. The absolute calibration method begins (step 4201). The cell is programmed with a default starting value v0 (step 4202). The control gate voltage (VCGRx) of the cell is programmed with a current value I target The new desired voltage v1 is measured and stored (step 4203) using the stored control gate voltage and current target and offset values ​​I offset +I target (step 4204). For example, the new desired voltage v1 can be calculated as follows: v1=v0+(VCGBIAS-storedVCGR), where VCGBIAS is the default read control gate voltage at the maximum target current, e.g., about 1.5V, and storedVCGR is the measured read control gate voltage of step 4203.

[0176] The cell then i When i=1, the voltage v1 from step 4204 is used. When i>1, the voltage v i =vi-1 +v increment is used. increment corresponds to the target current value, v increment A verify operation is then performed and a read operation is performed on the selected cell to measure the current drawn through the selected cell (I cell ) is I CT (Step 4206). cell I CT If so, the absolute calibration method 4200 is complete and the fine programming method 3506 can begin. cell I CT If it is not less than or equal to, steps 4205-4206 are repeated and i is incremented.

[0177] A single weight verify method can be used to verify whether a cell achieved its weight target as a result of a programming operation: A memory cell is selected for a verify operation, and then the output of that memory cell is verified by a verify mechanism described below with reference to Figures 43-49.

[0178] The differential weight verification method can be used to determine whether a differential cell (formed from two cells, the stored value of which is the difference between the values ​​stored in the two cells) has achieved a weight target as a result of a programming operation. Two cells associated with the differential weight are selected for a verification operation. The difference in output between the cells is then verified by a verification mechanism described below with reference to FIGS. 43-49. For example, if cell 1 stores a w+ value and cell 2 stores a w- value, then w = w+ - w- is the differential weight. Cell 1 and cell 2 are the two cells selected for a verification operation to determine whether the weight w has achieved the target. Alternatively, the w- value of cell 2 is verified first, and then the differential weight w is verified. Alternatively, the w+ value of cell 1 is verified first, and then the differential weight w is verified. Alternatively, the w+ value and w- value of cell 1 and cell 2 are verified in a first operation, and then the differential weight w is verified in a second operation.

[0179] FIG. 43 shows a VMM system 4300. A current-to-voltage converter and analog-to-digital converter block 4301 receives current from a VMM array 3401, typically from a bit line or source line within the VMM array 3401, and provides an output to a verify circuit 4302. The current-to-voltage converter and analog-to-digital converter block 4301 and verify circuit 4302 together are output blocks coupled to the VMM array 3401 that generate a voltage during a verify operation of the VMM array 3401 and generate a digital output during a read operation of the VMM array 3401. Each current-to-voltage converter in block 4301 converts a current to a voltage. The analog-to-digital converters in block 4301 are reconfigured (such as in the manner described below with reference to FIG. 44A) for use during a verify operation (also known as a read verify operation). During a verify operation, a reference array 4304 is used to generate all N possible current targets (e.g., 32 values ​​ranging from 3 to 96 nA in 3 nA increments). Each of the N possible current targets corresponds to one of the N weight targets stored in a respective reference memory cell in the reference array 4304. Alternatively, a main reference current generator 4305 is used to generate all N current targets. A reference current from either the reference array 4304 or the main reference current generator 4305 is provided to a reference voltage generator 4303, which includes a voltage DAC and utilizes it to convert the reference current to a reference voltage, with N possible voltages corresponding to the N possible values. For example, for a 5-bit cell, there are 32 reference voltages corresponding to 32 current targets. An appropriate one of the N voltage values ​​is selected for comparison by the verification circuit 4302 with the voltage provided by the corresponding current-to-voltage converter 4301. This comparison is the verification operation performed by the verification circuit 4302. In this manner, the weights can be verified after being programmed into the VMM array 3401. In this approach, verification is performed by comparing the output voltage from the memory cell with the reference voltage from the voltage reference generator 4303.

[0180] Alternatively, a reference current digital-to-analog converter (IDAC) is used to verify the cell current directly without using a current-to-voltage converter, which means that the cell current is compared to a reference current. Under this approach, the latency and variation are usually larger due to the settling time of low current (e.g., a few nA) circuits.

[0181] Figure 44A shows a neuron output ITV+ADC+VERIFY circuit 4488, which includes a current-to-voltage converter (ITV) 4401, a successive approximation register (SAR) analog-to-digital converter (ADC) 4402, and a verification circuit 4403. The verification circuit 4403 includes a comparator 4404 (also used to generate a digital output during a readout or read neuron operation), a reference voltage selection circuit 4406, and a verification register 4405. The verification register 4405 is the data output register of the SAR ADC 4402 and is used here to perform the verification function, but can also be used to generate a digital output during a readout or read neuron operation. Current-to-voltage converter 4401 and SAR analog-to-digital converter 4402 are an example of an implementation of current-to-voltage converter and analog-to-digital converter 4301 of FIG. 43, and verification circuit 4403 is an example of an implementation of verification circuit 4302 of FIG. 43.

[0182] The current-to-voltage converter 4401 and the SAR analog-to-digital converter 4301 may be used during a read operation or a neural read operation, but may also be used during a verify operation in which weights (intended to be one of N possible weight values) programmed into non-volatile memory cells in the VMM array are verified.

[0183] The current-to-voltage converter 4401 receives current from the VMM array from a single selected cell and converts the current to a voltage. The current-to-voltage conversion can be performed by multiple resistors ITV (RITV) 4490R or multiple capacitors ITV (CITV) 4490C. One of N possible reference voltages is provided to the verify circuit 4403 via a verify register 4405 and a verify reference voltage selection circuit 4406. The verify register may be, for example, an 8-bit register used to select one of 256 voltage reference levels in the verify reference voltage selection circuit 4406. The verify reference voltage as an input to the verify reference voltage selection circuit 4406 (via a verify reference voltage line) is provided by a global verify reference voltage generator such as that shown in FIG. 45. A comparator 4404 then compares the voltage from the current-to-voltage converter 4401 with one of the N possible reference voltages to indicate whether the cell is storing the correct value. The capacitors and SAR logic in the SAR ADC 4402 are not used during the verify operation. In one example, the control circuit closes switch S1A in SAR ADC4402 to provide the positive output Vinp of ITV4401 directly to the non-inverting input of comparator 4404, opens one switch (unnamed), and closes one switch (unnamed) to provide the output of verification reference voltage selection circuit 4406 to the inverting input of comparator 4404.

[0184] The ITV+ADC+VERIFY circuit 4488 can be used for a differential weight verify operation as well as a single weight verify operation. For a single weight verify operation, only one input from one cell is required. The output voltage of the ITV 4401 is proportional to the value of the cell current and is verified against a reference voltage level provided by the verify reference voltage selection circuit 4406. For a differential weight verify operation, two inputs from two cells are the two inputs to the ITV+ADC+VERIFY circuit 4488, and the output voltage of the ITV 4401 (e.g., Vinp) is proportional to the difference between the two cell currents and is verified against a reference voltage level provided by the verify reference voltage selection circuit 4406.

[0185] The overall offset compensation of the ITV+ADC+VERIFY circuit 4488 can be trimmed by using the offset trim of the comparator 4404. This offset can be further trimmed by trimming resistor 4490R or capacitor 4490C of the ITV circuit 4401.

[0186] In another example, the overall gain compensation of the ITV+ADC+VERIFY circuit 4488 can be trimmed by trimming resistor 4490R or capacitor 4490C of the ITV circuit 4401.

[0187] An alternative method of offset compensation can be performed in the time domain by using an ITV 4401 with a capacitor 4490C. A variable width pulse with a reference current input to enable the incorporation of capacitor 4490C is used by the ITV 4401 to generate an output voltage. The output voltage from the ITV 4401 is compared to a reference voltage by a comparator 4404. The parameters of the variable width pulse are stored, for example, by a counter (not shown) in the digital domain or by a table (not shown) that stores analog voltages in the analog domain for each ITV (the analog voltages are converted from the variable pulse input). This information is used by a controller (not shown) to enable the ITV using an enable signal (not shown) for verify operations.

[0188] Figure 44B shows a comparator and offset circuit 4490 that can be used in place of comparator 4404 of Figure 44A to add the additional functionality of offset compensation. Comparator and offset circuit 4490 includes a comparator 4491 that compares inputs VINP and VINN (which may be the same signals shown in Figure 44A) to generate outputs COMPOUT and its complement COMPOUTB. A calibration circuit 4492 can be adjusted to provide an offset voltage VON to comparator 4491, and a calibration circuit 4493 can be adjusted to provide an offset voltage VOP to comparator 4492.

[0189] 45 illustrates a reference voltage generator 4500. The reference voltage generator 4500 is one exemplary implementation of the reference voltage generator 4303. In one example, the reference array 4304 (not shown) sources a maximum current from the reference cells, which represents the highest possible weight (out of N possible weights) that can be stored in the non-volatile memory cells. The maximum current provided from the reference cells is converted to a high verification reference voltage by a current-to-voltage converter 4501, which can be done using either a resistor current-to-voltage converter (RITV) 4511 or a capacitor current-to-voltage converter (CITV) 4510.

[0190] This voltage is then used to generate 32 verification reference voltages for the 5-bit cell, such as by resistor string 4504, here comprising N-1 resistors in series. In another example, the reference array provides a reference current that is converted to a reference voltage; for example, the reference current can be a mid-range value that is appropriately converted to all N reference voltages (e.g., by a current ratio mirror, by trimmed resistor values, or by trimmed capacitor values ​​through an ITV circuit). The illustrated ITV 4501 uses a differential operational amplifier. This ITV is a replica of subcircuit ITV 4301 in VMM system 4300 and is also shown as ITV 4401 in ITV+ADC+verification circuit 4488. The differential operational amplifier (opamp) is a replica of local differential opamp 4480 in FIG. 44, so that the N global references can track the local voltages from ITV 4301 over PVT (process, power supply, or temperature) variations. Alternatively, ITV4501 can be based on a single-ended operational amplifier. Resistors 4511x and capacitors 4510x can be trimmed to adjust the range and compensate for mismatch or offset variations. Resistor string 4504 can be trimmed to adjust range VN to V1, to shift range VN up / down to V1, or to adjust local value VN to V1.

[0191] In another example, a constant current bias (such as from an IDAC) is used instead of a reference current from a reference array.

[0192] The current bias or reference current from the reference array can be adjusted to reach a target value. They are also compensated for PVT (process, power supply, or temperature) variations.

[0193] The overall global offset and mismatch compensation of the ITV+ADC+VERIFY circuit 4488 can be trimmed by using the offset and mismatch trimming of the reference generator 4500. This can be done by adjusting the current bias 4512 or by trimming resistors 4511a and 4511b, capacitors 4510a and 4510b, or resistor string 4504.

[0194] Buffer 4502 is used to buffer a high verify reference voltage, for example, representing the 32nd level (L31) of the 32 reference voltage levels (L0-31) for a 5-bit cell, to drive resistor string 4504 at one end of resistor string 4504. In another example, buffer 4503 is provided to buffer a low verify reference voltage VREF2 corresponding to the 1st level (L0) of the 32 levels (L0-31) for a 5-bit cell and provide that voltage to one end of resistor string 4504. For example, the high verify reference voltage may be 900 mV and the low verify reference voltage may be 300 mV. Voltage ladder (resistor string) 4504 generates N voltages ranging from V0 to VN, which represent the N possible values ​​that can be stored in the VMM array. These reference voltages are then used by verify circuit 4403 of FIG. 44. In another example, the input and / or output voltages of buffers 4502 and 4503 are trimmed to adjust range and calibrate any offsets, such as buffer offsets. Alternatively, ITV4501 can directly drive resistor string 4504 to provide 32 reference levels (L0-L31).

[0195] In one example, K verify reference voltage lines can be used to provide N different voltages. For example, for a 5-bit cell, 32 verify reference voltage lines are needed to feed the verify reference voltage selection circuit 4406, and for a 6-bit cell, 64 verify reference voltage lines are needed. The 64 verify reference voltages can be provided by using each of the 32 reference voltage lines twice and time-multiplexing their use so that the 32 lines provide a first set of 32 voltages during a first verify period and a second set of 32 voltages during a second verify period. This approach can be extended by using four verify periods to provide 128 voltages for a 7-bit cell, or eight verify periods to provide 256 voltages for an 8-bit cell, or more without limitation.

[0196] In one example, bias voltages (such as CG bias and EG bias) for the inputs of the array for verify operations are generated from a reference array so that these biases adapt to temperature to keep the array current as constant as possible.

[0197] 46-50 show examples of reference arrays that can be used for reference array 4304 of FIG.

[0198] FIG. 46 shows a physical array 4600. The physical array 4600 includes an array of non-volatile memory cells. The non-volatile memory cells may optionally include stacked gate flash memory cells or split gate flash memory cells. The physical array 4600 is divided into two types of arrays: a VMM array 3401 (as in FIG. 34) and a reference array 4304. In one example, the VMM array 3401 and the reference array 4304 share the same bit lines. In another example, the VMM array 3401 and the reference array 4304 use separate sets of bit lines, and the two sets of bit lines are separated.

[0199] 47 shows a physical array 4700 that is divided into two arrays: a VMM array 3401 and a reference array 4304. In one example, the VMM array 3401 and the reference array 4304 share one or more sets of horizontal lines, such as word lines, control gate lines, and erase lines. In another example, the VMM array 3401 and the reference array 4304 do not share any sets of horizontal lines.

[0200] 48 shows an example where reference array 4304 and VMM array 3401 are located in separate physical arrays. For example, there may be substrate separation or active diffusion separation between the two arrays. Physical array 4801 includes VMM array 3401, and physical array 4802 includes reference array 4304. VMM array 3401 and reference array 4304 do not share any bit lines, word lines, control gate lines, or erase lines.

[0201] FIG. 49 shows an example of a reference array 4304. Here, reference array 4304 includes multiple reference subarrays, such as reference subarrays 4901-0, 4901-1, ..., 4901-(n-1), and 4901-n. Thus, reference array 4304 includes n+1 different reference subarrays. The different reference subarrays can have different characteristics that cause each reference array to be characterized by a different IV curve than the other reference subarrays. For example, each reference subarray can differ in one or more of the following dimensions: (1) the width of the control gate lines of the transistors in each reference array; (2) the width of the word lines of the transistors in each reference array; (3) the width of the floating gates of the transistors in each reference array; (4) the overall width of the non-volatile memory cells in each reference array; (5) the spacing of shallow trench isolation (STI) in each reference array; or (6) other features. Additionally, each of the reference sub-arrays may differ in one or more device implant conditions or doping characteristics (such as, but not limited to, well implant conditions, source implant conditions, drain implant conditions, etc.).

[0202] FIG. 50 shows another example of a reference array 4304. Here, reference array 4303 includes multiple reference subarrays, such as reference subarrays 5001-0, 5001-1, ..., 5001-(n-1), and 5001-n, and 5001-0, 5002-1, ..., 5002-(n-1), and 5002-n. Thus, reference array 4304 includes 2×(n+1) different reference subarrays, i.e., twice the number of different reference subarrays as in FIG. 49. The different reference subarrays in FIG. 50, similar to those in FIG. 49, can have different characteristics that cause each reference subarray to be characterized by a different IV curve from the other reference arrays. For example, each reference array can differ in one or more of the following dimensions: control gate width, word line width, floating gate width, total non-volatile memory cell width within the array, STI spacing, and device implant conditions, without limitation.

[0203] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, each of said non-volatile memory cells being capable of storing one of N possible levels corresponding to one of N possible currents; a plurality of output blocks for receiving currents from respective columns of the vector x matrix multiplication array, generating voltages during verify operations of the vector x matrix multiplication, and generating digital outputs during read operations of the vector x matrix multiplication array; A system comprising:

2. The system of claim 1 , wherein the plurality of output blocks convert current from columns of the array into voltage using a plurality of resistors or a plurality of capacitors.

3. 2. The system of claim 1, further comprising a reference voltage generator that generates one of N voltages during the verify operation.

4. 4. The system of claim 3, further comprising a verification circuit for comparing a voltage from said reference voltage generator with a voltage from one of said plurality of output blocks.

5. The system of claim 4 , wherein the verification circuit generates a digital output indicative of the result of the comparison.

6. The system of claim 3 , wherein the reference voltage generator generates the one of N voltages in response to a current received from a reference array.

7. 4. The system of claim 3, wherein the reference voltage generator generates the one of N voltages in response to a current received from a master reference current generator.

8. The reference voltage generator a current-to-voltage converter for converting a maximum current of the N possible currents into a maximum voltage; a resistor string for generating N voltages ranging from the maximum voltage to the minimum voltage; The system of claim 3 , comprising:

9. 9. The system of claim 8, wherein the resistor string comprises (N-1) resistors in series.

10. 9. The system of claim 8, further comprising a first buffer for providing the maximum voltage to a first end of the resistor string.

11. 11. The system of claim 10, further comprising a second buffer for providing the minimum voltage to a second end of the resistor string.

12. 1. A system comprising: a current-to-voltage converter for converting currents from the vector x matrix array into voltages; a successive approximation register analog-to-digital converter for receiving the voltage from the current-to-voltage converter and for generating a digital output during a read operation; a verify circuit for receiving the voltage from the current-to-voltage converter and comparing it to a reference voltage during a verify operation; A system comprising:

13. The reference voltage is provided by a reference voltage generator, the reference voltage generator comprising: a current-to-voltage converter that converts the maximum current of the N possible currents into a maximum voltage; a resistor string for generating N voltages ranging from the maximum voltage to the minimum voltage; The system of claim 12, comprising:

14. 14. The system of claim 13, wherein the resistor string comprises (N-1) resistors in series.

15. 14. The system of claim 13, comprising a first buffer for providing the maximum voltage to a first end of the resistor string.

16. 16. The system of claim 15, further comprising a second buffer for providing the minimum voltage to a second end of the resistor string.

17. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of nonvolatile memory cells arranged in rows and columns, each of the nonvolatile memory cells being capable of storing one of N possible voltages corresponding to one of N possible currents; a plurality of current-to-voltage converters and a plurality of verify circuits for receiving currents from columns of the array, for generating voltages during verify operations of the vector x matrix multiplication array, and for generating digital outputs during read operations of the vector x matrix multiplication array; A system comprising:

18. 20. The system of claim 17, comprising a reference voltage generator for generating one of N voltages during the verify operation of the vector by matrix multiplication array.

19. 20. The system of claim 18, further comprising a comparator that compares a voltage from the reference voltage generator with a voltage from one of the plurality of current-to-voltage converters.

20. 20. The system of claim 19, wherein the comparator performs an offset calibration.

21. The system of claim 20 , wherein the offset calibration is performed in the time domain.

22. 20. The system of claim 17, wherein the current-to-voltage converter converts current from columns of the array into a voltage using multiple resistors or multiple capacitors.

23. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, each of said non-volatile memory cells being capable of storing one of N possible levels corresponding to one of N possible currents; a plurality of output blocks for receiving differential currents from columns of the vector by matrix multiplication array and for generating voltages during a verify operation of the vector by matrix multiplication array; A system comprising:

24. 24. The system of claim 23, further comprising a verification circuit that generates an output.

25. 24. The system of claim 23, wherein the plurality of output blocks comprises respective current-to-voltage converters for converting currents from columns of the vector by matrix multiplication array into voltages using a plurality of resistors or a plurality of capacitors.

26. 26. The system of claim 25, wherein the plurality of output blocks comprise respective analog-to-digital converters for converting the voltages from the current-to-voltage converters to digital outputs, and wherein the verify operation utilizes the digital outputs.

27. 1. A method comprising: receiving a differential current according to the equation w=(w+)-(w-), where (w+) is received from a first column of a vector by matrix multiplication array and (w-) is received from a second column of said vector by matrix multiplication array; verifying the differential current against a reference current; A method comprising:

28. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, each of said non-volatile memory cells being capable of storing one of N possible levels corresponding to one of N possible currents; a plurality of reference voltage generators generating K reference voltages on K reference voltage lines, where K is less than N, and the K reference voltage lines verify N possible currents in a time division multiplexed manner; A system comprising:

29. 30. The system of claim 28, comprising a plurality of current-to-voltage converters for receiving currents from columns of the vector by matrix multiplication array and generating voltages during a verify operation of the vector by matrix multiplication array.

30. 30. The system of claim 29, wherein the current-to-voltage converter converts currents from columns of the vector by matrix multiplication array into voltages using multiple resistors or multiple capacitors.

31. 30. The system of claim 28, further comprising a verification circuit that generates a comparison output.

32. 29. The system of claim 28, further comprising an analog-to-digital converter that generates the comparison output.

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