Method and apparatus for determining time of flight

Abstract

A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. A logic circuit of the first communication device detects multiple timing signals from a second communication device based on analysis of the digital receive signal. The logic circuit adjusts a sampling phase of the ADC associated with at least some of the timing signals so that the ADC uses different sampling phases when different ones of the timing signals are detected. The logic circuit determines timing information based on detecting the multiple timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 417,984, filed October 20, 2022, entitled "Clock-Based Topology Discovery," the entire disclosure of which is expressly incorporated herein by reference.

[0002] The present disclosure relates generally to in-vehicle communication networks, and more particularly to topology discovery within in-vehicle communication networks. [Background technology]

[0003] In-vehicle communication networks allow components within a vehicle to exchange data. The Institute of Electrical and Electronics Engineers (IEEE) 802.3cg Standard defines a communication protocol for use in vehicles, sometimes referred to as 10BASE-T1S, for communication over a single twisted pair cable at rates up to 10 megabits per second (Mbps). The 10BASE-T1S standard supports both point-to-point and multi-drop communication. Multi-drop communication allows three or more communication devices to communicate over a single cable.

[0004] In a multi-drop network using the 10BASE-T1S standard, there may be multiple identical devices connected to a single twisted pair cable, with each device's function depending on its physical location within the vehicle. For example, there may be multiple identical radar sensors connected to a single twisted pair cable, with a first radar located at the rear of the vehicle, a second radar located at the front of the vehicle, a third radar located near the front driver's side, and a fourth radar located near the front passenger's side. Due to their locations, the first radar functions to provide object detection behind the vehicle (e.g., for when the vehicle is traveling in reverse); the second radar functions to provide object detection in front of the vehicle; the third radar functions to provide object detection in a side view from the driver's side of the vehicle; and the fourth radar functions to provide object detection in a side view from the passenger's side of the vehicle.

[0005] When the general physical arrangement of cables within a vehicle is known, a controller connected to the cables can identify the functions of the devices connected to the cables based on the devices' respective distances along the cable from the controller. Figure 1 is a simplified diagram of a vehicle 100 having an in-vehicle communication network 102 including an electronic control unit (ECU) 104 and sensors 108, 112, 116, and 120 (e.g., radar sensors, lidar sensors, etc.) electrically connected to a cable 124. Sensor 108 is located a first distance D1 along the cable 124 from ECU 104; sensor 112 is located a second distance D2 along the cable 124 from ECU 104; sensor 116 is located a third distance D3 along the cable 124 from ECU 104; and sensor 120 is located a fourth distance D4 along the cable 124 from ECU 104. When ECU 104 knows the general physical arrangement of cable 124 within the vehicle and knows the distance of each of sensors 108, 112, 116, and 120 along cable 124 from ECU 104, ECU 104 can determine the function of each of sensors 108, 112, 116, and 120. For example, when sensors 108, 112, 116, and 120 are radar sensors, ECU 104 can use their respective distances from ECU 104 to determine that i) radar sensor 108 is a rear-facing radar; ii) sensor 112 is a side-facing driver's side radar; iii) sensor 116 is a forward-facing radar, and iv) sensor 120 is a side-facing passenger's side radar.

[0006] Although FIG. 1 illustrates a communication network with ECUs and sensors, the communication network may include other suitable components such as actuators (e.g., for door locks, windows, sun / moon roof, side view mirrors, etc.), buttons, lights, etc.

[0007] One technique for determining the distance between two devices in a network such as in-vehicle communication network 102 is to measure the time required for a signal (e.g., a pulse) to travel over a communication medium from a first device to a second device (sometimes referred to as the "time of flight"). For example, the first device may transmit a forward pulse to the second device, and in response to receiving the forward pulse, the second device transmits a reverse pulse back to the first device. The first device measures the length of time between transmitting the forward pulse and receiving the reverse pulse and uses the time to calculate the distance between the first and second devices. To improve accuracy, the first and second devices may repeatedly transmit forward and reverse pulses and measure the cumulative length of time for transmitting and receiving the forward and reverse pulses. For example, in response to receiving the reverse pulse, the first device transmits another forward pulse to the second device, and the second device responds by transmitting another reverse pulse to the first device, and so on. The first device then measures the length of time between sending the first forward pulse and receiving the last reverse pulse, and uses the length of time to calculate the distance between the first device and the second device. Summary of the Invention

[0008] In an embodiment, a transceiver associated with a first communication device comprises: an analog-to-digital converter (ADC) configured to generate a digital received signal based on an analog received signal received via a communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of timing signals from a second communication device based on analysis of the digital received signal; a sampling phase generation circuit coupled to the ADC, the sampling phase generation circuit configured to adjust the sampling phase used by the ADC in relation to at least some of the timing signals, such that when different ones of the timing signals are detected, the ADC is using a different sampling phase; a timing information determination circuit configured to determine timing information based on detection of the plurality of timing signals when the ADC is using a different sampling phase when different ones of the timing signals are detected; and a processor configured to determine a time of flight based on the timing information.

[0009] In another embodiment, a method for measuring time of flight between a first communication device and a second communication device includes: receiving, at the first communication device, an analog received signal via a communication medium; converting, at an ADC of the first communication device, the analog received signal to a digital received signal; detecting, at a logic circuit of the first communication device, a plurality of timing signals from the second communication device based on analysis of the digital received signal; adjusting, at the logic circuit, a sampling phase of the ADC relative to at least some of the timing signals, so that when different ones of the timing signals are detected, the ADC is using different sampling phases; determining timing information based on detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected, at the logic circuit; and determining, at the first communication device, the time of flight based on the timing information.

[0010] In yet another embodiment, a transceiver associated with a first communication device comprises: a forward signal generation circuit configured to generate a digital transmit signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal; a clock phase adjustment circuit configured to adjust a phase of a clock provided to the DAC relative to at least some of the forward timing signals, such that the DAC uses different phases of the clock when different ones of the forward timing signals are transmitted; a driver circuit configured to transmit the analog transmit signal over a communication medium, wherein each forward timing signal prompts a second communication device to transmit a respective reverse timing signal, and wherein the DAC's use of different phases of the clock when different ones of the forward timing signals are transmitted affects the timing of each transmission of each one of the reverse timing signals; an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over the communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of reverse timing signals from the second communication device based on analysis of the digital receive signal; a timing information determination circuit configured to determine timing information based on detection of the plurality of reverse timing signals; and a processor configured to determine a time of flight based on the timing information.

[0011] In yet another embodiment, a method for measuring time of flight between a first communication device and a second communication device includes: generating, at the first communication device, a digital transmit signal including a plurality of forward timing signals; generating, at a DAC of the first communication device, an analog transmit signal based on the digital transmit signal; adjusting, in logic circuitry of the first communication device, a phase of a clock provided to the DAC relative to at least some of the forward timing signals, so that the DAC is using different phases of the clock when different ones of the forward timing signals are transmitted; transmitting, by the first communication device, the analog transmit signal over a communication medium, wherein each forward timing signal is transmitted in a manner that transmits a respective reverse timing signal. The method includes two communication devices, wherein the use by a DAC of different phases of the clock when different ones of the forward timing signals are transmitted affects the timing of the respective transmission of each of the reverse timing signals; receiving an analog receive signal via a communication medium at the first communication device; converting the analog receive signal to a digital receive signal at an analog-to-digital converter (ADC) of the first communication device; detecting, at a logic circuit, a plurality of reverse timing signals from the second communication device based on analysis of the digital receive signal; determining timing information at the logic circuit based on the detection of the plurality of reverse timing signals; and determining a time of flight at the first communication device based on the timing information. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a simplified diagram illustrating an example of a vehicle with an in-vehicle communication network in which various aspects, features, and elements described herein may be implemented, according to embodiments of the present disclosure.

[0013] [Figure 2] 1 is a simplified diagram of an exemplary communication network in which various aspects, features, and elements described herein may be implemented, according to embodiments of the present disclosure.

[0014] [Figure 3] 1 is a simplified diagram of an exemplary communications device in which various aspects, features, and elements described herein may be implemented, according to embodiments of the present disclosure.

[0015] [Figure 4] 4 is an illustrative example diagram of a sampling phase output by a phase generator of the communication device of FIG. 3 in response to a number of inverse pulses received by the communication device of FIG. 3, according to an embodiment.

[0016] [Figure 5] 4 is a simplified diagram of an example phase generator of the communication device of FIG. 3, according to an embodiment.

[0017] [Figure 6] 4 is a set of diagrams illustrating multiple inverse pulses received by the communication device of FIG. 3 while the analog-to-digital converter (ADC) of the communication device of FIG. 3 uses different sampling phases, according to an embodiment.

[0018] [Figure 7] 1 is a flow diagram of an exemplary method for measuring time of flight between a first communication device and a second communication device, according to an embodiment.

[0019] [Figure 8] 1 is a simplified diagram of another exemplary communications device in which various aspects, features, and elements described herein may be implemented, according to embodiments of the present disclosure.

[0020] [Figure 9] 10 is a set of diagrams illustrating multiple reverse pulses received by the communication device of FIG. 8 in conjunction with a digital-to-analog converter (DAC) that uses different clock phases when transmitting corresponding forward pulses that prompt the reverse pulses, according to an embodiment.

[0021] [Figure 10]10 is a flow diagram of another exemplary method for measuring time of flight between a first communication device and a second communication device, according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0022] The OPEN Alliance, in "TC14 - 10BASE-T1S Topology Discovery," proposes a procedure for measuring distance between devices using the 10BASE-T1S standard in a multidrop configuration. A first device initializes a counter to zero and transmits an initial forward pulse to a second device over the twisted pair cable. In response to receiving the forward pulse, the second device transmits a reverse pulse over the cable to the first device. In response to receiving the reverse pulse, the first device increments the counter. Additionally, in response to receiving the reverse pulse, the first device transmits another forward pulse over the cable to the second device. In response to receiving the forward pulse, the second device transmits a reverse pulse over the cable to the first device. Transmitting pulses in this manner continues for a predetermined length of time. The distance between the first and second devices is then calculated based on i) the number of reverse pulses received by the first device, as indicated by the counter, and ii) the time required to receive the reverse pulse.

[0023] The OPEN Alliance also proposes that distance measurements have an accuracy of ±15 centimeters (cm), corresponding to a time measurement resolution on the order of 100 picoseconds (ps). If pulse detection is implemented in the digital domain, this measurement accuracy suggests that the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in the transceiver that perform the procedure be clocked to provide a sampling rate of 10 gigahertz (GHz). However, the 10BASE-T1S standard specifies transmission speeds of 10 to 100 megahertz (MHz), corresponding to clock rates several orders of magnitude less than 10 GHz. In a transceiver operating at a transmission rate of 10 to 100 MHz, including an ADC and DAC capable of operating at a 10 GHz sampling rate significantly increases cost compared to, for example, an ADC and DAC capable of operating at a 10 to 100 MHz sampling rate.

[0024] In embodiments described below, techniques for achieving relatively high measurement accuracy at relatively low sampling rates are utilized to measure the time required for a signal to travel between devices over a communication medium (the "time of flight"). For example, in some embodiments, the sampling phase of an ADC is adjusted in conjunction with receiving multiple timing signals (e.g., pulses), such that different respective sampling phases are used by the ADC in conjunction with receiving different ones of the timing signals. In at least some embodiments, significantly higher resolution is achieved when calculating the time of flight based on receiving multiple timing signals (received when the ADC was using different sampling phases) compared to when the sampling phase of the ADC is controlled according to conventional methods.

[0025] In other embodiments, the phase of the clock used by the DAC is adjusted in relation to the transmission of multiple timing signals (e.g., pulses), whereby different respective phases of the clock are provided to the DAC in relation to the transmission of different ones of the timing signals. In at least some embodiments, significantly greater resolution is achieved when calculating time of flight based on the transmission of multiple timing signals (corresponding to times when the clock provided to the DAC had different phases) compared to when the phase of the clock provided to the DAC is constant.

[0026] In at least some embodiments, the application of different sampling phases and / or different clock phases, such as those described above, achieves relatively high measurement resolution at relatively low clock rates, which may reduce costs because ADCs and DACs that operate at relatively slower speeds may be used.

[0027] 2 is a simplified diagram of an exemplary communication network 200 (sometimes referred to herein as “network 200”) in which various aspects, features, and elements described herein may be implemented, according to embodiments of the present disclosure. The network includes a first communication device 204 and a second communication device 208 that are communicatively coupled via a cable 212. In an embodiment, the network 200 includes one or more other communication devices (not shown) electrically connected to the cable 212. In an embodiment, the cable 212 is a single twisted pair cable, and the first communication device 204 and the second communication device 208 are configured to operate according to 10BASE-T1S. In other embodiments, the cable 212 is another suitable type of cable (e.g., including multiple twisted pairs, coaxial cable, fiber optic cable, etc.). In other embodiments, the cable 212 is omitted, and the first communication device 204 and the second communication device 208 communicate wirelessly. In some embodiments, the first communication device 204 and the second communication device 208 communicate according to another suitable communication protocol other than 10BASE-T1S.

[0028] Network 200 corresponds to network 102 of Figure 1, and in an embodiment, Figure 2 is described with reference to Figure 1 for illustrative purposes. For example, in an embodiment, first communication device 204 corresponds to ECU 104, and second communication device 208 corresponds to one of sensors 108, 112, 116, and 120. However, in other embodiments, first communication device 204 is one of sensors 108, 112, 116, and 120, and second communication device 208 is ECU 104. In other embodiments, network 200 corresponds to another suitable network different from network 102.

[0029] The first communication device 204 and the second communication device 208 are configured to perform a procedure for determining a distance between the first communication device 204 and the second communication device 208 along the cable 212. For example, the procedure may include exchanging timing signals (e.g., pulses or other suitable timing signals) and using the exchange of timing signals to measure a time of flight between the first communication device 204 and the second communication device 208. The first communication device 204 and / or the second communication device 208 are configured to use the time of flight to determine a distance between the first communication device 204 and the second communication device 208.

[0030] As part of the distance determination procedure, the first communication device 204 is configured to transmit an initial forward timing signal 220 (e.g., a pulse) to the second communication device 208 via the cable 212. In response to receiving the forward timing signal 220, the second device transmits a reverse timing signal 224 (e.g., a pulse) to the second communication device 208 via the cable 212. The forward timing signal 220 and the reverse timing signal 224 are pulses and, in embodiments, may be simply referred to herein as "forward pulse 220" and "reverse pulse 224." However, according to other embodiments, the forward timing signal 220 and the reverse timing signal 224 are suitable timing signals other than pulses.

[0031] In conjunction with receiving the reverse pulse 224, the first communication device 204 transmits another forward pulse 220 to the second communication device 208 via the cable 212. In response to receiving the forward pulse 220, the second communication device 208 transmits a reverse pulse 224 to the first communication device 204 via the cable 212. The transmission of pulses 220, 224 continues in this manner until a period of time has expired, and a first number of forward pulses 220 have been transmitted by the first communication device 204 and / or the first communication device 204 has received a second number of reverse pulses 224, etc.

[0032] The first communication device 204 includes a front-end circuit 240 communicatively coupled to the cable 212. The front-end circuit 240 includes an ADC 244 that converts an analog receive signal to a digital receive signal. The front-end circuit 240 also includes a DAC 248 that converts a digital transmit signal to an analog transmit signal. The ADC 244 and the DAC 248 are communicatively coupled to the cable 212. In some embodiments, the front-end circuit 240 includes other circuitry (e.g., one or more of a hybrid circuit, an amplifier, a driver, a filter, etc.) that is not shown for purposes of simplicity. In some embodiments in which the cable 212 is not a single twisted pair cable or is omitted entirely, the front-end circuit 240 has another structure appropriate for the communication medium used.

[0033] In some embodiments, the sampling phase of the ADC 244 is adjusted in relation to the receipt of multiple inverse pulses 224, such that different respective sampling phases are used by the ADC in relation to the receipt of different ones of the timing signals. In at least some embodiments, significantly higher resolution is achieved when calculating time of flight based on the receipt of multiple inverse pulses 224 (received when the ADC 244 was using different sampling phases) compared to when the sampling phase of the ADC 244 is controlled according to conventional methods.

[0034] In other embodiments, the phase of the clock used by the DAC 248 is adjusted in relation to the transmission of the multiple forward pulses 220, such that different respective phases of the clock are provided to the DAC 248 in relation to the transmission of different ones of the forward pulses 220. In at least some embodiments, significantly greater resolution is achieved when calculating time of flight based on the transmission of multiple forward pulses 220 (corresponding to times when the clock provided to the DAC 248 had different phases) compared to when the phase of the clock provided to the DAC 248 is constant.

[0035] Figure 3 is a simplified diagram of an exemplary communications device 300, according to an embodiment. In an embodiment, communications device 300 is utilized in network 200 of Figure 2, and Figure 3 is described with reference to Figure 2 for illustrative purposes. For example, communications device 300, in an embodiment, corresponds to first communications device 204 of Figure 2. In other embodiments, first communications device 204 has a different suitable structure than communications device 300 and / or communications device 300 is used in a different suitable communications network than network 200.

[0036] Communications device 300 includes transmit circuitry 308 and receive circuitry 312, both of which are coupled to analog front-end circuitry 316. Front-end circuitry 316 is communicatively coupled to cable 320. In an embodiment, cable 320 is a single twisted pair cable, and communications device 300 is configured to operate in accordance with 10BASE-T1S. In other embodiments, cable 320 is another suitable type of cable (e.g., including multiple twisted pairs, coaxial cable, fiber optic cable, etc.). In other embodiments, cable 320 is omitted, and communications device 300 communicates wirelessly. In some embodiments, communications device 300 is configured to operate in accordance with another suitable communications protocol different from 10BASE-T1S.

[0037] Front-end circuitry 316 includes an ADC 324 that converts analog receive signals received via cable 320 to digital receive signals. Front-end circuitry 316 also includes a DAC 328 that converts digital transmit signals to analog transmit signals for transmission via cable 320. Front-end circuitry 316 also includes a driver circuit 332 coupled to the output of DAC 328. Driver circuit 332 and ADC 324 are communicatively coupled to cable 320 via a hybrid circuit 336. In some embodiments, front-end circuitry 316 includes other circuitry (e.g., one or more of amplifiers, drivers, filters, etc.) that is not shown for purposes of simplicity. In some embodiments in which cable 320 is not a single twisted pair cable or is omitted entirely, front-end circuitry 316 has another structure appropriate for the communication medium used.

[0038] Communications device 300 includes a timing measurement system 340 configured to determine time of flight with respect to another communications device (not shown) based on timing signals received from the other communications device via cable 320 .

[0039] The transmit circuitry 308 and the timing measurement system 340 are selectively coupled to the DAC 328 via switch 344. The receive circuitry 312 and the timing measurement system 340 are selectively coupled to the ADC 324 via switch 348 and switch 352. During normal operation (e.g., when the communications device 300 is communicating user information over the cable 320), the switches 344, 348, and 352 are controlled to i) couple the transmit circuitry 308 and the receive circuitry 312 to the analog front end 316 and ii) isolate the timing measurement system 340 from the analog front end 316. However, during flight measurement procedures, the switches 344, 348, and 352 are controlled to i) couple the timing measurement system 340 to the analog front end 316 and ii) isolate the transmit circuitry 308 and the receive circuitry 312 from the analog front end 316.

[0040] Timing measurement system 340 includes a pulse generator 368 having an output coupled to an input of switch 344. Pulse generator 368 is configured to generate a digital transmit signal including a plurality of forward pulses, such as forward pulse 220. When pulse generator 368 is coupled to DAC 328 by switch 344, DAC 328 converts the digital transmit signal into an analog transmit signal including a plurality of analog forward pulses for transmission over cable 320.

[0041] Timing measurement system 340 also includes a pulse detector 360 having an input coupled to the output of switch 348. Pulse detector 360 is configured to analyze the digital receive signal output by ADC 324 and detect multiple inverse pulses, such as inverse pulse 224, in the digital receive signal. Thus, when pulse detector 360 is coupled to ADC 324 by switch 348, pulse detector 360 analyzes the digital receive signal output by ADC 324 to detect multiple inverse pulses received from other communication devices via cable 320. When pulse detector 360 detects a pulse in the digital receive signal, the pulse detector generates a pulse detect signal.

[0042] Counter 364 (referred to herein as "pulse counter 364") is coupled to pulse detector 360. Pulse counter 364 counts the inverse pulses detected by pulse detector 360. Pulse counter 364 is configured to increment a count in response to each pulse detect signal output by pulse detector 360.

[0043] The pulse generator 368 is also coupled to the pulse detector 360. The pulse generator 368 is configured to generate a forward pulse in the digital transmit signal in response to each of at least some of the pulse detect signals output by the pulse detector 360. In an embodiment, the pulse generator 368 is configured to introduce a time delay between when a pulse detect signal is output by the pulse detector 360 and the start of the corresponding forward pulse output by the pulse generator 368, such that in response to the communications device 300 receiving a reverse pulse via the cable 320, the communications device 300 transmits a forward pulse.

[0044] Timing measurement system 340 also includes processor 372. Processor 372 is configured to control operation of timing measurement system 340 during a flight measurement procedure. For example, in an embodiment, processor 372 is configured to prompt pulse generator 368 to transmit a first forward pulse during a flight measurement procedure. In connection with the completion of the flight measurement procedure, processor 372 is also configured to calculate a time-of-flight based on i) the count of reverse pulses output by pulse counter 364, and ii) the duration between when the first forward pulse was transmitted and when the last reverse pulse was received. In an embodiment, processor 372 includes counter 376 used to count the number of clock cycles between when the first forward pulse was transmitted and when the last reverse pulse was received, where the number of clock cycles output by counter 376 indicates the duration between when the first forward pulse was transmitted and when the last reverse pulse was received. In an embodiment, processor 372 starts counter 376 in connection with communications device 300 transmitting the first forward pulse of the flight measurement procedure time and stops counter 376 in connection with communications device 300 receiving the last reverse pulse of the flight measurement procedure time. In an embodiment, processor 372 starts counter 376 in response to the start of the flight measurement procedure time and stops counter 376 in response to pulse detector 360 detecting the last reverse pulse of the flight measurement procedure time.

[0045] In another embodiment, counter 376 is a countdown counter, and processor 372 starts counter 376 in response to the start of the time for the flight measurement procedure. When counter 376 reaches a predetermined value (e.g., zero), processor 372 determines that the time for the flight measurement procedure has ended.

[0046] Timing measurement system 340 also includes a phase generator 380 having an output coupled to an input of switch 352. During normal operation, switch 352 couples the output of receive circuit 312 to the sampling phase input of ADC 324, and receive circuit 312 controls the sampling phase of ADC 324 to clock other communications devices (not shown) sending transmit symbols to communications device 300. On the other hand, during flight measurement procedures, the sampling phase of ADC 324 is adjusted by phase generator 380.

[0047] The phase generator 380 is configured to provide different sampling phases to the ADC 324 in association with the communication device 300 receiving the inverse pulses, such that different respective sampling phases are used by the ADC 324 in association with receiving different ones of the inverse pulses. In an embodiment, the phase generator 380 is coupled to the pulse detector 360 and configured to change the sampling phase in response to the pulse detector 360 detecting the inverse pulses. In an embodiment, the phase generator 380 changes the sampling phase in response to each inverse pulse detected by the pulse detector 360. In other embodiments, the phase generator 380 changes the sampling phase i) every N inverse pulses detected by the pulse detector 360, where N is a suitable integer greater than 1; ii) every M clock cycles, where M is a suitable positive integer; or iii) at some other suitable frequency, such as a suitable time frequency. In an embodiment, the phase generator 380 is configured to change the sampling phase by incrementing the sampling phase by a fixed amount at a suitable frequency, such as that described above. In an embodiment, the phase generator 380 increments the sampling phase modulo-wise so that the sampling phase remains within a predetermined range of the sampling phase. For example, the phase generator 380 increments the sampling phase by a predetermined amount modulo-wise at a suitable frequency, such as that described above.

[0048] In some embodiments, timing measurement system 340 includes logic circuitry configured to perform operations such as those described above. For example, in some embodiments, processor 372 includes logic circuitry such as a hardware state machine configured to perform operations corresponding to processor 372, such as those described above. In other embodiments, timing measurement system 340 also includes a processor that executes machine-readable instructions stored in a memory coupled to the processor, where the machine-readable instructions, when executed by the processor, cause the processor to perform operations such as those described above. For example, processor 372 includes a processor that executes machine-readable instructions that, when executed by the processor, cause the processor to perform operations corresponding to processor 372, such as those described above.

[0049] 4 is a diagram of an illustrative example of the sampling phase output by the phase generator 380 depending on the number of inverse pulses received by the communication device 300, according to an embodiment. In other embodiments, the phase generator 380 outputs other suitable sampling phases different from the example of FIG. 4. As illustrated in FIG. 4, the sampling phase increases in steps in a modulo manner as the number of inverse pulses increases, so that the sampling phase remains within a fixed range of sampling phases.

[0050] Figure 5 is a simplified diagram of an exemplary phase generator 500 according to an embodiment. Phase generator 500 corresponds to phase generator 380 of Figure 3, and in embodiments, Figure 5 is described with reference to Figure 3 for illustrative purposes. In other embodiments, phase generator 380 has a different suitable structure than phase generator 500 and / or phase generator 500 is used in a different suitable communication device than communication device 300.

[0051] Phase generator 500 includes a multiplexer 504 having a first input set to zero and a second input set to a value ("phase delta") by which the sampling phase is to be adjusted. The select input of multiplexer 504 is coupled to the output of pulse detector 360. When a reverse pulse is not detected by pulse detector 360, multiplexer 504 outputs zero. On the other hand, when pulse detector 360 detects a reverse pulse, multiplexer 504 outputs phase delta.

[0052] The output of multiplexer 504 is coupled to a first input of adder 508. The output of adder 508 is coupled to an input of register 512. The output of register 512 is coupled to a second input of adder 508.

[0053] In operation, phase generator 500 begins by outputting zero. As each inverse pulse is detected, the output of phase generator 500 increments by a phase delta. Because adder 508 and register 512 have a limited number of bits, the sampling phase (e.g., the output of register 512) wraps around in a manner similar to the sampling phase illustrated in FIG. 4. Phase generator 500 thereby increments the sampling phase in a modulo manner, so that the sampling phase, in embodiments, remains within a fixed range of sampling phases.

[0054] Referring again to FIG. 3 , in other embodiments, phase generator 380 is configured to adjust the sampling phase in a different suitable manner, such that the sampling phase output by phase generator 380 does not increment, such as described above with reference to FIGS. 4 and 5 . For example, phase generator 380 adjusts the sampling phase so that the sampling phase output by phase generator 380 decrements in a modulo manner similar to the methods / apparatuses described above with reference to FIGS. 4 and 5 . As another example, according to an embodiment, phase generator 380 adjusts the sampling phase in a predetermined manner (e.g., according to a pseudo-random sequence of different sampling phases, according to a repeating fixed sequence of different sampling phases, etc.) such that each sampling phase of the set of sampling phases is used in connection with detecting approximately equal numbers of timing signals during the measurement procedure (i.e., no sampling phase is used in connection with detecting more than one additional timing signal compared to any other sampling phase during the measurement procedure). In other words, according to an embodiment, each sampling phase is used in connection with detecting at least X timing signals during the measurement procedure, and no sampling phase is used in connection with detecting more than X+1 timing signals during the measurement procedure, where X is a suitable positive integer greater than 1.

[0055] As an illustrative example, according to an embodiment, the measurement procedure has a time length spanning multiple time intervals, and the phase generator 380 adjusts the sampling phases in a predetermined manner so that each sampling phase of the set of sampling phases is used in connection with detecting only an equal number (e.g., 1, 2, 3, etc.) of timing signals during each time interval.

[0056] More generally, according to some embodiments, the measurement procedure has a time length spanning multiple time intervals, and the phase generator 380 adjusts the sampling phases so that each sampling phase of the set is used in connection with detecting only an equal number (e.g., 1, 2, 3, etc.) of timing signals during each time interval.

[0057] FIG. 6 is a set of diagrams illustrating multiple inverse pulses received by communication device 300 while ADC 324 uses different sampling phases, according to an embodiment.

[0058] Diagram 604 illustrates inverse pulse 1 received while ADC 324 is using a sampling phase of zero. The rising edge of inverse pulse 1 occurs between clock edge L and clock edge L+1. As a result, inverse pulse 1 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect inverse pulse 1 until after clock edge L+1.

[0059] Diagram 608 illustrates inverse pulse 2 being received while ADC 324 is using a sampling phase of Δ. Again, the rising edge of inverse pulse 2 occurs between clock edge L and clock edge L+1. As a result, inverse pulse 2 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect inverse pulse 2 until after clock edge L+1.

[0060] Diagram 612 illustrates inverse pulse 3 received while ADC 324 is using a sampling phase of 2Δ. Again, the rising edge of inverse pulse 3 occurs between clock edge L and clock edge L+1. As a result, inverse pulse 3 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect inverse pulse 3 until after clock edge L+1.

[0061] Diagram 616 illustrates inverse pulse 4 received while ADC 324 is using a sampling phase of 3Δ. Again, the rising edge of inverse pulse 4 occurs between clock edge L and clock edge L+1. As a result, inverse pulse 4 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect inverse pulse 4 until after clock edge L+1.

[0062] Diagram 620 illustrates inverse pulse 5 received while ADC 324 is using a sampling phase of 4Δ, where the rising edge of inverse pulse 5 occurs before clock edge L. As a result, inverse pulse 5 is reflected at the output of ADC 324 at clock edge L, and pulse detector 360 detects inverse pulse 5 relative to clock edge L.

[0063] Diagram 624 illustrates an inverse pulse 6 received while ADC 324 is using a sampling phase of 5Δ, where the rising edge of inverse pulse 6 occurs before clock edge L. As a result, inverse pulse 6 is reflected at the output of ADC 324 at clock edge L, and pulse detector 360 detects inverse pulse 6 relative to clock edge L.

[0064] More generally, during a timing measurement procedure in which the sampling phase of ADC 324 is adjusted as described above, m inverse pulses are detected relative to clock edge L and n inverse pulses are detected relative to clock edge L+1, where the ratio of m to n varies depending on how far from clock edge L the inverse pulses occur when the sampling phase is zero.

[0065] The total measurement time for receiving m+n multiple inverse pulses can be expressed as: (m*L+n*(L+1))*T Equation 1 where T is the period of the sampling clock. The average time to receive each reverse pulse can be expressed as: (L+n / (m+n))*T Equation 2 As can be seen by Equation 2, adjusting the sampling phase of the ADC 324 as described above while receiving multiple inverse pulses provides, in at least some embodiments, a higher resolution time measurement compared to receiving multiple inverse pulses while maintaining a constant sampling phase of the ADC 324. For example, the term n / (m+n) indicates where between clock edges L and L+1 the inverse pulse occurs when the sampling phase is zero.

[0066] FIG. 7 is a flow diagram of an exemplary method 700 for measuring time of flight between a first communication device and a second communication device, according to an embodiment. Method 700 is implemented in network 102 of vehicle 100 of FIG. 1, according to an embodiment. In some embodiments, additionally or alternatively, method 700 is implemented by a communication device having a structure similar to communication device 300 of FIG. 3. FIG. 7 is described with reference to FIG. 3 for ease of explanation. In other embodiments, method 700 is implemented in another suitable vehicle other than vehicle 100 of FIG. 1 and / or another suitable communication device other than communication device 300 of FIG. 3.

[0067] In block 704, the first communication device receives the analog receive signal over the communication medium, for example, the communication device 300 receives the analog receive signal over the cable 320.

[0068] In block 708, the ADC of the first communication device converts the analog receive signal to a digital receive signal. For example, the ADC 324 converts the analog receive signal received via the cable 320 to a digital receive signal.

[0069] In block 712, the logic circuitry of the first communication device detects a plurality of timing signals from the second communication device based on analysis of the digital received signal. For example, pulse detector 360 detects a plurality of inverse pulses from the second communication device based on analysis of the digital received signal output by ADC 324. In other embodiments, the timing signal is a suitable signal other than a pulse. For example, in other embodiments, the timing signal includes a predetermined pattern and the logic circuitry includes correlation or autocorrelation circuitry used to detect the predetermined pattern.

[0070] In block 716, the logic circuit adjusts the sampling phase of the ADC relative to at least some of the timing signals so that the ADC is using a different sampling phase when different ones of the timing signals are detected. For example, the output of phase generator 380 is used to adjust the sampling phase of ADC 324.

[0071] Adjusting the sampling phase of the ADC in block 716 includes adjusting the sampling phase in relation to detecting each of at least some of the timing signals. For example, the phase generator 380 adjusts the sampling phase in response to the pulse detector 360 detecting an inverse pulse. In an embodiment, the phase generator 380 increments the sampling phase by a predetermined amount in response to the pulse detector 360 detecting an inverse pulse. In an embodiment, the phase generator 380 increments the sampling phase modulo-wise so that the sampling phase remains within a predetermined range of the sampling phase.

[0072] In an embodiment, adjusting the sampling phase in block 716 includes adjusting the sampling phase in response to each timing signal detected in block 712. In other embodiments, adjusting the sampling phase in block 716 includes adjusting the sampling phase i) every N timing signals detected in block 712, where N is a suitable integer greater than 1; ii) every M clock cycles, where M is a suitable positive integer; or iii) at some other suitable frequency, such as a suitable time frequency.

[0073] In an embodiment, adjusting the sampling phase at block 716 includes incrementing the sampling phase by a fixed amount at a suitable frequency, such as that described above. In an embodiment, the sampling phase is incremented modulo-wise, so that the sampling phase remains within a predetermined range of the sampling phase.

[0074] In an embodiment, adjusting the sampling phase at block 716 includes adjusting the sampling phase in response to detecting each of at least some of the timing signals at block 712 .

[0075] In block 720, the logic circuit determines timing information based on detecting the multiple timing signals in block 712 when the ADC uses different sampling phases when different ones of the timing signals are detected. For example, the pulse counter 364 counts the detected inverse pulses, and the counter 376 measures the period (e.g., number of clocks) during which the detected inverse pulses are received by the communication device 300.

[0076] At block 724, the first communications device determines the time of flight based on the timing information, for example, processor 372 determines the time of flight based on the count of detected reverse pulses (measured by pulse counter 364) and the period during which the detected reverse pulses were received by communications device 300 (measured by counter 376).

[0077] In an embodiment, determining the timing information at block 720 includes: counting, at the logic circuit, timing signals detected by the logic circuit and determining, at the first communications device, a period until the number of timing signals is detected; determining the time-of-flight at block 724 includes determining the time-of-flight based on i) the number of timing signals and ii) the period. In an embodiment, determining the period includes counting the number of clock cycles until the number of timing signals is detected; determining the time-of-flight includes determining the time-of-flight based on i) the number of timing signals and ii) the number of clock cycles.

[0078] In another embodiment, the timing signal is a reverse timing signal; method 700 further comprises: generating, at the first communication device, an analog transmit signal including a plurality of forward timing signals; and transmitting, by the first communication device, the analog transmit signal over the communication medium, wherein each forward timing signal prompts the second communication device to transmit a respective reverse timing signal.

[0079] In some embodiments, the phase of the clock provided to the DAC of the communications device is adjusted relative to the transmission of the forward timing signal, rather than by adjusting the sampling phase of the ADC relative to the reception of the reverse timing signal.

[0080] Figure 8 is a simplified diagram of another exemplary communications device 800 according to another embodiment. In an embodiment, communications device 800 is utilized in network 200 of Figure 2, and Figure 8 is described with reference to Figure 2 for illustrative purposes. For example, communications device 800, in an embodiment, corresponds to first communications device 204 of Figure 2. In other embodiments, first communications device 204 has a different suitable structure than communications device 800 and / or communications device 800 is used in a different suitable communications network than network 200.

[0081] Communications device 800 is similar to communications device 300 of FIG. 3 and includes similarly numbered elements that will not be described in detail again for the sake of brevity.

[0082] Unlike communications device 300, communications device 800 omits phase generator 380, and instead the input of switch 352 receives a fixed phase input. During normal operation, switch 352 couples the output of receive circuit 312 to the sampling phase input of ADC 324, and receive circuit 312 controls the sampling phase of ADC 324 to clock other communications devices (not shown) sending transmit symbols to communications device 300. On the other hand, in an embodiment, during flight measurement procedures, the sampling phase of ADC 324 is set to a fixed sampling phase.

[0083] Also, unlike communications device 300, communications device 800 includes a phase generator 824 having i) an input for receiving a clock, and ii) an output coupled to the clock input of DAC 328. Phase generator 824 includes another input coupled to pulse detector 360. According to an embodiment, during normal operation, phase generator 824 passes the clock to DAC 328 without adjusting the phase of the clock. On the other hand, during flight measurement procedures, phase generator 824 adjusts the phase of the clock provided to DAC 328.

[0084] The phase generator 824 is configured to provide different clock phases to the DAC 328 in association with the communications device 800 transmitting forward pulses, such that different respective clock phases are used by the DAC 328 in association with transmitting different ones of the forward pulses. In an embodiment, the phase generator 824 is configured to change the clock phase in response to the pulse detector 360 detecting a reverse pulse. In an embodiment, the phase generator 824 changes the clock phase in response to each reverse pulse detected by the pulse detector 360. In other embodiments, the phase generator 824 changes the clock phase i) every N reverse pulses detected by the pulse detector 360, where N is a suitable integer greater than 1; ii) every M clock cycles, where M is a suitable positive integer; or iii) at some other suitable frequency, such as a suitable time frequency. In an embodiment, the phase generator 824 is configured to change the clock phase by incrementing the clock phase by a fixed amount at a suitable frequency, such as that described above. In an embodiment, the phase generator 824 increments the clock phase modulo-wise so that the clock phase remains within a predetermined range of the clock phase. For example, the phase generator 824 increments the clock phase by a predetermined amount modulo-wise at a suitable frequency, such as that described above.

[0085] In some embodiments, timing measurement system 820 includes logic circuitry configured to perform operations such as those described above. For example, in some embodiments, processor 372 includes logic circuitry such as a hardware state machine configured to perform operations corresponding to processor 372, such as those described above. In other embodiments, timing measurement system 820 also includes a processor that executes machine-readable instructions stored in a memory coupled to the processor, where the machine-readable instructions, when executed by the processor, cause the processor to perform operations such as those described above. For example, processor 372 includes a processor that executes machine-readable instructions that, when executed by the processor, cause the processor to perform operations corresponding to processor 372, such as those described above.

[0086] In embodiments in which another communications device transmits a reverse timing signal (e.g., a reverse pulse) in response to a forward timing signal (e.g., a forward pulse), the use by DAC 328 of different phases of the clock when different ones of the forward timing signals are transmitted affects the timing of the transmission of each one of the reverse timing signals in a manner similar to that described above with reference to FIGS. 3 and 6.

[0087] FIG. 9 is a set of diagrams illustrating multiple reverse pulses received by communication device 800 in association with DAC 328 using different clock phases when transmitting the corresponding forward pulses that prompted the reverse pulses, according to an embodiment.

[0088] Diagram 904 illustrates reverse pulse 1 corresponding to DAC 328 using a sampling phase of zero relative to transmitting transmit pulse 1, which prompted reverse pulse 1. The rising edge of reverse pulse 1 occurs between clock edge L and clock edge L+1. As a result, reverse pulse 1 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect reverse pulse 1 until after clock edge L+1.

[0089] Diagram 908 illustrates reverse pulse 2 corresponding to DAC 328 using a sampling phase of −Δ relative to transmitting transmit pulse 2, which prompted reverse pulse 2. Again, the rising edge of reverse pulse 2 occurs between clock edge L and clock edge L+1. As a result, reverse pulse 2 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect reverse pulse 2 until after clock edge L+1.

[0090] Diagram 912 illustrates reverse pulse 3 corresponding to DAC 328 using a sampling phase of −2Δ relative to transmitting transmit pulse 3, which prompted reverse pulse 3. Again, the rising edge of reverse pulse 3 occurs between clock edge L and clock edge L+1. As a result, reverse pulse 3 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect reverse pulse 3 until after clock edge L+1.

[0091] Diagram 916 illustrates reverse pulse 4 corresponding to DAC 328 using a sampling phase of −3Δ relative to transmitting transmit pulse 4, which prompted reverse pulse 4. Again, the rising edge of reverse pulse 4 occurs between clock edge L and clock edge L+1. As a result, reverse pulse 4 is not reflected at the output of ADC 324 until clock edge L+1, and pulse detector 360 does not detect reverse pulse 4 until after clock edge L+1.

[0092] Diagram 920 illustrates reverse pulse 5 corresponding to DAC 328 using a sampling phase of −4Δ relative to transmitting transmit pulse 5, which prompted reverse pulse 5. Here, the rising edge of reverse pulse 5 occurs before clock edge L. As a result, reverse pulse 5 is reflected at the output of ADC 324 at clock edge L, and pulse detector 360 detects reverse pulse 5 relative to clock edge L.

[0093] Diagram 924 illustrates reverse pulse 6 corresponding to DAC 328 using a sampling phase of −5Δ relative to transmitting transmit pulse 6, which prompted reverse pulse 6. Here, the rising edge of reverse pulse 6 occurs before clock edge L. As a result, reverse pulse 6 is reflected at the output of ADC 324 at clock edge L, and pulse detector 360 detects reverse pulse 6 relative to clock edge L.

[0094] More generally, during a timing measurement procedure in which the sampling phase of DAC 328 is adjusted as described above, m inverse pulses are detected relative to clock edge L and n inverse pulses are detected relative to clock edge L+1, where the ratio of m to n varies depending on how far from clock edge L the inverse pulses occur when the sampling phase is zero.

[0095] The total measurement time (in terms of clock cycles) for receiving m+n reverse pulses may be expressed as shown in Equation 1, and the average of the time (in terms of clock cycles) to receive each reverse pulse may be expressed as shown in Equation 2. As can be seen from Equation 2, in at least some embodiments, adjusting the clock phase of DAC 328 as described above while transmitting multiple forward pulses provides a higher resolution time measurement compared to transmitting multiple forward pulses while maintaining the clock phase of DAC 328 constant. For example, the term n / (m+n) indicates where the reverse pulse occurs between clock edges L and L+1 when the sampling phase is zero.

[0096] Figure 10 is a flow diagram of an exemplary method 1000 for measuring time of flight between a first communication device and a second communication device, according to an embodiment. Method 1000 is implemented in network 102 of vehicle 100 of Figure 1, according to an embodiment. In some embodiments, additionally or alternatively, method 1000 is implemented by a communication device having a structure similar to communication device 800 of Figure 8. Figure 10 is described with reference to Figure 8 for ease of explanation. In other embodiments, method 1000 is implemented in another suitable vehicle other than vehicle 100 of Figure 1 and / or another suitable communication device other than communication device 800 of Figure 8.

[0097] In block 1004, the first communication device generates a digital transmit signal including a plurality of forward timing signals. For example, the pulse generator 368 generates the digital transmit signal including a plurality of forward pulses. In other embodiments, the forward timing signals are suitable signals other than pulses. In other embodiments, for example, the forward timing signals include a predetermined pattern, and the first communication device includes circuitry configured to generate each forward signal according to the predetermined pattern.

[0098] At block 1008, the DAC of the first communication device generates an analog transmit signal based on the digital transmit signal. For example, the DAC 328 generates the analog transmit signal based on the digital transmit signal. According to an embodiment, the analog transmit signal is for transmission over the cable 320. The analog transmit signal includes an analog version of the forward timing signal in the digital transmit signal.

[0099] In block 1012, logic circuitry of the first communication device adjusts the phase of a clock provided to the DAC relative to at least some of the forward timing signals so that the DAC uses different phases of the clock when different ones of the forward timing signals are transmitted by the first communication device. Adjusting the phase of the clock in block 2008 is described further below.

[0100] At block 1016, the first communication device transmits an analog transmit signal over the communication medium. For example, communication device 800 transmits the analog transmit signal over cable 320. In an embodiment, the analog version of each forward timing signal prompts the second communication device to transmit a respective reverse timing signal. In an embodiment, the use by the DAC of different phases of the clock when different ones of the analog versions of the forward timing signal are transmitted affects the timing of the respective transmission of each one of the reverse timing signals.

[0101] In block 1020, the first communication device receives the analog receive signal over the communication medium. For example, the communication device 800 receives the analog receive signal over the cable 320.

[0102] The ADC of the first communication device converts the analog receive signal to a digital receive signal in block 1024. For example, the ADC 324 converts the analog receive signal received via the cable 320 to a digital receive signal.

[0103] At block 1028, the logic circuitry detects a plurality of inverse timing signals from the second communication device based on an analysis of the digital received signal. For example, pulse detector 360 detects a plurality of inverse pulses from the second communication device based on an analysis of the digital received signal output by ADC 324. In other embodiments, the timing signal is a suitable signal other than a pulse. For example, in other embodiments, the timing signal includes a predetermined pattern and the logic circuitry includes a correlation or autocorrelation circuit used to detect the predetermined pattern.

[0104] Referring again to block 1012, adjusting the phase of the clock provided to the DAC in block 1012 includes adjusting the phase of the clock in association with detecting each of at least some of the reverse timing signals in block 1028. For example, phase generator 380 adjusts the phase of the clock in response to pulse detector 360 detecting a reverse pulse. In an embodiment, phase generator 380 increments the phase of the clock by a predetermined amount in response to pulse detector 360 detecting a reverse pulse. In an embodiment, phase generator 380 increments the phase of the clock in a modulo manner such that the phase of the clock remains within a predetermined range of clock phases.

[0105] In an embodiment, adjusting the phase of the clock in block 1012 includes adjusting the phase of the clock in response to detecting each reverse timing signal in block 1028. In some other embodiments, adjusting the phase of the clock in block 1012 includes adjusting the phase of the clock i) every N reverse timing signals detected in block 1028, where N is a suitable integer greater than 1, ii) every M clock cycles, where M is a suitable positive integer, or iii) at some other suitable frequency, such as a suitable time frequency.

[0106] In an embodiment, adjusting the phase of the clock in block 1012 includes incrementing the phase of the clock by a fixed amount at a suitable frequency, such as that described above. In an embodiment, the phase of the clock is incremented modulo-wise so that the phase of the clock remains within a predetermined range of the sampling phase.

[0107] In an embodiment, adjusting the phase of the clock at block 1012 includes adjusting the phase of the clock in response to detecting each of at least some of the reverse timing signals at block 1028 .

[0108] At block 1032, the logic circuit determines timing information based on the detection of the multiple reverse timing signals at block 1028. For example, pulse counter 364 counts the detected reverse pulses, and counter 376 measures the period (e.g., number of clocks) during which the detected reverse pulses are received by communication device 300.

[0109] At block 1036, the first communications device determines the time of flight based on the timing information determined at block 1032. For example, the processor 372 determines the time of flight based on the count of detected reverse pulses (measured by pulse counter 364) and the period during which the detected reverse pulses were received by communications device 800 (measured by counter 376).

[0110] In an embodiment, determining the timing information at block 1036 includes: counting in the logic circuit reverse timing signals detected by the logic circuit and determining in the first communication device a period until the number of reverse timing signals is detected; determining the time of flight at block 1036 includes determining the time of flight based on i) the number of reverse timing signals and ii) the period. In an embodiment, determining the period includes counting the number of cycles of a clock until the number of reverse timing signals is detected; determining the time of flight includes determining the time of flight based on i) the number of reverse timing signals and ii) the number of cycles of the clock.

[0111] For purposes of explanation, time-of-flight measurement techniques are described above in the context of an in-vehicle communication network, however, similar time-of-flight measurement techniques may be implemented in other suitable environments such as industrial communication networks (e.g., in process plants, manufacturing plants, etc.), sensor networks, remote sensing applications, indoor or outdoor positioning applications, etc.

[0112] Some of the various blocks, operations, and techniques described above may be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any suitable combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions may be stored in any suitable computer-readable memory, such as random access memory (RAM), read-only memory (ROM), solid-state memory (e.g., flash memory), etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various operations, such as those described above.

[0113] Embodiment 1: A transceiver associated with a first communication device includes: an analog-to-digital converter (ADC) configured to generate a digital received signal based on an analog received signal received over a communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of timing signals from a second communication device based on analysis of the digital received signal; a sampling phase generation circuit coupled to the ADC, the sampling phase generation circuit configured to adjust the sampling phase used by the ADC in relation to at least some of the timing signals, such that when different ones of the timing signals are detected, the ADC is using different sampling phases; a timing information determination circuit configured to determine timing information based on detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected; and a processor configured to determine a time of flight based on the timing information.

[0114] Embodiment 2: The transceiver of embodiment 1, wherein the sampling phase generation circuit is configured to adjust a sampling phase relative to detecting each of at least some of the timing signals.

[0115] Embodiment 3: The transceiver of embodiment 2, wherein the sampling phase generation circuit is configured to adjust the sampling phase in response to detecting each of at least some of the timing signals.

[0116] Embodiment 4: The transceiver of any of embodiments 1 to 3, wherein the sampling phase generation circuit is configured to adjust the sampling phase so that, for each of a plurality of time intervals during the flight measurement period, each sampling phase from a set of multiple sampling phases is used by the ADC in connection with detecting only the same number of timing signals.

[0117] Embodiment 5: The transceiver of embodiment 4, wherein the sampling phase generation circuit is configured to adjust the sampling phase so that, for each of a plurality of time intervals during the flight measurement period, each sampling phase from a set of multiple sampling phases is used by the ADC in connection with detecting only one respective timing signal.

[0118] Embodiment 6: The transceiver of any of embodiments 1 to 5, wherein the sampling phase generation circuit is configured to adjust the sampling phase such that, during the time of the flight measurement period, each sampling phase from the set of multiple sampling phases is used by the ADC in association with detecting at least X timing signals during the measurement procedure, and no sampling phase is used by the ADC in association with detecting more than X+1 timing signals during the measurement procedure, where X is a suitable positive integer greater than 1.

[0119] Embodiment 7: The transceiver of any one of embodiments 1 to 6, wherein the sampling phase generation circuit is configured to adjust the sampling phase by at least incrementing the sampling phase by the same amount in a modulo manner.

[0120] Embodiment 8: The transceiver of any one of embodiments 1 to 6, wherein the sampling phase generation circuit is configured to adjust the sampling phase by at least modulo decrementing the sampling phase by the same amount.

[0121] Embodiment 9: The transceiver of any one of embodiments 1 to 8, wherein the sampling phase generation circuit is configured to adjust the sampling phase according to a repetitive fixed sequence of different sampling phases.

[0122] Embodiment 10: The transceiver of any one of embodiments 1 to 6, wherein the sampling phase generation circuit is configured to adjust the sampling phase pseudo-randomly.

[0123] Embodiment 11: A transceiver of any of embodiments 1 to 10, wherein the timing information determination circuit includes a counter configured to count timing signals detected by the timing signal detection circuit; and the processor is configured to: determine the period until the number of timing signals is detected; and determine the time of flight based on i) the number of timing signals and ii) the period.

[0124] Embodiment 12: A transceiver of embodiment 11, wherein the counter is a first counter, and wherein the processor includes a second counter configured to count the number of cycles of the clock until a number of timing signals is detected, the number of cycles of the clock indicating a period; and the processor is configured to determine the time of flight based on i) the number of timing signals and ii) the number of cycles of the clock.

[0125] Embodiment 13: A transceiver of any of embodiments 1 to 12, wherein the timing signal is a reverse timing signal, and wherein the transceiver further comprises a transmitting circuit configured to: generate an analog transmit signal including a plurality of forward timing signals; and transmit the analog transmit signal over a communication medium, wherein each forward timing signal prompts a second communication device to transmit a respective reverse timing signal.

[0126] Embodiment 14: A communication system including the transceiver of embodiment 13, wherein the communication system further includes a second communication device.

[0127] Embodiment 15: A communication system including the transceiver of any one of embodiments 1 to 13 and / or the communication system of embodiment 14, the communication system further including a communication medium.

[0128] Embodiment 16: A method for measuring time of flight between a first communication device and a second communication device, comprising: receiving, at the first communication device, an analog received signal via a communication medium; converting, at an analog-to-digital converter (ADC) of the first communication device, the analog received signal into a digital received signal; detecting, at a logic circuit of the first communication device, a plurality of timing signals from the second communication device based on analysis of the digital received signal; adjusting, at the logic circuit, a sampling phase of the ADC relative to at least some of the timing signals, so that when different ones of the timing signals are detected, the ADC is using different sampling phases; determining, at the logic circuit, timing information based on detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected; and determining, at the first communication device, the time of flight based on the timing information.

[0129] Embodiment 17: The method of embodiment 16, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase relative to detecting each of at least some of the timing signals.

[0130] Embodiment 18: The method of embodiment 17, wherein adjusting the sampling phase in association with detecting each of at least some of the timing signals includes adjusting the sampling phase in response to detecting each of at least some of the timing signals.

[0131] Embodiment 19: The method of any of embodiments 16 to 18, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase so that, for each of a plurality of time intervals during the flight measurement period, each sampling phase from a set of multiple sampling phases is used by the ADC in connection with detecting only the same number of timing signals.

[0132] Embodiment 20: The method of embodiment 19, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase so that, for each of a plurality of time intervals during the flight measurement period, each sampling phase from a set of multiple sampling phases is used by the ADC in connection with detecting only one respective timing signal.

[0133] Embodiment 21: The method of any of embodiments 16 to 20, wherein adjusting the sampling phase of the ADC includes adjusting the sampling phase so that, during the flight measurement period, each sampling phase from a set of multiple sampling phases is used by the ADC in connection with detecting at least X timing signals during the measurement procedure, and no sampling phase is used by the ADC in connection with detecting more than X+1 timing signals during the measurement procedure, where X is a suitable positive integer greater than 1.

[0134] Embodiment 22: The method of any of embodiments 16 to 21, wherein adjusting the sampling phase of the ADC includes at least adjusting the sampling phase by incrementing the sampling phase by the same amount in a modulo manner.

[0135] Embodiment 23: The method of any of embodiments 16 to 21, wherein adjusting the sampling phase of the ADC includes at least adjusting the sampling phase by decrementing the sampling phase by the same amount in a modulo fashion.

[0136] Embodiment 24: The method of any of embodiments 16 to 23, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase according to a repeating fixed sequence of different sampling phases.

[0137] Embodiment 25: The method of any of embodiments 16 to 21, wherein adjusting the sampling phase of the ADC comprises pseudo-randomly adjusting the sampling phase.

[0138] Embodiment 26: A method of any of embodiments 16 to 25, wherein the step of determining timing information includes: in the logic circuit, counting timing signals detected by the logic circuit, and in the first communication device, determining the period until the number of timing signals is detected; and the step of determining the time of flight includes determining the time of flight based on i) the number of timing signals and ii) the period.

[0139] Embodiment 27: The method of embodiment 26, wherein the step of determining the period includes a step of counting the number of cycles of the clock until the number of timing signals is detected; and the step of determining the time of flight includes a step of determining the time of flight based on i) the number of timing signals and ii) the number of cycles of the clock.

[0140] Embodiment 28: The method of any of embodiments 16 to 27, wherein the timing signal is a reverse timing signal, and wherein the method further comprises: generating, at the first communication device, an analog transmission signal including a plurality of forward timing signals; transmitting, by the first communication device, the analog transmission signal over a communication medium, wherein each forward timing signal prompts the second communication device to transmit a respective reverse timing signal.

[0141] Embodiment 29: A method of any of embodiments 16 to 28, further comprising: receiving, at the second communication device, a plurality of forward timing signals via a communication medium; detecting, at the second communication device, at least some forward timing signals of the plurality of forward timing signals; and transmitting, by the first communication device, a respective reverse timing signal in response to receiving each of the at least some forward timing signals.

[0142] Embodiment 30: A transceiver associated with a first communication device comprises: a forward signal generation circuit configured to generate a digital transmit signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal; a clock phase adjustment circuit configured to adjust a phase of a clock provided to the DAC relative to at least some of the forward timing signals, such that the DAC uses different phases of the clock when different ones of the forward timing signals are transmitted; a driver circuit configured to transmit the analog transmit signal over a communication medium, wherein each forward timing signal prompts a second communication device to transmit a respective reverse timing signal, and wherein the DAC's use of different phases of the clock when different ones of the forward timing signals are transmitted affects the timing of each transmission of each one of the reverse timing signals; an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over the communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of reverse timing signals from the second communication device based on analysis of the digital receive signal; a timing information determination circuit configured to determine timing information based on detection of the plurality of reverse timing signals; and a processor configured to determine a time of flight based on the timing information.

[0143] Embodiment 31: The transceiver of embodiment 30, wherein the clock phase adjustment circuit is configured to adjust a clock phase in association with the transceiver transmitting each of at least some of the forward timing signals.

[0144] Embodiment 32: The transceiver of embodiment 31, wherein the clock phase adjustment circuit is configured to adjust the clock phase in response to the transceiver transmitting each of at least some of the forward timing signals.

[0145] Embodiment 33: The transceiver of embodiment 30, wherein the clock phase adjustment circuit is configured to adjust the clock phase in association with the timing signal detection circuit detecting each of at least some of the reverse timing signals.

[0146] Embodiment 34: The transceiver of embodiment 33, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock in response to the timing signal detection circuit detecting each of at least some of the reverse timing signals.

[0147] Embodiment 35: A transceiver of any of embodiments 30 to 34, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock so that, for each of a plurality of time intervals during the flight measurement period, each phase from a set of multiple clock phases is used by the DAC in connection with transmitting only the same number of forward timing signals.

[0148] Embodiment 36: The transceiver of embodiment 35, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock so that, for each of a plurality of time intervals during the flight measurement period, each phase from a set of multiple clock phases is used by the DAC in connection with transmitting only one forward timing signal.

[0149] Embodiment 37: The transceiver of any of embodiments 30 to 36, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock so that, during the time of the flight measurement period, each clock phase from a set of multiple clock phases is used by the DAC in connection with transmitting at least X forward timing signals during the measurement procedure, and no clock phase is used by the DAC in connection with transmitting more than X+1 forward timing signals during the measurement procedure, where X is a suitable positive integer greater than 1.

[0150] Embodiment 38: The transceiver of any of embodiments 30 to 37, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock by at least incrementing the phase of the clock by the same amount in a modulo manner.

[0151] Embodiment 39: The transceiver of any of embodiments 30 to 37, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock by at least modulo decrementing the phase of the clock by the same amount.

[0152] Embodiment 40: The transceiver of any of embodiments 30 to 39, wherein the clock phase adjustment circuit is configured to adjust the phase of the clock according to a repeating fixed sequence of different clock phases.

[0153] Embodiment 41: The transceiver of any of embodiments 30 to 37, wherein the clock phase adjustment circuit is configured to pseudo-randomly adjust the phase of the clock.

[0154] Embodiment 42: A transceiver of any of embodiments 30 to 41, wherein the timing information determination circuit includes a counter configured to count the reverse timing signals detected by the timing signal detection circuit; and the processor is configured to: determine the period until the number of reverse timing signals is detected, and determine the time of flight based on i) the number and ii) the period of the reverse timing signals.

[0155] Embodiment 43: A transceiver of embodiment 42, wherein the counter is a first counter, and wherein: the processor includes a second counter configured to count the number of clock cycles until a number of reverse timing signals is detected, the number of clock cycles indicating a period; and the processor is configured to determine the time of flight based on i) the number of reverse timing signals and ii) the number of clock cycles.

[0156] Embodiment 44: A communication system comprising the transceiver of any one of embodiments 30 to 43, the communication system further comprising a second communication device.

[0157] Embodiment 45: A communication system including the transceiver of any one of embodiments 30 to 43 and / or the communication system of embodiment 44, the communication system further including a communication medium.

[0158] Embodiment 46: A method for measuring time of flight between a first communication device and a second communication device, the method comprising: generating, at the first communication device, a digital transmit signal including a plurality of forward timing signals; generating, at a digital-to-analog converter (DAC) of the first communication device, an analog transmit signal based on the digital transmit signal; adjusting, in logic circuitry of the first communication device, a phase of a clock provided to the DAC relative to at least some of the forward timing signals, so that the DAC is using different phases of the clock when different ones of the forward timing signals are transmitted; transmitting, by the first communication device, the analog transmit signal over a communication medium, wherein each forward timing signal transmits a respective reverse timing signal. the second communication device to transmit a signal to the DAC, wherein use of different phases of the clock when different ones of the forward timing signals are transmitted affects the timing of the transmission of each of the reverse timing signals; receiving, at the first communication device, an analog receive signal via a communication medium; converting, at an analog-to-digital converter (ADC) of the first communication device, the analog receive signal to a digital receive signal; detecting, at a logic circuit, a plurality of reverse timing signals from the second communication device based on analysis of the digital receive signal; determining, at the logic circuit, timing information based on the detection of the plurality of reverse timing signals; and determining, at the first communication device, a time of flight based on the timing information.

[0159] Embodiment 47: The method of embodiment 46, wherein adjusting the phase of the clock provided to the DAC includes adjusting the phase of the clock in relation to transmitting each of at least some of the forward timing signals.

[0160] Embodiment 48: The method of embodiment 47, wherein adjusting the phase of the clock provided to the DAC includes adjusting the phase of the clock in response to transmitting each of at least some of the forward timing signals.

[0161] Embodiment 49: The method of embodiment 46, wherein adjusting the phase of the clock provided to the DAC includes adjusting the phase of the clock in association with detecting each of at least some of the reverse timing signals.

[0162] Embodiment 50: The method of embodiment 49, wherein adjusting the phase of the clock in association with detecting each of at least some of the reverse timing signals includes adjusting the phase of the clock in response to detecting each of at least some of the reverse timing signals.

[0163] Embodiment 51: The method of any of embodiments 46 to 50, wherein the step of adjusting the clock phase includes a step of adjusting the clock phase so that, for each of a plurality of time intervals during the flight measurement period, each clock phase from a set of multiple clock phases is used by the DAC in connection with transmitting only the same number of forward timing signals.

[0164] Embodiment 52: The method of embodiment 51, wherein the step of adjusting the clock phase includes a step of adjusting the clock phase so that, for each of a plurality of time intervals during the flight measurement period, each clock phase from a set of multiple clock phases is used by the DAC in connection with transmitting only one forward timing signal.

[0165] Embodiment 53: The method of any of embodiments 46 to 52, wherein adjusting the clock phase includes adjusting the clock phase so that, during the flight measurement period, each clock phase from a set of multiple clock phases is used by the DAC in connection with transmitting at least X forward timing signals during the measurement procedure, and no clock phase is used by the DAC in connection with transmitting more than X+1 forward timing signals during the measurement procedure, where X is a suitable positive integer greater than 1.

[0166] Embodiment 54: The method of any of embodiments 46 to 53, wherein adjusting the phase of the clock includes at least adjusting the phase of the clock by incrementing the phase of the clock by the same amount in a modulo manner.

[0167] Embodiment 55: The method of any of embodiments 46 to 53, wherein adjusting the phase of the clock includes adjusting the phase of the clock by decrementing the phase of the clock by the same amount in a modulo fashion.

[0168] Embodiment 56: The method of any of embodiments 46 to 55, wherein adjusting the phase of the clock includes adjusting the phase of the clock according to a fixed sequence of repetitions of different sampling phases.

[0169] Embodiment 57: The method of any of embodiments 46 to 53, wherein adjusting the phase of the clock includes pseudo-randomly adjusting the phase of the clock.

[0170] Embodiment 58: A method of any of embodiments 46 to 57, wherein the step of determining timing information includes: in the logic circuit, counting the reverse timing signals detected by the logic circuit, and in the first communication device, determining the period until the number of reverse timing signals is detected; and the step of determining the time of flight includes determining the time of flight based on i) the number of reverse timing signals and ii) the period.

[0171] Embodiment 59: The method of embodiment 58, wherein the step of determining the period includes a step of counting the number of cycles of the clock until the number of reverse timing signals is detected; and the step of determining the time of flight includes a step of determining the time of flight based on i) the number of reverse timing signals and ii) the number of cycles of the clock.

[0172] Embodiment 60: A method of any of embodiments 46 to 59, further comprising: receiving, at a second communication device, a plurality of forward timing signals via a communication medium; detecting, at the second communication device, at least some forward timing signals of the plurality of forward timing signals; and transmitting, by the first communication device, a respective reverse timing signal in response to receiving each of the at least some forward timing signals.

[0173] Embodiment 61: A first communication device comprising a transceiver configured to perform any of the methods of embodiments 46 to 60.

[0174] Embodiment 62: A communication system comprising the first communication device of embodiment 61, the communication system further comprising a second communication device.

[0175] Embodiment 63: A communication system comprising the first communication device of embodiment 61 and / or the communication system of embodiment 62, the communication system further comprising a communication medium.

[0176] Embodiment 64: A first communication device comprising a transceiver configured to perform the method of any of embodiments 16 to 29.

[0177] Embodiment 65: A communication system comprising the first communication device of embodiment 64, the communication system further comprising a second communication device.

[0178] Embodiment 66: A communication system comprising the first communication device of embodiment 64 and / or the communication system of embodiment 65, the communication system further comprising a communication medium.

[0179] When implemented in hardware, the hardware may comprise one or more of discrete components, an integrated circuit, an application specific integrated circuit (ASIC), a programmable logic device (PLD), and so on.

[0180] While the present invention has been described with reference to particular examples, it is intended that they be illustrative only and not limiting, and that modifications, additions, and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received over the communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of timing signals from a second communication device based on an analysis of the digital received signal; a sampling phase generation circuit coupled to the ADC, the sampling phase generation circuit configured to adjust the sampling phase used by the ADC relative to at least some of the timing signals, such that when different ones of the timing signals are detected, the ADC is using different sampling phases; a timing information determination circuit configured to determine timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and a processor configured to determine a time of flight based on the timing information. a transceiver associated with the first communication device,

2. 2. The transceiver of claim 1, wherein the sampling phase generation circuitry is configured to adjust the sampling phase in relation to detecting each of the at least some of the timing signals.

3. 3. The transceiver of claim 2, wherein the sampling phase generation circuit is configured to adjust the sampling phase in response to detecting each of the at least some of the timing signals.

4. the timing information determination circuit includes a counter configured to count the timing signals detected by the timing signal detection circuit; The processor: determining a period of time until a number of timing signals are detected; and determining the time of flight based on i) the number of timing signals, and ii) the period; The transceiver of claim 1 , configured to:

5. The counter is a first counter, where: the processor includes a second counter configured to count a number of cycles of a clock until the number of timing signals is detected, the number of cycles of the clock indicating the period; and the processor is configured to determine the time-of-flight based on i) the number of timing signals, and ii) the number of cycles of the clock.

5. The transceiver of claim 4.

6. The timing signal is a reverse timing signal, wherein the transceiver further comprises: generating an analog transmit signal including a plurality of forward timing signals; and transmitting the analog transmit signal over the communications medium, wherein each forward timing signal prompts the second communications device to transmit a respective reverse timing signal; 10. The transceiver of claim 1, comprising a transmitter circuit configured to:

7. 1. A method for measuring a time of flight between a first communication device and a second communication device, comprising: receiving, at the first communication device, an analog receive signal via a communication medium; converting the analog receive signal to a digital receive signal in an analog-to-digital converter (ADC) of the first communication device; detecting, in logic circuitry of the first communication device, a plurality of timing signals from the second communication device based on analysis of the digital received signal; adjusting, in the logic circuit, a sampling phase of the ADC relative to at least some of the timing signals, so that when different ones of the timing signals are detected, the ADC is using different sampling phases; determining, in the logic circuit, timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected; and determining, at the first communication device, the time of flight based on the timing information; A method for providing the above.

8. 8. The method of claim 7, wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase relative to detecting each of the at least some of the timing signals.

9. 9. The method of claim 8, wherein adjusting the sampling phase in association with detecting each of the at least some of the timing signals comprises adjusting the sampling phase in response to detecting each of the at least some of the timing signals.

10. The step of determining timing information comprises: in the logic circuit, counting timing signals detected by the logic circuit; and determining, at the first communication device, a period of time until a number of timing signals are detected; Including; determining the time-of-flight includes determining the time-of-flight based on i) the number of timing signals, and ii) the period. The method of claim 7.

11. determining the period includes counting cycles of a clock until the number of timing signals is detected; determining the time of flight includes determining the time of flight based on i) the number of timing signals, and ii) the number of cycles of the clock. The method of claim 10.

12. The timing signal is an inverse timing signal, and the method further comprises: generating, at the first communication device, an analog transmit signal including a plurality of forward timing signals; transmitting, by the first communication device, the analog transmit signal over the communication medium, wherein each forward timing signal prompts the second communication device to transmit a respective reverse timing signal; The method of claim 7, comprising:

13. a forward signal generation circuit configured to generate a digital transmit signal including a plurality of forward timing signals; a digital-to-analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal; a clock phase adjustment circuit configured to adjust the phase of a clock provided to the DAC relative to at least some of the forward timing signals, such that the DAC is using different phases of the clock when different ones of the forward timing signals are transmitted; a driver circuit configured to transmit the analog transmit signal over a communications medium, wherein each forward timing signal prompts a second communications device to transmit a respective reverse timing signal, and wherein the use by the DAC of the different phases of the clock when different ones of the forward timing signals are transmitted affects the timing of the transmission of each respective one of the reverse timing signals; an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received via the communication medium; a timing signal detection circuit coupled to the ADC, the timing signal detection circuit configured to detect a plurality of reverse timing signals from the second communication device based on an analysis of the digital received signal; a timing information determination circuit configured to determine timing information based on the detection of the plurality of reverse timing signals; and a processor configured to determine a time of flight based on the timing information a transceiver associated with the first communication device, the transceiver comprising:

14. 14. The transceiver of claim 13, wherein the clock phase adjustment circuitry is configured to adjust the phase of the clock in relation to the transceiver transmitting each of the at least some of the forward timing signals.

15. 15. The transceiver of claim 14, wherein the clock phase adjustment circuitry is configured to adjust the phase of the clock in response to the transceiver transmitting each of the at least some of the forward timing signals.

16. 14. The transceiver of claim 13, wherein the clock phase adjustment circuitry is configured to adjust the phase of the clock in association with the timing signal detection circuitry detecting each of at least some of the reverse timing signals.

17. 17. The transceiver of claim 16, wherein the clock phase adjustment circuitry is configured to adjust the phase of the clock in response to the timing signal detection circuitry detecting each of at least some of the reverse timing signals.

18. the timing information determination circuit includes a counter configured to count the reverse timing signals detected by the timing signal detection circuit; The processor: determining the period until the number of reverse timing signals is detected; and determining the time of flight based on i) the number of reverse timing signals, and ii) the period; 14. The transceiver of claim 13, configured to:

19. The counter is a first counter, where: the processor includes a second counter configured to count a number of cycles of the clock until the number of reverse timing signals is detected, the number of cycles of the clock indicating the period; the processor is configured to determine the time-of-flight based on i) the number of reverse timing signals, and ii) the number of cycles of the clock.

20. The transceiver of claim 18.

20. 1. A method for measuring a time of flight between a first communication device and a second communication device, the method comprising: generating, at the first communication device, a digital transmit signal including a plurality of forward timing signals; generating an analog transmit signal based on the digital transmit signal in a digital-to-analog converter (DAC) of the first communication device; adjusting, in logic circuitry of the first communication device, a phase of a clock provided to the DAC relative to at least some of the forward timing signals, so that the DAC is using different phases of the clock when different ones of the forward timing signals are transmitted; transmitting, by the first communication device, the analog transmit signal over a communication medium, wherein each forward timing signal prompts the second communication device to transmit a respective reverse timing signal, and wherein the use by the DAC of the different phases of the clock when different ones of the forward timing signals are transmitted affects the timing of the transmission of each respective one of the reverse timing signals; receiving, at the first communication device, an analog receive signal via the communication medium; converting the analog receive signal to a digital receive signal in an analog-to-digital converter (ADC) of the first communication device; detecting, in the logic circuit, a plurality of reverse timing signals from the second communication device based on analysis of the digital received signal; determining timing information in the logic circuit based on the detection of the plurality of inverse timing signals; and determining, at the first communication device, the time of flight based on the timing information; A method for providing the above.

21. 21. The method of claim 20, wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock relative to transmitting each of the at least some of the forward timing signals.

22. 22. The method of claim 21 , wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in response to transmitting each of the at least some of the forward timing signals.

23. The step of determining timing information comprises: in the logic circuit, counting the reverse timing signals detected by the logic circuit; and determining, at the first communication device, a period of time until a number of reverse timing signals are detected; Including; determining the time of flight includes determining the time of flight based on i) the number of reverse timing signals, and ii) the period.

21. The method of claim 20.

24. determining the period includes counting cycles of the clock until the number of reverse timing signals is detected; determining the time of flight includes determining the time of flight based on i) the number of reverse timing signals, and ii) the number of cycles of the clock.

24. The method of claim 23.

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