Systems and methods for fast control of impedance associated with the output of a plasma source

Abstract

Systems and methods are described for fast control of impedance associated with the output of a plasma source. One system includes a plasma source generating a radio frequency (RF) signal. The system further includes a load coupled to the plasma source via an RF connection. The RF connection has a point. The system further includes an adjustable impedance matching section coupled to the point between the plasma source and the load. The adjustable impedance matching section includes a dependent voltage source and a circuit network. The dependent voltage source is coupled in series with the circuit network. The adjustable impedance matching section modifies the impedance of the RF signal and outputs the modified RF signal, which is provided to the load.

Description

[Technical Field]

[0001] The present embodiments relate to a system and method for fast control of the impedance associated with the output of a plasma source. [Background technology]

[0002] In a plasma tool, there is a radio frequency (RF) generator. The RF generator is coupled to a plasma chamber through a matching section. A wafer is placed in the plasma chamber for processing. The RF generator generates an RF signal and feeds the RF signal to the matching section. The matching section matches the output impedance to the input impedance and outputs the RF signal to the plasma chamber. The RF signal is used to generate a plasma for processing the wafer. However, operating the RF generator or the matching section in a desired manner can be difficult.

[0003] The background description provided herein is intended to present the contents of the present disclosure generally. Work by the presently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004]

[0006] Embodiments of the present disclosure provide systems, apparatus, methods, and computer programs for fast control of impedance associated with the output of a plasma source. It should be appreciated that the embodiments can be implemented in various ways, such as a process, an apparatus, a system, a device, or a method on a computer-readable medium. Some embodiments are described below.

[0005] In one embodiment, the effective impedance of an inductor-capacitor (LC) network changes rapidly depending on the gain of a dependent voltage source (DVS). An example of effective impedance is the impedance seen from the perspective of the DVS.

[0006] In one embodiment, an alternating current (AC) voltage source such as a DVS represents a switch-mode inverter, e.g., a power amplifier. In the case of zero voltage switching (ZVS), the switch-mode inverter drives a resistive or inductive impedance.

[0007] In one embodiment, an adjustable impedance matching section is provided. The adjustable impedance matching section enables high-speed impedance matching for a radio frequency (RF) generator driving a variable plasma load. To achieve high-speed impedance matching, the variable plasma load impedance is matched to a desired impedance (50 ohms). The adjustable impedance matching section augments or replaces an impedance matching circuit that includes one or more mechanically variable vacuum capacitors, each adjusted by a stepper motor. The impedance matching circuit operates on a time scale of one millisecond or longer to complete impedance adjustment. The adjustable impedance matching section can complete impedance adjustments, such as impedance matching, on a time scale of tens of microseconds. This microsecond time scale is used to track plasma load variations during capacitively coupled (E-mode) strikes, capacitively coupled to inductively coupled transitions (E-to-H transitions), and many other plasma load variations encountered during semiconductor wafer processing. This order-of-magnitude improvement in adjustment speed improves RF power system performance.

[0008] In one embodiment, an adjustable impedance matching section is provided, which includes one or more dependent voltage sources connected to an inductor-capacitor (LC) network. The adjustable impedance matching section includes a dependent voltage source that includes a half-bridge direct current-to-RF (DC-RF) inverter. The half-bridge DC-RF inverter drives a series inductor of the adjustable impedance matching section. In this configuration, the apparent inductance seen from the end of the series inductor is inversely proportional to the voltage gain of the dependent voltage source. Therefore, the apparent inductance can be modified by varying the voltage gain of the dependent voltage source. In a practical circuit implementation, the voltage gain variation is achieved by a half-bridge DC-RF inverter powered by a variable DC supply voltage (also known as an agile rail) or by outphasing control, which is phase control.

[0009] In one embodiment, a system for fast control of impedance associated with an output of a plasma source is described. The system includes a plasma source generating an RF signal. The system further includes a load coupled to the plasma source via an RF connection. The RF connection has a point. The system further includes an adjustable impedance matching section coupled to the point between the plasma source and the load. The adjustable impedance matching section includes a dependent voltage source and a circuit network. The circuit network includes a capacitor or an inductor or a combination thereof. The dependent voltage source is coupled in series with the circuit network. The adjustable impedance matching section modifies the impedance of the RF signal and outputs the modified RF signal, and the modified RF signal is provided to the load.

[0010] In one embodiment, a system for controlling impedance associated with an output of a plasma source is described. The system includes a plasma source generating an RF signal and a load coupled to the plasma source via an RF connection. The RF connection has a point. The system further includes a plurality of adjustable impedance matching sections coupled to the point between the plasma source and the load. The plurality of adjustable impedance matching sections includes a first adjustable impedance matching section and a second adjustable impedance matching section. The first adjustable impedance matching section includes a first dependent voltage source and a first circuit network. The second adjustable impedance matching section includes a second dependent voltage source and a second circuit network. The first circuit network includes a first capacitor or a first inductor, or a combination thereof. The first dependent voltage source is coupled in series with the first circuit network. The second circuit network includes a second capacitor or a second inductor, or a combination thereof. The second dependent voltage source is coupled in series with the second circuit network. The plurality of adjustable impedance matching sections modify the impedance of the RF signal and output the modified RF signal. The modified RF signal is provided to a load.

[0011] In one embodiment, a system for controlling the impedance associated with an output of an RF generator is described. The system includes an RF generator that generates an RF signal and an adjustable impedance match that is coupled to the RF generator via an RF cable and receives the RF signal. The adjustable impedance match includes a dependent voltage source. The adjustable impedance match modifies the impedance of the RF signal and outputs the modified RF signal. The system includes a load that is coupled to the adjustable impedance match via an RF transmission line and receives the modified RF signal.

[0012] Some advantages of the systems and methods described herein for fast control of impedance associated with the output of a plasma source include quickly modifying the impedance of an RF signal generated by the plasma source. An adjustable impedance matching section is provided. The adjustable impedance matching section includes a direct current (DC) voltage source and a plurality of pulse signal sources. The DC voltage of the DC voltage source, or the phase of the pulse signal generated by the pulse signal source, or a combination thereof, is modified to output a modified waveform. The modified waveform quickly and efficiently modifies the impedance of the RF signal generated by the plasma source. The impedance is modified quickly compared to when an impedance matching circuit having only mechanical components is used.

[0013] The systems and methods described herein potentially reduce system complexity and construction costs because two power transistors are used to implement an adjustable impedance matching section. Furthermore, the reactance can be continuously adjusted, enabling precise impedance matching. Compared to mechanically variable vacuum capacitors, the systems and methods increase impedance adjustment speed by more than 100 times. This faster adjustment speed significantly reduces the RF generator's operating time under undesirable mismatched impedance conditions, thereby improving RF system reliability. Furthermore, accurate, real-time tracking of RF power system plasma load fluctuations enables the development of new semiconductor processes that are currently underexplored due to their slow impedance adjustment speed.

[0014] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0015] The embodiments can be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0016] [Figure 1]FIG. 1 is a diagram of one embodiment of a system illustrating the use of an adjustable impedance match.

[0017] [Figure 2] FIG. 2 is a diagram of one embodiment of a dependent voltage source (DVS).

[0018] [Figure 3A] FIG. 3A is a diagram of one embodiment of a system illustrating an inductor-capacitor (LC) network.

[0019] [Figure 3B] FIG. 3B is a diagram of an embodiment of a system illustrating another LC network.

[0020] [Figure 3C] FIG. 3C is a diagram of an embodiment of a system illustrating yet another LC network.

[0021] [Figure 3D] FIG. 3D is a diagram of an embodiment of a system illustrating yet another LC network.

[0022] [Figure 3E] FIG. 3E is a diagram of an embodiment of a system illustrating another LC network.

[0023] [Figure 3F-1] FIG. 3F-1 is a diagram of one embodiment of a system illustrating multiple adjustable impedance matching sections.

[0024] [Figure 3F-2] FIG. 3F-2 is a diagram of one embodiment of a system illustrating details of the DVS of FIG. 3F-1.

[0025] [Figure 4A] FIG. 4A is a diagram of one embodiment of a system illustrating the use of multiple DVSs within a matching section.

[0026] [Figure 4B] FIG. 4B is a diagram of an embodiment of a system illustrating the use of multiple DVSs within another matching section.

[0027] [Figure 5] FIG. 5 is a diagram of one embodiment of a system illustrating the use of a DVS and LC network with mechanical components in a hybrid matching section.

[0028] [Figure 6] FIG. 6 is a diagram of one embodiment of a graph illustrating the operation of a hybrid matching section. DETAILED DESCRIPTION OF THE INVENTION

[0029] In the following embodiments, systems and methods for fast control of impedance associated with the output of a plasma source are described. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail so as not to unnecessarily obscure the embodiments.

[0030] 1 is a diagram of an embodiment of a system 100 illustrating the use of an adjustable impedance matching section 102. The system 100 includes the adjustable impedance matching section 102, a host computer 104, a plasma source 106, and a load 108. Examples of a host computer, as used herein, include a desktop computer, a controller, a laptop computer, a tablet, and a smartphone.

[0031] The plasma source 106 may include a combination of a matchless plasma source and a reactive circuit, or may include a radio frequency (RF) generator. Examples of reactive circuits include a capacitor and an inductor. For example, the reactive circuit may include a single capacitor or a single inductor. The reactive circuit is coupled to the matchless plasma source. When the plasma source 106 is a matchless plasma source or an RF generator, there is no matching section, such as an impedance matching circuit or impedance matching network, other than the adjustable impedance matching section 102 between the plasma source 106 and the load 108, and the load 108 includes a plasma chamber.

[0032] The host computer 104 includes a processor 110 and a memory device 112. By way of example, the processor 110 is an application specific integrated circuit (ASIC), a central processing unit (CPU), a field programmable gate array (FPGA), a microprocessor, a programmable logic device (PLD), an integrated controller, or a microcontroller. Examples of the memory device 112 include read-only memory (ROM) and random access memory (RAM). Illustratively, the memory device 112 is a flash memory or a redundant array of independent disks (RAID). The processor 110 is coupled to the memory device 112.

[0033] The adjustable impedance matching section 102 includes an inductor-capacitor (LC) network 114 and a dependent voltage source (DVS) 116. The processor 110 is coupled to the plasma source 106 and the DVS 116. The dependent voltage source 116 is coupled to the LC network 114, which is coupled to a point P1 on an RF connection 118. The RF connection 118 couples the output 107 of the plasma source 106 to the input 133 of the load 108.

[0034] Point P1 is located between the plasma source 106 and the load 108. For example, point P1 is located between the output 107 and the input 133. One example of point P1 is a connector connecting the RF connection 118 to the RF connection 130. Another example of point P1 is a soldered connection between the RF connections 118 and 130. One example of the RF connection 118 includes one or more conductors for transferring an RF signal when the plasma source 106 is a matchless plasma source. When the plasma source 106 is a matchless plasma source, the RF connection 118 does not include a 50-ohm RF cable. Another example of the RF connection 118 includes a 50-ohm RF cable when the plasma source 106 is an RF generator. Yet another example of the RF connection 118 includes a combination of a 50-ohm RF cable and an RF transmission line. Illustratively, the RF connection 118 includes a 50-ohm RF cable from the output 107 to point P1 and an RF transmission line from point P1 to the electrode. RF transmission lines are discussed further below.

[0035] The processor 110 is coupled to the plasma source 106 and the DVS 116. For example, the processor is coupled to the plasma source 106 via a transfer cable 123 and to the DVS 116 via another transfer cable 126. Examples of transfer cables, as used herein, include a cable for transferring data in a serial manner, a cable for transferring data in a parallel manner, and a cable for transferring data using the Universal Serial Bus (USB) protocol. The DVS 116 is coupled to the LC network 114 via an RF connection 128, which is coupled in series with the RF connection 128, and the LC network is coupled to point P1 via an RF connection 130.

[0036] The processor 110 controls the plasma source 106 to generate an RF signal 120 and supply the RF signal 120 to the load 108. For example, the processor 110 transmits the phase, frequency, and voltage amplitude of the RF signal 120 to the plasma source 106 via a transmission cable 123. Upon receiving the phase, frequency, and amplitude, the plasma source 106 generates the voltage of the RF signal 120 having the phase, frequency, and amplitude. When the RF signal 120 is generated, the voltage at the output 107 of the plasma source 106 relative to ground potential is V A For example, the voltage of the RF signal 120 is V A is.

[0037] Furthermore, the processor 110 controls the DVS 116 to generate a square waveform 122 at a high frequency. Also, by controlling the DVS 116, high-speed control of the impedance of the square waveform 122 output from the DVS 116 is achieved. The DVS 116 generates the square waveform 122 and supplies the square waveform 122 to the LC network 114. The LC network 114 modifies the impedance of the square waveform 122 to output a modified waveform 124, and provides the modified waveform 124 to point P1. The LC network 114 includes only electronic components, such as one or more electronic inductors, one or more electronic capacitors, or a combination thereof, to achieve high-speed control, such as modification of the square waveform 122, and output the modified waveform 124. Examples of electronic components are provided below. The modified waveform 124 has a sinusoidal shape at a high frequency. When the square waveform 122 is generated, the voltage at or output from the DVS 116 relative to ground potential is V B For example, the voltage of the square waveform 122 is V B is.

[0038] Modified waveform 124 is combined with RF signal 120 at point P1 to generate RF signal 132, which is provided to load 108 for processing a semiconductor substrate, such as a wafer, in a plasma chamber. For example, the power of RF signal 120 is summed with the power of modified waveform 124 to output the power of RF signal 132.

[0039] The RF signal 132 is transferred to an electrode, such as an RF coil or upper electrode or electrostatic chuck (ESC) of the plasma chamber via RF connection 118. If the plasma chamber is a capacitively coupled plasma (CCP) chamber, the plasma chamber includes an upper electrode and an ESC. If the plasma chamber is an inductively coupled plasma (ICP) chamber, the plasma chamber includes an RF coil and an ESC.

[0040] It should be noted that if the load 108 is resistive or inductive, the processor 110 controls the DVS 116 to remain off, e.g., in an inoperative state, or substantially off. For example, the processor may control the DVS 116 to supply a voltage V of 0 volts. B As another example, the processor may control the DVS116 to output a voltage V within a predetermined range, such as 5% to 10%, of 0 volts, so that the DVS116 remains essentially off. B Also, when the DVS 116 is substantially off or turned off, the processor 110 controls the plasma source 106 to provide the RF signal 120 to the load 108. The RF signal 108 provides a majority of the current to the load 108. On the other hand, if the load 108 is resistive or capacitive, the processor 110 controls the DVS 116 to remain on, e.g., in an operable state, and provide a majority of the capacitive current. For example, the processor controls the DVS 116 to provide a voltage V that is greater than a predetermined range from 0 volts. B Additionally, when DVS 116 is on, processor 110 controls plasma source 106 to provide a majority of resistive current. For example, processor 110 controls plasma source 106 to generate RF signal 120 having a majority of resistive current.

[0041] FIG. 2 is a diagram of one embodiment of the DVS 116. The DVS 116 includes a direct current (DC) voltage source 200, a capacitor 202, a pulse signal source 204, another pulse signal source 206, and a half-bridge circuit (HBC) 208. The half-bridge circuit, also referred to herein as a half-bridge DC-RF inverter, is an example of an inverter circuit. As used herein, an example of a pulse signal source is a digital pulse signal source such as a clock oscillator. The HBC 208 includes a transistor 210, another transistor 212, a diode D1, and another diode D2. Each of the transistors 210 and 212 is a metal-oxide semiconductor field-effect transistor (MOSFET). Each of the transistors 210 and 212 has a gate (G), a source (S), and a drain (D).

[0042] One end of DC voltage source 200 is coupled to transmission cable 126, to capacitor 202 via point 219, and to the drain of transistor 210 via point 219. The other end of DC voltage source 200 is coupled to ground potential. One end of capacitor 202 is coupled to DC voltage source 200 via point 219, and the other end is coupled to ground potential.

[0043] The source of transistor 210 is coupled to output O1, which is coupled to RF connection 128. Output O1 is coupled to the drain of transistor 212, and the source S of transistor 212 is coupled to ground potential. DC voltage source 200, capacitor 202, and HBC 208 are coupled to each other at the same point 219 and to ground potential, such that DC voltage source 200, capacitor 202, and HBC 208 are coupled to each other in parallel. Pulse signal source 204 is coupled to processor 110 (FIG. 1) via transfer cable 214 and to the gate of transistor 210. Pulse signal source 206 is also coupled to processor 110 via transfer cable 216 and to the gate of transistor 212.

[0044] The processor 110 controls the pulse signal source 204 to generate the pulse signal 1. For example, the processor 110 provides the frequency, phase, and duty cycle to the pulse signal source 204 via the transmission cable 214. Upon receiving the frequency, phase, and duty cycle, the pulse signal source 204 generates the pulse signal 1 having the duty cycle, phase, and frequency and sends the pulse signal 1 to the gate of the transistor 210.

[0045] Similarly, upon receiving the duty cycle, phase, and frequency from processor 110 via transmission cable 216, pulse signal source 206 generates pulse signal 2 having the duty cycle, phase, and frequency. Processor 110 controls pulse signal 2 so that it is inversely synchronized with pulse signal 1. For example, processor 110 sets the phase of pulse signal 2 to be 180 degrees out of phase with pulse signal 1. The phase of pulse signal 2 is provided to pulse signal source 206. Pulse signal 2 is sent from pulse signal source 206 to the gate of transistor 212.

[0046] The processor 110 controls the DC voltage source 202 to adjust the amplitude V of the voltage signal 218. DC For example, the processor 110 controls the amplitude V DC is provided to the DC voltage source 202. DC Upon receiving the voltage, the DC voltage source 200 generates a voltage of amplitude V DC A capacitor 202 filters the alternating current (AC) signal from the voltage signal 218 and provides a voltage signal 220 to the drain of the transistor 210.

[0047] The voltage signal 220 has substantially the same amplitude, e.g., the same amplitude, as the voltage signal 218. For example, the voltage signal 220 has an amplitude V DC As another example, the voltage signal 220 may have an amplitude V DCand the amplitude of the filtered AC signal. When voltage signal 220 is provided to transistor 210, transistors 210 and 212 operate in push-pull mode based on pulse signals 1 and 2 to provide square waveform 122 at output O1. For example, in push-pull mode, when transistor 210 is on, transistor 212 is off, and when transistor 210 is off, transistor 212 is on. The voltage of square waveform 122 at output O1 is V B is.

[0048] Each diode D1 and D2 protects the respective transistor 210 and 212 from excessive voltage. For example, diode D1 protects transistor 210 by acting as a short circuit when the voltage across transistor 210 exceeds a predetermined threshold of diode D1.

[0049] Note that to achieve zero voltage switching (ZVS), the impedance from output O1 to point P1 and load 108 (FIG. 1) is either resistive or inductive.

[0050] In one embodiment, the DVS 116 does not include the capacitor 202 .

[0051] 3A is a diagram of one embodiment of a system 300 illustrating an LC network 302. The LC network 302 is an example of the LC network 114 (FIG. 1). The system 300 includes a circuit 301 including the DVS 116 and the LC network 302. The LC network 302 includes an inductor 304 having an inductance L0. The DVS 116 is coupled to the inductor 304 via the RF connection 128. The inductor 304 is coupled to the RF connection 130. The DVS 116 generates the square waveform 122 and transmits the square waveform 122 to the inductor 304. The inductor 304 reduces (e.g., removes) harmonic frequencies of the square waveform 122 and outputs a modified waveform 305, which is an example of the modified waveform 124 (FIG. 1).

[0052] The amplitude V of the voltage signal 218 (Figure 2) DC For example, the processor 110 (FIG. 1) controls the amplitude V provided to the DC voltage source 200 (FIG. 2). DC , for example by increasing or decreasing the amplitude V of the voltage signal 218. DC Increase or decrease the amplitude V DC is increased for increasing values ​​of the variable k, and is decreased for decreasing values ​​of the variable k.

[0053] Additionally, processor 110 controls the phase of pulse signals 1 and 2 (FIG. 2) to increase or decrease the value of variable k. For example, processor 110 may provide the phase of pulse signals 1 and 2 to pulse signal sources 204 and 206 (FIG. 2) to control voltage V A and increases the value of variable k. The processor 110 provides the phases of pulse signals 1 and 2 to pulse signal sources 204 and 206 to generate voltages V A Delay the phase of and decrease the value of variable k. DC or by controlling the phase of pulse signals 1 and 2, or by controlling the amplitude V DC By controlling the amplitude V and controlling the phase of pulse signals 1 and 2, the variable k can be quickly and efficiently controlled, e.g., modified. By modifying the variable k, the impedance of square waveform 122 is quickly modified, which modifies the impedance of modified waveform 305. Also, the amplitude V DC By controlling the control of and / or the phase of pulse signals 1 and 2 to output modified waveform 305, the impedance of RF signal 120 (FIG. 1) is rapidly modified by modified waveform 305 to modify the impedance of RF signal 132 (FIG. 1).

[0054] When the LC network 302 includes an inductor 304, the variable k is B and V A is the negative value of the ratio between V and V, and k is greater than or equal to 0. B =-kV A, k≧0. By controlling the value of the variable k, for example by increasing or decreasing it, the voltage V B For example, when the value of the variable k increases, the voltage V B As the amplitude of decreases and the value of variable k decreases, the voltage V B The amplitude of increases. Circuit 301 is equivalent to another circuit 306 having an inductance L0 in parallel with an inductance L0 / k. Note that the impedance seen by the DVS 116 is inductive. For example, the impedance seen by the DVS 116 is purely inductive to achieve ZVS.

[0055] In one embodiment, DVS 116 (FIG. 2) does not include DC voltage source 200 (FIG. 2). In an embodiment, capacitor 202 is included. Also, in an embodiment, processor 110 modifies variable k by controlling the phase of pulse signals 1 and 2 in the manner described herein. To control variable k, DC voltage source 200 is not controlled.

[0056] In one embodiment, processor 110 modifies variable k by controlling DC voltage source 200 in the manner described herein. In an embodiment, variable k is not controlled by controlling the phase of pulse signals 1 and 2.

[0057] 3B is a diagram of one embodiment of a system 320 illustrating an LC network 322. The LC network 322 is an example of the LC network 114 (FIG. 1). The system 320 includes a circuit 324 including the DVS 116 and the LC network 322. The LC network 322 includes a capacitor 326 having a capacitance C0. The DVS 116 is coupled to the capacitor 326 via the RF connection 128. The capacitor 326 is coupled to the RF connection 130. The DVS 116 generates the square waveform 122 and transmits the square waveform 122 to the capacitor 326. The capacitor 326 reduces (e.g., removes) harmonic frequencies of the square waveform 122 and outputs a modified waveform 328, which is an example of the modified waveform 124 (FIG. 1).

[0058] amplitude VDC or by controlling the phase of pulse signals 1 and 2, or by controlling the amplitude V DC By controlling the amplitude V and the phase of pulse signals 1 and 2, the variable k is quickly and efficiently controlled. By modifying the variable k, the impedance of square waveform 122 is quickly modified, which in turn modifies the impedance of modified waveform 328, and so on. DC and / or by controlling the phase of pulse signals 1 and 2 to output modified waveform 328, the impedance of RF signal 120 (FIG. 1) is rapidly modified by modified waveform 328, which modifies the impedance of RF signal 132 (FIG. 1).

[0059] When the LC network 322 includes the capacitor 326, the variable k is B and V A where k is between 0 and 1. For example, V B =kV A , 0≦k≦1. By controlling the value of the variable k, such as by increasing or decreasing it, the voltage V B For example, when the value of the variable k increases, the voltage V B As the amplitude of increases and the value of variable k decreases, the voltage V B The circuit 324 is equivalent to another circuit 330 having a capacitance C0 in parallel with an inductance L0 / k.

[0060] Note that the impedance from the perspective of the DVS 116 is inductive, e.g., only inductive or purely inductive. For example, the voltage V B The phase of the current I B The current I B is the voltage V B In high power plasma applications, the voltage V B The phase of the current I B , power dissipation in transistors 210 and 212 (FIG. 2) is reduced and ZVS is achieved.

[0061] 3C is a diagram of one embodiment of a system 340 illustrating an LC network 342. The LC network 342 is an example of the LC network 114 (FIG. 1). The system 340 includes a circuit 344 that includes the DVS 116 and the LC network 342. The LC network 342 includes a capacitor 346 having a capacitance C, an inductor 350 having an inductance L, and another capacitor 348 having a capacitance C. The LC network 342 is a CLC T-network immittance converter.

[0062] DVS 116 is coupled to capacitor 346 via RF connection 128. Capacitor 346 is coupled to inductor 350 and capacitor 348. Capacitor 348 is coupled to RF connection 130. DVS 116 generates square waveform 122 and sends square waveform 122 to LC network 342. LC network 342 reduces (e.g., removes) harmonic frequencies of square waveform 122 and outputs modified waveform 352, which is an example of modified waveform 124 (FIG. 1).

[0063] amplitude V DC or by controlling the phase of pulse signals 1 and 2, or by controlling the amplitude V DC By controlling the amplitude V and the phase of pulse signals 1 and 2, the variable k is efficiently and quickly modified. By modifying the variable k, the impedance of square waveform 122 is quickly modified, which modifies the impedance of modified waveform 352. DC By controlling the phase of pulse signals 1 and 2 to control the impedance of correction waveform 352, the impedance of RF signal 120 (FIG. 1) is rapidly modified by correction waveform 352 to control the impedance of RF signal 132 (FIG. 1).

[0064] When the LC network 342 is used, the variable k is B and V A where k is greater than 0. For example, VB =kV A , k>0. By controlling the value of the variable k, such as by increasing or decreasing it, the voltage V B For example, when the value of the variable k increases, the voltage V B As the amplitude of increases and the value of variable k decreases, the voltage V B The amplitude of decreases. Circuit 344 is equivalent to another circuit 354 with inductance L / k. Note that the impedance seen from the perspective of DVS 116 towards point P1 is inductive to achieve ZVS.

[0065] In one embodiment, capacitor 346 has a different capacitance than capacitor 348 .

[0066] 3D is a diagram of one embodiment of a system 341 illustrating an LC network 343. The LC network 343 is an example of the LC network 114 (FIG. 1). The system 341 includes a circuit 345 that includes the DVS 116 and the LC network 343. The LC network 343 includes an inductor 347 having an inductance L, a capacitor 349 having a capacitance C, and another inductor 351 having an inductance L. The LC network 343 is an LCL T-network immittance converter.

[0067] DVS 116 is coupled to inductor 347 via RF connection 128. Inductor 347 is coupled to capacitor 349 and inductor 351. Inductor 351 is coupled to RF connection 130. DVS 116 generates square waveform 122 and sends square waveform 122 to LC network 343. LC network 343 reduces (e.g., removes) harmonic frequencies of square waveform 122 and outputs modified waveform 353, which is an example of modified waveform 124 (FIG. 1).

[0068] amplitude V DC or by controlling the phase of pulse signals 1 and 2, or by controlling the amplitude V DCBy controlling the amplitude V and the phase of pulse signals 1 and 2, the variable k is efficiently and quickly modified. By modifying the variable k, the impedance of square waveform 122 is quickly modified, which modifies the impedance of modified waveform 353. DC By controlling the impedance of RF signal 120 (FIG. 1) rapidly by controlling the phase of pulse signals 1 and 2, and / or by controlling the phase of pulse signals 1 and 2 to modify the impedance of modification waveform 353, the impedance of RF signal 120 (FIG. 1) is rapidly modified by modification waveform 353 to control the impedance of RF signal 132 (FIG. 1).

[0069] When an LC network 343 is used, the variable k is B and V A is the negative value of the ratio between V and V, and k is greater than 0. For example, V B =-kV A , k>0. By controlling the value of the variable k, such as by increasing or decreasing it, the voltage V B For example, when the value of the variable k increases, the voltage V B As the amplitude of decreases and the value of variable k decreases, the voltage V B The circuit 341 is equivalent to another circuit 355 with an inductance L0 / k.

[0070] In one embodiment, inductor 347 has a different inductance than inductor 351 .

[0071] 3E is a diagram of one embodiment of a system 360 illustrating an LC network 362. The LC network 362 is an example of the LC network 114 (FIG. 1). The system 360 includes a circuit 364 that includes the DVS 116 and the LC network 362. The LC network 362 includes an inductor 366 having an inductance L0, an inductor 368 having an inductance L1, another inductor 370 having an inductance L1, and a capacitor 372 having a capacitance C1. The inductors 368 and 370 and the capacitor 372 form an LCL T-network immittance converter 374.

[0072] DVS 116 is coupled to inductor 366 via RF connection 128. Inductor 366 is coupled to inductor 368, which is coupled to inductor 370 and capacitor 372. Inductor 370 is coupled to RF connection 130. DVS 116 generates square waveform 122 and sends square waveform 122 to LC network 362. LC network 362 reduces (e.g., removes) harmonic frequencies of square waveform 122 and outputs modified waveform 376, which is an example of modified waveform 124 (FIG. 1).

[0073] amplitude V DC or by controlling the phase of pulse signals 1 and 2, or by controlling the amplitude V DC By controlling the amplitude V and the phase of pulse signals 1 and 2, the variable k is efficiently and quickly modified. By modifying the variable k, the impedance of square waveform 122 is quickly modified, which modifies the impedance of modified waveform 376. DC By controlling the control of and / or the phase of pulse signals 1 and 2 to output modified waveform 376, the impedance of RF signal 120 (FIG. 1) is rapidly modified by modified waveform 376 to modify, etc., the impedance of RF signal 120 (FIG. 1). The impedance of RF signal 120 is modified to control the impedance of RF signal 132 (FIG. 1). Circuit 344 is equivalent to another circuit 378 having a series coupling between a capacitance (L0 / L1)C1 and an inductance L0C1 / kL1.

[0074] In one embodiment, inductor 368 has an inductance that is different from the inductance of inductor 370 .

[0075] 3F-1 is a diagram of an embodiment of a system 380 illustrating the use of multiple adjustable impedance matching sections 382A and 382B. The system 380 includes adjustable impedance matching sections 382A and 382B and a host computer 104.

[0076] The adjustable impedance matching section 382A includes an LC network 384A and a DVS 386A. The LC network 384A includes an inductor 394A having an inductance L0. The processor 110 is coupled to the DVS 386A via a transfer cable 388A. The DVS 386A is coupled to the LC network 384A via an RF connection 390A so as to be coupled in series with the LC network 384A. The LC network 384A is coupled to a junction J1 via an RF connection 392A, and the junction J1 is coupled to a point P1 via an RF connection 130.

[0077] Additionally, adjustable impedance matching section 382B includes LC network 384B and DVS 386B. LC network 384B includes inductor 394B having an inductance L0. Processor 110 is coupled to DVS 386B via transfer cable 388B. DVS 386B is coupled to LC network 384B via RF connection 390B so as to be coupled in series with LC network 384B. LC network 384B is coupled to junction J1 via RF connection 392B.

[0078] The circuit 303 is equivalent to another circuit 305 having a parallel combination between an inductance L0 / 2 and another inductance L0 / (2kcosθ), where θ is the voltage V B Circuit 303 includes DVSs 386A and 386B, LC networks 384A and 384B, and junction J1.

[0079] Processor 110 controls DVS 386A to generate a square waveform 396A at a high frequency. DVS 386A generates square waveform 396A and provides square waveform 396A to LC network 384A. LC network 384A reduces (e.g., removes) the harmonics of square waveform 396A to output modified waveform 398A, which is provided to junction J1. Modified waveform 398A has a sinusoidal shape. When square waveform 396A is generated, the voltage at DVS 386A relative to ground potential is VB1 For example, the voltage of square waveform 396A is V B1 Voltage V B1 is the magnitude V Bm1 and phase θ1. The processor 110 calculates the magnitude V Bm1 or phase θ1, or magnitude V Bm1 and phase θ1, and controls DVS 386A. DVS 386A is controlled to modify the impedance of square waveform 396A, and further controls to modify the impedance of modified waveform 398A.

[0080] Processor 110 also controls DVS 386B to generate a square waveform 396B at a high frequency. DVS 386B generates square waveform 396B and provides square waveform 396B to LC network 384B. LC network 384B reduces (e.g., removes) the harmonics of square waveform 396B to output modified waveform 398B, which is provided to junction J1. Modified waveform 398B has a sinusoidal shape. When square waveform 396B is generated, the voltage at DVS 386B relative to ground potential is V B2 For example, the voltage of square waveform 396B is V B2 Voltage V B2 is the magnitude V Bm2 and phase θ2. For example, the voltage V B2 The phase of the voltage V B1 The processor 110 may be configured to generate a signal of magnitude V Bm2 or phase θ2, or magnitude V Bm2 and phase θ2, and controls DVS 386B. DVS 386B is controlled to modify the impedance of square waveform 396B, and further controls to modify the impedance of modified waveform 398B.

[0081] Modified waveform 398A is combined with modified waveform 398B at junction J1 to produce modified waveform 399, which is provided to point P1. Voltage V B1 and V B2 The magnitude of V Bm1 and VBm2 and one or more of phases θ1 and θ2, thereby controlling the impedance of modified waveform 399. Modified waveform 399 is an example of modified waveform 124 (FIG. 1). Controlling the impedance of modified waveform 399 rapidly modifies the impedance of RF signal 120 (FIG. 1), which in turn modifies the impedance of RF signal 132 (FIG. 1).

[0082] In one embodiment, LC network 384A is replaced with LC network 322 (FIG. 3B), LC network 342 (FIG. 3C), LC network 343 (FIG. 3D), or LC network 362 (FIG. 3E). Similarly, in one embodiment, LC network 384B is replaced with LC network 322, LC network 342, LC network 343, or LC network 362.

[0083] In one embodiment, the inductance of inductor 394A is different from the inductance of inductor 394B.

[0084] 3F-2 is a diagram of one embodiment of a system 307 including a DVS 386A and a DVS 386B. The DVS 386A includes a DC voltage source 309A, a capacitor 311A, a pulse signal source 313A, another pulse signal source 313B, and an HBC 315A. The HBC 315A includes a transistor 317A, another transistor 317B, a diode D3, and another diode D4. Each of the transistors 317A and 317B is a MOSFET and has a gate (G), a source (S), and a drain (D).

[0085] DC voltage source 309A is coupled to processor 110 via transfer cable 319A. DC voltage source 309A is also coupled to capacitor 311A ​​via point Po1 and to the drain of transistor 317A via point Po1. The other end of DC voltage source 309A is coupled to ground potential. Capacitor 311A ​​has one end coupled to DC voltage source 309A and the other end coupled to ground potential.

[0086] The source of transistor 317A is coupled to output O2, which is coupled to RF connection 390A. Output O2 is coupled to the drain of transistor 317B, and the source S of transistor 317B is coupled to ground. Because DC voltage source 309A, capacitor 311A, and HBC 315A are coupled to the same point Po1 and ground, DC voltage source 309A, capacitor 311A, and HBC 315A are coupled to each other in parallel. Pulse signal source 313A is coupled to processor 110 via transfer cable 319B and is coupled to the gate of transistor 317A. Pulse signal source 313B is coupled to processor 110 via transfer cable 319C and is coupled to the gate of transistor 317B.

[0087] The processor 110 controls the pulse signal source 313A to generate the pulse signal 3. For example, the processor 110 provides a frequency, a phase, and a duty cycle to the pulse signal source 313A via the transmission cable 319B. Upon receiving the frequency, the phase, and the duty cycle, the pulse signal source 313A generates the pulse signal 3 having the duty cycle, the phase, and the frequency, and sends the pulse signal 3 to the gate of the transistor 317A.

[0088] Similarly, upon receiving the duty cycle, phase, and frequency from processor 110 via transmission cable 319C, pulse signal source 313B generates pulse signal 4 having the duty cycle, phase, and frequency and sends pulse signal 4 to the gate of transistor 317B. The phase of pulse signals 3-4 is controlled by processor 110, which controls the phase of square waveform 396A. Processor 110 controls pulse signal 4 so that it is inversely synchronized with pulse signal 3. For example, processor 110 sets the phase of pulse signal 4 to be 180 degrees out of phase with pulse signal 3. The phase of pulse signal 4 is provided to pulse signal source 313B.

[0089] The processor 110 controls the DC voltage source 309A to adjust the amplitude V of the voltage signal 321A. DC1For example, the processor 110 controls the amplitude V DC1 is provided to DC voltage source 309A. DC1 Upon receiving this, DC voltage source 309A generates a voltage with amplitude V DC1 To the drain of transistor 317A, a voltage signal 321A having a voltage Vout of 1 V is output. Capacitor 311A ​​filters the AC signal from voltage signal 321A and provides voltage signal 323A to the drain of transistor 317A.

[0090] The voltage signal 323A has substantially the same amplitude as, for example, the same amplitude as, the voltage signal 321A. For example, the voltage signal 323A has an amplitude V DC1 As another example, voltage signal 323A may have an amplitude V DC1 and the amplitude of the filtered AC signal. When voltage signal 323A is provided to transistor 317A, transistors 317A and 317B operate in push-pull mode based on pulse signals 3 and 4 to provide square waveform 396A at output O2. For example, in push-pull mode, when transistor 317A is on, transistor 317B is off, and when transistor 317A is off, transistor 317B is on. The voltage of square waveform 396A at output O2 is V B1 is.

[0091] Each diode D3 and D4 protects the respective transistor 317A and 317B from excessive voltage. For example, diode D3 protects transistor 317A by acting as a short circuit when the voltage across transistor 317A exceeds a predetermined threshold of diode D3.

[0092] DVS386B includes DC voltage source 309B, capacitor 311B, pulse signal source 313C, another pulse signal source 313D, and HBC 315B. HBC 315B includes transistor 317C, another transistor 317D, diode D5, and another diode D6. Each of transistors 317C and 317D is a MOSFET and has a gate (G), a source (S), and a drain (D).

[0093] DC voltage source 309B is coupled to processor 110 via transfer cable 319D. DC voltage source 309B is also coupled to capacitor 311B via point Po2 and to the drain of transistor 317C via point Po2. The other end of DC voltage source 309B is coupled to ground potential. Capacitor 311B has one end coupled to DC voltage source 309B and the other end coupled to ground potential.

[0094] The source of transistor 317C is coupled to output O3, which is coupled to RF connection 390B. Output O3 is coupled to the drain of transistor 317D, and the source S of transistor 317D is coupled to ground. Because DC voltage source 309B, capacitor 311B, and HBC 315B are coupled to the same point Po2 and ground, DC voltage source 309B, capacitor 311B, and HBC 315B are coupled to each other in parallel. Pulse signal source 313C is coupled to processor 110 via transfer cable 319E and is coupled to the gate of transistor 317C. Pulse signal source 313D is also coupled to processor 110 via transfer cable 317F and is coupled to the gate of transistor 317D.

[0095] Processor 110 controls pulse signal source 313C to generate pulse signal 5. For example, processor 110 provides a frequency, phase, and duty cycle to pulse signal source 313C via transmission cable 319E. Upon receiving the frequency, phase, and duty cycle, pulse signal source 313C generates pulse signal 5 having the duty cycle, phase, and frequency and sends pulse signal 5 to the gate of transistor 317C.

[0096] Similarly, upon receiving the duty cycle, phase, and frequency from the processor 110 via the transmission cable 319F, the pulse signal source 313D generates a pulse signal 6 having the duty cycle, phase, and frequency. The phase of the pulse signals 5-6 is controlled by the processor 110, which controls the phase of the square waveform 396B. The processor 110 controls the pulse signal 6 so that it is inversely synchronized with the pulse signal 53. For example, the processor 110 sets the phase of the pulse signal 6 to be 180 degrees out of phase with the phase of the pulse signal 5. The phase of the pulse signal 6 is provided to the pulse signal source 313D. The pulse signal 6 is sent from the pulse signal source 313D to the gate of the transistor 317D.

[0097] The processor 110 controls the DC voltage source 309B to adjust the amplitude V DC2 For example, the processor 110 controls the amplitude V DC2 is provided to DC voltage source 309B. DC2 Upon receiving this, DC voltage source 309B generates a voltage of amplitude V DC2 To the drain of transistor 317C, a voltage signal 321B having a voltage Vout of 1 V is output. Capacitor 311B filters the AC signal from voltage signal 321B and provides voltage signal 323B to the drain of transistor 317C.

[0098] The voltage signal 323B has substantially the same amplitude as, e.g., the same amplitude as, the voltage signal 321B. For example, the voltage signal 323B has an amplitude V DC2 As another example, the voltage signal 323B has an amplitude VDC2 and the amplitude of the filtered AC signal. When voltage signal 323B is provided to transistor 317C, transistors 317C and 317D operate in push-pull mode based on pulse signals 5 and 6 to generate square waveform 396B at output O3. For example, in push-pull mode, when transistor 317C is on, transistor 317D is off, and when transistor 317C is off, transistor 317D is on. The voltage of square waveform 396B at output O3 is V B2 is.

[0099] Each diode D5 and D6 protects the respective transistor 317C and 317D from excessive voltage. For example, diode D5 protects transistor 317C by acting as a short circuit when the voltage across transistor 317C exceeds a predetermined threshold of diode D5.

[0100] In one embodiment, DVS 386A does not include capacitor 311A, and DVS 386B does not include capacitor 311B.

[0101] In one embodiment, another inverter circuit is used in place of an HBC, such as the HBC208 (FIG. 2), HBC315A, or HBC315B. For example, a first full-bridge circuit is used in place of the HBC315A, and a second full-bridge circuit is used in place of the HBC315B. As another example, a full-bridge circuit is used in place of the HBC208. Examples of other inverter circuits include a full-bridge circuit, a Class E circuit, and any other switching-mode power inverter.

[0102] In one embodiment, the terms inverter circuit and rectifier circuit are used interchangeably herein.

[0103] FIG. 4A is a diagram of an embodiment of a system 400 illustrating the use of multiple DVSes 402 and 404 within a matching section 406. The DVS 402 is a series DVS, and the DVS 404 is a shunt DVS. The DVS 116 (FIG. 2) is an example of a DVS 402. The DVS 116 is also an example of a DVS 404. The system 400 includes an RF generator 408, a matching section 406, and a plasma chamber 410. An example of the RF generator 408 is an RF generator having a low, medium, or high operating frequency. An example of a low operating frequency is 400 kilohertz (kHz) or 2 megahertz (MHz). An example of a medium operating frequency is 27 MHz, and an example of a high operating frequency is 60 MHz. The RF generator 408 is an example of the plasma source 106 (FIG. 1), and the plasma chamber 410 is an example of the load 108 (FIG. 1).

[0104] The matching unit 406 includes a DVS 402, a transformer 420, a capacitor 422, a DVS 404, an LC network 434, and an LC network 436. An example of the LC network 434 is the LC network 114 ( FIG. 1 ), and an example of the LC network 436 is the LC network 114. As an example, the matching unit 406 does not include any mechanical components such as a mechanical inductor and a mechanical capacitor. An example of a mechanical inductor is a coil and a core passing through the coil. The core is movable relative to the coil by a motor. An example of a mechanical capacitor is a fixed plate and a movable plate spaced a certain distance from the fixed plate. The movable plate is rotatable relative to the fixed plate by a motor.

[0105] Capacitor 422 is an electronic capacitor. For example, capacitor 422 is not a mechanical capacitor. As an example, the electronic capacitor is an integrated circuit or a ceramic capacitor. DVS 402 is coupled to LC network 434, which is coupled to a primary winding of transformer 420, and input 414 is coupled to a secondary winding of transformer 420. The secondary winding of transformer 420 is coupled to capacitor 422 via RF path 421 and to input 414 of matching unit 406 via RF path 421. RF path 421 extends from input 414 to output 416. Capacitor 422 is a shunt circuit. DVS 404 is coupled to LC network 436, which is coupled to output 416 of matching unit 406 via RF path 421. The combination of DVS 404 and LC network 436 forms a shunt circuit. The secondary winding forms part of RF path 421. An RF path, as used herein, includes one or more RF connections and one or more matching network components, such as inductors or capacitors or windings of a transformer.

[0106] The RF generator 408 is coupled to an input 414 of the matching unit 406 via an RF cable 412, such as a 50 ohm RF cable. An output 416 of the matching unit 406 is coupled to the plasma chamber 410 via an RF transmission line 418. One example of the RF transmission line 418 is a combination of an RF rod and an RF sheath. An insulator is placed between the RF rod and the RF sheath. The processor 110 is coupled to the DVS 402 via a transfer cable 424 and to the DVS 404 via a transfer cable 426. The processor 110 is also coupled to the RF generator 408 via a transfer cable 428.

[0107] The processor 110 controls the RF generator 408 to generate the RF signal 430. For example, the processor 110 provides the frequency and power of the RF signal 430 to the RF generator 408 via the transmission cable 428. Upon receiving the frequency and power, the RF generator 408 generates the RF signal 430, which is a sine wave signal, and transmits the RF signal 430 to the matching unit 406 via the RF cable 412.

[0108] While RF signal 430 is routed through matching unit 406, processor 110 controls one or more of DVSes 402 and 404 to output one or more square waveforms 438 and 442. For example, processor 110 controls DVS 402 to output square waveform 438. Square waveform 438 is processed by LC network 434 in the manner described above to output modified waveform 440. The voltage of modified waveform 440 is modified, such as increased or decreased, by transformer 420 to output an amplified waveform. Similarly, processor 110 controls DVS 404 to output square waveform 442. Square waveform 442 is processed by LC network 436 in the manner described above to output modified waveform 444.

[0109] The amplified waveform, capacitor 422, and modified waveform 444 modify the impedance of RF signal 430. The impedance of RF signal 430 is modified to match the impedance of a load coupled to output 416 with the impedance of a source coupled to input 414. An example of a load coupled to output 416 is RF transmission line 418 and plasma chamber 410, and an example of a source coupled to input 414 is RF cable 412 and RF generator 408. The impedance of RF signal 430 is modified to output modified RF signal 432 at output 416. Modified RF signal 432 is transmitted via RF transmission line 418 to an electrode, such as an ESC or RF coil or upper electrode, of plasma chamber 410 to process a semiconductor substrate placed in plasma chamber 410. The amplitude V of DVS 402 DC , the amplitude V of the DVS404 DC, the phase of pulse signals 1 and 2 of DVS 402 , and the phase of pulse signals 1 and 2 of DVS 404 , the impedance of RF signal 430 is rapidly modified to output modified RF signal 432 .

[0110] Note that although the potential of both DVS 402 and 404 is shown to be the same as VB, the potential of DVS 404 is different from the potential of DVS 402.

[0111] In one embodiment, matching unit 406 does not include DVS 402 or DVS 404 .

[0112] 4B is a diagram of an embodiment of a system 450 illustrating the use of DVS 402 and 404 within a matching section 452. System 450 includes an RF generator 408, a matching section 452, and a plasma chamber 410.

[0113] Matching section 452 includes DVS 402, inductor 454, capacitor 456, DVS 404, LC network 434, LC network 436, inductor 458, and capacitor 460. As an example, matching section 452 does not include any mechanical components.

[0114] Each of capacitors 456 and 460 is an electronic capacitor. For example, capacitor 456 is not a mechanical capacitor. Also, inductor 458 is an electronic inductor. For example, inductor 458 is not a mechanical inductor. As an example, the electronic inductor is an integrated circuit.

[0115] Inductor 454 is coupled to an input 462 of matching section 452 via RF path 459. RF path 459 extends from input 462 to output 464 of matching section 452. Inductor 454 is coupled to capacitor 456 via RF path 459 and to inductor 458 via RF path 459. Capacitor 456 is coupled to LC network 434 via RF path 459 and to inductor 458 via RF path 459. LC network 434 is coupled to inductor 458 via RF path 459. Capacitor 460 is coupled to LC network 436 via RF path 459. LC network 436 is coupled to an output 464 of matching section 452 via RF path 459. Capacitor 456 is a shunt circuit, and capacitor 460 is also a shunt circuit. The combination of LC network 434 and DVS 402 forms a shunt circuit, and the combination of LC network 436 and DVS 404 forms a shunt circuit. RF path 459 includes inductors 454 and 458 and one or more RF connections.

[0116] The RF generator 408 is coupled to an input 462 of the matching section 452 via an RF cable 412. An output 464 of the matching section 452 is coupled to the plasma chamber 410 via an RF transmission line 418.

[0117] The RF generator 408 transmits the RF signal 430 to the matching unit 452 via the RF cable 412. While the RF signal 430 is being transmitted through the matching unit 452, the processor 110 controls one or more of the DVSs 402 and 404 to output one or more of the square waveforms 438 and 442. The modified waveforms 440 and 444, the inductor 454, the capacitor 456, the inductor 458, and the capacitor 460 then modify the impedance of the RF signal 430. The impedance of the RF signal 430 is modified to match the impedance of a load coupled to the output 464 with the impedance of a source coupled to the input 462. Examples of loads coupled to the output 464 include the RF transmission line 418 and the plasma chamber 410, and examples of sources coupled to the input 462 include the RF cable 412 and the RF generator 408. The impedance of the RF signal 430 is modified to output a modified RF signal 466 at the output 464. The modified RF signal 466 is transmitted via RF transmission line 418 to an electrode in the plasma chamber 410 to process a semiconductor substrate placed in the plasma chamber 410. The amplitude V DC , the amplitude V of the DVS404 DC , the phase of pulse signals 1 and 2 of DVS 402 , and the phase of pulse signals 1 and 2 of DVS 404 , the impedance of RF signal 430 is rapidly modified to output modified RF signal 466 .

[0118] In one embodiment, in place of inductor 458, a capacitor is used.

[0119] 5 is a diagram of one embodiment of a system 500 illustrating the use of a DVS 402 with mechanical components and an LC network 434. The system 500 includes an RF generator 408, a hybrid match section 502, a plasma chamber 418, and a driver and motor system (DMS) 503.

[0120] Hybrid matching section 502 includes DVS 402, LC network 434, component network 504, and variable capacitor 509. Component network 504 includes one or more mechanical inductors, one or more mechanical capacitors, or a combination thereof. In component network 504, the mechanical inductors are coupled to each other, the mechanical capacitors are coupled to each other, or the mechanical inductors are coupled with the mechanical capacitors. DMS 503 includes one or more drivers, such as transistors, and an electric motor.

[0121] The RF generator 408 is coupled to an input 506 of the hybrid match section 502 via an RF cable 412, and the output 508 of the hybrid match section 502 is coupled to an electrode of the plasma chamber 410 via an RF transmission line 418. The LC network 434 is coupled to a variable capacitor 509 via an RF path 507 and to the input 506 via the RF path 507. The variable capacitor 509 is coupled to a component network 504 via the RF path 507, and the component network 504 is coupled to an output 508 via the RF path 507. The RF path 507 extends from the input 506 to the output 508 and includes the variable capacitor 509 and the component network 504.

[0122] The processor 110 is coupled to a driver via an RF connection 505, which is coupled to a motor. The motor is coupled to a variable capacitor 509.

[0123] The RF generator 408 transmits an RF signal 430 to the hybrid matching unit 502 via an RF cable 412. While the RF signal 430 is being transmitted through the hybrid matching unit 502, the processor 110 controls the DVS 402 to output a square waveform 438. The processor 110 also controls the variable capacitor 509 via the DMS 503 to modify the capacitance of the variable capacitor 509.

[0124] The modified waveform 440, variable capacitor 509, and component network 504 then modify the impedance of the RF signal 430. The impedance of the RF signal 430 is modified to match the impedance of a load coupled to the output 508 with the impedance of a source coupled to the input 506. An example of a load coupled to the output 508 includes the RF transmission line 418 and the plasma chamber 410, and an example of a source coupled to the input 506 includes the RF cable 412 and the RF generator 408. The impedance of the RF signal 430 is modified to output a modified RF signal 510 at the output 508. The modified RF signal 510 is transmitted via the RF transmission line 418 to an electrode of the plasma chamber 410 to process a semiconductor substrate placed in the plasma chamber 410. The amplitude V of the DVS 402 DC , and one or more of the phases of pulse signals 1 and 2 of DVS 402, the impedance of RF signal 430 is rapidly modified to output modified RF signal 510.

[0125] In one embodiment, variable capacitor 509 is replaced by a fixed mechanical capacitor, a variable mechanical inductor, or a fixed mechanical inductor.

[0126] FIG. 6 is a diagram of one embodiment of a graph 600 illustrating the operation of the hybrid matching section 502 (FIG. 5). The graph 600 plots the operation of the hybrid matching section 502 on the y-axis and time t on the x-axis. At time t0, both the mechanical components (M) and the electronic components (E) of the hybrid matching section 502 are simultaneously controlled by the processor 110 (FIG. 5) with the RF generator 408. The processor 110 controls the RF generator 408 to achieve a steady state of the RF signal 430 (FIG. 5) from time t0 until a time between time t0 and time t8. Time t8 occurs after time t0.

[0127] During the period between times t0 and t8, the processor 110 controls the mechanical and electronic components of the hybrid matching unit 502. The electronic components of the hybrid matching unit 502 facilitate matching the load impedance to the source impedance faster than the mechanical components of the hybrid matching unit 502. For example, at time t0, the mechanical components are disabled and the electronic components are enabled, and matching is achieved. As time progresses from time t0 to time t8, the mechanical components gradually begin to operate to achieve matching, and the electronic components continue to achieve matching at a faster rate than the mechanical components. At time t8, matching is achieved during the steady state of the RF generator 408. From time t8 onwards, the mechanical components continue to achieve matching.

[0128] In this way, by controlling the mechanical and electronic components to operate simultaneously within the hybrid matching unit 502, impedance matching between the load and source can be achieved quickly with low power loss. The electronic components adjust quickly but have higher losses than the mechanical components. The mechanical components adjust slowly but have a high quality (Q) factor to achieve accurate impedance matching.

[0129] Broadly, in various embodiments, a controller, as used herein, is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, coefficients, variables, etc., for performing a particular process on or for a semiconductor wafer or system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0130] In various embodiments, exemplary systems to which the methods are applied include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0131] It is further noted that in some embodiments, the operations described above apply to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, conductor tools, dielectric tools, and electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are coupled to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a flat coil, and the like.

[0132] Some of the embodiments also relate to hardware units or apparatus for performing these operations. The apparatus is specially constructed for use as a special purpose computer. When defined as a special purpose computer, the computer is operable for its dedicated purpose, while also performing other processes, program execution, or routines that are not part of its dedicated purpose.

[0133] One or more embodiments may also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit (e.g., a memory device, etc.) that stores data, which is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed manner.

[0134] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between each operation, or each method operation is coordinated to occur at slightly different times, or is distributed across a system that allows each method operation to occur at various intervals, or is performed in an order other than that set forth above.

[0135] It is further noted that in one embodiment, one or more features of any of the above-described embodiments may be combined with one or more features of any other of the above-described embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0136] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered illustrative rather than restrictive, and the embodiments should not be limited to the details set forth herein.

Claims

1. 1. A system for controlling impedance associated with an output of a plasma source, comprising: the plasma source configured to generate a radio frequency (RF) signal; a load coupled to the plasma source via an RF connection, the RF connection having a point; an adjustable impedance matching section coupled to the point between the plasma source and the load, the adjustable impedance matching section including a dependent voltage source and a circuit network, the dependent voltage source coupled in series with the adjustable impedance matching section and the circuit network; A system comprising:

2. 10. The system of claim 1, The system includes a circuit network including a capacitor or an inductor or a combination thereof, the dependent voltage source including a direct current (DC) voltage source, and the system includes a processor configured to modify a voltage output from the DC voltage source to achieve control of the impedance.

3. 10. The system of claim 1, The system, wherein the dependent voltage source includes a direct current (DC) voltage source and an inverter circuit, the DC voltage source coupled in parallel to the inverter circuit.

4. 4. The system of claim 3, The DC voltage source is configured to modify a voltage output from the DC voltage source to control the impedance.

5. 4. The system of claim 3, the dependent voltage source includes a plurality of pulse signal sources including a first pulse source and a second pulse source, the inverter circuit includes a first transistor and a second transistor, the first pulse source is coupled to the first transistor and provides a first pulse signal to the first transistor, the second pulse source is coupled to the second transistor and provides a second pulse signal to the second transistor, the first pulse source is configured to modify a phase of the first pulse signal, and the second pulse source is configured to modify a phase of the second pulse signal, thereby achieving control of the impedance.

6. 6. The system of claim 5, the second pulse signal is counter-synchronized with respect to the first pulse signal, and the phases of the first and second pulse signals are modified to either lead the phase of the voltage at the point or lag the phase of the voltage at the point to achieve control of the impedance.

7. 10. The system of claim 1, The system, wherein the dependent voltage source includes a capacitor and an inverter circuit, the capacitor coupled in parallel with the inverter circuit.

8. 1. A system for controlling impedance associated with an output of a plasma source, comprising: the plasma source configured to generate a radio frequency (RF) signal; a load coupled to the plasma source via an RF connection, the RF connection having a point; a plurality of adjustable impedance matching sections coupled to the point between the plasma source and the load, the plurality of adjustable impedance matching sections including a first adjustable impedance matching section and a second adjustable impedance matching section, the first adjustable impedance matching section including a first dependent voltage source and a first circuit network, the second adjustable impedance matching section including a second dependent voltage source and a second circuit network, the first dependent voltage source coupled in series with the first circuit network, and the second dependent voltage source coupled in series with the second circuit network; A system comprising:

9. 9. The system of claim 8, The system, wherein the first circuit network includes a first capacitor or a first inductor or a combination thereof, the second circuit network includes a second capacitor or a second inductor or a combination thereof, the plasma source is a matchless plasma source or a radio frequency (RF) generator, and the load includes a plasma chamber.

10. 9. The system of claim 8, The system, wherein the plurality of adjustable impedance matching units are configured to modify the impedance of the RF signal and output a modified RF signal, the modified RF signal being provided to the load, the RF signal being a sinusoidal signal, and the load comprising a plasma chamber.

11. 9. The system of claim 8, the first dependent voltage source includes a first pulse source and a second pulse source, the second dependent voltage source includes a third pulse source and a fourth pulse source, the first pulse source is configured to generate a first pulse signal, the second pulse source is configured to generate a second pulse signal, the second pulse signal being anti-synchronized with the first pulse signal, the third pulse source is configured to generate a third pulse signal, and the fourth pulse source is configured to generate a fourth pulse signal, the fourth pulse signal being anti-synchronized with the third pulse signal.

12. 9. The system of claim 8, the first dependent voltage source includes a first direct current (DC) voltage source, a first pulse source, a second pulse source, and a first inverter circuit, and the second dependent voltage source includes a second DC voltage source, a third pulse source, a fourth pulse source, and a second inverter circuit.

13. 13. The system of claim 12, The system, wherein the first DC voltage source is coupled in parallel with the first inverter circuit and the second DC voltage source is coupled in parallel with the second inverter circuit.

14. 14. The system of claim 13, The system, wherein the first dependent voltage source includes a first capacitor and the second dependent voltage source includes a second capacitor.

15. 15. The system of claim 14, The system, wherein the first capacitor is connected in parallel with the first inverter circuit and the second capacitor is connected in parallel with the second inverter circuit.

16. 1. A system for controlling impedance associated with an output of a radio frequency (RF) generator, comprising: the RF generator configured to generate an RF signal; an adjustable impedance matching unit coupled to the RF generator via an RF cable to receive the RF signal, the adjustable impedance matching unit including a dependent voltage source, the adjustable impedance matching unit configured to modify the impedance of the RF signal and output the modified RF signal; a load coupled to the adjustable impedance match section via an RF transmission line to receive the modified RF signal; A system comprising:

17. 17. The system of claim 16, an additional adjustable impedance matching section coupled to the RF generator via the RF cable, the additional adjustable impedance matching section including an additional dependent voltage source, the additional adjustable impedance matching section configured to modify the impedance of the RF signal and output the modified RF signal; The system further comprises:

18. 18. The system of claim 17, The system further comprising a matching section including the adjustable impedance matching section, the matching section including a mechanical circuit component coupled to the adjustable impedance matching section.

19. 20. The system of claim 18, The system, wherein the mechanical circuit component is a mechanical capacitor or a mechanical inductor.

20. 17. The system of claim 16, The system wherein the adjustable impedance match section includes an inductor-capacitor network coupled to the dependent voltage source.

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