Battery pack processing device and electronic device

Abstract

The present disclosure provides a battery pack processing device and electronic equipment, belonging to the battery technology field, in which a first chip of a charge / discharge management circuit is electrically connected to a charge / discharge interface, pin 11 of the first chip is electrically connected to pin 24 of a second chip of a logic control circuit, pin 12 of the first chip is electrically connected to pin 23 of the second chip, the positive electrode of the battery pack is electrically connected to pin 1 of a fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, CO, and 9 of the fifth chip by a lithium battery protection circuit, a first signal output terminal of a battery pack communication circuit is electrically connected to pin 13 of the second chip, and a second signal output terminal of the battery pack communication circuit is electrically connected to pin 14 of the second chip, the battery pack communication circuit sends a control signal to the second chip, and the second chip determines whether the battery packs are connected in parallel or in series based on the control signal, thereby realizing the series or parallel connection of the battery packs and improving the operating efficiency of the battery packs.

Description

[Technical Field]

[0001] This disclosure claims priority to a Chinese patent application entitled "Battery Pack Processing Device and Electronic Device," filed with the State Intellectual Property Office of the People's Republic of China on October 30, 2023, bearing application number 202311412338.3, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The present disclosure relates to the field of battery technology, and more particularly to processing devices and electronics for battery packs. [Background technology]

[0003] Battery pack management systems often need to detect and control the battery status. Currently, the I2C (Inter-Integrated Circuit) communication protocol is used to exchange data between the battery pack and the main control device. To meet the demands for higher voltage and capacity, multiple battery packs must be stacked together. This results in low battery pack utilization efficiency in the prior art. Summary of the Invention [Problem to be solved by the invention]

[0004] To solve the above technical problems, embodiments of the present disclosure provide a processing device and electronics for a battery pack. [Means for solving the problem]

[0005] According to a first aspect, an embodiment of the present disclosure provides a processing device for a battery pack, comprising: The battery pack includes a charge / discharge management circuit, a logic control circuit, a battery pack protection circuit, and a battery pack communication circuit. The charge / discharge management circuit includes a first chip and a charge / discharge interface electrically connected to each other; the logic control circuit includes a second chip; Pin 11 of the first chip is electrically connected to pin 24 of the second chip, and pin 12 of the first chip is electrically connected to pin 23 of the second chip; the battery pack protection circuit includes a fifth chip, a lithium battery protection circuit, and a battery pack cut-off protection circuit, the positive electrode of the battery pack is electrically connected to pin 1 of the fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, 12, and 13 of the fifth chip by the lithium battery protection circuit; a first signal output terminal of the battery pack communication circuit electrically connected to pin 13 of the second chip, and a second signal output terminal of the battery pack communication circuit electrically connected to pin 14 of the second chip; the battery pack communication circuit transmits a control signal to the second chip through the first signal output terminal and the second signal output terminal; The second chip determines whether the battery packs are connected in parallel or in series based on the control signal.

[0006] In some embodiments, the battery pack communication circuit includes a switch module, the switch module includes a twelfth field effect transistor and a thirteenth field effect transistor, and a connection point between a source of the twelfth field effect transistor and a source of the thirteenth field effect transistor is electrically connected to a fifteenth pin of a second chip; The second chip determines whether the battery packs are connected in parallel or in series, and then controls the switch module to be turned on or off.

[0007] In some embodiments, the battery pack communication circuit includes a sixth chip, wherein pin 8 of the sixth chip is electrically connected to pin 16 of the second chip, and pin 1 of the sixth chip is electrically connected to pin 15 of the second chip; The second chip determines whether the battery packs are connected in parallel or in series, and then sends an enable signal to pin 1 of the sixth chip to activate the sixth chip; The sixth chip transmits the read output current value of the sixth chip to pin 15 of the second chip.

[0008] In some embodiments, the charging / discharging interface includes an activation module, the activation module including a 12th resistor, a second field effect transistor, an 11th resistor, a 13th resistor, and a 17th capacitor, a first end of the 12th resistor connected to a power supply, a second end of the 12th resistor electrically connected to a base of the second field effect transistor, an emitter of the second field effect transistor grounded, a gate of the second field effect transistor electrically connected to the first end of the 11th resistor, a first end of the 13th resistor, and a second end of the 13th resistor grounded, a first end of the 17th capacitor electrically connected to the second end of the 13th resistor, a connection point between the second end of the 17th capacitor and the second end of the 11th resistor is a control end of the activation module, and the control end of the activation module is electrically connected to the output end of the charging / discharging interface.

[0009] In some embodiments, the device further includes a voltage control circuit, the voltage control circuit including a third chip and a fourth chip, wherein a junction point between pin 3 and pin 5 of the fourth chip is electrically connected to pin 16 of the third chip, pin 4 of the fourth chip is electrically connected to pin 10 of the second chip, and pin 6 of the fourth chip is electrically connected to pin 11 of the second chip; The fourth chip determines whether a device is inserted into the charging / discharging interface, and if a device is inserted, sends a corresponding level to the second chip.

[0010] In some embodiments, the fourth chip further determines whether the charging / discharging is in a single-port state or a dual-port state, and if in a single-port state, the Type-C port or the USB port has a fast charging function, and if in a dual-port state, the Type-C port and the USB port have a normal charging function.

[0011] In some embodiments, the battery pack shutdown protection circuit includes a seventh field effect transistor, a 65th resistor, and a 69th resistor, wherein the base of the seventh field effect transistor is electrically connected to pin 14 of the fifth chip by the 65th resistor, the emitter of the seventh field effect transistor and a first end of the 69th resistor are grounded, and the connection point of the gate of the seventh field effect transistor and a second end of the 69th resistor is electrically connected to pin 2 of the second chip.

[0012] In some embodiments, the device further includes a Bluetooth power module, the Bluetooth power module including an amplifier and a Bluetooth module, an input of the amplifier receiving a battery voltage, and an output of the amplifier electrically connected to the Bluetooth module; The Bluetooth power module determines the location of the device.

[0013] In some embodiments, the device further includes an illumination and sampling circuit, the illumination and sampling circuit including a seventh chip, wherein pin 6 of the seventh chip is electrically connected to pin 27 of the second chip; The lighting sampling circuit detects the presence or absence of a load.

[0014] According to a second aspect, an embodiment of the present disclosure provides an electronic device including the processing device of the battery pack provided in the first aspect. [Effects of the Invention]

[0015] In the battery pack processing device and electronic device provided by the present disclosure, the charge / discharge management circuit includes a first chip and a charge / discharge interface that are electrically connected to each other; the logic control circuit includes a second chip, pin 11 of the first chip is electrically connected to pin 24 of the second chip, and pin 12 of the first chip is electrically connected to pin 23 of the second chip; the battery pack protection circuit includes a fifth chip, a lithium battery protection circuit, and a battery pack cut-off protection circuit, the positive electrode of the battery pack is electrically connected to pin 1 of the fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, CO, and 9 of the fifth chip by the lithium battery protection circuit; the first signal output terminal of the battery pack communication circuit is electrically connected to pin 13 of the second chip, and the second signal output terminal of the battery pack communication circuit is electrically connected to pin 13 of the second chip; the battery pack communication circuit sends a control signal to the second chip via the first signal output terminal and the second signal output terminal; and the second chip determines whether the battery packs are connected in parallel or in series based on the control signal. By realizing series or parallel connection of battery packs, the operating efficiency of the battery packs is improved. [Brief explanation of the drawings]

[0016] In order to more clearly describe the technical solution of the present disclosure, the following briefly introduces the necessary drawings of the embodiments, where the following drawings only illustrate some embodiments of the present disclosure and do not limit the protection scope of the present disclosure, and similar symbols are used for similar structural parts in each drawing. [Figure 1] 1 is a structural schematic diagram of a battery pack processing device provided by an embodiment of the present disclosure; FIG. [Figure 2A] FIG. 2 is a schematic diagram of a local structure of a charge / discharge management circuit provided by an embodiment of the present disclosure. [Figure 2B] FIG. 2 is another partial structural schematic diagram of a charge / discharge management circuit provided by an embodiment of the present disclosure. [Figure 3] 1 is a structural schematic diagram of a logic control circuit provided by an embodiment of the present disclosure; FIG. [Figure 4] 1 is a structural schematic diagram of a battery pack protection circuit provided by an embodiment of the present disclosure; [Figure 5]1 is a structural schematic diagram of a voltage control circuit provided by an embodiment of the present disclosure; [Figure 6] 1 is a structural schematic diagram of a battery pack communication circuit provided by an embodiment of the present disclosure; [Figure 7] FIG. 2 is another structural schematic diagram of a battery pack communication circuit provided by an embodiment of the present disclosure. [Figure 8] FIG. 2 is a structural schematic diagram of a Bluetooth power supply circuit provided by an embodiment of the present disclosure. [Figure 9] 1 is a structural schematic diagram of an illumination and sampling circuit provided by an embodiment of the present disclosure. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, the technical solutions of the embodiments of the present disclosure will be clearly and completely described in combination with the drawings of the embodiments of the present disclosure, and the described embodiments are not all embodiments but only some embodiments of the present disclosure.

[0018] Generally, the units of the embodiments of the present disclosure shown in the drawings herein may be installed and designed in various different configurations. Therefore, the detailed description of the embodiments of the present disclosure provided in the drawings below does not limit the scope of protection of the present disclosure, but merely represents preferred embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by a person skilled in the art without any inventive effort fall within the scope of protection of the present disclosure.

[0019] Hereinafter, the terms "comprise", "comprise" and their synonyms that can be used in each embodiment of the present disclosure should not be understood as excluding the presence of one or more other features, numbers, steps, operations, elements, units or combinations thereof, or as the possibility of adding one or more features, numbers, steps, operations, elements, units or combinations thereof, but merely indicate certain features, numbers, steps, operations, elements, units or combinations thereof.

[0020] Furthermore, the terms "first," "second," "third," etc., do not indicate or imply relative importance, but are merely used for descriptive purposes.

[0021] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art in each embodiment of the present disclosure. In each embodiment of the present disclosure, unless otherwise clearly specified, the terms (e.g., terms defined in commonly used dictionaries) have the same meaning as the contextual meaning in the relevant technical field, without any ideal or overly formal meaning.

[0022] Example 1 An embodiment of the present disclosure provides a battery pack processing device 1. The following description will be given in conjunction with FIGS.

[0023] 1 to 9, a processing device 1 for a battery pack includes a charge / discharge management circuit 10, a logic control circuit 20, a battery pack protection circuit 30, and a battery pack communication circuit 50.

[0024] The charge / discharge management circuit 10 includes a first chip U1 and a charge / discharge interface 101 electrically connected to each other.

[0025] The logic control circuit 20 includes a second chip U2, where pin 11 of the first chip U1 is electrically connected to pin 24 of the second chip U2, and pin 12 of the first chip U1 is electrically connected to pin 23 of the second chip U2. Pin 11 of the first chip U1 is the SDA pin. Pin 12 of the first chip U1 is the SCK pin. Pin 23 of the second chip U2 is the PT21 / AIN9 pin. Pin 24 of the second chip U2 is the PT20 / AIN8 pin.

[0026] The battery pack protection circuit 30 includes a fifth chip U5, a lithium battery protection circuit 301, and a battery pack shutdown protection circuit 302. The positive electrode of the battery pack BAT1 is electrically connected to pin 1 of the fifth chip U5, and the negative electrode of the battery pack BAT1 is electrically connected to pins 11, CO, and 9 of the fifth chip U5 by the lithium battery protection circuit. Pin 1 of the fifth chip U5 is the VDD pin, pin 11 of the fifth chip U5 is the VM pin, pin CO of the fifth chip U5 is the control voltage terminal, and pin 9 of the fifth chip U5 is the DO pin.

[0027] The first signal output terminal BAT-SDA of the battery pack communication circuit 50 is electrically connected to pin 13 of the second chip U2, and the second signal output terminal BAT-SCL of the battery pack communication circuit 50 is electrically connected to pin 14 of the second chip U2. Pin 13 of the second chip U2 is a PT36 / AIN6 / RX / DMC pin. Pin 14 of the second chip U2 is a PT35 / AIN5 / TX / DPC pin.

[0028] the battery pack communication circuit 50 transmits a control signal to the second chip U2 via the first signal output terminal and the second signal output terminal; The second chip U2 determines whether the battery packs are connected in parallel or in series based on the control signal.

[0029] The charging / discharging interface 101 includes a USB interface and a Type C port. The Type C port and the first chip U1 form a DC / DC converter (DCDC) for charging and discharging the battery. The Type C port is a standard Type C interface that can be used for charging and discharging.

[0030] The first chip U1 acquires the battery charge and voltage, and pins 11 and 12 of the first chip U1 are electrically connected to pins 23 and 24 of the second chip U2. Pins 11 and 12 of the first chip U1 are SDA and SCK pins, respectively. Pins 23 and 24 of the second chip U2 are PT21 / AIN9 and PT20 / AIN8 pins, respectively.

[0031] The second chip U2 acquires the voltage and current from the first chip U1, performs logical management of charging and discharging to control charging and discharging, and determines the charging and discharging power based on the battery voltage and current acquired by the second chip U2.

[0032] Referring to Figures 2A and 2B, by matching the cut point A-1 in Figure 2A with the cut point A-2 in Figure 2B, matching the cut point B-1 in Figure 2A with the cut point B-2 in Figure 2B, and matching the cut point C-1 in Figure 2A with the cut point C-2 in Figure 2B, an overall structural schematic diagram of the charge / discharge management circuit is obtained.

[0033] The charging / discharging interface 101 includes an activation module 102, which includes a twelfth resistor R12, a second field effect transistor Q2, an eleventh resistor R11, a thirteenth resistor R13, and a seventeenth capacitor C17, a first end of the twelfth resistor R12 is connected to a power supply MCU-VCC, a second end of the twelfth resistor R12 is electrically connected to a base of the second field effect transistor Q2, an emitter of the second field effect transistor Q2 is grounded, and a seventeenth capacitor C17 is connected to the base of the second field effect transistor Q2. The gate of transistor Q2 is electrically connected to the first end of the 11th resistor R11 and the first end of the 13th resistor R13, the second end of the 13th resistor R13 is grounded, the first end of the 17th capacitor C17 is electrically connected to the second end of the 13th resistor R13, and the connection point between the second end of the 17th capacitor C17 and the second end of the 11th resistor R11 is the control end of the activation module 102, and the control end of the activation module 102 is electrically connected to the output end of the charging / discharging interface 101.

[0034] In this embodiment, for devices with non-standard Type-C interfaces, devices that only have Vbus and GND, the activation module 102 activates the second chip U2 to recognize the insertion of non-standard devices. In the charge / discharge management circuit configured as a whole shown in Figures 2A and 2B, QP1, QP2, QP3, and QP4 are power transistors that form step-up and step-down voltages. In Figure 2A, VBAT_O represents the battery voltage. When the battery voltage VBAT_O enters the charge / discharge management circuit 10 and becomes, for example, 9V, 15V, or 20V, the QP1 and QP4 power transistors are turned on and in a step-down state. QP1 passes through a 15uH inductor from SW2 to QP4 via SW1 and is then in a step-down state. From QP2, it reaches the Type-C interface and is also in a step-down state. LD1 / HD1 are driving voltages provided by the first chip U1 and can be either high or low. When high, they are turned on, and when low, they are not turned on. 2B, LED1 to LED4 are electricity amount indicator lamps, and the number of lights indicates 25%, 50%, 75%, and 100%, for example. TVS1 to TVS4 constitute an anti-surge protection circuit to prevent ESD surges.

[0035] Referring to Figure 3, the logic control circuit 20 includes a second chip U2 and a first amplifier AU1. The second chip U2 is further connected to other chips. Pin 2 of the first amplifier AU1 is connected to the V-VBAT terminal by a third diode D3, and pin 3 of the first amplifier AU1 is connected to the MCU_VCC terminal, realizing MCU logic control. Pin 1 of the first amplifier AU1 is the GND pin, pin 2 of the first amplifier AU1 is the VIN pin, and pin 3 of the first amplifier AU1 is the OUT pin.

[0036] 4, the battery pack protection circuit 30 includes a lithium battery protection circuit 301 and a battery pack shutdown protection circuit 302. The battery pack shutdown protection circuit 302 includes a seventh field effect transistor Q7, a sixteenth resistor R65, and a sixteenth resistor R69. The base of the seventh field effect transistor Q7 is electrically connected to pin 14 of the fifth chip U5 by the sixteenth resistor R65. The emitter of the seventh field effect transistor Q7 and the first end of the sixteenth resistor R69 are grounded. The junction of the gate of the seventh field effect transistor Q7 and the second end of the sixteenth resistor R69 is electrically connected to pin 2 of the second chip. Pin 14 of the fifth chip U5 is the RCOT pin. Pin 2 of the second chip is the PT30 / AIN0 / NTC / VREF pin.

[0037] The battery pack protection circuit 30 protects the battery, for example, against overvoltage and overcharge of the battery.

[0038] The fifth chip U5 controls the magnitude of the voltage output from the TypeC port and the USB port, specifically, controls the magnitude of the voltage based on the communication protocol, and controls the single-port state (TypeC port or USB port) or the dual-port state (TypeC port and USB port).

[0039] Referring to FIG. 5, the voltage control circuit 40 includes a third chip U3 and a fourth chip U4. The connection point between pins 3 and 5 of the fourth chip U4 is electrically connected to pin 16 of the third chip U3. Pin 4 (LINKA1 signal) of the fourth chip U4 is electrically connected to pin 10 (LINKA_1 signal) of the second chip U2. Pin 6 (LINKB signal) of the fourth chip U4 is electrically connected to pin 11 (LINKB_1 signal) of the second chip U2. Pin 11 of the second chip U2 is the PT16 pin. Pin 16 of the third chip U3 is the FB pin. Pins 3 and 5 of the fourth chip U4 are the CMPI / SDA pin and the FB pin, respectively. Pin 4 of the fourth chip U4 is the SCL pin.

[0040] The fourth chip U4 determines whether a device is inserted into the charging / discharging interface 101, and if a device is inserted, sends a corresponding level to the second chip U2.

[0041] In some embodiments, the fourth chip U4 further determines whether the charging / discharging is in a single-port state or a dual-port state, and if in a single-port state, the Type-C port or the USB port has a fast charging function, and if in a dual-port state, the Type-C port and the USB port have a normal charging function.

[0042] In this embodiment, the Type C port is an interface for charging the device end or the battery pack, and can be charged and discharged.

[0043] The third chip U3 is a step-down IC that outputs electrical energy to the Type-C port and the USB port. The Type-C port outputs electrical energy to the mobile phone or tablet for external charging, and reduces the battery voltage before outputting it externally.

[0044] 6, the battery pack communication circuit 50 includes a switch module, which includes a twelfth field effect transistor Q12 and a thirteenth field effect transistor Q13, and the connection point between the source of the twelfth field effect transistor Q12 and the source of the thirteenth field effect transistor Q13 is electrically connected to pin 15 of the second chip U2, which is a PT34 / AIN4 / RX / DMD / CC2B pin.

[0045] The second chip U2 determines whether the battery packs are connected in parallel or in series, and then controls the switch module to be on or off.

[0046] As shown in Figure 6, there are four signal terminals: VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND. Whether the battery packs are connected in parallel or in series is determined based on the information from two signal terminals, BAT-SDA and BAT-SCL. For example, Figures 2A and 2B form an overall charge / discharge management circuit, and Figures 3 to 6 are combined to form a single circuit. Figures 2A and 2B form an overall charge / discharge management circuit, and Figures 3 to 5 and 7 to 9 are combined to form a single circuit. Whether the battery packs are connected in parallel or in series is determined based on the input signal from the BAT-SDA or BAT-SCL signal terminal among the VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND signal terminals. For example, if a battery has a current of 30,000 mA, when two batteries are connected in parallel, the current becomes 60,000 mA.

[0047] 6, when devices are normally inserted into the four signal terminals VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND, parallel connection of the battery packs is realized, and when devices are reversely inserted into the four signal terminals VBAT_OUT, BAT-SDA, BAT-SCL, and VBAT_GND, series connection of the battery packs is realized. For example, if the SDA and SCL signals are 01, they are connected in parallel, and if the SDA and SCL signals are 01, they are connected in series, and the SDA and SCL signals are sent to the second chip U2. When the second chip U2 does not recognize the SDA and SCL signals, the 12th and 13th field-effect transistors Q12 and Q13 included in the switch module do not turn on. Only when the second chip U2 recognizes the SDA and SCL signals does it turn on. Pin 15 (PT34 / AIN4 / RX / DMD / CC2B pin) of the second chip U2 controls the turning on of the 12th and 13th field-effect transistors Q12 and Q13. The SDA and SCL signals are 00 by default, and the 12th and 13th field-effect transistors Q12 and Q13 do not turn on by default. When the device determines that the battery packs are connected in the forward direction, the battery packs are connected in parallel. When the device determines that the battery packs are connected in the reverse direction, the battery packs are connected in series. When the device determines that the battery packs are connected in series or parallel, the second chip U2 outputs current and voltage normally, and the 12th and 13th field-effect transistors Q12 and Q13 of the switch module turn on.

[0048] For example, if a Type-C port can only discharge for three hours, after connecting in parallel it can discharge for six hours, increasing the capacity. If the voltage of the Type-C port is simply 10-20V and the battery voltage is 9-12.6V, after connecting in series the battery voltage will be 23.2V, which increases the battery voltage and allows more devices to be powered. Furthermore, after determining whether to connect in series or parallel, when charging the battery pack, the control is performed to charge the battery with the lower voltage first, and the second chip U2 determines the master device and slave device based on the amount of electricity, or determines the master device or slave device based on the usage status, and then controls the second chip U2 of the master device.

[0049] 7, the battery pack communication circuit 50 includes a sixth chip U6, whose pin 8 is electrically connected to pin 16 of the second chip U2 and whose pin 1 is electrically connected to pin 15 of the second chip U2. After determining whether the battery packs are connected in parallel or series, the second chip U2 sends an enable signal to pin 1 of the sixth chip U6 to activate the sixth chip U6, and the sixth chip U6 transmits the read output current value of the sixth chip U6 to pin 15 of the second chip U2. Pin 8 of the sixth chip U6 is an IMON pin, and pin 16 of the second chip U2 is a PT33 / AIN3 / TX / DPD / CC1B pin. Pin 1 of the sixth chip U6 is an EN pin (enable terminal), and pin 15 of the second chip U2 is a PT34 / AIN4 / RX / DMD / CC2B pin.

[0050] In Figure 7, pin 1 of the sixth chip U6 is an enable terminal (BAT-H1 signal) that activates the sixth chip U6 to start, and pin 8 (IMON pin) of the sixth chip U6 reads its own output current value BAT_I. In Figure 7, there are BAT_SDA and BAT_SCL signal terminals, and the second chip U2 determines whether the battery packs are connected in parallel or in series based on the BAT_SDA and BAT_SCL signal terminals. After the communication between the BAT_SDA and BAT_SCL signal terminals and the second chip U2 is completed, the second chip U2 sends a BAT_H1 signal to the sixth chip U6 to control it to activate.

[0051] 8, the Bluetooth power supply module 60 includes an amplifier AU2 and a Bluetooth module BT1, the input terminal of the amplifier AU2 receives the battery voltage VBAT_O, and the output terminal of the amplifier AU2 is electrically connected to the Bluetooth module BT1. The 1st pin of the amplifier AU2 is a GND pin, the 2nd pin of the amplifier AU2 is an input terminal (VIN pin), and the 3rd pin of the amplifier AU2 is an output terminal (OUT pin).

[0052] The Bluetooth charging module 60 determines the location of the device, which may be a mobile phone, tablet, or other device to be charged.

[0053] In this embodiment, the Bluetooth power supply module 60 senses the Bluetooth devices within a certain sensing range and locates the associated devices.

[0054] 9, the illumination and sampling circuit 70 includes a seventh chip U7, and pin 6 of the seventh chip U7 is electrically connected to pin 27 of the second chip U2. Pin 6 of the seventh chip U7 is an OUT pin, and pin 27 of the second chip U2 is a PT24 / AIN12 / DMB pin.

[0055] The illumination sampling circuit 70 detects the presence or absence of a load.

[0056] In this embodiment, the lighting and sampling circuit 70 is used as a flashlight to provide illumination. Pin 6 (OUT pin) of the seventh chip U7 of the lighting and sampling circuit 70 is electrically connected to pin 27 (PT24 / AIN12 / DMB pin) of the second chip U2, and the current Qi-I at pin 6 of the seventh chip U7 is detected to determine whether a load is present. Based on the presence or absence of a load, it is determined whether an indicator lamp needs to be turned on.

[0057] In this embodiment, the first chip U1, the second chip U2, the third chip U3, the fourth chip U4, the fifth chip U5, the sixth chip U6, and the seventh chip U7 are chips with corresponding pins and can realize corresponding functions.

[0058] In the battery pack processing device 1 provided by the present disclosure, the charge / discharge management circuit 10 includes a first chip and a charge / discharge interface 101 electrically connected to each other; the logic control circuit 20 includes a second chip, and pin 11 of the first chip is electrically connected to pin 24 of the second chip, and pin 12 of the first chip is electrically connected to pin 23 of the second chip; the battery pack protection circuit 30 includes a fifth chip, a lithium battery protection circuit 301, and a battery pack cut-off protection circuit 302, and the positive electrode of the battery pack is electrically connected to pin 1 of the fifth chip. The negative pole of the battery pack is electrically connected to pins 11, 12, and 13 of the fifth chip by the lithium battery protection circuit, the first signal output terminal of the battery pack communication circuit 50 is electrically connected to pin 13 of the second chip, and the second signal output terminal of the battery pack communication circuit 50 is electrically connected to pin 13 of the second chip. The battery pack communication circuit 50 sends a control signal to the second chip via the first signal output terminal and the second signal output terminal, and the second chip determines whether the battery packs are connected in parallel or in series based on the control signal. This realizes the series or parallel connection of the battery packs, thereby improving the operating efficiency of the battery packs.

[0059] Example 2 Furthermore, an embodiment of the present disclosure provides an electronic device including the processing device of the battery pack provided in the first embodiment.

[0060] Here, the electronic device provided in this embodiment includes the battery pack processing device 1 provided in the embodiment, realizes the processing process of the battery pack processing device 1 of embodiment 1, and can achieve the corresponding effects of the battery pack processing device 1 of embodiment 1, and in order to avoid duplication, no further details will be given here.

[0061] Although the above describes examples of the present disclosure in conjunction with the drawings, the present disclosure is not limited to the above specific embodiments, and the above specific embodiments are not intended to be limiting but merely illustrative. Based on the teachings of the present disclosure, a person skilled in the art may make various modifications without departing from the spirit of the present disclosure and the scope of protection of the claims, and all of them belong to the scope of protection of the present disclosure. [Industrial Applicability]

[0062] The present disclosure provides a battery pack processing device and electronic equipment, belonging to the battery technology field, in which a first chip of a charge / discharge management circuit is electrically connected to a charge / discharge interface, pin 11 of the first chip is electrically connected to pin 24 of a second chip of a logic control circuit, pin 12 of the first chip is electrically connected to pin 23 of the second chip, the positive electrode of the battery pack is electrically connected to pin 1 of a fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, CO, and 9 of the fifth chip by a lithium battery protection circuit, a first signal output terminal of a battery pack communication circuit is electrically connected to pin 13 of the second chip, and a second signal output terminal of the battery pack communication circuit is electrically connected to pin 14 of the second chip, the battery pack communication circuit sends a control signal to the second chip, and the second chip determines whether the battery packs are connected in parallel or in series based on the control signal, thereby realizing the series or parallel connection of the battery packs and improving the operating efficiency of the battery packs.

[0063] Furthermore, the battery pack processing device and electronic device of the present disclosure can be reproduced and applied to various industrial applications, for example, the battery pack processing device and electronic device of the present disclosure can be applied to the battery technology field. [Explanation of symbols]

[0064] 1. Battery pack processing device, 10 charge / discharge management circuit, 101 charging and discharging interface, 20 logic control circuits, 30 Battery pack protection circuit, 301 Lithium battery protection circuit, 302 Battery pack cutoff protection circuit, 102 activation module, 40 voltage control circuit, 50 Battery pack communication circuit, 60 Bluetooth power supply module, 70 Lighting and sampling circuit

Claims

1. A processing device for a battery pack, comprising: a charge / discharge management circuit, a logic control circuit, a battery pack protection circuit, and a battery pack communication circuit; The charge / discharge management circuit includes a first chip and a charge / discharge interface electrically connected to each other; the logic control circuit includes a second chip; Pin 11 of the first chip is electrically connected to pin 24 of the second chip, and pin 12 of the first chip is electrically connected to pin 23 of the second chip; the battery pack protection circuit includes a fifth chip, a lithium battery protection circuit, and a battery pack cutoff protection circuit, the positive electrode of the battery pack is electrically connected to pin 1 of the fifth chip, and the negative electrode of the battery pack is electrically connected to pins 11, 12, and 13 of the fifth chip by the lithium battery protection circuit; a first signal output terminal of the battery pack communication circuit electrically connected to pin 13 of the second chip, and a second signal output terminal of the battery pack communication circuit electrically connected to pin 14 of the second chip; the battery pack communication circuit transmits a control signal to the second chip through the first signal output terminal and the second signal output terminal; The battery pack processing device is characterized in that the second chip determines whether the battery packs are connected in parallel or in series based on the control signal.

2. the battery pack communication circuit includes a switch module, the switch module includes a twelfth field effect transistor and a thirteenth field effect transistor, and a connection point between a source of the twelfth field effect transistor and a source of the thirteenth field effect transistor is electrically connected to a fifteenth pin of the second chip; The battery pack processing device according to claim 1 , wherein the second chip controls the on / off of the switch module after determining whether the battery packs are connected in parallel or in series.

3. the battery pack communication circuit includes a sixth chip, pin 8 of the sixth chip is electrically connected to pin 16 of the second chip, and pin 1 of the sixth chip is electrically connected to pin 15 of the second chip; The second chip determines whether the battery packs are connected in parallel or in series, and then sends an enable signal to pin 1 of the sixth chip to activate the sixth chip; 2. The battery pack processing device according to claim 1, wherein the sixth chip transmits the read output current value of the sixth chip to pin 15 of the second chip.

4. 2. The battery pack processing device of claim 1, wherein the charging / discharging interface includes an activation module, the activation module including a twelfth resistor, a second field-effect transistor, an eleventh resistor, a thirteenth resistor, and a seventeenth capacitor, a first end of the twelfth resistor connected to a power supply, a second end of the twelfth resistor electrically connected to a base of the second field-effect transistor, an emitter of the second field-effect transistor grounded, a gate of the second field-effect transistor electrically connected to the first end of the eleventh resistor and the first end of the thirteenth resistor, and a second end of the thirteenth resistor grounded, a first end of the seventeenth capacitor electrically connected to the second end of the thirteenth resistor, a connection point between the second end of the seventeenth capacitor and the second end of the eleventh resistor is a control end of the activation module, and the control end of the activation module is electrically connected to an output end of the charging / discharging interface.

5. further comprising a voltage control circuit, the voltage control circuit comprising a third chip and a fourth chip, a connection point between pin 3 and pin 5 of the fourth chip being electrically connected to pin 16 of the third chip, pin 4 of the fourth chip being electrically connected to pin 10 of the second chip, and pin 6 of the fourth chip being electrically connected to pin 11 of the second chip; 5. The battery pack processing device according to claim 4, wherein the fourth chip determines whether a device is inserted into the charging / discharging interface, and if a device is inserted, transmits a corresponding level to the second chip.

6. 6. The battery pack processing device of claim 5, wherein the fourth chip further determines whether the charging / discharging is in a single-port state or a dual-port state, and if in the single-port state, the Type C port or the USB port has a fast charging function, and if in the dual-port state, the Type C port and the USB port have a normal charging function.

7. 2. The battery pack processing device of claim 1, wherein the battery pack cutoff protection circuit includes a seventh field effect transistor, a sixty-fifth resistor, and a sixty-ninth resistor, wherein a base of the seventh field effect transistor is electrically connected to pin 14 of the fifth chip by the sixty-fifth resistor, an emitter of the seventh field effect transistor and a first end of the sixty-ninth resistor are grounded, and a connection point of a gate of the seventh field effect transistor and a second end of the sixty-ninth resistor is electrically connected to pin 2 of the second chip.

8. The Bluetooth power supply module further includes an amplifier and a Bluetooth module, the input terminal of the amplifier receives the battery voltage, and the output terminal of the amplifier is electrically connected to the Bluetooth module; The battery pack processing device according to claim 1 , wherein the Bluetooth power supply module determines the location of the device.

9. further comprising an illumination and sampling circuit, the illumination and sampling circuit including a seventh chip, pin 6 of the seventh chip electrically connected to pin 27 of the second chip; 9. The battery pack processing device according to claim 8, wherein the illumination and sampling circuit detects the presence or absence of a load.

10. An electronic device comprising the battery pack processing device according to any one of claims 1 to 9.

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