FEFET devices, systems and manufacturing methods

Abstract

A FeFET transistor (600) is disclosed having a source electrode (602), a drain electrode (602), and a channel structure (604). A first portion (606) is disposed parallel to the source electrode along a first length. A second portion (608) is disposed parallel to the insulating layer and adjacent to the first portion. A third portion (610) is disposed parallel to the drain electrode and adjacent to the second portion. A ferroelectric structure (612) has a first portion (614), a second portion (616), and a third portion (618). The first portion of the ferroelectric structure is disposed parallel to the first portion of the channel structure. The second portion of the ferroelectric structure is disposed parallel to the second portion of the channel structure. The third portion of the ferroelectric structure is disposed parallel to the third portion of the channel structure. A gate structure (620) is disposed within a space defined by the first, second, and third portions of the ferroelectric structure.

Description

[Technical Field]

[0001] The present disclosure relates to transistors involving ferroelectric materials. In particular, the present disclosure relates to ferroelectric transistor devices, systems and manufacturing methods. [Background technology]

[0002] A field-effect transistor ("FET") is a transistor that uses an electric field to control or modify the current flowing between its source and drain terminals. The electric field is generated by a voltage applied to the gate terminal of the FET. FETs use electrons and / or holes as charge carriers to achieve this effect. FETs can be primarily majority or minority charge carrier devices. A voltage applied to the gate of a FET creates an active channel through which charge carriers flow from the source terminal to the drain terminal. The nonlinear impedance through this channel can be varied by applying a different voltage to the gate terminal compared to the source and / or drain terminals. However, these characteristics are temporary, as the FET rapidly returns to its original, resting state as soon as the voltage is removed.

[0003] A ferroelectric field effect transistor ("FeFET") is a FET that includes a ferroelectric material. A ferroelectric material is a material that has an electric polarization (or polarization density). The electric field polarization of a ferroelectric material can be used to create an active channel within the FeFET. By utilizing this property of ferroelectric materials, the electric field polarization within the ferroelectric material can be used to retain the state of the FeFET in the absence of any electrical bias. That is, the FeFET can retain information within the ferroelectric material even without any external power applied. This feature makes the FeFET well suited for non-volatile memory applications involving discrete or continuous values. Summary of the Invention

[0004] One or more computer systems can be configured to perform particular operations or actions by having software, firmware, hardware, or a combination thereof installed on the system that causes the system to perform an action during operation. One or more computer programs can be configured to perform particular operations or actions by including instructions that, when executed by a data processing device, cause the device to perform the action.

[0005] In one general aspect, an integrated circuit device may include a first layer having a semiconductor substrate. The integrated circuit device may also include a second layer disposed parallel to the first layer. The second layer has an insulating layer and a transistor disposed on the insulating layer. The transistor has: a source electrode disposed on the insulating layer along a first length parallel to the insulating layer; a drain electrode disposed on the insulating layer parallel to the source electrode, the drain electrode being disposed a predetermined distance from the source electrode; a channel structure having a first portion, a second portion, and a third portion, the first portion disposed along the first length parallel to the source electrode, the second portion disposed parallel to the insulating layer and adjacent to the first portion, and the third portion disposed parallel to the drain electrode and adjacent to the second portion; a ferroelectric structure having a first portion, a second portion, and a third portion, the ferroelectric structure configured to have at least one polarization, the first portion of the ferroelectric structure being disposed parallel to the first portion of the channel structure, the second portion of the ferroelectric structure being disposed parallel to the second portion of the channel structure, and the third portion of the ferroelectric structure being disposed parallel to the third portion of the channel structure; and a gate structure disposed within a space defined by the first, second, and third portions of the ferroelectric structure.

[0006] Implementations may include one or more of the following features: The first layer may be a front-end-of-line layer; The second layer may be a back-end-of-line layer; The second layer may include a three-dimensional stack of memory cells including transistors; The transistors may be configured to store neuromorphic values; The ferroelectric structure may be configured to have a selectable polarization, such that the polarization corresponds to a stored value; The stored value may be a discrete value or a continuous value; A second insulating layer may be disposed over the first and third portions of the channel structure, over the first and second portions of the ferroelectric structure, and over the gate structure; The source electrode may have a height defined by a second length extending orthogonally from the insulating layer such that the source electrode has a thickness defined by a third length orthogonal to the first length and the second length; The computer system may include an integrated circuit configured as an artificial intelligence accelerator.

[0007] In one general aspect, a method for fabricating an integrated circuit may include forming an insulating layer. The method may also include forming a source electrode parallel to the insulating layer along a first length. The method may further include forming a drain electrode parallel to the insulating layer and parallel to the source electrode, the drain electrode being disposed a predetermined distance from the source electrode. The method may further include forming a channel structure having a first portion, a second portion, and a third portion, the first portion being parallel to the source electrode along the first length, the second portion being adjacent to the first portion along the insulating layer, and the third portion being parallel to the drain electrode and adjacent to the second portion. Additionally, the method may include forming a ferroelectric structure having a first portion, a second portion, and a third portion, the first portion of the ferroelectric structure being parallel to the first portion of the channel structure, the second portion of the ferroelectric structure being parallel to the second portion of the channel structure, and the third portion of the ferroelectric structure being parallel to the third portion of the channel structure. The ferroelectric structure is configured to have at least one polarization. The method may also include forming a gate structure disposed within a space defined by the first, second, and third portions of the ferroelectric structure. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0008] Implementations may include one or more of the following features: the method, wherein the act of forming a channel structure includes depositing the channel structure using atomic layer deposition; the act of forming a ferroelectric structure includes depositing the ferroelectric structure using atomic layer deposition; the act of forming a gate structure may include: depositing a gate structure including an excess gate structure using atomic layer deposition; and removing the excess gate structure using chemical mechanical planarization; the method may include forming a second insulating layer; and forming at least one coupling with at least one of a source electrode, a drain electrode, and the gate structure. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0009] In one general aspect, an integrated circuit device may include an insulating layer. The integrated circuit device may also include a plurality of parallel electrodes each extending along a first direction parallel to the insulating layer and arranged in a spaced-apart relationship with one another, thereby defining a plurality of spaces between each adjacent pair of the plurality of parallel electrodes, with predetermined spaces interposed between each adjacent pair of the plurality of parallel electrodes. The integrated circuit may further include a plurality of channel structures each disposed within the plurality of spaces, with each channel structure cooperating with both the adjacent pair of the plurality of parallel electrodes and the insulating layer. The integrated circuit may further include a plurality of ferroelectric structures each disposed adjacent to a respective one of the plurality of channel structures, each configured to include a respective channel. The integrated circuit may further include a plurality of gate structures each disposed within a respective channel of the plurality of ferroelectric structures.

[0010] Implementations may include one or more of the following features: The integrated circuit may have at least one of the plurality of parallel electrodes being a drain or a source electrode. The computer system may have a central processing unit; a memory in operative communication with the central processing unit; and an integrated circuit configured as an artificial intelligence accelerator.

[0011] In one general aspect, a manufacturing method may include forming an insulating layer. The method may also include forming a plurality of parallel electrodes each extending along a first direction parallel to the insulating layer, the parallel electrodes being arranged in a spaced-apart relationship with one another such that adjacent pairs of the parallel electrodes have predetermined spaces interspaced therebetween, thereby defining a plurality of spaces between each adjacent pair of the parallel electrodes. The method may further include forming a plurality of channel structures each disposed within the plurality of spaces, each channel structure cooperating with both an adjacent pair of the parallel electrodes and the insulating layer. The method may further include forming a plurality of ferroelectric structures each disposed adjacent to a respective one of the plurality of channel structures, each ferroelectric structure configured to include a respective channel. The method may further include forming a plurality of gate structures each disposed within a respective channel of the plurality of ferroelectric structures. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0012] Implementations may include one or more of the following features. The method may include depositing an electrode using atomic layer deposition. The method may include forming a plurality of channel structures, including depositing a channel structure using atomic layer deposition. The method may include depositing a ferroelectric structure using atomic layer deposition. The method may include depositing a gate structure, including an excess gate structure, using atomic layer deposition; and removing the excess gate structure using chemical mechanical planarization. The method may include forming a second insulating layer; and forming at least one contact with at least one of a gate structure of the plurality of gate structures and an electrode of the plurality of parallel electrodes. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0013] These and other aspects will become more apparent from the following detailed description of various embodiments of the present disclosure when taken in conjunction with the drawings. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram of an artificial intelligence accelerator that utilizes FeFET memory according to one embodiment of the present disclosure. [Figure 2] FIG. 2 shows a diagram of a memory cell utilizing FeFET transistors according to one embodiment of the present disclosure. [Figure 3] FIG. 3 illustrates the operational characteristics of the FeFET of FIG. 2 when used to store binary states, according to one embodiment of the present disclosure. [Figure 4] FIG. 4 illustrates the operational characteristics of the FeFET of FIG. 2 when used to store continuous values ​​such as the weights of a neuromorphic cell, according to one embodiment of the present disclosure. [Figure 5] FIG. 5 illustrates a memory array utilizing FeFET transistors according to one embodiment of the present disclosure. [Figure 6]FIG. 6 illustrates an FeFET transistor configured for miniaturization for the back-end-of-line portion of an integrated circuit semiconductor according to one embodiment of the present disclosure. [Figure 7] FIG. 7 illustrates an FeFET transistor configured for miniaturization for the back-end-of-line portion of an integrated circuit semiconductor according to one embodiment of the present disclosure. [Figure 8] FIG. 8 illustrates a bit cell array formed by a plurality of FeFETs of FIGS. 5-7 according to one embodiment of the present disclosure. [Figure 9A] FIG. 9A illustrates a manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 9B] FIG. 9B illustrates a manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 9C] FIG. 9C illustrates a manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 9D] FIG. 9D illustrates a manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 9E] FIG. 9E illustrates a manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 10] FIG. 10 illustrates a flow diagram of a method for fabricating the bit cell array illustrated in FIGS. 9A-9E according to one embodiment of the present disclosure. [Figure 11A] FIG. 11A illustrates another manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 11B] FIG. 11B illustrates another manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 11C] FIG. 11C illustrates another manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 11D] FIG. 11D illustrates another manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 11E] FIG. 11E illustrates another manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 11F] FIG. 11F illustrates another manufacturing process for fabricating the bit cell array of FIG. 8 according to one embodiment of the present disclosure. [Figure 12] FIG. 12 illustrates a flow diagram of a method for fabricating the bit cell array illustrated in FIGS. 11A-11F according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] FIG. 1 illustrates a block diagram of an artificial intelligence (AT) accelerator 100 utilizing FeFET memory 112 according to one embodiment of the present disclosure. The AI ​​accelerator 100 may be implemented on a semiconductor device, a custom integrated circuit, an application-specific integrated circuit ("ASIC"), a graphics processing unit ("GPU"), a field-programmable gate array ("FPGA"), any device known to those skilled in the art, or some combination thereof. The AI ​​accelerator 100 includes a processing element ("PE") array 102 that performs the majority of the AI ​​computations. The PE array 102 performs the AI ​​computations using multiple processing elements 110. These processing elements 110 can form a many-core processor, with each processing element 110 performing AI computations in parallel with the other processing elements 110. Additionally or alternatively, processing element 110 may include an arithmetic logic unit, a neuromorphic computing element, a processor, a multi-core processor, a many-core processor, a reduced instruction set computer ("RISC") processor, and / or other computing devices known to those skilled in the art.

[0016] Each processing element 110 may be part of a neuromorphic circuit; for example, each processing element 110 may, in some particular embodiments, form part of an artificial neural network in which each associated memory 112 is an analog memory configured to serve as parameters (e.g., weights) for an artificial neuron. Each processing element 110 and its respective memory 112 may, in yet additional embodiments, form an in-memory processing architecture, for example, to enable efficient parallel execution of multiply-accumulate operations.

[0017] Memory 112 is implemented using FeFETs, which are described in further detail below. Memory 112 can store binary data and / or, in some particular embodiments, analog data. Additionally or alternatively, memory 112 can store a combination of binary and analog data in some embodiments.

[0018] The AI ​​accelerator 100 may include a shared memory 108. Computations performed by the PE array 102 may be stored on and / or instructed by information stored on a shared memory 104 internal to the AI ​​accelerator and / or on a shared memory 108 stored external to the AI ​​accelerator 100. The shared memory 104 and / or the shared memory 108 may use FeFET memory cells as described herein. The AI ​​accelerator 100 also includes a network-on-chip 106 for communicating with other devices, e.g., via TCP / IP, Ethernet, Wi-Fi, etc.

[0019] 2 shows a diagram of a memory cell 200 utilizing an FeFET 202 according to one embodiment of the present disclosure. The memory cell 200 also includes a program signal circuit 206 and a sense circuit 204. The program signal circuit 206 can apply one or more positive or negative voltage pulse signals to program the FeFET 202. The FeFET 202 includes a drain 210, a source 212, and a gate 208. However, due to the symmetry of the FeFET 202, the operation of the drain 210 and the source 212 can be reversed.

[0020] The FeFET 202 may be powered by a Vread voltage relative to a voltage SL. The Vread voltage may be ground, a fixed voltage, a programmable voltage, or a variable voltage, and may be coupled to a voltage source or ground via another transistor (not shown), or the like. Similarly, the SL reference may be ground, a fixed voltage, a programmable voltage, or a variable voltage, and may be coupled to ground or a voltage source via another transistor (not shown), or the like. For example, the Vread and SL voltages may be predetermined values ​​to enable a fixed voltage, e.g., intermittently or continuously, between the drain 210 and the source 212. In other embodiments, the Vread and SL voltages may be set to enable a constant current, e.g., intermittently or continuously, from the drain 210 to the source 212.

[0021] A voltage applied to the gate 208 of the FeFET 202 by the program signal circuit 206 can cause an electric polarization to form in the ferroelectric material within the FeFET 202. The ferroelectric polarization can remain (or substantially remain) long after the voltage applied to the gate 208 of the FeFET 202 is removed, provided that the applied voltage is of sufficient magnitude and duration to change the state of the ferroelectric material. This results in a stable electric polarization in the ferroelectric material. A ferroelectric material is an insulator in which the electric polarization induced by the applied electric field from the voltage applied to the gate 208 remains after the voltage is removed.

[0022] A positive voltage bias (or pulse) from program-signal circuit 206 applied to gate 208 of FeFET 202 results in a lowering of the threshold voltage of FeFET 202, causing the channel of FeFET 202 to enter accumulation mode. And, a negative voltage bias (or pulse) from program-signal circuit 206 applied to gate 208 of FeFET 202 results in an increase in the threshold voltage of FeFET 202, causing the channel of FeFET 202 to enter depletion mode. The first state may correspond to a 0 value, and the second state may correspond to a 1 value, or vice versa.

[0023] 2-3, FIG. 3 illustrates, in the form of a graph 300, the operational characteristics of the FeFET 202 of FIG. 2 when used to store a binary state, according to one embodiment of the present disclosure. Graph 300 shows an axis 302 that represents the current Ids, which is the current flowing from the drain 210 through the FeFET 202 and through the source 212 to ground. The current Ids passes through the channel of the FeFET 202, where the channel has characteristics based on the polarization of the ferroelectric material. Graph 300 also includes an axis 304 that represents the voltage at the gate 208 of FIG. 2. The Vg value applied to the gate 208 may be within a voltage range for determining the state of the FeFET without significantly perturbing the polarization of the ferroelectric material.

[0024] FIG. 3 illustrates the relationship between Ids and Vg based on the state of FeFET 202 according to one embodiment of the present disclosure. A first curve 306 shows FeFET 202 in a first state because it has a first threshold voltage 308. A second curve 308 shows FeFET 202 in a second state because it has a second threshold voltage 312. The state of FeFET 202 may be programmed by program signal circuit 206 to change the electric polarization of the ferroelectric material within FeFET 202. These states may be detected by sense circuit 302. In some embodiments, no Vg voltage needs to be applied to FeFET 202 to determine the state. However, in other embodiments, a sufficient voltage needs to be applied to gate 208 to determine the state of the FeFET, but the FeFET 202 is not programmed.

[0025] 2 and 4, FIG. 4 illustrates, in the form of a graph 400, the operating characteristics of the FeFET 202 of FIG. 2 when the FeFET 202 is used to store continuous values, such as the weights of a neuromorphic cell, in accordance with one embodiment of the present disclosure.

[0026] Graph 400 shows an axis 402 of current Ids. Ids is the current flowing from drain 210 through FeFET 202 and through source 212 to ground. Current Ids passes through the channel of FeFET 202, where this channel has characteristics based on the polarization of the ferroelectric material. Graph 400 also includes an axis 404 that shows the voltage at gate 208 of FIG. 2. The Vg value applied to gate 208 may be within a range of voltages to determine the state of the FeFET without significantly disturbing the polarization of the ferroelectric material.

[0027] FIG. 4 illustrates the relationship between Ids and Vg based on the polarization of an FeFET 202 according to one embodiment of the present disclosure. As the polarization changes, the characteristic curve shifts, as indicated by arrow 408. These shifting curves also shift the threshold voltages 406. These values ​​may be mapped to the weights of an artificial neural network. For example, an arithmetic logic unit may read these values ​​for calculation within the processing element of FIG. 1. In some embodiments, memory may be used for in-memory calculations, along with other analog circuits, to perform calculations of the artificial neural net according to the mapped values ​​corresponding to the weights of neural network cells, such as neurons. During the neural network training phase, the AI ​​accelerator 100 may use the program signal circuit 206 to change the electric polarization of the ferroelectric material in the FeFET 202 to correspond to the neuron weights. These threshold voltages 406 may be detected by the sense circuit 204. In some embodiments, it is not necessary to apply a Vg voltage to the FeFET 202 to determine its state. However, in other embodiments, a voltage is applied to the gate 208.

[0028] FIG. 5 illustrates a memory array 500 utilizing FeFET transistors 514 according to one embodiment of the present disclosure. Each FeFET transistor 514 has a polarization state. An interface circuit (not shown) can select one of word lines 502, 504, or 506 to activate a column of FeFET transistors 514. These activated FeFETs 514, coupled to an activated word line, e.g., 504, output a state (or value) on each of bit lines 508, 510, and 512, each corresponding to the electric polarization of the ferroelectric material within the respective FeFET 514. Those skilled in the art will recognize that the array of FeFETs 514 can be expanded to accommodate a desired memory size. Furthermore, those skilled in the art will recognize that programming circuitry may be added to the memory array 500.

[0029] FeFET transistor 512 may be powered by a voltage from bit lines 502, 504, 506 that is relative to voltage SL. The SL reference may be ground, a fixed voltage, a programmable voltage, or a variable voltage, and may be coupled to ground or a voltage source through another transistor (not shown).

[0030] 6-7 illustrate FeFETs 600, 700 configured for scaling to the back-end-of-line ("BEOL") portion of an integrated circuit semiconductor according to one embodiment of the present disclosure. FIG. 6 illustrates FeFET 600, which may be a BEOL FeFET that is not built in a silicon substrate but instead rests in the BEOL between different metal layers. Some of the layers shown in FeFETs 600, 700 may be formed using atomic layer deposition ("ALD"), which, in some specific embodiments, can achieve layer thicknesses as low as 2 nm to 10 nm. However, other deposition techniques, different thicknesses, or technologies may also be used.

[0031] The FeFET 600 includes a source or drain terminal 602. Due to symmetry, the terminal 602 can be used to introduce Ids in either direction of current flow, and therefore can act as a source or a drain. The terminal 602 can be formed from a metal such as Pd, Mo, Al / Ti, W, Cu, TiN, or Pt.

[0032] The FeFET 600 includes a channel structure 604 having a first portion 606, a second portion 608, and a third portion 610. The first portion 606 is disposed adjacent to a terminal 602, and the second portion 608 is disposed on top of an insulating layer, which may be an insulating layer disposed on the back-end of an integrated circuit. The third portion 610 is disposed adjacent to the terminal 602. The channel material may be n-type, such as ITO, IGZO, IZO, AZO, a-Si, ZnO, a-Ge, polysilicon, or poly-Si or poly-III-V such as InAs. In some embodiments, the channel material may be p-type, such as a-Si, ZnO, a-Ge, polysilicon, polygermanium, poly-III-V such as InAs, CuO, SnO, or the like. The channel structure 604 may have a channel length of 5 nm to 100 nm in some specific embodiments. However, other lengths may also be used. Similarly, in some particular embodiments, the width of the channel structure 604 may be any width as known to those skilled in the art.

[0033] The FeFET 600 also includes a ferroelectric structure 612 including a first portion 614, a second portion 616, and a third portion 618. The first portion 614 is disposed adjacent to the first portion 606 of the channel structure 604. The second portion 616 of the ferroelectric structure 616 is disposed adjacent to the second portion 608 of the channel structure 604. The third portion 618 of the ferroelectric structure 616 is disposed adjacent to the third portion 610 of the channel structure 604. The ferroelectric material may be made of one or more of lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO), lead titanate (PbTiO), and doped hafnium dioxide (HfO). The doped HfO may include one or more of silicon-doped HfO, yttrium-doped HfO, and aluminum-doped HfO.

[0034] FeFET 600 also includes a gate structure 620 corresponding to gate 208 shown in FIG. 2. Gate structure 620 may be made of any suitable material, such as a metal, alloy, W, Cu, Al, TiN, or combinations thereof. Gate structure 620 may have a positive or negative voltage applied to it, e.g., a voltage that is positive or negative with respect to ground or with respect to terminal 602. The voltage applied to gate structure 620 may be of a voltage and duration that changes, reverses, or modifies the electric polarization of the ferroelectric material in ferroelectric structure 612.

[0035] The FeFET 700 of FIG. 7 is similar to the FeFET 600 of FIG. 6, but has a relatively shorter gate length L2. That is, the FeFET 600 has a gate length L1 that is greater than the gate length L2 of the FeFET 700. These different gate lengths (L1 vs. L2) are intended to illustrate the scaling process that may occur during the design of an integrated circuit. Note that as the device footprint decreases (e.g., from L1 to L2), the density achievable by including additional FeFETs increases. Furthermore, the FeFET 700 can be further scaled without reducing the magnitude of polarization because the area of ​​the FE layer experiencing polarization is primarily between the gate structure 620 and the source or drain wall 601 or 602 (within the width of the FeFET). Furthermore, the structure of the FeFET 700 can increase the device height to increase the FE area, thus increasing the grain density, which in turn results in a higher magnitude of polarization within the ferroelectric material without increasing the footprint of the device. That is, the footprint of the FeFET 700 is partially separated from the polarizable ferroelectric region because a portion of the ferroelectric structure 612 lies in a separate plane. Because of this compact device arrangement of the FeFETs 600, 700, the source or drain gate 620 overlap (e.g., the two terminals of 602) is located in another dimension and orthogonal to the direction of the channel length, allowing for an increase in the ferroelectric layer area 612 without having to increase the footprint and overall area of ​​the FeFETs 600, 700. Moreover, as will be readily apparent to those skilled in the art, the design of the FeFETs 600, 700 allows for favorable control of the interfaces, dimensions, and interactions of the ferroelectric, channel, and source or drain layers.

[0036] 8 shows an array 800 of bit cells 802a-802c formed by a plurality of FeFETs of FIGS. 5-7 according to one embodiment of the present disclosure. The FeFETs can be linearly arranged in the array 800 such that between each pair of terminals 602 there is a channel structure 610, a ferroelectric structure 612, and a gate structure 620 that form a bit, such as bits 1-3 shown in FIG. 8. The bits can extend any length beyond the three bits shown in FIG. 8.

[0037] Reference is now made to Figures 9A-9E and 10, which together illustrate a manufacturing process for fabricating the bitcell of Figure 8 according to one embodiment of the present disclosure. One such manufacturing method is depicted in Figure 10, which shows a flow chart of a method 1000 for fabricating a bitcell array such as that illustrated in Figures 9A-9E.

[0038] Method 1000 includes acts 1002-1012. Act 1002 forms an insulating layer, such as insulating layer 900 of FIGS. 9A-9E. Insulating layer 900 may be formed as part of the formation of back-end electrical layers. Act 1004 forms a plurality of parallel electrodes 902 (e.g., source and drain electrodes) as shown in FIG. 9A. These electrodes 902 may be formed using deposition, patterning, and / or a combination of deposition and patterning. Act 1006 forms a plurality of channel structures 904 by depositing and planarizing a channel layer, resulting in the structure shown in FIG. 9B. Planarization may be performed by chemical-mechanical polishing, chemical etching, mechanical polishing (e.g., abrasive polishing), or any combination thereof. Act 1008 forms a plurality of ferroelectric structures 906 by depositing and planarizing a ferroelectric layer, resulting in the configuration of FIG. 9C. Act 1010 forms gate structures 908 by depositing a gate layer and planarizing, as shown in Figure 9D. The FeFET transistors are now complete as shown in Figure 9D, but metal connections are required to the different terminals of the transistors. Act 1012 forms insulation 912 and wiring layers 910 (e.g., metal connectors) for wiring electrical connections to the gate, source, and drain electrodes.

[0039] 12 and 11A-11F, FIG. 12 shows a flow chart illustrating a method 1200 for fabricating the bit cell array of FIG. 8 using the stages shown in FIGS. 11A-11F, according to one embodiment of the present invention.

[0040] The method 1200 includes acts 1202-1214. Act 1202 forms an insulating layer 1100 shown in FIGS. 11A-11F. The insulating layer 1110 may be formed as part of the formation of back-end electrical layers. Act 1204 forms a plurality of parallel electrodes 1102 (e.g., source and drain electrodes), resulting in the structure shown in FIG. 11A. Act 1206 forms a plurality of channel structures by depositing a channel layer 1104 shown in FIG. 11B. Act 1208 forms a plurality of ferroelectric structures by depositing a ferroelectric layer 1106 shown in FIG. 11C. Act 1210 forms a plurality of gate structures by depositing a gate layer 1108 shown in FIG. 11D. Act 1212 planarizes the channel, ferroelectric, and gate structures shown in FIG. 11E. Act 1214 forms an insulating and wiring layer 1110 for wiring electrical connections to the gate, source and drain electrodes shown in Figure 11F.

[0041] Those skilled in the art may devise various alternatives and modifications without departing from the disclosure. Accordingly, the present disclosure is intended to embrace all such alternatives, modifications, and variations. Moreover, while several embodiments of the present disclosure have been shown in the drawings and / or discussed herein, it is not intended that the disclosure be limited to those embodiments, as the disclosure is intended to be of the broadest scope permitted by the art and the specification be construed accordingly. Therefore, the foregoing description should not be considered limiting, but merely illustrative of particular embodiments. Moreover, those skilled in the art will envision other modifications that fall within the scope and spirit of the appended claims. Other elements, steps, methods, and techniques that differ insubstantially from those described above and / or in the appended claims are also intended to fall within the scope of the present disclosure.

[0042] The embodiments shown in the drawings are presented only to demonstrate some examples of the present disclosure. Also, the depicted drawings are merely exemplary and non-limiting. In the drawings, for illustrative purposes, the size of some elements may be exaggerated and not drawn to a particular scale. Furthermore, elements shown in the drawings with the same number may be identical or similar elements, depending on the context.

[0043] The term "comprising," when used in the specification and claims, does not exclude other elements or steps. Where an indefinite or definite article, e.g., "a," "an," or "the," is used when referring to a singular noun, this includes a plural of that noun unless specifically stated otherwise. Thus, the term "comprising" should not be construed as being limited to the items listed thereafter and does not exclude other elements or steps; thus, the phrase "a device comprising items A and B" should not be limited to a device consisting only of components A and B. This phrase means that, in the context of this disclosure, the only relevant components of the device are A and B.

[0044] Furthermore, terms such as "first," "second," "third," etc., whether used in the specification or in the claims, are provided to distinguish between similar elements and not necessarily to describe a sequence or chronology. Terms so used are intended to be interchangeable under appropriate circumstances (unless expressly disclosed otherwise), and it should be understood that the disclosed embodiments described herein are capable of operation in sequences and / or arrangements other than those described or illustrated herein.

Claims

1. In an integrated circuit device: a first layer having a semiconductor substrate; and a second layer disposed parallel to the first layer and having an insulating layer and a transistor disposed on the insulating layer, the transistor comprising: a source electrode disposed on the insulating layer along a first length parallel to the insulating layer; a drain electrode disposed on the insulating layer parallel to the source electrode, the drain electrode being disposed a predetermined distance from the source electrode; a channel structure having a first portion, a second portion, and a third portion, the first portion disposed parallel to the source electrode along the first length, the second portion disposed parallel to the insulating layer and adjacent to the first portion, and the third portion disposed parallel to the drain electrode and adjacent to the second portion; a ferroelectric structure configured to have at least one polarization, the ferroelectric structure having a first portion, a second portion, and a third portion, the first portion of the ferroelectric structure being disposed parallel to the first portion of the channel structure, the second portion of the ferroelectric structure being disposed parallel to the second portion of the channel structure, and the third portion of the ferroelectric structure being disposed parallel to the third portion of the channel structure; a gate structure disposed within a space defined by the first, second, and third portions of the ferroelectric structure; a transistor including:

1. An integrated circuit device comprising:

2. The device of claim 1 , wherein the first layer is a front-end-of-line layer.

3. The device of claim 1 , wherein the second layer is a back-end-of-line layer.

4. The device of claim 1 , wherein the second layer comprises a three-dimensional stack of memory cells including the transistor.

5. The device of claim 1 , wherein the transistor is configured to store a neuromorphic value.

6. The device of claim 1 , wherein the ferroelectric structure is configured to have a selectable polarization, the polarization corresponding to a stored value.

7. The device of claim 6 , wherein the stored values ​​are discrete values.

8. The device of claim 6 , wherein the stored values ​​are continuous values.

9. 10. The device of claim 1, further comprising a second insulating layer disposed over the first and third portions of the channel structure, over the first and second portions of the ferroelectric structure, and over the gate structure.

10. 10. The device of claim 1, wherein the source electrode has a height defined by a second length extending orthogonally from the insulating layer, and the source electrode has a thickness defined by a third length orthogonal to the first length and the second length.

11. central processing unit; memory in operative communication with said central processing unit; and 10. The integrated circuit of claim 1 configured as an artificial intelligence accelerator. A computer system comprising:

12. In a method of manufacturing an integrated circuit: forming an insulating layer; forming a source electrode disposed parallel to the insulating layer along a first length; forming a drain electrode disposed parallel to the insulating layer and parallel to the source electrode, the drain electrode being disposed a predetermined distance from the source electrode; forming a channel structure having a first portion, a second portion, and a third portion, the first portion disposed parallel to the source electrode along the first length, the second portion disposed adjacent to the first portion along the insulating layer, and the third portion disposed parallel to the drain electrode and adjacent to the second portion; forming a ferroelectric structure having a first portion, a second portion, and a third portion, the first portion of the ferroelectric structure being disposed parallel to the first portion of the channel structure, the second portion of the ferroelectric structure being disposed parallel to the second portion of the channel structure, and the third portion of the ferroelectric structure being disposed parallel to the third portion of the channel structure, the ferroelectric structure being configured to have at least one polarization; forming a gate structure disposed within a space defined by the first, second, and third portions of the ferroelectric structure; A method comprising:

13. The method of claim 12 , wherein the act of forming the channel structure includes depositing the channel structure using atomic layer deposition.

14. 13. The method of claim 12, wherein the act of forming the ferroelectric structure includes depositing the ferroelectric structure using atomic layer deposition.

15. forming the gate structure; depositing the gate structure, including the redundant gate structure, using atomic layer deposition; removing the excess gate structure using chemical mechanical planarization; 13. The method of claim 12, comprising:

16. forming a second insulating layer; forming at least one contact with at least one of the source electrode, the drain electrode, and the gate structure; The method of claim 12 further comprising:

17. In an integrated circuit device, an insulating layer; a plurality of parallel electrodes each extending along a first direction parallel to the insulating layer, the parallel electrodes being disposed in a spaced apart relationship to one another so as to have predetermined spaces interspaced between each adjacent pair of the plurality of parallel electrodes thereby defining a plurality of spaces between each adjacent pair of the plurality of parallel electrodes; a plurality of channel structures respectively disposed within the plurality of spaces, each channel structure cooperating with both the adjacent pairs of the plurality of parallel electrodes and the insulating layer; a plurality of ferroelectric structures each disposed adjacent a respective one of the plurality of channel structures, each configured to include a respective channel; a plurality of gate structures each disposed within the respective channels of the plurality of ferroelectric structures; 1. An integrated circuit device comprising:

18. 20. The device of claim 17, wherein at least one of the plurality of parallel electrodes is a drain or source electrode.

19. central processing unit; memory in operative communication with said central processing unit; and 18. The integrated circuit of claim 17 configured as an artificial intelligence accelerator. A computer system comprising:

20. 1. A method for manufacturing an integrated circuit, comprising: forming an insulating layer; forming a plurality of parallel electrodes each extending parallel to the insulating layer along a first direction, the plurality of parallel electrodes being disposed in spaced-apart relation to one another with predetermined spaces interposed between adjacent pairs of the plurality of parallel electrodes thereby defining a plurality of spaces between adjacent pairs of the plurality of parallel electrodes; forming a plurality of channel structures respectively disposed within the plurality of spaces, each channel structure cooperating with both the adjacent pairs of the plurality of parallel electrodes and the insulating layer; forming a plurality of ferroelectric structures each disposed adjacent a respective one of the plurality of channel structures, each of the ferroelectric structures configured to include a respective channel; forming a plurality of gate structures each disposed within the respective channels of the plurality of ferroelectric structures; A method comprising:

21. 21. The method of claim 20, wherein the act of forming a plurality of parallel electrodes includes depositing the electrodes using atomic layer deposition.

22. 21. The method of claim 20, wherein the act of forming the plurality of channel structures includes depositing the channel structures using atomic layer deposition.

23. 21. The method of claim 20, wherein the act of forming a plurality of ferroelectric structures includes depositing the ferroelectric structures using atomic layer deposition.

24. forming the gate structure; depositing a gate structure including a redundant gate structure using atomic layer deposition; removing the excess gate structure using chemical mechanical planarization; 21. The method of claim 20, comprising:

25. forming a second insulating layer; forming at least one contact with at least one of a gate structure of the plurality of gate structures and an electrode of the plurality of parallel electrodes; 21. The method of claim 20, further comprising:

Images