Nonvolatile memory cell grouping and error correction

Abstract

Numerous examples of improved grouping and error correction systems for non-volatile memory cells are disclosed. In one example, the system includes a memory array including non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the memory array storing a first group of first bits and a second group of second bits, the first data grouping supported by a first ECC block and the second data grouping supported by a second ECC block.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 427,406, filed November 22, 2022, entitled "Level Assignment and Error Correction for Multilevel Non-Volatile Memory Cells," and U.S. Patent Application No. 18 / 106,421, filed February 6, 2023, entitled "Grouping and Error Correction for Non-Volatile Memory Cells."

[0002] FIELD OF THE INVENTION Numerous examples of improved level assignment and error correction systems for multi-level non-volatile memory cells are disclosed. [Background technology]

[0003] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 110 is shown in FIG. 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0004] The memory cell 110 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0005] The memory cell 110 is programmed by source side injection (SSI) of hot electrons (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electron current flows from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0006] The memory cell 110 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0007] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the flash memory cell 110 of FIG. 1 [Table 1]

[0008] Other split-gate memory cell configurations, which are other types of flash memory cells, are also known. For example, FIG. 2 shows a four-gate memory cell 210 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0009] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 2: Operation of flash memory cell 210 of FIG. 2 [Table 2]

[0010] Figure 3 shows another type of flash memory cell, a three-gate memory cell 310. Memory cell 310 is identical to memory cell 210 of Figure 2, except that memory cell 310 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 2, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0011] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 310 of FIG. 3 [Table 3]

[0012] 4 shows another type of flash memory cell, a stacked gate memory cell 410. Memory cell 410 is similar to memory cell 110 of FIG. 1, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are accomplished by electrons flowing from the source region 14 toward the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0013] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 410 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 410 of FIG. 4 [Table 4]

[0014] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable), and CeRAM (correlated electron ram).

[0015] FIG. 5 shows a block diagram of a prior art memory system 500 suitable for analog multi-level cell (MLC) memory storage (e.g., where the separation between levels is 1-2 variation sigma, less stringent than digital MLC memory storage) or vector-matrix multiplication neural network applications (e.g., where the separation between levels is 1-2 variation sigma, less stringent than digital MLC memory storage).

[0016] The memory system 500 includes an array 501, a row decoder 502, a high-voltage decoder 503, a column decoder 504, a bit line driver 505, input circuits 506, output circuits 507, control logic 508, and a bias generator 509. The memory system 500 further includes a high-voltage generation block 510, including a charge pump 511, a charge pump regulator 512, and a high-voltage level generator 513. The memory system 500 further includes a (program / erase or weight tuning) algorithm controller 514, analog circuitry 515, a control engine 516 (which may include special functions such as, but are not limited to, arithmetic functions, activation functions, embedded microcontroller logic, etc.), test control logic 517, and an SRAM block 518 for storing intermediate data, such as for input circuits (e.g., activation data) or output circuits (neuron output data), or data input for programming (e.g., data input for an entire row or multiple rows).

[0017] Array 501 includes rows and columns of non-volatile memory cells, such as memory cells 110, 210, 310, or 410 of FIGS. 1-4, respectively.

[0018] The input circuit 506 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 506 may implement one or more of a normalization, a linear or nonlinear up / downscaling function, or an arithmetic function. The input circuit 506 may implement a temperature compensation function for the input level. The input circuit 506 may implement an activation function such as a ReLU or a sigmoid. The input circuit 506 may store digital activation data that is applied as an input signal or combined with an input signal during a program or read operation. The digital activation data may be stored in a register. The input circuitry 506 may include circuitry for driving the array terminals, such as the CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. DACs may be used to convert digital activation data into analog input voltages that are applied to the array.

[0019] The output circuit 507 may include circuits such as a current-to-voltage circuit (ITV), an analog-to-digital converter (ADC), an analog-to-analog converter (AAC), an analog-to-pulse converter (APC), or any other type of converter. The output circuit 507 can convert the array output into activation data. The output circuit 507 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 507 may implement one or more of statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) of the neuron output. The output circuit 507 may implement a temperature compensation function for the neuron output or array output (e.g., bit line output) to keep the power consumption of the array approximately constant over temperature changes or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over temperature changes. The output circuit 507 may include registers to store output data. The output circuit 507 may include error correction logic to correct errors from the neuron output. The error correction may be a Hamming code capable of single error correction and double error detection (SECDED). The errors may be from noise, data retention, external disturbances, etc.

[0020] For digital MLC memory storage (e.g., where level separation is typically 12 sigma and can be 4-6 sigma), input circuit 506 need not include analog circuitry such as a D / A converter, scaling, activation function, or arithmetic circuit, and output circuit 507 need not include analog circuitry such as an A / D (analog-to-digital) converter, scaling, activation function, or arithmetic circuit. However, output circuit 507 may require a multi-level sense amplifier circuit to convert the analog output (cell current) from the selected memory cell into digital output bits. For example, the output of a 4-level cell may be represented by 2 digital output bits, and the output of a 16-level cell may be represented by 4 digital output bits.

[0021] The algorithm controller 514 includes an ECC (Error Correction Code) engine 519, which can generate ECC data as described below.

[0022] Referring to FIG. 6, in the prior art, it is common to store data in words, such as word 601, in an array 501 of analog multilevel memory cells (each memory cell can store two or more levels using a range of analog voltages or currents to represent each level) or digital multilevel memory cells (each memory cell can store two or more levels using discrete levels of voltage or current to represent each level). The array includes multiple rows and multiple columns. A word can contain, for example, 128 bits. For single-level cells, 128 bits requires 128 cells to store the information. A row may consist of multiple words. For example, a row of 4096 cells can contain 32 words of 128 bits per word. To select one 128-bit word, one row is selected and 128 of the 4096 columns are selected.

[0023] 6 shows a single exemplary word 601, which in this example includes a particular number of non-volatile memory cells in array 501. The prior art also includes various error detection and error correction schemes that can be implemented by ECC engine 519.

[0024] If the memory system 500 conforms to a NOR memory structure, one error correction scheme that can be applied is a scheme that uses a Hamming code, in which for each group of bits (e.g., word 601), a set of error correction data (e.g., ECC 602) is generated and stored with the group of bits. For example, ECC 602 can be generated by performing a Hamming function on word 601. In this manner, each bit in word 601 is supported by ECC 602. During a read operation, memory system 500 reads word 601 and ECC 602. ECC 602 indicates whether the read word 601 contains an error, and ECC 602 can be used to correct up to one single-bit error (e.g., a "1" erroneously read as a "0" or a "0" erroneously read as a "1"). ECC 602 has limitations. Specifically, in this example, ECC 602 can only be used to correct single-bit errors. If two or more bit errors occur, ECC 602 cannot correct the errors.

[0025] In situations where memory system 500 is used for neural network vector-matrix multiplication, error correction may be performed on digital output bits from output circuit 507, such as from an ADC output. In this case, multiple words in multiple rows may be selected instead of a single word. Also, in this case, multiple cells in multiple rows in a single column may be selected instead of a single cell in a single row in a single column.

[0026] Examples of single-bit errors and multiple-bit errors can be explained with reference to Table 5. Table 5: Multi-level cell allocation [Table 5]

[0027] In the example of Table 5, each cell can store two bits of data, DINO0 and DIN1, which means it can store four analog levels of data. A value of 00 corresponds to a read current of 1 μA, 01 corresponds to 2 μA, 10 corresponds to 3 μA, and 11 corresponds to 4 μA. If a cell is intended to store a 00 value but the sensed current is incorrectly detected as 2 μA instead of 1 μA (single-level error), the data will be interpreted as 01 instead of 00, which contains a single-bit error. If no other errors are present, ECC 601 can be used to correct the 01 to 00. However, if a cell is intended to store a 00 value but the sensed current is incorrectly detected as 4 μA instead of 1 μA (multi-level error, e.g., >2 levels), the data will be interpreted as 11 instead of 00, which contains a two-bit error. ECC 601 cannot correct this data.

[0028] Improved error correction schemes are needed for multi-level memory cells that can correct more than a single bit error or more than two levels of errors. Summary of the Invention

[0029] Numerous examples of improved level assignment and error correction systems for multi-level non-volatile memory cells are disclosed.

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037] [Brief explanation of the drawings]

[0038] [Figure 1] 1 shows a prior art split-gate flash memory cell. [Figure 2] 1 illustrates another prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates a prior art memory system. [Figure 6] 1 shows a prior art word of data and associated ECC data. [Figure 7A] 1 shows an improved error correction system. [Figure 7B] 1 shows an improved error correction system. [Figure 7C] 1 shows an improved error correction system. [Figure 8] 1 illustrates an ECC engine for implementing an improved error correction system. [Figure 9] An example using the ECC engine of FIG. 8 is shown below. DETAILED DESCRIPTION OF THE INVENTION

[0039] 7A, 7B, and 7C show an improved error correction scheme for multi-level non-volatile memory cells.

[0040] 7A and 7B, the data stored in array 501 is divided into subwords, such as halfwords, instead of complete words, and two ECC blocks are generated and stored instead of one ECC block. This example shows halfword 701, halfword 702, ECC block 703 associated with halfword 701, and ECC block 704 associated with halfword 702.

[0041] 7A and 7B, where a word contains n cells, referred to as cell n through cell 0. As an example, one physical cell can store two digital bits. One bit of a halfword in cell n is backed by an ECC code in ECC 703, and one bit of another halfword in cell n is backed by an ECC code in ECC 704. One physical cell contains one bit for halfword 701 and another bit for halfword 702. For example, cell n stores the d bit of halfword 701. n and halfword 702 d n If a cell is intended to store a 00 value, but the sensed current is incorrectly detected as 4 μA instead of 1 μA, the data will be interpreted as 11 instead of 00, which contains a two-bit error. ECC703 is used to correct the first bit error, and ECC704 is used to correct the second bit error, with the end result being that the erroneous value of 11 is corrected to the intended value of 00. This is a significant improvement over the prior art.

[0042] The physical cells that store the ECC bits can be combined in the same way as one physical cell that stores one bit for ECC703 and another bit for ECC704 in the case of a two-bit cell example (one cell can store four levels).

[0043] 7A-7C illustrate a multi-level cell that can store two bits representing four different levels. Those skilled in the art will understand that the same principles can be applied to multi-level cells that store more than two bits by using additional ECC blocks.

[0044] Alternatively, a word may be divided into more than two subwords, for example four subwords, and ECC implemented for each subword. One physical cell contains the bits for all the subwords.

[0045] Alternatively, multiple words can be combined into a superword, which is a structure containing two or more words with ECC implemented on each word. One physical cell contains bits for two or more words.

[0046] These concepts are illustrated in Figure 8. In Figure 8, a system stores data represented by data grouping 801. Data grouping 801 is a collection of bits and may be a word, superword, subword, or any other grouping of data. Data grouping 801 is provided to ECC engine 800 (which is an example of ECC engine 519, which implements the ECC algorithm described herein), which separates data grouping 801 into data groupings 802-n, ..., 802-1. For example, if n = 2, two data groupings 802-2 and 802-1 are generated. If n = 3, three data groupings 802-3, 803-3, and 803-1 are generated. If n = 4, four data groupings 802-4, 803-3, 803-2, and 803-1 are generated. In one example, n also equals the number of bits stored in each memory cell. The ECC engine 800 also generates ECC blocks 803-n, ..., 803-1, and each bit stored in a memory cell is backed by one of the ECC blocks 803-n, ..., 803-1, such that each memory cell in its entirety is collectively backed by the ECC blocks 803-n, ..., 803-1, and each of the ECC blocks backs one bit of each memory cell.

[0047] For example, if data grouping 801 is a word and n=4, four quarter-word groupings (which are sub-word groupings) are generated, namely, data groupings 802-4 (first quarter-word or first sub-word), 802-3 (second quarter-word or second sub-word), 802-2 (third quarter-word or third sub-word), and 802-1 (fourth quarter-word or fourth sub-word), and memory cells store bits from each of data groupings 802-4, 802-3, 802-2, and 802-1. ECC engine 800 also generates ECC blocks 803-4, 803-3, 803-2, and 803-1, and each bit stored in a memory cell is supported by ECC blocks 803-4, 803-3, 803-2, and 803-1, such that each memory cell in its entirety is collectively supported by ECC blocks 803-4, 803-3, 803-2, and 803-1, and each ECC block supports one bit of each memory cell.

[0048] 9 illustrates this example, where memory cell 901 stores a bit from data grouping 802-4 (labeled d(802-4)), a bit from data grouping 802-3 (labeled d(802-3)), a bit from data grouping 802-2 (labeled d(802-2)), and a bit from data grouping 802-1 (labeled d(802-1)), supported by ECC blocks 803-4, 803-3, 803-3, and 803-1, respectively. Under this scheme, up to four bit errors in cell 901 (i.e., a first error, a second error, a third error, and a fourth error) can be corrected by ECC blocks 803-4, 803-3, 803-3, and 803-1.

[0049] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising:

1. A system comprising: a memory array comprising non-volatile memory cells arranged in rows and columns, the non-volatile memory cells of the memory array storing first bits of a first data grouping and second bits of a second data grouping, the first data grouping being backed by a first ECC block and the second data grouping being backed by a second ECC block.

2. 2. The system of claim 1, wherein the first data grouping is a first halfword, the second data grouping is a second halfword, and the first halfword and the second halfword form a word.

3. 2. The system of claim 1, wherein the first data grouping is a first word, the second data grouping is a second word, and the first word and the second word form a superword.

4. 2. The system of claim 1, wherein the first ECC block is capable of correcting a first single-bit error in the non-volatile memory cell and the second ECC block is capable of correcting a second single-bit error in the non-volatile memory cell.

5. 2. The system of claim 1, wherein each non-volatile memory cell of the memory array further stores a third bit of a third data grouping backed by a third ECC block and a fourth bit of a fourth data grouping backed by a fourth ECC block.

6. 6. The system of claim 5, wherein the first group is a first quarter word, the second group is a second quarter word, the third group is a third quarter word, and the fourth group is a fourth quarter word, and the first quarter word, the second quarter word, the third quarter word, and the fourth quarter word form one word.

7. 10. The system of claim 1, wherein the non-volatile memory cells are digital multi-level memory cells.

8. 10. The system of claim 1, wherein the non-volatile memory cells are analog multi-level memory cells.

9. 10. The system of claim 1, wherein the memory array is a vector-matrix multiplication array in a neural network.

10. The system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.

11. The system of claim 1 , wherein the non-volatile memory cells are stacked gate flash memory cells.

12. 1. A system comprising:

1. A system comprising: a memory array comprising non-volatile memory cells arranged in rows and columns, the array storing a plurality of words, each word being divided into a plurality of sub-words, and each non-volatile memory cell in the memory array storing digital bits belonging to a different one of the plurality of sub-words.

13. 13. The system of claim 12, wherein each non-volatile memory cell of the memory array stores a first bit of a first sub-word of the plurality of sub-words and a second bit of a second sub-word of the plurality of sub-words, the first sub-word being backed by a first ECC block and the second sub-word being backed by a second ECC block.

14. 14. The system of claim 13, wherein the first ECC block is capable of correcting a first single-bit error in the non-volatile memory cell and the second ECC block is capable of correcting a second single-bit error in the non-volatile memory cell.

15. 14. The system of claim 13, wherein each non-volatile memory cell further stores a third bit of a third sub-word of the plurality of sub-words and a fourth bit of a fourth sub-word of the plurality of sub-words, the third sub-word being backed by a third ECC block and the fourth sub-word being backed by a fourth ECC block.

16. 13. The system of claim 12, wherein each non-volatile memory cell is a digital multi-level memory cell.

17. 13. The system of claim 12, wherein each non-volatile memory cell is an analog multi-level memory cell.

18. The system of claim 12 , wherein the array is a vector-matrix multiplication array in a neural network.

19. 13. The system of claim 12, wherein each non-volatile memory cell is a split-gate flash memory cell.

20. 13. The system of claim 12, wherein each non-volatile memory cell is a stacked gate flash memory cell.

21. 1. A method comprising: storing a first bit of a first grouping of data in a non-volatile memory cell in the array; storing second bits of a second grouping of data in the non-volatile memory cells; storing ECC data for the first bit in a first ECC block in the array; storing ECC data for the second bits in a second ECC block in the array; A method comprising:

22. 22. The method of claim 21, wherein the first group is a first halfword, the second group is a second halfword, and the first halfword and the second halfword form a word.

23. 22. The method of claim 21, wherein the first group is a first word, the second group is a second word, and the first word and the second word form a superword.

24. 22. The method of claim 21, wherein the first ECC block is capable of correcting a first single bit error in the non-volatile memory cell and the second ECC block is capable of correcting a second single bit error in the non-volatile memory cell.

25. storing a third bit of a third data grouping in the non-volatile memory cells; storing a fourth bit of a fourth data grouping in the non-volatile memory cells; storing ECC data for the third bit in a third ECC block in the array; storing ECC data for the fourth bit in a fourth ECC block in the array.

26. 26. The method of claim 25, wherein the first data grouping is a first quarter word, the second data grouping is a second quarter word, the third data grouping is a third quarter word, the fourth data grouping is a fourth quarter word, and the first quarter word, the second quarter word, the third quarter word, and the fourth quarter word form a word.

27. 22. The method of claim 21, wherein the non-volatile memory cells are digital multi-level memory cells.

28. 22. The method of claim 21, wherein the non-volatile memory cells are analog multi-level memory cells.

29. 22. The method of claim 21, wherein the array is a vector-matrix multiplication array in a neural network.

30. 22. The method of claim 21, wherein the non-volatile memory cells are split-gate flash memory cells.

31. 22. The method of claim 21, wherein the non-volatile memory cells are stacked gate flash memory cells.

32. 1. A method comprising:

1. A method comprising: storing a plurality of words in a memory array comprising non-volatile memory cells arranged in rows and columns, each of the plurality of words being divided into a plurality of sub-words, each of the non-volatile memory cells storing a plurality of digital bits belonging to a different sub-word.

33. storing ECC data for a first bit of the plurality of digital bits in a first ECC block in the array; storing ECC data for a second bit of the plurality of digital bits in a second ECC block in the array.

34. correcting a first error in one bit of the plurality of digital bits using the first ECC block; and correcting a second error in one bit of the plurality of digital bits in the non-volatile memory cell using the second ECC block.

35. storing ECC data for a third bit of the plurality of digital bits in a third ECC block in the array; storing ECC data for a fourth bit of the plurality of digital bits in a fourth ECC block in the array.

36. correcting a third error in one bit of the plurality of digital bits using the third ECC block; and correcting a fourth error in one bit of the plurality of digital bits in the non-volatile memory cell using the fourth ECC block.

37. 33. The method of claim 32, wherein the non-volatile memory cells are digital multi-level memory cells.

38. 33. The method of claim 32, wherein the non-volatile memory cells are analog multi-level memory cells.

39. 33. The method of claim 32, wherein the array is a vector matrix multiplication array in a neural network.

40. 33. The method of claim 32, wherein the non-volatile memory cells are split-gate flash memory cells.

41. 33. The method of claim 32, wherein the non-volatile memory cells are stacked gate flash memory cells.

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