Delay Locked Loop Offset Calibration and Correction

Abstract

A clock circuit is provided using a master delay-locked loop (DLL) and a slave DLL. The master DLL code indicates the delay adjustment made in the master DLL. The delay of the slave DLL is adjusted based on the master DLL code. A replica phase detector in the slave DLL is temporarily enabled during interface idle periods. The slave DLL code is determined, and a configuration value for the master DLL code is determined based on the slave DLL code. The replica phase detector is then disabled.

Description

[Background technology]

[0001] In order for a memory controller, such as a dynamic random-access memory (DRAM) controller, to properly capture the data being sent from the DRAM, the DRAM controller typically frequently uses a delay-locked loop (DLL) circuit to adjust the read clock or strobe signal from the DRAM so that it can be used to properly latch the input data (DQ) signals. For similar reasons, DRAM controllers utilize DLL circuits to center outgoing data on the transitions of the memory's write clock.

[0002] A DLL locks to a reference clock signal to keep the delay of the DLL output signal substantially constant over process, voltage, and temperature variations. Some DLLs maintain a continuous lock to the reference signal, while others intermittently lock to the reference signal, continuously using the loop filter voltage to set their delay because this voltage varies slowly.

[0003] In some DRAM systems, such as graphics double data rate (GDDR) systems, the read clock is configured as a strobe, activated only to fulfill a read command and otherwise idle to conserve power on the DRAM interface. A DLL is typically used at the receiver of each data lane to provide a consistent clock signal based on the received read clock. During idle periods, when no read clock signal is received, the DLL does not operate normally; therefore, the voltage and temperature conditions of the receiver's DLL can drift significantly from their original values ​​without being compensated for. Such drift makes maintaining lock at the DLL more time-consuming and difficult. [Brief explanation of the drawings]

[0004] [Figure 1] 1 is a block diagram of a delay-locked loop (DLL) clock circuit according to the prior art. [Figure 2] 2 is a block diagram of a DLL clock circuit 200 according to some embodiments. [Figure 3] 1A and 1B are circuit and block diagrams of a DLL clock circuit, according to some embodiments. [Figure 4] 1 is a flowchart of a process for operating a DLL clock circuit according to some embodiments. [Figure 5] 5 is a block diagram of a portion of a data processing system 500 according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following description, the use of the same reference numerals in different figures indicates similar or identical items. Unless otherwise stated, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means known in the art, and unless otherwise stated, any description of a direct connection also refers to an alternative embodiment using a suitable form of indirect electrical connection.

[0006] A clock circuit for a communications link includes a master delay-locked loop (DLL) circuit, a slave DLL circuit, and an arbiter circuit. The master DLL circuit includes a plurality of delay elements arranged in series between its input and output, and a phase detector circuit coupled to the input and output for detecting a phase offset and providing a master DLL code for adjusting the delay elements of the master DLL. The slave DLL circuit provides an oscillator signal to a receiver of the communications link. The slave DLL includes a plurality of delay elements arranged in series between its input and output, and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL. The arbiter circuit is operable to temporarily enable the replica phase detector of the slave DLL during idle periods of the communications link to update a configuration value based on the master DLL code and the slave DLL code, and to adjust the delay elements of the slave DLL during active periods of the communications link based on the configuration value and the master DLL code.

[0007] A method for operating an interface circuit is provided. The method includes providing a master delay-locked loop (DLL) lock value indicative of a delay adjustment made in a master DLL. The method includes adjusting a delay of a slave DLL based on a master DLL code. The method includes temporarily enabling a replica phase detector in the slave DLL during an interface idle period, determining the slave DLL code, determining a configuration value for the master DLL code based on the slave DLL code, and then disabling the replica phase detector.

[0008] The data processing system includes a data processor, a memory coupled to the data processor by a communications link, and a clock circuit for the communications link. The clock circuit includes a master DLL circuit, a slave DLL circuit, and an arbiter circuit. The master DLL circuit includes a plurality of delay elements arranged in series between its input and output, and a phase detector circuit coupled to the input and output for detecting a phase offset and providing a master DLL code for adjusting the delay elements of the master DLL. The slave DLL circuit provides an oscillator signal to a receiver of the communications link. The slave DLL includes a plurality of delay elements arranged in series between its input and output, and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL. The arbiter circuit is operable to temporarily enable the replica phase detector of the slave DLL during idle periods of the communications link to update a configuration value based on the master DLL code and the slave DLL code, and to adjust the delay elements of the slave DLL during active periods of the communications link based on the configuration value and the master DLL code.

[0009] 1 is a block diagram of a prior art delay-locked loop (DLL) clock circuit 100. DLL clock circuit 100 includes a primary or master DLL 110, a phase detector 115, and a secondary or slave DLL 120.

[0010] Generally, slave DLL 120 has an input that receives a strobe clock, such as a GDDR read clock (RCK), an input that receives a lock code from phase detector 115, and an output that provides a phase-shifted or multi-phase version of the strobe clock. Master DLL 110 has an input that receives a reference clock, typically set to the expected frequency of the strobe clock, an input that receives a lock code from phase detector 115, and an output connected to the input of phase detector 115. Phase detector 115 detects the phase difference between the input and output of master DLL 110 and provides a phase-lock code that controls one or more delay elements in master DLL 110 to stabilize the phase of master DLL 110. This phase-lock code is then used to stabilize slave DLL 120 without the need for a phase detector in slave DLL 120. Generally, multiple slave DLLs are placed near master DLL 110 and connected to phase detector 115 to receive the phase-lock code. This architecture allows multiple slave DLLs to each provide a clock signal to local circuitry, typically a receiver circuitry, without requiring a phase detector circuit.

[0011] DLL clock circuit 100 is often used in communication interfaces, such as memory interfaces, where the read or write clock operates in burst or strobe mode to improve power efficiency. Specifically, to improve power efficiency, the clock is turned off in low-power or idle states where no data is being transmitted or received. However, the slave DLL clock must be turned back on as quickly as possible during the transition from idle to active mode. Rapid clock turn-on to active mode upon exiting idle mode is one major design challenge for burst-mode systems. In the illustrated conventional slave DLL implementation, slave DLL 120 operates as an open-loop circuit by using the lock code from the master DLL in both active and idle states. As a result, conventional implementations of open-loop slave DLLs can have significant offsets between the master and slave DLLs, which can cause timing errors or clock integrity issues due to factors such as random device mismatches, supply / ground voltage differences, and thermal gradient differences. These factors can change over time as the circuit operates.

[0012] 2 is a block diagram of a DLL clock circuit 200 according to some embodiments. DLL clock circuit 200 includes a primary or master DLL 110, a phase detector 215, a secondary or slave DLL 220, and a replica phase detector and arbiter circuit 230. DLL clock circuit 200 is generally implemented in the physical layer circuitry (PHY) of an integrated circuit, such as a system-on-chip, data processor, or graphics processor, to provide a clock signal to an interface circuit, such as a memory bus interface.

[0013] Master DLL 210 has an input that receives a reference clock labeled "Reference Clk," an input that receives a lock code from phase detector 215, and an output that provides a delayed version of the input signal to the input of phase detector 215. Phase detector 215 detects the phase difference between the input and output of master DLL 210 and provides the phase lock code to control one or more delay elements within master DLL 210 to stabilize the phase of master DLL 210.

[0014] Slave DLL 220 has an input labeled "Strobe Clk" that receives a strobe clock, such as the GDDR read clock (RCK), and an output labeled "Phase-Shifted or Multi-Phase Strobe Clock" that provides a phase-shifted or multi-phase version of the strobe clock. Replica phase detector and arbiter circuit 230 includes two inputs connected to the input and output of slave DLL 220, an input that receives the lock code from phase detector 215, and an output connected to slave DLL 220.

[0015] During operation, the DLL clock circuit 200 activates a duplicate phase detector to temporarily create a local replica feedback loop for the slave DLL 220 via the phase detector and arbiter circuit 230 and performs an offset correction calibration to cancel offsets between the master DLL 210 and the slave DLL 220, improving performance. The arbiter circuit is operable to temporarily enable the replica phase detector both during initial calibration and during idle periods of the communication link to update configuration values ​​based on the master DLL lock code and the slave DLL lock code. A reference clock is provided to the input of the slave DLL 220 to perform the initial calibration and update the configuration values. The replica phase detector is then disabled and the reference clock signal is removed. During active periods of the communication link, when a strobe clock signal is present, the delay elements of the slave DLL are adjusted based on the configuration values ​​and the master DLL code.

[0016] Although one slave DLL is shown, typically many slave DLLs exist and are coupled to master DLL 210 in a similar manner to perform such calibration. The local replica feedback loop of slave DLL 220 can be continuously on in active mode when the input strobe clock is available, while in idle mode when the input clock is absent, the loop can be open. The arbiter circuit of replica phase detector and arbiter circuit 230 is used to combine information from the offset correction loop of slave DLL 220 with locked information from master DLL 210 to reduce or cancel the offset between the two DLLs and improve performance.

[0017] In some embodiments, DLL clock circuit 200 can also perform continuous slave DLL offset correction in the active state. The local replica feedback loop through replica phase detector and arbiter circuit 230 can be continuously on in the active state when the input strobe clock is available, while in idle mode when the input strobe clock is absent, the replica loop is disabled. In idle mode, slave DLL 220 relies on locked information updates from master DLL 210 because its feedback loop is open.

[0018] 3 is a circuit diagram and block diagram of a DLL clock circuit 300 according to some embodiments. DLL clock circuit 300 includes a primary or master DLL 310, a phase detector 315, a secondary or slave DLL 320, and a phase detector and arbiter circuit 330. DLL clock circuit 300 is shown coupled to two phase interpolator (PI) blocks 340 and 345 to illustrate how the output signal of master DLL 310 may be employed in some embodiments. DLL clock circuit 300 is one exemplary embodiment of circuit 200 of FIG. 2 , embodied on an integrated circuit.

[0019] The master DLL 310 includes a first delay line 302, a second delay line 304, a multiplexer 305, two analog bias loop circuits 306 and 308, and a master digital-to-analog converter (DAC) 314. The master DLL 310 includes an input that receives a reference clock signal "PLL_ref_clk," an input that receives a range select signal labeled "range_h," an input that receives a range select signal labeled "range_l," and an output.

[0020] In this embodiment, the first delay line 302 is an ultra-low voltage threshold (ULVT) delay line containing several delay elements, typically a series of complementary metal-oxide semiconductor (CMOS) inverters constructed with ULVT transistors. The first delay line 302 is used for the higher frequency clock signal and has an input that receives an enable signal labeled "range_h." The second delay line 304 is a low voltage threshold (LVT) delay line containing several delay elements constructed with LVT transistors and has an input that receives an enable signal labeled "range_l." The PLL_ref_clk signal is provided to the inputs of the first delay line 302 and the second delay line 304. The output of each delay line—in this example, a group of five clock signals, each with a different phase—is provided to a multiplexer 305, which selects which group to pass to the PLL output based on the value of the range_h signal. In this embodiment, two separate range delay lines are used for high and low frequencies, although in other embodiments where a narrow range of operation is expected, a single delay line may be used. Furthermore, although two different types of devices (LVT and ULVT) are shown in this embodiment, in other embodiments the second delay line 304 may be implemented using ULVT transistors having a channel length longer than the channel length of the first delay line 302.

[0021] Master DAC 314 has an input connected to master DLL logic 313 and an output connected to the inputs of analog bias loop 306 and analog bias loop 308. Analog bias loop 306 generates analog bias voltages that are supplied to the delay elements of first delay line 302. Similarly, analog bias loop 308 generates analog bias voltages that are supplied to the delay elements of second delay line 304. Separate analog bias voltages are supplied to both the p-type and n-type portions of the delay elements to adjust the delay of the delay elements.

[0022] Phase detector 315 includes multiplexer 311, a "bang-bang" (BB) phase detector 312, master DLL logic circuitry 313, and an input that receives an enable signal labeled "master_pd_en." Multiplexer 311 has an input that receives the PLL_ref_clk signal, an input coupled to ground or a VSS voltage, and an output that selectively passes either input based on the value of enable signal master_pd_en. BB phase detector 312 has an input connected to the output of multiplexer 311, an input connected to the initial output (phase 0) of multiplexer 305, and an output that provides an up-down signal labeled "updown_m." Master DLL logic 313 has an input that receives the updown_m signal and an output connected to an input of master DAC 314 to provide a master lock code signal labeled "Master_lock_code." The master DLL logic 313 includes digital circuitry to low pass filter the updown_m signal and generate a lock code that digitally represents the DAC input that generates the lock for the master DLL 310 .

[0023] Slave DLL 320 includes a first delay line 322, a second delay line 324, a multiplexer 325, two analog bias loop circuits 326 and 328, and a slave digital-to-analog converter (DAC) 334. Slave DLL 320 also includes an input for receiving a clock or strobe signal "Slave_clk," an input for receiving a range select signal range_h, an input for receiving a range select signal range_l, and an output.

[0024] Slave DLL 320 is preferably constructed similarly to master DLL 310, except that the first delay line 322 is implemented as an LVT delay line containing several delay elements, typically CMOS inverters. The first delay line 322 is used for the higher-frequency clock signal and has an input that receives an enable signal labeled range_h. The second delay line 324 is an LVT delay line containing several delay elements and has an input that receives an enable signal labeled range_l. The Slave_clk signal is provided to the inputs of the first delay line 322 and the second delay line 324. The output of each delay line—in this example, a group of five clock signals, each with a different phase—is provided to multiplexer 325, which selects which group to pass to the PLL output based on the value of the range_h signal. As shown on the right, in this embodiment, the multiphase outputs of slave DLL 320 provide quadrature clock signals to the PI circuit of the DQ receiver in the memory interface PHY circuit. In other embodiments, the output of slave DLL 320 may provide a clock signal to other interface circuits.

[0025] The phase detector and arbiter circuit 330 includes a multiplexer 331, a calibration circuit 332, a slave DLL logic circuit 333, an offset register labeled "offset," a weight register labeled "weight," an input for receiving a lock code signal Master_lock_code, an input for receiving a Slave_clk signal, an input for receiving a PLL_ref_clk signal, and an input for receiving an enable signal labeled "slave_pd_en."

[0026] Multiplexer 331 has an input that receives the PLL_ref_clk signal, an input that receives the Slave_clk signal, and an output that selectively passes either input based on the value of enable signal slave_pd_en. Calibration circuit 332 has an input connected to the output of multiplexer 331, an input connected to the initial output (phase 0) of multiplexer 325, and an output that provides an up-down signal labeled "updown_s." Calibration circuit 332 includes a replica BB phase detector that is used to perform phase detection using the PLL_ref_clk signal, similar to BB phase detector 312, during calibration and calibration updates to generate a calibration value. In this embodiment, the calibration value is an offset value that is stored in an offset register, as described further below. Calibration circuit 332 can also provide continuous closed-loop operation using the Slave_clk signal in situations where open-loop operation is undesirable, i.e., allowing slave DLL 320 to operate as a normal DLL rather than a slave DLL.

[0027] The slave DLL logic circuit 333 has an input for receiving the Master_lock_code signal, an input for receiving the updown_s signal, an input connected to an offset register, an input connected to a weight register, and an output connected to the input of the master DAC 314. The slave DLL logic 333 includes digital circuitry for low-pass filtering the updown_s signal during the calibration and update process to generate a lock code that digitally represents the DAC input that generates the lock for the slave DLL 320. This circuitry is also active during closed-loop operation, in some embodiments. This circuitry measures and stores the difference between Master_lock_code and Slave_lock_code during closed-loop operation when the replica slave DLL phase detector is enabled. The slave DLL logic 333 includes digital circuitry for applying a value from the offset register during open-loop operation to offset the value of Master_lock_code to generate the value of Slave_lock_code for open-loop operation. In this operation, the offset value is added to the value of Master_lock_code. In some embodiments, the value in the weight register is also used to scale the offset value before addition. The values ​​in the weight registers are preferably determined by characterization of the circuit during manufacturing or an initial training process, but in some embodiments may be updated during operation by a training process.

[0028] The operation of DLL clock circuit 300 is further described with reference to the flowchart of Figure 4, which shows a flowchart 400 of a process for operating a DLL clock circuit according to some embodiments. The illustrated process is implemented by a DLL clock circuit such as that shown in Figure 2 or 3, or other suitable clock circuit, under the control of a power state controller or initialization controller that controls the initialization of the associated PHY circuit to which the slave DLL provides a clock signal. The process is executed during the initialization and operation of the associated PHY circuit.

[0029] At block 402, the process begins initialization and calibration of the master DLL and the slave DLLs controlled by the master DLL. At block 404, the process enables the replica phase detector in each slave DLL for operation in closed-loop mode and acquires the slave DLL lock code from closed-loop mode operation. This calibration is performed with the Slave_clk signal active.

[0030] In block 406, the process calculates an offset between the master DLL lock code and the slave DLL lock code. This offset is stored in an offset register (FIG. 3) or other suitable storage circuitry maintained during idle periods of the associated communication link, which in this exemplary embodiment is a DQ receive circuit configuration. While an offset value is shown here, another suitable configuration value, such as a fractional ratio or percentage, can be calculated based on the master DLL lock code and the slave DLL lock code. The offset is unique to each slave DLL. In some embodiments, the process has the ability to generate a negative value of the offset for use in bidirectional mode, where the slave DLL provides the lock code used by the master.

[0031] In block 408, weighting coefficients may also be configured as in the weight registers (FIG. 3). This operation may include loading weighting coefficient values ​​from firmware or calculating such values ​​based on training. Some embodiments may not use weighting coefficients. Weighting coefficient values ​​are preferably unique to each slave DLL, as they depend on local voltage, temperature, and process variations in and around each slave DLL circuit.

[0032] At block 410, the process disables the replica phase detector of the slave DLL, placing the slave DLL in open-loop mode operation. At block 412, the slave DLL for the RCK signal provided to the receiver circuitry of the PHY, in this example, is operated in open-loop mode, and DLL adjustments are made based on the master DLL lock code and the offset and weight values ​​determined during the calibration process. This open-loop mode operation continues until, at block 414, the process enters an idle period of the RCK signal, meaning that no read operations are occurring and the RCK strobe signal is stopped. Although described here for use with the RCK signal, this process can be used with other interface circuit clock signals, as discussed above.

[0033] Upon entering the idle period at block 414, the process proceeds to block 420, where the slave DLL is inactive because no RCK signal is provided. In block 420, the process waits for a specified period of time and then enters a periodic calibration mode in which the slave DLL's offset value is updated (blocks 422-428). If the idle period ends while waiting in idle mode, the process at block 421 returns to block 412 for open-loop operation of the slave DLL with the updated offset value. Note that idle time can vary significantly during operation, and therefore thermal and voltage conditions can change significantly during the idle period. The idle period is preferably configured to capture typical periods during which thermal and voltage conditions change.

[0034] After the specified period of time, the process proceeds to block 422 and initiates a configuration update similar to the original configuration of the slave DLL. A replica phase detector is enabled and the master DLL reference clock (e.g., PLL_ref_clk in FIG. 3) is provided to the slave DLL. This updated value is saved in an offset register. At block 424, the offset between the master DLL lock code and the slave DLL lock code is calculated. At optional block 426, the weighting coefficients may also be updated. Following the configuration update, the process returns to block 420 to wait for the end of the idle period or the expiration of another periodic configuration update.

[0035] 5 is a block diagram of a portion of a data processing system 500, according to some embodiments. The depicted portion of the data processing system includes one or more data processors 501, such as a central processing unit (CPU), graphics processing unit (GPU), or accelerated processing unit (APU). The data processor 500 accesses DRAM 540, e.g., GDDR7 DRAM, via a memory controller 520 and a PHY circuit 530. The PHY circuit 530 includes a master DLL circuit 503, three receiver circuits 504, 506, and 508, and three transmitter circuits 510, 512, and 514, all for a particular memory channel. The master DLL circuit 503 may also provide clock signals for one or more additional memory channels. Various other portions of the circuitry are not included to avoid obscuring the clock configuration.

[0036] Each of the receivers 504, 506, and 508 includes four phase interpolators labeled "PI." Slave DLL circuits 505, 507, and 509 provide clock signals to the PIs within their respective receivers. Similarly, in this embodiment, each of the transmitters 510, 512, and 514 includes four phase interpolators labeled "PI." Slave DLL circuits 511, 513, and 515 provide clock signals to the PIs within their respective transmitters.

[0037] The illustrated slave DLL circuits 505, 507, 509 are constructed according to the slave DLL circuits of Figure 2 or Figure 3. The transmitter slave DLL circuits may be similarly constructed or may be constructed to operate solely in an open-loop configuration.

[0038] 4 to update their calibration during receiver idle periods in the absence of a read clock signal. In some embodiments, the DLL replica control signals for the receiver and transmitter slave DLL replicas PD may be generated in response to read and write commands, respectively, dispatched from memory controller 520.

[0039] Thus, a clock circuit, system, and method have been described that uses a local arbiter to combine information from a local slave DLL offset correction loop with locked information from a master DLL to effectively cancel offsets between the two DLLs and track power supply and temperature drift in idle mode for improved performance. While this exemplary application of the circuits and techniques is provided herein, the same techniques are applicable to other receiver and transmitter circuits.

[0040] DLL clock circuit 200, DLL clock circuit 300, or any portion thereof, may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, the data structure may be a behavioral or register transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that comprises the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0041] While specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, other communication links that would benefit from a slave DLL circuit may employ the circuits and processes herein. Furthermore, while this circuit is useful for clocking strobed clock signals, such as the RCK signal used in various GDDR memory standards, the circuits herein may be used for non-strobed signals, such as a continuous read clock signal, and gating may be applied to the read clock signal to provide an idle mode for the slave DLL in the PHY.

[0042] Therefore, it is intended that the appended claims cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. 1. A method for operating an interface circuit, comprising: providing a master delay locked loop (DLL) lock value indicative of a delay adjustment made in a master DLL; adjusting the delay of the slave DLL based on the master DLL code; temporarily enabling a replica phase detector in the slave DLL during an interface idle period, determining a slave DLL code, determining a configuration value for the master DLL code based on the slave DLL code, and disabling the replica phase detector. method.

2. the configuration value is based on an offset between the master DLL code and the slave DLL code; 10. The method of claim 1.

3. applying a weighting factor to the configuration value when adjusting the delay elements of the slave DLL. The method of claim 2.

4. adjusting the delay of the slave DLL based on the master DLL code includes providing a bias voltage to a delay element of the slave DLL based on the master DLL code and the configuration value; 10. The method of claim 1.

5. saving the configuration values ​​to register settings that are maintained during the interface idle period; 10. The method of claim 1.

6. 1. A clock circuit for a communications link, comprising: a master delay locked loop (DLL) circuit comprising a plurality of delay elements and a phase detector circuit for detecting a phase offset and providing a master DLL code for adjusting the delay elements of the master DLL circuit; a slave DLL circuit for providing an oscillator signal to a receiver of the communications link, the slave DLL circuit comprising a plurality of delay elements and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL circuit; an arbiter circuit operable to temporarily enable the replica phase detector circuit of the slave DLL circuit during idle periods of the communication link to update configuration values ​​based on the master DLL code and the slave DLL code. Clock circuit.

7. the arbiter circuit is operable to adjust the delay elements of the slave DLL circuit during an active period of the communication link based on the configuration value and the master DLL code; the configuration value is based on an offset between the master DLL code and the slave DLL code; 7. The clock circuit of claim 6.

8. the arbiter circuit applies a weighting factor to the configuration value when adjusting the delay element of the slave DLL circuit.

8. The clock circuit of claim 7.

9. the master DLL circuit includes a digital-to-analog converter (DAC) for providing bias voltages to its delay elements based on the master DLL code; the slave DLL circuit includes a DAC for providing a bias voltage to its delay elements based on the master DLL code and the configuration value; 8. The clock circuit of claim 7.

10. The replica phase detector comprises: a phase detector providing an up / down signal indicating whether the delay of the delay element should be increased or decreased; a digital logic circuit for generating the slave DLL code based on the up / down signal; 10. The clock circuit of claim 9.

11. the arbiter circuit is operable to perform an initial calibration process to determine the configuration values ​​for storing the configuration values ​​by enabling the replica phase detector circuit and generating the configuration values ​​based on the master DLL code and the slave DLL code.

7. The clock circuit of claim 6.

12. the arbiter circuit is operable to store the configuration values ​​in register settings that are maintained during the idle period; 7. The clock circuit of claim 6.

13. there are multiple instances of the slave DLL circuit, each providing an oscillator signal to a phase interpolator of a respective receiver circuit for a respective data (DQ) signal of a memory interface; 7. The clock circuit of claim 6.

14. 1. A data processing system comprising: A data processor; a memory coupled to said data processor by a communications link; a clock circuit for the communication link; The clock circuit a master delay locked loop (DLL) circuit comprising a plurality of delay elements and a phase detector circuit for detecting a phase offset and providing a master DLL code for adjusting the delay elements of the master DLL circuit; a slave DLL circuit for providing an oscillator signal to a receiver of the communications link, the slave DLL circuit comprising a plurality of delay elements and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL circuit; an arbiter circuit operable to temporarily enable the replica phase detector circuit of the slave DLL circuit during idle periods of the communication link to update configuration values ​​based on the master DLL code and the slave DLL code. Data processing system.

15. the arbiter circuit is operable to adjust the delay elements of the slave DLL circuit during an active period of the communication link based on the configuration value and the master DLL code; the configuration value is based on an offset between the master DLL code and the slave DLL code; 15. The data processing system of claim 14.

16. the arbiter circuit applies a weighting factor to the configuration value when adjusting the delay element of the slave DLL circuit.

16. The data processing system of claim 15.

17. the master DLL circuit comprising a digital-to-analog converter (DAC) for providing bias voltages to its delay elements based on the master DLL code; the slave DLL circuit comprising a DAC for providing a bias voltage to its delay elements based on the master DLL code and the configuration value; 16. The data processing system of claim 15.

18. The replica phase detector comprises: a phase detector providing an up / down signal indicating whether the delay of the delay element should be increased or decreased; a digital logic circuit for generating the slave DLL code based on the up / down signal; 20. The data processing system of claim 17.

19. the arbiter circuit is operable to store the configuration values ​​in register settings that are maintained during the idle period; 15. The data processing system of claim 14.

20. there are multiple instances of the slave DLL circuit, each providing an oscillator signal to a phase interpolator of a respective receiver circuit for a respective data (DQ) signal of a memory interface; 15. The data processing system of claim 14.

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