Fast mapper restoration method, system, and processor core

Abstract

A method for restoring a mapper of a processor core is provided, comprising: storing first information in a staging latch, the first information representing a newly dispatched first instruction of the processor core, and stored in an entry latch of a save and restore buffer. In response to receiving a flush command for the processor core, restoring the mapper with the first information from the staging latch is initiated without waiting to compare a flash tag of the flush command with the entry latch of the save and restore buffer. A processor core configured to perform the above method is also provided. A processor core is also provided, comprising a dispatch, a mapper, a save and restore buffer having an entry latch and connected to the mapper via at least one pipeline, and a register disposed in the at least one pipeline. (Figure 3)

Description

[Background technology]

[0001] The present invention relates generally to processors used in computer systems that read and execute software code input into the processor. Such processors are used on computer chips implemented in computer systems such as personal computers, servers, and / or other computers. The processor executes the software code by accessing instructions from the code and executing those instructions.

[0002] In processor designs, mappings, i.e., logical-to-physical mappings, are read from the mapper as required by dispatched instructions. The mapper also provides new physical mappings for the logical destinations required by the instruction. Dispatched instructions are written to the mapper, and this write to the mapper causes the prior mapper state to be written for safekeeping to a save-and-restore buffer (SRB). This saving of the prior mapper state is for use in the event that an instruction is flushed out before it can be completed. Flushing instructions may be necessary due to a branch misprediction or an exception event. When an instruction is flushed, the flushed destination in the mapper must be restored to the previous state that the mapper held before the flush. This restoration is a return to the correct state to allow proper execution of instructions. This restoration must occur before dispatching of new instructions can resume. This creates a race condition between (1) the newly refetched instructions coming down from the I-cache after the flush and (2) the save-and-restore buffer restoring the mapper to its previous state. If it takes too long to restore the previous destination to the mapper, new instructions coming down from the I-cache will have to stall in dispatch until the mapper is fully restored. This stall in dispatch hurts performance.

[0003] In the paper "Speculative Restore of History Buffer in a Microprocessor" from ip.com (ip.com number: IPCOM000250357D), a register recovery pipeline is disclosed that involves checking all entries in the history buffer when faced with a branch flush and determining that its evictor has been flushed. If an evictor is flushed, the previous producer instruction tag data must be recovered. If the evictor is newer than the flush and the producer entry instruction tag is older than the flush, the entry is restored. The collection of the entry may set a status bit. An entry may be selected from the restore pending entries. The entry is broadcast to the issue queue and to the mapper to recover the data and instruction tag back to the register file.

[0004] The process in this ip.com paper improves save and restore buffer latency, but does so by assuming full flush handling.

[0005] Speeding up the save and restore buffers has also been achieved by adding additional restore ports to the mapper.

[0006] However, adding more restoration ports is expensive in terms of power and congestion. Summary of the Invention

[0007] A method is provided for restoring a mapper of a processor core. First information is stored in a staging latch. The first information represents a newly dispatched first instruction of the processor core. The first information is also stored in an entry latch of a save and restore buffer of the processor core. In response to receiving a flush command for the processor core, mapper restoration is initiated with the first information from the staging latch without waiting to compare a flash tag of the flush command with the entry latch of the save and restore buffer. A processor core configured to perform the above method is also provided.

[0008] These embodiments provide a novel way to speed up restore after a flush that avoids the need to add an additional expensive restore port. These embodiments improve restore latency with a low overhead mechanism.

[0009] In another embodiment, a processor core is provided, including a dispatcher, a mapper, a save and restore buffer having an entry latch and connected to the mapper via at least one pipeline, and a first register disposed in the at least one pipeline. The processor core is configured to store first information in the register. The first information represents a newly dispatched first instruction from the dispatcher. The processor core is also configured to store the first information in the entry latch of the save and restore buffer. The processor is also configured to restore the first instruction in the mapper using the first information stored in the first register in the at least one pipeline in response to receiving a flush command for the processor core.

[0010] This embodiment speeds up restore after a flush in a manner that avoids the requirement to add additional expensive wires between design entities for the restore port. These embodiments improve restore latency with a low overhead mechanism.

[0011] In at least some further embodiments, in response to a dispatch of a second instruction after the dispatch of the first instruction, the first information is transferred from the staging latch into another staging latch, second information representing the second instruction is stored in the staging latch, and the second information is stored in another entry latch of the save and restore buffer. Further in response to receiving a flush command from the processor core, restore of the mapper also proceeds with the second information from the staging latch without waiting to compare the flash tag of the flush command with the other entry latch of the save and restore buffer.

[0012] In this embodiment, restore after a flush can be sped up by at least two processor cycles. This speedup of only two processor cycles allows restore latency to be improved without adding additional expensive restore ports, e.g., without adding additional wires running between design elements.

[0013] In at least some further embodiments, the transfer of the first information from the staging latch into the other staging latch occurs in a direction against the mapper restore direction of the restore pipe.

[0014] In these further embodiments, the maximum assumption of relevance for mapper restoration may be placed on the most recently dispatched instruction rather than the second most recently dispatched instruction.

[0015] In at least some further embodiments, further in response to receiving the flush command, the first information is marked as restored in an entry latch of the save and restore buffer.

[0016] In these embodiments, redundant restore actions are avoided, which can help reduce or eliminate unnecessary energy consumption for the processor core during the flash restore process.

[0017] In at least some further embodiments, the first information is cleared from the staging latch in response to completion of a flush corresponding to the flush command or completion of the first information in the mapper.

[0018] In these embodiments, the accuracy of the expedited flash restore may be improved if the mapper is restored to a pre-error state. [Brief explanation of the drawings]

[0019] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. The illustrations are for clarity in facilitating understanding of the invention by those skilled in the art, together with the detailed description, and various features of the drawings are not to scale. In the drawings:

[0020] [Figure 1] FIG. 1 is a block diagram illustrating a processing system according to at least one embodiment.

[0021] [Figure 2] 2 is a block diagram illustrating portions of an accelerated flash restore processor core implemented in one or more of the processors of the processing system shown in FIG. 1 according to at least one embodiment.

[0022] [Figure 3] 3 is a processor pipeline diagram illustrating an accelerated flash restore process performed by the accelerated flash restore processor core shown in FIG. 2, according to at least one embodiment.

[0023] [Figure 4] 2 is a block diagram illustrating portions of an alternative accelerated flash restore processor core implemented in one or more of the processors of the processing system shown in FIG. 1 , according to at least one embodiment.

[0024] [Figure 5] 5 is a processor pipeline diagram illustrating an alternative accelerated flash restore process performed by the alternative accelerated flash restore processor core shown in FIG. 4, according to at least one embodiment.

[0025] [Figure 6] FIG. 10 is a block diagram illustrating a computing environment with multiple computing systems in which the accelerated flash restore processor core shown in FIGS. 2 and / or 4 and the processor pipeline diagrams of FIGS. 3 and / or 5 may be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0026] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. The present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0027] Exemplary embodiments described below provide a processor, a computer system, and a method for operating a processor that increases the latency of the restore process associated with flushing, thereby increasing overall computer processing speed. Restoration in the save and restore buffer is accelerated due to a design evolution based on the observation that the most recently dispatched instructions are most likely to be flushed. By restoring the most recently dispatched instructions first, the time required for flush restoration is reduced without the need to compare instruction tags with the save and restore buffer's entry latches. This speculative restore process can be accelerated by one or more cycles, e.g., two or more cycles, from flushing the save and restore buffer. These cycles may refer to processor core clock cycles. The accelerated flush restore can allow one or more cycles of dispatch pending to be avoided.

[0028] This latency speedup is achieved by storing newly dispatched instructions in one or more staging latches, for example, a series of staging latches for two cycles, while these instructions are also written to the entry latches of the save and restore buffer. These staging latches are part of and / or adjacent to the restore pipe between the entry latches of the save and restore buffer and the mapper. The staging latches may be instances of the respective register states. These staging latches may be flush+1 cycle and flush+2 cycle latches. When a flush occurs, instructions from these staging latches are compared with a flushed mask to determine whether they have been flushed. Identified flushed instructions from these stages are restored first, while the rest of the destinations in the entry latches of the save and restore buffer are processed for restoration. Instructions to be restored from these stages are multiplexed to the buffer restore port without needing to be compared with the instruction tags from the entry latches of the save and restore buffer. This allows the mapper's restore process to start one or more cycles earlier. This use of the most recently dispatched instructions in these staging latches prioritizes information representing the most recently dispatched instruction or instructions in the flash restore process. The staging latches represent secondary backup entries located closer and / or in the restore pipeline.

[0029] The expedited flush saves the time previously required to select the correct instruction from the save and restore buffer and pipe the selected instruction down the correct stage of the restore pipeline. Information from the most recently dispatched instruction is used to enter the correct start action stage of the restore pipeline before the flush command is received. A traditional flush comparison may be used to identify a later instruction to terminate the flush restore rather than identifying the most recently dispatched instruction. In the expedited path, the first dispatch cycle may be performed in the traditional flush+3 cycle of the restore pipeline. An entry with restore information may be read from the save and restore buffer in parallel with determining whether a restore is required. Furthermore, in the expedited path, information from additional staging latches may be queued in an expedited manner for movement to the traditional flush+3 cycle position and comparison with the flush information in parallel. Thus, the traditional later stages of the flush restore process are achieved and executed more quickly in embodiments of the present disclosure. By allowing earlier processing of the most recently dispatched instruction, embodiments of the present disclosure offset the constraint of processing one instruction per pipe per cycle. The earlier processing occurs through providing a new storage location for the instruction information that is also stored in the entry latches of the save and restore buffer.

[0030] Instructions restored from these staging latches in the expedited path are, in at least some embodiments, marked in the save and restore buffer as "restored" to prevent them from being restored again. Such attempts at redundant restoration are redundant and slow down the restoration process.

[0031] At dispatch time, in at least some embodiments, a processor core of the present disclosure may write an entry evicted from the mapper to an entry in a save and restore buffer. The save and restore buffer address of this entry is written to the restore pipe for the slice to which this entry was dispatched, if the entry does not simultaneously flush / restore other threads. The thread ID is also stored in the restore pipe along with the entry data. The SRB address and valid bit are written to a staging latch that is part of the main path Flush+2 cycle stage. This information in the staging latch can be accessed without adding much new state and without waiting for a traditional initial confirmation lookup. This information can be used to write to the restore latch associated with the entry location. In one embodiment with two staging latches, at each new dispatch time, the dispatch information from the first staging latch can be pipelined to the second staging latch. The staging latch entry can be cleared as normal after the flush.

[0032] During a flush, in at least some embodiments, the processor core described in this disclosure detects whether the same thread is being flushed. If the flush is for a different thread, this particular staging latch is not used for mapper restore. If the processor core is flushing the same thread and the restore address is valid, the processor core uses data from the staging latch to obtain the correct information from the entry latch of the save and restore buffer and then drives the obtained information to the next stage of the save and restore buffer restore pipe, e.g., the output latch. If this stage of the mapper restore is active and looking up an entry, in some embodiments, a new dispatch from the save latch takes priority. Priority is design-specific. If the flush restore pipeline is currently active for a known restore, the existing known restore has priority over a newly dispatched restore operation.

[0033] Upon completion of an instruction whose information is held in one or more staging latches as described herein, in at least some embodiments, a processor core of the present disclosure clears the instruction information located in one or more involved staging latches to prevent those instructions from being restored during flushing. This clearing operation may occur via changing valid bits to indicate invalid information.

[0034] This embodiment helps achieve faster mapper restoration and therefore improves processing speed. Thus, a computer system with at least one of the improved processors described herein performs and performs flash restoration more quickly to restore the correct order and information of instructions in the mapper. With this improved mapper restoration, the described embodiments can improve processing performance and processing speed for computer processors.

[0035] Referring now to FIG. 1, a processing system 100 according to one embodiment of the present disclosure is shown. The illustrated processing system 100 includes multiple processors, including a first processor 10A, a second processor 10B, a third processor 10C, and a fourth processor 10D. Each of the first processor 10A, the second processor 10B, the third processor 10C, and the fourth processor 10D may be designed and have components compatible with one or more of the present embodiments, such as the accelerated flash restore processor core 22 shown in FIG. 2 and configured to execute the accelerated flash restore process described and shown in FIG. 3. The processing system 100 shown with multiple processors is illustrative. Other processing systems according to other embodiments may include a single processor with a symmetric multi-threading (SMT) core. The first processor 10A includes a first processor core 11A, a second processor core 11B, and local storage 12, which may reside at a cache level or at the level of internal system memory. The second processor 10B, the third processor 10C, and the fourth processor 10D may have similar internal components and / or the same design of internal components as those shown as having the first processor 10A. The first processor 10A, the second processor 10B, the third processor 10C, and the fourth processor 10D are coupled to a main system memory 14 and to a storage subsystem 16, including non-removable drives and optical drives, for reading a first portable computer-readable tangible storage device 17. The processing system 100 also includes input / output (I / O) interfaces and devices 18, such as a mouse and keyboard, for receiving user input and a graphical display for displaying information. The various processors described may be microprocessors, integrated circuits, embedded systems, and / or equivalents.

[0036] As described with reference to FIG. 6, processing system 100 may be implemented in one or more of the computers described in computing environment 600.

[0037] While the system of Figure 1 is used to provide an example of a system in which the processor architecture of this embodiment may be implemented, it is understood that the system shown is not limiting and is intended to provide one example of a suitable computer system in which the techniques of this embodiment may be applied. It should be understood that Figure 1 does not imply any limitations with regard to the environment in which different processor core embodiments may be implemented. Many modifications to the depicted environment may be made based on design and implementation requirements.

[0038] Figure 2 shows a block diagram illustrating portions of an expedited flash restore processor core 200 implemented in one or more of the processors of processing system 100 shown in Figure 1, according to at least one embodiment. The expedited flash restore processor core 200 may include an instruction cache 201, a dispatch 202, a mapper 204, and multiple save and restore buffers 206a, 206b, 206c, and 206d separated as slices 0, 1, 2, and 3, respectively. The expedited flash restore processor core 200 may include additional components not shown in Figure 2, such as issue queues, execution slices, etc.

[0039] The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device so that they are executed via the accelerated flash processor core 200 to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process. The instructions are executed on the computer, other programmable apparatus, or other device via the accelerated flash restore processor core 200.

[0040] Instruction cache 201 may, for example, temporarily store one or more instruction streams fetched from another cache or system memory and forward the instruction streams to dispatch 202. Instruction cache 201 itself may include cache memory and, in some cases, an instruction buffer. Instruction cache 201 may flow into dispatch 202, which may include a routing network and may send received instructions to a queue in preparation to be scheduled for issue and execution. Dispatch 202 in the illustrated embodiment flows directly into mapper 204.

[0041] Mapper 204 manages register tags, e.g., slice target file (STF) tags, that act as pointers to data in arrays within the processor. Mapper 204 is logically a table that maps logical registers, e.g., general-purpose registers ("GPRs"), to result-producing instructions and to destination locations for executing the instructions. Mapper 204 may perform this mapping using tags. For example, mapper may use instruction tags ("ITAGs") to point to result-producing instructions. Mapper 204 may use STF tags to point to destination locations for instructions. A destination location is a physical location where data is written as part of executing an instruction.

[0042] Mapper 204 may be a system logic mapper and may be partitioned into multiple sections by logical register type. For example, the mapper may be partitioned into a general purpose register ("GPR") section, a floating point register / lower vector scalar register ("V0") section, and an upper vector scalar register ("V1") section. As an example, a logical register mapper may have 96 registers, 32 GPR registers, 32 V0 registers, and 32 V1 registers. The most significant bit of each of the mapper registers may be used to distinguish between various logical register assignments, with registers 0-31 being GPRs, 32-63 being V0 registers, and 64-95 being V1 registers.

[0043] When the instruction is executed, logical register mapper values ​​may be copied to save and restore buffer locations in one or more save and restore buffers. This copy operation is illustrated in FIG. 2 by copy arrow 216 extending, for example, from mapper 204 to first save and restore buffer 206a, and specifically to entry latch 208a of first save and restore buffer 206a. Copy operations may also occur from mapper 204 to other save and restore buffers 206b, 206c, and 206d, and specifically to other entry latches 208b, 208c, and 208d of each of the other save and restore buffers 206b, 206c, and 206d.

[0044] The save and restore buffer is a structure that stores a pre-mapper state so that the state can be restored if one or more instructions need to be flushed. The save and restore buffer includes memory structures, such as latches, that store entries that hold information necessary to restore specific mapper registers to the mapper in response to a flush. The latches may include memory structures, such as pulse-sensitive memory cell circuit types, that are capable of changing state in response to specific input pulse levels. Latching is the process of temporarily storing a signal to maintain a specific level state and record information. The save and restore buffer in the accelerated flash restore processor core may have a greater number of entry latches than the number of staging latches in the accelerated flash restore processor core that store recently dispatched instructions as described in this disclosure because the save and restore buffer stores a complete set of instruction information for flash restore, while the staging latches contain a partial set that may include information representing the most recently dispatched instruction. The save and restore buffer entry latches may store, for example, four threads worth of information, eight threads worth of information, one thread worth of information, etc. Save and restore buffer entry latches are also located at and / or near the beginning stages of restore pipelines ("RPs") 210a, 210b, 210c, 210d, and staging latches are disposed in the middle stages of restore pipelines 210a, 210b, 210c, 210d. Save and restore buffer entry latches also retain their state until their contents are flushed or the instruction corresponding to their contents completes; however, staging latches may have their contents replaced with information corresponding to the next dispatch as part of cycling newly received information.

[0045] Instruction information may be retrieved from the save and restore buffer entry latches and sent to a particular restore pipeline 210a, 212a, 214a based on the type of instruction information. Instruction information from the first save and restore buffer 206a intended for the general purpose processor registers "GPR" may be restored through restore pipe 210a. Instruction information intended for the floating point register / lower vector scalar register ("V0") section of the first save and restore buffer 206a may be restored through restore pipe 212a. Instruction information intended for the upper vector scalar register ("V1") section of the first save and restore buffer 206a may be restored through restore pipe 214a. Similar instruction information type routing may be performed for the other save and restore buffers 206b, 206c, 206d. For example, the restoration pipes 210b, 210c, and 210d of the other three save and restore buffers 206b, 206c, and 206d may each be a GPR restoration pipe and directed to the GPR partition of the mapper 204. The restoration pipes 212b, 212c, and 212d of the other three save and restore buffers 206b, 206c, and 206d may each be a V0 restoration pipe and directed to the V0 partition of the mapper 204. The restoration pipes 214b, 214c, and 214d of the other three save and restore buffers 206b, 206c, and 206d may each be a V1 restoration pipe and directed to the V1 partition of the mapper 204.

[0046] 2 illustrates that in addition to copying the instruction information to the save and restore buffer entry latches, the instruction information is also copied to staging latches, such as first staging latches 22a, 22c, 22e and / or second staging latches 22b, 22d, 22e. This additional copying operation to first staging latch 22a is indicated by staging arrow 218 extending from mapper 204 to first staging latch 22a. These staging latches 22a, 22c, 22e, 22b, 22d, 22e may also include memory structures, such as a type of pulse-sensitive memory cell circuit capable of changing state in response to a particular input pulse level. These staging latches may temporarily store signals to maintain a particular level state and record information. The first staging latches may be disposed within and / or adjacent to the respective restore pipes, e.g., first staging latch 22a may be disposed within and / or adjacent to GPR restore pipe 210a of first save and restore buffer 206a, first staging latch 22c may be disposed within and / or adjacent to V0 restore pipe 212a of first save and restore buffer 206a, and first staging latch 22e may be disposed within and / or adjacent to V1 restore pipe 210c of first save and restore buffer 206a. The first staging latches 22a, 22c, 22e may each have ports connected to various restore pipes, e.g., GPR restore pipe 210a, V0 restore pipe 212a, and V1 restore pipe 214a, respectively. The second staging latches 22b, 22d, 22f may be in the same type of memory structure as the first staging latches 22a, 22c, 22e. In some embodiments, the first and second staging latches 22a, 22c, 22e, 22b, 22d, 22f are partially arranged in the normal restore pipe, but with some additional information to enable flush calculations.

[0047] The instruction information stored in the first and / or second staging latches may include a respective instruction tag and a logical register indicator. The logical register indicator indicates which portion and / or address of the save and restore buffer stores information about the respective instruction, e.g., which particular entry latch or latches of the save and restore buffer store the respective instruction information. The restore pipe 210a may include metal wiring 220 extending between different logical sections of the accelerated flash restore processor core 200. While these staging latches are shown in the various restore pipes of the first save and restore buffer 206a (“slice 0”), additional similar staging latches may also be implemented in the restore pipes of the other save and restore buffers, such as the second, third, and fourth save and restore buffers 206b, 206c, 206d.

[0048] The most recently dispatched instruction from dispatch 202 may be stored in one of the first staging latches 22a, 22c, or 22e. In response to another new instruction (e.g., a second instruction) being dispatched from dispatch 202 and the previous first instruction still being in the first staging latch 22a, 22c, or 22e, the first instruction may be transferred from the first staging latch 22a, 22c, or 22e to the corresponding second staging latch 22b, 22d, or 22f, respectively, to create room in the first staging latch to hold the newer instruction (the second instruction). The second staging latch is partially stored in a normal restore flow latch, but with some additional information to enable flush calculations. Latch transfer arrow 219 shown in FIG. 2 illustrates an example of such a circular flow transfer between the first staging latch 22a and the second staging latch 22b. Thus, after this rotational forwarding scenario is completed, the first staging latch may hold the second instruction, i.e., the new first instruction or the most recently dispatched instruction, and the second staging latch may hold the original first instruction or the second most recently dispatched instruction. In at least some embodiments, the expedited flash restore processor core 200 may include three pipes (GPR / V0 / V1) per slice, and multiple dispatch cycles, e.g., a first and second dispatch cycle, may occur for each of the three pipes per slice. The rotational cycles occur in pipe / register types, e.g., GPR / VR0 / VR1.

[0049] In response to a further instruction, for example a third instruction, being dispatched from dispatch 202, the original first instruction may be pushed out or deleted from the second staging latch 22b, the second instruction may be transferred from the first staging latch 22a to the second staging latch 22b, and the third instruction may be stored in the first staging latch 22a as a further new first instruction.

[0050] In this manner, the staging latches may capture instruction information for the most recently dispatched instructions in a rotational cycle fashion, with a particular number of instructions having their information temporarily held according to the staging latches for a particular save and restore buffer slice.

[0051] Staging latches and their role in accelerated flash restore are explained in more detail in the accelerated flash restore processor pipeline shown in FIG.

[0052] Restore pipes 210a, 212a, 214a, 210b, 212b, 214b, 210c, 212c, 214c, 210d, 212d, 214d may be provided between the entry latches 208a, 208b, 208c, 208d of the save and restore buffers 206a, 206b, 206c, 206d and the logical register mapper sections of the mapper 204 so that flash restore operations are performed on a section-type basis. The restore pipes may include one or more wired connections 220 in the processor unit architecture that link the save and restore buffers with registers of the logical register mapper locations. As an example, each section of the mapper, including 32 GPR registers, 32 V0 registers, and 32 V1 registers, may have a dedicated restore pipeline from the SRB such that each mapper register receives a specific type of instruction information through a restore pipeline with the same assigned logical register type. Any mapper content can be written to any of the SRB entry latches. The save and restore buffer in at least some embodiments is register type agnostic until the retrieved instruction information enters the restore pipeline on its way back to mapper 204. The copy operation of the mapper values ​​to the SRB locations occurs slice by slice as the instruction is dispatched. The save and restore buffer in at least some embodiments includes one or more of the mapper register value, the instruction tag of the instruction, a register file tag (e.g., STF tag) associated with the value that points to a register file location, and a flash recovery field. All or some of this information may be referred to as the entry data of the save and restore buffer's entry latches.

[0053] In normal execution of instructions, mapper 204 forwards instructions to other components of expedited flash restore processor core 200, such as issue queues and execution units. This normal forwarding is indicated by exit arrow 230 shown in FIG. 2. Speedup flash restore processor core 200 may be part of a single integrated circuit processor, such as a superscalar processor, and may include various execution units, registers, buffers, memory, and other functional units, such as an instruction decode unit, an instruction issue unit, a load / store unit, an operand address generation unit, a fixed-point unit, etc. Speedup flash restore processor core 200 in at least one embodiment is capable of issuing instructions for execution out-of-order.

[0054] After a flash-recovery event, such as a system exception, the expedited flash restore processor core 200 sets a restore-required bit as active. The flash recovery field of the SRB associated with the mapper values ​​at the time before the flash-recovery event is set to indicate the need to recover these values ​​to the mapper. The SRB values ​​are then restored to the mapper registers of the mapper 204 using the restore pipe 210. Because the restore pipe 210 and the mapper registers are each partitioned by logical type, the expedited flash restore processor core 200 may recover mapper registers in parallel, allowing multiple registers to be recovered each clock cycle. In one embodiment, two of the GPR, V0, and V1 register values ​​may be recovered from each of the four execution slices stored in the SRB locations per clock cycle. The recovered values ​​may then be mapped to the mapper 204 by the logical register-specific restore pipelines 210. The 96 register values ​​of mapper 204 may be recovered two per cycle from each of the four slices, and thus may be fully recovered in only four cycles. In at least some embodiments, restore pipe 210 is partitioned by logical partial registers to each of the corresponding 32 mapper registers of the same logical register type, rather than being directly wired to each of the 96 registers of mapper 204. This partitioning and / or partitioning of restore pipe 210 and mapper 204 enables rapid parallel recovery of mapper 204 from save and restore buffers 206a, 206b, 206c, 206d.

[0055] 3 is a processor pipeline diagram 300 illustrating the accelerated flash restore process performed by the accelerated flash restore processor core 200 shown in FIG. 2, according to at least one embodiment. Processor pipeline diagram 300 shows the repetition of some structures over some of the cycles but not during other cycles to highlight elements of particular importance for those cycles. Thus, for example, the SRB entry latch is shown in the main pass FL+1, FL+2, and FL+3 cycles, but not in the main pass FL+4, FL+5, and FL+6 cycles.

[0056] The left side of the processor pipeline diagram 300 shown in Figure 3 illustrates an accelerated flash restore and corresponding cycle modifications, while the right side of the processor pipeline diagram 300 shown in Figure 3 illustrates a main path flash restore and corresponding processor cycles. The accelerated flash restore processor core 200 may perform both the accelerated flash restore and the main path flash restore shown in Figure 3 and described herein.

[0057] The expedited flush restore is performed using the staging latches described above with respect to FIG. 2 for storing information representing the most recently dispatched instructions. The expedited flush utilizes the concept that the most recently dispatched instructions are most likely to be flushed. Thus, the placement of the most recently dispatched instructions in the staging latches of the save and restore buffer, which are disposed further along the restore pipe stage of the save and restore buffer, constitutes a prioritization of these most recently dispatched instructions. Instruction information from these staging latches is restored first, without waiting for the conventional instruction tag comparison with the entry latches of the save and restore buffer. The instruction information from the staging latches is prioritized over the regular entry latches of the save and restore buffer because the instruction information from the staging latches is sent to the mapper 204 and restored before the instruction information from the mapper 204 can travel far enough in the restore pipe 210 to be sent to the mapper 204. With two staging latches in place, this expedited process speeds up the restore of the mapper 204 by at least two cycles from the flush.

[0058] The top of processor pipeline diagram 300 shows the beginning of the flush process, which may be referred to as the flush plus zero ("Flush+0") cycle. In this portion of the pipeline, a flush command is broadcast and received at various design elements, such as save and restore buffers 206a, 206b, 206c, 206d and mapper 204. The design elements at this point have received the flush command but have not had time to respond to it. This receipt of the flush command causes the design elements to begin performing additional actions associated with flushing and flush restoration. Receipt of the flush command may trigger notifications to first staging latches 22a, 22c, 22e, second staging latches 22b, 22d, 22f, and entry latches 208a, 208b, 208c, 208d of save and restore buffers 206a, 206b, 206c, 206d. In the expedited flash restore processor core 200, the notification to the entry latches may cause the save and restore buffer entries corresponding to the instruction information stored in the first and second staging latches to be marked as restored so that the main restore path skips these entries. Marking these entries as already restored in the FL+1 cycle helps to prevent the Lreg information for these entries from being read, e.g., to prevent the remaining contents of their stored information from being read in subsequent cycles. Receipt of a flush command by the save and restore buffer also forwards the command's instruction tag to the first multiplexer 304 to initiate various processes, such as flash restore. The first multiplexer 304 performs the function of selecting the appropriate flash thread to be compared for the flash comparison in the comparison logic box 306.

[0059] The left portion of Figure 3 shows that for an expedited path flush, an entry from the second staging latch 22b is dispatched at a time equal to main path cycle III. While the main path flush cycle requires comparing instruction tag information with the save and restore buffer entry latch, the expedited path can immediately send the information stored in the staging latch in cycle FL+1 without having to wait for the instruction tag information comparison with the SRB entry latch. A first dispatch cycle 301 is shown in Figure 3 to illustrate the dispatch of information stored in the second staging latch 22b. This staging latch 22b may be along a stage of the restore pipeline 210a between the SRB entry latch 208a and the mapper 204. The staging latch may be used to store the most recently dispatched instruction because it is empty and / or unused during these early stages of the flush restore according to the main path procedure. The second staging latch 22b may typically be located at the output of a multiplexer, such as the staging latch multiplexer 320a. During this Flush+1 cycle, the information stored in the second staging latch 22b may be compared to the thread information in the flash mask to confirm a thread match. If a thread match is confirmed, flash restoration with the information stored in the second staging latch 22b may proceed. If a thread match is not confirmed, the information in this particular staging latch 22b is not relevant to the current flash restoration and may remain temporarily dormant in the staging latch 22b.

[0060] This information from the second staging latches 22b, 22d, 22f may be provided from the first staging latch for mapper restore in the first processor cycle. In at least some embodiments with the expediting process, a two-cycle advantage is achieved. While the main path flush cycle does not have instruction information provided until the third main path cycle (III), the expediting path has instruction information provided in the first stage / cycle after receiving the flush command. In the expediting path cycle, instruction information from the second staging latch 22b, specifically the lreg information of the relevant instruction, may be provided / read in the first processor cycle and used to look up instruction restore information from the correct address in the entry latch of the save and restore buffer.

[0061] The information in the second staging latch 22b in at least some embodiments was previously in the first staging latch 22a and is passed to the second staging latch 22b as new instructions come in. Thus, in some embodiments, the information in the second staging latch 22b may represent the second most recently dispatched instruction, and the information in the first staging latch 22a may represent the most recently dispatched instruction.

[0062] Also in the first processor cycle, instruction information from the first staging latch 22a may be multiplexed into the recovery pipe via the staging latch multiplexer 320a. At this point, before any information is forwarded from the entry latch of the mapper 204, the staging latch multiplexer 320a will, by default, select to forward the information received from the first staging latch 22a because no other information is present in this staging latch multiplexer 320a to conflict with the information received from the first staging latch 22a. The staging latch multiplexer 320a is labeled in FIG. 3. Each of the first staging latches 22a, 22c, 22e may be input to a separate staging latch multiplexer that selects between this information from its respective first staging latch and the information flowing along the main recovery pipeline.

[0063] A second dispatch cycle 303 is shown in Figure 3 to show that dispatching of information stored in the first staging latch 22a occurs at time intervals equal to the main path cycle II. In the second processor cycle, for an expedited path flush, instruction information retrieved from the entry latch may be driven to the mapper 204 using the address from the second staging latch 22b, while instruction information retrieved from the first staging latch 22a is also read as that first staging latch instruction information is currently located in the second staging latch 22b or equivalent location in the restore pipeline.

[0064] In the third processor cycle, for an expedited path flush, instruction information originally obtained from the entry latch by using the address from the first staging latch 22a (in some embodiments, passed from the first staging latch 22a to the second staging latch 22b) may be driven to mapper 204. Thus, in the expedited flush path, the first instruction information and the second instruction information have already been driven to mapper 204 in the third processor cycle. However, in the main path flush, the third processor cycle only reads information from the entry latch of the save restore buffer. This performance acceleration for the expedited flush path illustrates how using a staging latch can provide a cycle advantage, e.g., a two-cycle advantage, for achieving mapper restoration. If a main path flush occurs in conjunction with an expedited flush, the main path flush can provide information from the third most recently dispatched instruction or other earlier instructions to continue the expedited flush restoration after receiving a jump start from one or more staging latches. The main path flush may be designed to skip entries corresponding to the first and second most recently dispatched instructions, thereby providing other information to the middle or back of the flush restore. For this earlier instruction, e.g., the third instruction, the entry latch may be read in the third cycle after receiving the flush command. The retrieved / read entry may be driven to the mapper in the fourth cycle after receiving the flush command.

[0065] In the Flush+1 cycle, tag 302 is a flush tag or a completion tag and is compared against the tags in the entries of entry latches 208a, 208b, 208c, and 208d. The flush / completion tags for each thread go to every entry. Within the entries, each entry multiplexes the appropriate thread flush / completion i-tag and performs a comparison. A first multiplexer 304 may select between flush / completion among the four threads; for example, one entry can flush thread 0 and another can complete thread 1. By performing this selection, the first multiplexer 304 forwards flush-related instructions further in the flush restore pipeline. The first multiplexer 304 multiplexes the appropriate thread flush / completion i-tag within each entry; therefore, each entry has a mux 304 (although a single first multiplexer 304 is shown in FIG. 3). A comparison logic box 306 is also provided for each entry, should there be more than one. However, the components, namely, tag 302, restore vector 308, and dispatch pending logic 312, are either sent to or pulled from all of the entries of a particular slice. The number of instruction tags may be correlated to the number of threads in the save and restore buffer entry latch, and thus, the first multiplexer 304 selects the appropriate flush / completion tag to match against the information held in the entry. The received information indicates which save and restore buffer entry holds it. The first multiplexer 304 selects from the potential flush / completion tags 302 and provides them to the comparison logic box 306. The comparison logic box 306 performs a comparison of the flush tag against the entry tag (evictor) and the previous tag (evictee). If the evictor is flushed and the evictee is not, the entry must be restored to the mapper. The comparison helps make the decision on which instruction to flush based on. If the instruction is newer than the flush instruction, the newer instruction is involved in the flush and therefore the flush restore.All latch entries in the save and restore buffers are read in the flush+1 cycle to be checked for relevance to the flush command in the conventional pass.

[0066] When an instruction completes, the processor notifies the save and restore buffer so that an entry for the respective instruction is retired from the save and restore buffer. This retirement operation may be performed by removing the respective entry from the save and restore buffer. If one of the instruction tags 302 indicates that an instruction has completed, the two flush cycle paths shown in FIG. 3 do not need to honor that instruction tag. If such an instruction tag indicates instruction completion, the expedited flash restore processor core 200 may also compare against the entries in the first staging latches 22a, 22c, 22e and / or the entries in the second staging latches 22b, 22d, 22f, and clear the corresponding information from the staging latches if the entries match. This clearing of the staging latches prevents this information from the completed instruction from being injected into the flash restore process because information from successfully completed instructions is not needed for flash restore.

[0067] When a flush command is received, the flush command provides information about the instruction involved in the flush. The flush command information may be compared to the entries in the save and restore buffer entry latches 208a, 208b, 208c, and 208d in a comparison logic box 306. The comparison logic box 306 receives input from the entry latches 208a, 208b, 208c, and 208d and also receives output from a first multiplexer 304 to compare information from two different input streams to each other. The instruction tag flush tag in 302 indicates whether the tag is to be flushed and whether the flush tag is valid. For flush comparisons of staging latches, the comparison is performed further downstream in the restore pipeline than when comparisons are performed with respect to the save and restore buffer entry latches. If the instruction information saved by each instruction does not flush and each instruction does flush, a flush restore process must be performed. Thus, in the FL+1 cycle, the received new instruction tag is compared against all entries in entry latches 208a, 208b, 208c, and 208d. In some embodiments, entry latch 208a may include registers 0-31 and may point to the GPR, entry latch 208b may include registers 32-63 and may point to the V0 register, entry latch 208c may include registers 64-95 and may point to the V1 register, and entry latch 208d may include registers 96:127. The number of instruction tags 302 collected may correspond to the number of entry latch sections; for example, there are four instruction tags for the four entry latch sections 208a, 208b, 208c, and 208d for the four save and restore buffers 206a, 206b, 206c, and 206d, respectively.

[0068] If a need for flash restoration is identified based on the comparison in comparison logic box 306, comparison logic box 306 forwards the flash restoration information to both OR logic 310 and restore vector 308. OR logic 310 performs an OR operation on all instructions involved in the flash restoration and then sends the ORed group of instructions to dispatch reserve logic 312 to set a latch in dispatch reserve logic 312. Dispatch reserve logic 312 prevents any new dispatches on the associated thread until the entries in restore vector 308 are exhausted and completed. Arrows extending from dispatch reserve logic 312 without a receive box represent the transmission of pending instructions being sent to dispatch 202 and / or other components of the processor to perform the suspension / prevention of dispatch for a particular thread. Restore vector 308 may include latches with bits corresponding to entry latches 208a, 208b, 208c, 208d of save and restore buffers 206a, 206b, 206c, 206d. If the instruction involves a flash restore, the bit in the restore vector latch corresponding to the entry for this instruction in the entry latch is set.

[0069] The OR logic 310, dispatch pending logic 312, and restore vector 308 together form a loop that continues until the flash restore is complete. The relevant entries involved in the flush remain in the restore vector 308 until these instructions are processed. Instructions are processed one at a time per restore pipe. This loop helps to avoid a scenario in which the expedited flash restore processor core 200 attempts to simultaneously dispatch and restore flash on the same mapper entry. Such a scenario would likely trigger a processor error, and the loop helps to avoid this error.

[0070] In main stage cycle II, dispatch pending logic 312 contains bits set by threads to send to dispatch logic to prevent new dispatches from being dispatched to the restored thread. This setting of bits is accomplished by ORing the entries requesting restoration for each thread in OR logic 310. Once all entries have restored, the restore vector 308 clears the bit that set it, thereby clearing the path through the OR to dispatch pending logic 312. This loop is similar to or equivalent to the loop described above for the expedited path flush cycle shown on the left in FIG. 3.

[0071] In main path cycle stage II, restore requests are filtered from restore vector 308 by logical register for restoration. The filtered requests are passed to discovery logic 314, where an entry is selected for each of the register types. Discovery logic 314, in some embodiments, may include multiple partitions corresponding to multiple partitions of the save and restore buffers; for example, discovery logic 314 may include first discovery logic for general purpose registers GPR, second discovery logic for floating point registers / lower vector scalar register V0, and third discovery logic for upper vector scalar register V1.

[0072] Once the discovery logic 314 selects an entry to recover from each partition, the entry number, e.g., a number representing the bit or entry in the selected recovery vector, is encoded in the encoding logic 316 to reduce the number of bits passed down through the recovery logic.

[0073] Information for the relevant entry is sent from the second cycle stage as output 320. This output 320 is provided as an input to the third cycle stage.

[0074] These cycle stages I and II in the main path flush cycle include functions and elements that are also performed in cycle stages I and II in the expedited path flush cycle. However, the main path flush cycle does not include expedited activity on the first and second staging latches. The expedited path flush cycle in stages I and II includes a dispatch pending loop and a comparison of the instruction tag against the entry latch, but these actions are used for any later instructions that need to be flushed, rather than for the one or two most recently dispatched instructions.

[0075] During the Flush+3 cycle in the main path, instruction entries are read from entry latches 208a, 208b, 208c, and 208d to retrieve information therefrom for sending to mapper 204 to restore it. At that point, the lreg, part of output 320 for each entry retrieved in the Flush+2 stage, is used to find the correct address in entry latches 208a, 208b, 208c, and 208d. Each address is then read to retrieve the correct instruction information. The read information is provided to information multiplexer 322, which flows into stage 3 multiplexer 324 and optimization multiplexer 326. Information multiplexer 322 selects the appropriate SRB interface layer 328 for the particular instruction information type. Optimization multiplexer 326 receives input from second optimization latch 331, which receives input from first optimization latch 329. The optimization latches 329, 331 facilitate customization according to port availability for simultaneous multithreading, which allows multiple instruction streams (threads) to execute simultaneously on the same physical processor.

[0076] For the expedited path, a get / read has already occurred at the corresponding pipeline position in the Flush+1 cycle and again at the corresponding pipeline position in the Flush+2 cycle. The get in the Flush+1 cycle is for an entry from the second staging latch, which holds information for the second most recently dispatched instruction. The get in the Flush+2 cycle is for an entry from the first staging latch, which holds information for the most recently dispatched instruction.

[0077] During the Flush+4 cycle in the main path, the retrieved / read instruction information is driven from the stage 3 multiplexer 324 and the optimization multiplexer 326 to the SRB interface layer 328, which drives the information to the mapper 204. The SRB interface layer 328 may drive this information via a transmission to the mapper interface layer 330. This transmission may occur through the pipe wiring 220 shown in FIG. 2. The mapper interface layer 330 receives the transmission. This pipe wiring 220 may, in some instances, be referred to as a recovery cycle pipeline. The SRB interface layer 328 and the mapper interface layer 330 may include latches specific to the recovery pipe section.

[0078] For the expedited path, this drive for the read / fetched information representing the second most recently dispatched instruction has already occurred at its corresponding pipeline location in the Flush+2 cycle, and this drive for the read / fetched information representing the most recently dispatched instruction has already occurred at its corresponding pipeline location in the Flush+3 cycle.

[0079] During the Flush+5 cycle in the main path, the mapper interface layer 330 provides the received command information to the mapper multiplexer 332 for selection to the appropriate mapper section 334. Upon receipt, the received / obtained command information is stored in the appropriate mapper section 334.

[0080] With respect to the expedited path, this feeding to mapper multiplexer 332 and selection to and storage in the appropriate mapper section has already been done for the read / fetched information representing the second most recently dispatched instruction at the corresponding pipeline locations in the Flush+3 cycle. This feeding, selection, and storage has already been done for the read / fetched information representing the most recently dispatched instruction at their corresponding pipeline locations in the Flush+4 cycle.

[0081] In the Flush+6 cycle, the read / retrieved information that was saved in mapper 204 can now be read from mapper 204. Mapper restore may complete unless additional instructions have also been restored for this particular flush. The above steps may be repeated for each additional instruction involved in this particular flush operation.

[0082] For the expedited path, availability for a read from mapper 204 already occurred for the read / fetched information representing the second most recently dispatched instruction in the Flush+4 cycle. This availability for a read from mapper 204 already occurred for the read / fetched information representing the most recently dispatched instruction in the Flush+5 cycle.

[0083] In a writeback, a detection is made as to whether the writeback is to the same thread. If the writeback is to the same thread, the writeback instruction tag is compared to the instruction tag of the instruction in the expedited restore staging latch. A read bit, e.g., the W bit, in mapper 204 is set equal to 1 if this comparison indicates a match. A writeback affects data held in the save and restore buffers that is restored to the mapper. The writeback function is for a write bit to indicate that a register has been written. This write bit can be read to know if the data is ready. This write bit is cleared from mapper 204 in response to receiving a new instruction from dispatch 202 that writes to a register in mapper 204.

[0084] Upon completion of the flash restore, the mapper 204 may release the dispatch pending and new instructions may be written to the mapper 204 .

[0085] 2 and 3 provide only examples of some embodiments, but do not imply any limitations on how different embodiments may be implemented. Many modifications to the illustrated embodiments, such as to the depicted sequence of steps or placement of processor components, may be made based on design and implementation requirements.

[0086] Table 1 below summarizes the advantages of the expedited path compared to the main path for restoring the mapper with the first staging latch. Table 2 below summarizes the advantages of the expedited path compared to the main path for restoring the mapper with two staging latches during operation. [Table 1] Table 1 [Table 2] Table 2

[0087] Tests performed with the accelerated flash restore processor core 200 showed improvements in processing speed.

[0088] FIG. 4 is a block diagram illustrating a portion of an alternative accelerated flash restore processor core 400 that includes most of the same components, structure, and arrangement as the accelerated flash restore processor core 200 shown in FIG. 2, but with a reversed order of the first and second staging latches. FIG. 5 illustrates an alternative processor pipeline diagram 500 executed by the alternative accelerated flash restore processor core 400 shown in FIG. 4, according to at least one embodiment. FIGS. 4 and 5 illustrate that for this alternative embodiment, the positions of the first and second staging latches are reversed so that the alternative first staging latch 44a is disposed downstream of the alternative second staging latch 44b in the mapper restore direction of the restore pipe. This alternative may include additional first and second staging latches as implemented with respect to the embodiment of FIGS. 2 and 3, but for simplicity, only the alternative first and second staging latches 44a, 44b are labeled in FIGS. 4 and 5.

[0089] FIG. 4 illustrates that in this alternative arrangement, circular flow transfers between staging latches occur upstream relative to the mapper restore direction of the restore pipe. Circular flow transfers refer to the passing of instruction information between latches when a new instruction is dispatched, with the information being stored in the save and restore buffers and in the staging latches. As described above, a first instruction may initially reside in a first one of the staging latches, and then, as a new instruction arrives, it may be pushed into another one of the staging latches. Specifically, the alternative latch transfer arrow 419 illustrated in FIG. 4 illustrates an example of an alternative circular flow transfer between the alternative first staging latch 44 a and the alternative second staging latch 44 b. In contrast, the latch transfer arrow 219 illustrated in FIG. 2 illustrates a circular flow transfer between the first staging latch 22 a and the second staging latch 22 b occurring downstream relative to the mapper restore direction of the restore pipe.

[0090] This alternative embodiment of FIGS. 4 and 5 achieves the advantage that, in an embodiment with two staging latches per instruction type per slice, the most recently dispatched instruction receives the advanced position (downstream in the mapper restore direction) of the staging latch. In the embodiment shown in FIGS. 2 and 3, the second-most recently dispatched instruction was held in the advanced position (downstream in the mapper restore direction) of the staging latch. Thus, the alternative embodiment of FIGS. 4 and 5 emphasizes the concept of achieving faster restore by assuming that the most recently dispatched instruction is most likely to participate in mapper restore. As shown in FIG. 5, the alternative embodiment may include a circular multiplexer 55 in the flow path for circular transfer between the alternative first staging latch 44a and the alternative second staging latch 44b. The circular multiplexer 55 may select the correct second staging latch for passback instruction information released from the first staging latch 44a due to the arrival of a new instruction. The embodiment shown in Figures 2 and 3 may be advantageous due to the fact that it does not require such an additional cyclic multiplexer to be added to the usual main flow path components.

[0091] For this alternative embodiment, the most recently dispatched instruction is driven to the mapper before the second most recently dispatched instruction. In the embodiment of Figures 2 and 3 as previously described, the second most recently dispatched instruction is driven to the mapper before the most recently dispatched instruction. The remaining components of the expedited path flush cycle and main path flush cycle for the alternative embodiment shown in Figures 4 and 5 function largely in the same way as described for these components and cycles with respect to the embodiment of Figures 2 and 3.

[0092] 4 and 5 provide only examples of some embodiments, but do not imply any limitations on how different embodiments may be implemented. Many modifications may be made to the illustrated embodiments, for example, to the depicted sequence of steps or placement of processor components, based on design and implementation requirements.

[0093] 6 is a block diagram of internal and external components of a computer system in which one or more of the processors described herein may be implemented. Computing environment 600 illustrates an example of one or more computers with a processor that performs accelerated flash restore. Computing environment 600 includes, for example, computer 601, wide area network (WAN) 602, end user device (EUD) 603, remote server 604, public cloud 605, and private cloud 606. In this embodiment, computer 601 includes a processor set 610 (including processing circuitry 620 and cache 621), a communications fabric 611, volatile memory 612, persistent storage 613 (including an operating system 622 and software programs 616), a peripheral device set 614 (including an interface (UI) device set 623, storage 624, and an Internet of Things (IoT) sensor set 625), and a network module 615. Remote server 604 includes a remote database 630. Public cloud 605 includes a gateway 640, a cloud orchestration module 641, a set of host physical machines 642, a set of virtual machines 643, and a set of containers 644. The various computers shown may each include one or both of the accelerated flash restore processor core 200 and the alternative accelerated flash restore processor core 400 as described above.

[0094] Computer 601 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or developed in the future that is capable of executing programs, accessing a network, or querying a database such as remote database 630. Various computers may execute methods distributed among multiple computers and / or across multiple locations. While in this presentation of computing environment 600, to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 601. Although computer 601 is not shown in the cloud in FIG. 6, it may be located in a cloud. However, computer 601 need not be within a cloud.

[0095] The processor set 610 includes one or more computer processors of any type now known or later developed that are configured to execute the accelerated flash restore process described in this disclosure. The processing circuitry 620 may be distributed across multiple packages, e.g., multiple integrated circuit chips coupled together. The processing circuitry 620 may implement multiple processor threads and / or multiple processor cores. The cache 621 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on the processor set 610. Cache memory is typically divided into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all of the cache for a processor set may be located “off-chip.” In some computing environments, the processor set 610 may be designed to operate on qubits and perform quantum computing. The processor set 610 may include one or more accelerated flash restore processor cores 200 and alternative accelerated flash restore processor cores 400, as described above.

[0096] Computer readable program instructions are typically loaded into computer 601 and cause a series of operational steps to be performed by processor set 610 of computer 601. These computer readable program instructions are stored in various types of computer readable storage media, such as cache 621 and other storage media described below. The program instructions and associated data are accessed by processor set 610 to control and direct the execution of the methods of the invention.

[0097] Communications fabric 611 is a signal-conducting pathway that allows the various components of computer 601 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways, such as fiber optic and / or wireless communication pathways, may also be used.

[0098] Volatile memory 612 may be any type of volatile memory now known or later developed. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory 612 is characterized by random access, although this is not required unless affirmatively indicated. In computer 601, volatile memory 612 is located in a single package and is internal to computer 601, although alternatively or additionally, volatile memory may be distributed across multiple packages and / or may be located external to computer 601.

[0099] Persistent storage 613 is any form of non-volatile storage for a computer, now known or later developed. The term non-volatile storage means that stored data remains regardless of whether power is supplied to computer 601 and / or to persistent storage 613 directly. Persistent storage 613 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, data to be erased, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 622 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that utilize a kernel.

[0100] Peripheral device set 614 includes the set of peripheral devices of computer 601. Data communication connections between peripheral devices and other components of computer 601 may be implemented in various ways, such as Bluetooth connections, near field communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertable connections (e.g., a Secure Digital (SD) card), connections made by a local area communication network, and even connections made by a wide area network such as the Internet. In various embodiments, UI device set 623 may include multiple components, such as a display screen, speakers, a microphone, wearable devices (such as goggles and a smartwatch), a keyboard, a mouse, a printer, a touchpad, a game controller, and a haptic device. Storage 624 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 624 may be persistent and / or volatile. In some embodiments, storage 624 may take the form of a quantum computing storage device that stores data in the form of qubits. In embodiments where computer 601 needs to have large amounts of storage (e.g., computer 601 stores and manages a large database locally), then this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. IoT sensor set 625 is made up of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector. Various sensors and / or UI devices may each include separate packages with one or more of the enhanced processors as described herein.

[0101] The network module 615 is a collection of computer software, hardware, and firmware that enables the computer 401 to communicate with other computers over the WAN 602. The network module 615 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of the network module 615 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN)), the control and forwarding functions of the network module 615 are performed on physically separate devices, whereby the control function manages multiple different network hardware devices. Computer-readable program instructions for implementing the methods of the invention can be downloaded to the computer 601 from an external computer or external storage device, typically via a network adapter card or network interface included in the network module 615.

[0102] WAN 602 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any technology for communicating computer data, now known or later developed. In some embodiments, WAN 602 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0103] End-user device (EUD) 603 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 601) and may take any of the forms described above with respect to computer 601. EUD 603 typically receives useful and useful data from the operation of computer 601. For example, in the hypothetical case where computer 601 is designed to provide recommendations to the end user, the recommendations would typically be communicated from computer 601's network module 615 over WAN 602 to EUD 603. In this manner, EUD 603 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 603 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc. Each EUD 603 may include a package with an enhanced processor as described herein.

[0104] Remote server 604 is any computer system that provides at least some data and / or functionality to computer 601. Remote server 604 may be controlled and used by the same entity that operates computer 601. Remote server 604 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 601. For example, in the hypothetical case where computer 601 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 601 from a remote database 630 of remote server 604. Remote server 604 may include a package with one or more of the enhanced processors as described herein.

[0105] A public cloud 605 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct, active management by users. Cloud computing typically leverages resource sharing to achieve consistency and economies of scale. Direct, active management of the computing resources of the public cloud 605 is performed by computer hardware and / or software in a cloud orchestration module 641. The computing resources provided by the public cloud 605 are typically realized through virtual computing environments running on various computers that make up a host physical machine set 642, which represents the total set of physical computers included in and / or available to the public cloud 605. Each of these physical computers may include a respective package with one or more of the enhanced processors described herein.

[0106] Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 643 and / or containers from container set 644. It is understood that these VCEs may be stored as images and may be transferred between various physical machine hosts either as images or after instantiating the VCE. Cloud orchestration module 641 manages the transfer and storage of images, deploys newly instantiated VCEs, and manages active instances of VCE deployments. Gateway 640 is a collection of computer software, hardware, and firmware that enables public cloud 605 to communicate over WAN 602.

[0107] Some further discussion of virtualized computing environments (VCEs) is now provided. A VCE can be stored as an "image." From this image, new, active instances of the VCE can be instantiated. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of operating systems in which the kernel allows the existence of multiple isolated user space instances called containers. These isolated user space instances typically behave as actual computers from the perspective of the programs running within them. A computer program running on a typical operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and the devices assigned to the container, a feature known as containerization.

[0108] Private cloud 606 is similar to public cloud 605, except that its computing resources are available only for use by a single enterprise. While private cloud 606 is shown in communication with WAN 602, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often implemented by different vendors. While each of the multiple clouds remains a separate, discrete entity, they are bound together in a larger hybrid cloud architecture by standardized or proprietary technologies, which enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 605 and private cloud 606 are part of a larger hybrid cloud.

[0109] In computing environment 600, computer 601 is shown as connected to the Internet (see WAN 602). However, in many embodiments, computer 601 is isolated from communications over a communications network, is not connected to the Internet, and operates as a stand-alone computer. In these embodiments, network module 615 of computer 601 may not be necessary or even desirable to ensure isolation and prevent external communications from reaching computer 601. Stand-alone computer embodiments are potentially advantageous in at least some applications of the present invention because they are typically more secure. In other embodiments, computer 601 is connected to a secure WAN or secure LAN rather than WAN 602 and / or the Internet. In these network-connected (i.e., non-stand-alone) embodiments, system designers may wish to take appropriate security measures, now known or developed in the future, to reduce the risk that incoming network communications will cause a security breach.

[0110] Some or all of the computer 601, the computer components of the wide area network 602, the end user device 603, the remote server 604, the computers of the public cloud 605, and the computers of the private cloud 606 may include one or more processors that execute the accelerated flash restore process as described herein.

[0111] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present invention. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be implemented as a single step, executed concurrently, substantially concurrently, partially, or fully in a time-overlapping manner, or the blocks may possibly be executed in reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or acts or executes a combination of special-purpose hardware and computer instructions.

[0112] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "have," "having," "with," and the like, when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0113] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for restoring a mapper of a processor core, the method comprising: storing first information in a staging latch, the first information representing a newly dispatched first instruction of the processor core; storing the first information in an entry latch of a save and restore buffer of the processor core; and initiating the restoration of the mapper with the first information from the staging latch in response to receiving a flush command of the processor core without waiting to compare a flash tag of the flush command with the entry latch of the save and restore buffer. A method for providing

2. 2. The method of claim 1, further comprising: marking the first information in the entry latch of the save and restore buffer as restored, further responsive to the receipt of the flush command.

3. The method of claim 1 , further comprising, further responsive to the receipt of the flush command, processing remaining instruction information from the save and restore buffer for transmission to the mapper.

4. in response to a dispatch of a second instruction after the dispatch of the first instruction, transferring the first information from the staging latch into another staging latch; storing second information representing the second instruction in the staging latch; and storing the second information in another entry latch of the save and restore buffer; and further responsive to the receipt of the flush command by the processor core, proceeding with the restoration of the mapper with the second information from the staging latch without waiting to compare the flash tag of the flush command with other entry latches of the save and restore buffer. The method of claim 1 further comprising:

5. 5. The method of claim 4, further comprising: reading entry data from the entry latch of the save and restore buffer using a first logical register from the first information in the staging latch in a first processor cycle following the receipt of the flush command.

6. 6. The method of claim 5, wherein the transfer of the first information from the staging latch into the other staging latch occurs in the first processor cycle.

7. 5. The method of claim 4, wherein the transfer of the first information from the staging latch to the other staging latch occurs via a multiplexer in a restore pipeline of the processor core.

8. 5. The method of claim 4, wherein in a second processor cycle following said receipt of said flush command, first entry data read from said entry latch is driven to said mapper.

9. 9. The method of claim 8, wherein in the second processor cycle, a second logical register from the second information in the staging latch is used to read second entry data from the other entry latch of the save and restore buffer.

10. 10. The method of claim 9, wherein the read second entry data is driven to the mapper in a third processor cycle following the receipt of the flush command.

11. 10. The method of claim 9, wherein in a fourth processor cycle following the receipt of the flush command, a third entry data read from the save and restore buffer is driven to the mapper.

12. 5. The method of claim 4, wherein the second instruction is from a most recently dispatched instruction and the first instruction is from a second most recently dispatched instruction.

13. 5. The method of claim 4, wherein the transfer of the first information from the staging latch into the other staging latch occurs in a direction against a mapper restore direction of a restore pipe.

14. 14. The method of claim 13, wherein the first instruction is from a most recently dispatched instruction and the second instruction is from a second most recently dispatched instruction.

15. 2. The method of claim 1, further comprising verifying thread agreement between the first information before initiating the restore of the flush command and the mapper and the first information from the staging latch.

16. clearing the first information from the staging latch in response to completion of the first instruction. The method of claim 1 further comprising:

17. clearing the first information from the staging latch in response to completion of a flush corresponding to the flush command; The method of claim 1 further comprising:

18. 2. The method of claim 1, wherein the first instruction is from a most recently dispatched instruction.

19. 1. A computer system comprising a processor core, the processor core comprising: storing first information in a staging latch, the first information representing a newly dispatched first instruction of the processor core; storing the first information in an entry latch of a save and restore buffer; In response to receiving a flush command, initiate the restoration of the mapper of the processor core with the first information from the staging latch without waiting to compare a flash tag of the flush command with the entry latch of the save and restore buffer.

1. A computer system configured to:

20. 1. A processor core comprising: a dispatcher, a mapper, a save and restore buffer having an entry latch and connected to the mapper via at least one pipeline, and a first register disposed in the at least one pipeline, the processor core comprising: storing first information in the first register, the first information representing a newly dispatched first instruction from the dispatcher; storing the first information in the entry latch of the save and restore buffer; Responsive to receiving a flush command for the processor core, restoring the first instruction in the mapper using the first information stored in the first register in the at least one pipeline. The processor core is configured as follows:

21. A computer program product comprising instructions executable by a processor to cause the processor to perform a method according to any of claims 1 to 18.

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