Hexadecimal floating-point multiply-add instruction

Abstract

An instruction is executed to perform an operation selected from a plurality of operations configured for the instruction. The executing includes determining a value of a selected operand of the instruction. Determining the value includes reading the selected operand of the instruction from the selected operand location to obtain a value of the selected operand based on control of the instruction, the control including a first value, and using a default value as the value of the selected operand based on the control including a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and the selected operand of the instruction to obtain an intermediate result. A result is obtained from the intermediate result and placed in the selected location.

Description

[Technical Field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and more particularly to improving such processing. [Background technology]

[0002] Applications executing within computing environments provide many operations used by a wide variety of technologies, including, but not limited to, design, manufacturing, medical technology, automotive technology, computer processing, etc. These applications, written in programming languages ​​such as COBOL, often perform complex calculations in performing their operations. Calculations include, for example, exponential functions, which often require converting data from binary-coded decimal to hexadecimal floating point, performing the function in hexadecimal floating point, and converting the result back to binary-coded decimal.

[0003] Performing a function in hexadecimal floating point involves hexadecimal floating point arithmetic. However, this arithmetic is not precise enough, so additional instructions are executed to achieve greater precision. Executing additional instructions increases complexity, reduces system performance, and increases system resource usage. Summary of the Invention

[0004] The shortcomings of the prior art are overcome and additional advantages are provided by providing a computer program product for facilitating processing within a computing environment. The computer program product includes one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media for performing a method. The method includes executing the instructions to perform selected operations from a plurality of operations configured for the instructions. In one example, executing the instructions includes determining a value for a selected operand of the instruction. Determining the value includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand based on control of the instruction, for example, based on the control of the instruction including a first value, and using a predetermined value as the value of the selected operand based on the control of the instruction including a second value. This value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and the selected operand of the instruction to obtain an intermediate result. A result is obtained from the intermediate result and placed in the selected location.

[0005] By performing multiplication and arithmetic operations using a single instruction, performance is improved and resource utilization is reduced. By performing multiplication and arithmetic operations using a single designed instruction, certain tasks such as multiplication and arithmetic operations can be performed much more efficiently than using a software paradigm. The multiplication and / or arithmetic operations are performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0006] By using a single instruction configured to perform multiple operations, performance is improved and resource utilization is reduced. By using a single designed instruction configured to perform multiplication and arithmetic operations or arithmetic-only operations, where multiplication is performed to provide greater precision for arithmetic operations, certain tasks such as multiplication and arithmetic operations can be performed much more efficiently than using a software paradigm. The multiplication and arithmetic operations are performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0007] Furthermore, in one example, performing arithmetic (e.g., addition) using a multiply instruction that also performs arithmetic increases precision, and using a single instruction instead of multiple instructions reduces complexity, improves performance, and reduces system resource usage. For example, multiplication of two operands results in a double-wide product; combining arithmetic operations in a single instruction allows the arithmetic to involve a full double-wide product rather than a rounded or truncated product. As an example, multiplication of two six-digit hexadecimal operands results in a 12-digit hexadecimal product. If these were separate operations, the product would be truncated to six hexadecimal digits before the next operation. Using the full intermediate result makes the combined operation more accurate. In other words, simple floating-point operations using truncation typically result in an error of 0 to 1 ulp (unit of last place). If there is a multiplication and truncation, the product will have an error of 1 ulp, and if there is an addition of the product to an addend, that will cause another 1 ulp of error, for a total error of 2 ulps. However, if the operation is a single compound operation, there will only be an error of 1 ulp. This is true for binary floating point; for hexadecimal floating point, the error is even worse.

[0008] In one example, using a default value as the value of the selected operand includes using the default value without reading the selected operand from the selected operand location, e.g., at least one register, thereby improving system performance, e.g., by eliminating the reading of one or more registers.

[0009] As an example, the default value includes a value of 1.

[0010] In one example, executing the instructions further includes determining whether rounding is to be performed and, based on a determination that rounding is to be performed, performing the rounding on a version of the intermediate result to obtain a result, where the version of the intermediate result includes, for example, a normalized result.

[0011] By using a single instruction to perform a multiplication, arithmetic, and / or rounding operation, performance is improved and resource utilization is reduced. By using a single, designed instruction to perform a multiplication, arithmetic, and / or rounding operation, certain tasks, such as multiplication, arithmetic, and / or rounding, can be performed much more efficiently than using a software paradigm. The multiplication, arithmetic, and / or rounding operation is performed much faster, reducing execution time and improving the performance of the processor and / or the overall system. Furthermore, rounding reduces the absolute error in both directions to 1 / 2 ulp. An unfused multiply-add operation contains a double rounding error, while a fused multiply-add operation contains a single rounding error.

[0012] In one example, determining whether rounding is performed includes checking a rounding mode control of the instruction, and rounding is performed based on the rounding mode control being equal to a value of 1. By including the rounding mode control as part of a single instruction, the direction and magnitude of the error may be controlled.

[0013] In one example, obtaining the result includes normalizing the intermediate result to obtain a normalized result and using the normalized result to obtain the result. Further, obtaining the result using the normalized result includes, for example, determining whether rounding is performed and, based on determining that rounding is performed, rounding the normalized result to obtain the result. Further, in one example, based on determining that rounding is not performed, truncating the normalized result to obtain the result.

[0014] By using a single instruction to perform a multiplication operation, an arithmetic operation, a normalization operation, a rounding operation, or a truncation operation, or a combination thereof, performance is improved and resource utilization is reduced. By using a single designed instruction to perform a multiplication operation, an arithmetic operation, a normalization operation, a rounding operation, or a truncation operation, or a combination thereof, certain tasks, such as a multiplication operation, an arithmetic operation, a normalization operation, a rounding operation, or a truncation operation, or a combination thereof, can be performed much more efficiently than using a software paradigm. The multiplication operation, the arithmetic operation, the normalization operation, the rounding operation, or a truncation operation, or a combination thereof, is performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0015] As an example, the selected location includes at least one register specified by at least one field of the instruction.

[0016] In one example, the control is an add-only control and the arithmetic operation includes an add operation. Based on the control including the second value, the control indicates that the instruction is to perform an add-only operation in which the other selected operand is multiplied by a predetermined value of 1. Further, based on the control including the first value, the control indicates that the instruction is to perform a multiply-add operation, and that the other selected operand is multiplied by a value read from the selected operand location.

[0017] By using a single instruction configured to perform multiple operations, performance is improved and resource utilization is reduced. By using a single designed instruction configured to perform a multiply-add or an add-only operation, where the multiplication is performed to provide greater precision for the addition operation but does not otherwise affect the sum, certain tasks, such as a multiply-add operation, can be performed much more efficiently than using a software paradigm. The multiply-add operation is performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0018] Additionally, in one example, performing the addition using a multiply instruction that also performs the addition increases precision, and using a single instruction rather than multiple instructions reduces complexity, improves performance, and reduces system resource usage.

[0019] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0020] Additional features and advantages are realized by the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0021] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing, together with objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0022] [Figure 1A] FIG. 1 illustrates an example computing environment for incorporating and using one or more aspects of the present invention. [Figure 1B] 1B illustrates further details of the processor of FIG. 1A in accordance with one or more aspects of the present invention. [Figure 2A] FIG. 2 illustrates an example format of a multiply-add instruction in accordance with one or more aspects of the present invention. [Figure 2B] FIG. 2 illustrates an example of further details of a mask field for multiply-add instructions (Multiply and Add) in accordance with one or more aspects of the present invention. [Figure 2C] FIG. 10 illustrates another example format of a multiply-add instruction in accordance with one or more aspects of the present invention. [Figure 3] FIG. 2 illustrates an example of processing associated with executing a multiply-add instruction in accordance with one or more aspects of the present invention. [Figure 4] FIG. 2 illustrates an example of further details associated with obtaining a result of a multiply-add instruction in accordance with one or more aspects of the present invention. [Figure 5A] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 5B] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 5C] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 6A] FIG. 1 illustrates another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 6B] FIG. 6B illustrates an example of further details of the memory of FIG. 6A in accordance with one or more aspects of the present invention. [Figure 6C] FIG. 6B illustrates another example of further details of the memory of FIG. 6A in accordance with one or more aspects of the present invention. [Figure 7A] FIG. 1 illustrates yet another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 7B]7B illustrates further details of the memory of FIG. 7A in accordance with one or more aspects of the present invention. [Figure 8] FIG. 1 illustrates one embodiment of a cloud computing environment in accordance with one or more aspects of the present invention. [Figure 9] FIG. 2 illustrates an example of an abstract model layer in accordance with one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] In accordance with aspects of the present invention, capabilities are provided for facilitating processing within a computing environment. As one example, a single instruction (e.g., a single designed hardware machine instruction at a hardware / software interface) is provided that is configured to perform multiple operations, including, for example, multiplication and arithmetic (e.g., addition) operations, as well as operations referred to herein as arithmetic-only (e.g., add-only) operations. The instructions referred to herein as multiply-add instructions (Multiply and Add) are part of the instruction set architecture (ISA) of a general-purpose processor, dispatched by a program on a processor such as a general-purpose processor (in another example, the instructions may be part of a special-purpose processor, such as a coprocessor configured for a specific function).

[0024] As part of the execution of a single instruction (e.g., a multiply-add instruction), various operations may be performed, including multiplication, addition, normalization, rounding, or truncation, or combinations thereof. Each of these operations is performed as part of executing the single instruction, improving system performance and reducing system resource usage.

[0025] Furthermore, in accordance with aspects of the present invention, a single instruction that can perform a multiplication and an arithmetic operation, such as a multiply-add operation, can also perform an arithmetic-only operation, such as the operation of an add-only instruction. As used herein, an arithmetic or add-only instruction indicates that a multiplication is performed, but the multiplier is 1 (e.g., in hexadecimal floating-point format) and is performed to provide greater precision to arithmetic, such as addition, but does not otherwise affect the arithmetic (e.g., adding values). The multiplier in the operation of an add-only instruction does not need to be read from a register file, reducing dependency on registers and eliminating the need for a register to hold the constant 1.0.

[0026] Additionally, in one embodiment, the single instruction includes a rounding mode specifier that can select between a truncated result or rounding to the nearest value away from 0, thereby controlling the direction and amount of rounding error.

[0027] In one example, the operand of the instruction is in hexadecimal floating-point format, which is a format for encoding floating-point numbers. In one example, a hexadecimal floating-point number includes a sign bit, an exponent (e.g., 7 bits), and a fraction (e.g., 6 digits, 14 digits, or 28 digits). The exponent represents a signed exponent and is obtained, for example, by adding 64 to the exponent value. The exponent ranges from 0 to 127, which corresponds to an exponent range of, for example, −64 to +63. The magnitude of the hexadecimal floating-point number is the product of the fraction and the number 16 raised to the power of the exponent represented by the exponent. The number can be positive or negative depending on whether the sign bit is, for example, 0 or 1, respectively.

[0028] Hexadecimal floating-point numbers may be represented in several different formats, including short format (e.g., 32 bits), long format (e.g., 64 bits), and extended format (e.g., 128 bits). In each format, the first bit (e.g., the first leftmost bit, bit 0) is a sign bit, the next selected number of bits (e.g., 7 bits) are an exponent, and in the short and long formats, the remaining bits are a fraction containing, for example, 6 or 14 hexadecimal digits, respectively. In the extended format, the fraction is, for example, a 28-digit fraction, and an extended hexadecimal floating-point number consists of two long-format numbers, called the high-order and low-order parts. The high-order part is an arbitrary long hexadecimal floating-point number. The high-order fraction includes, for example, the leftmost 14 hexadecimal digits of the 28-digit fraction, and the low-order fraction includes, for example, the rightmost 14 hexadecimal digits of the 28-digit fraction. The high-order exponent and sign are those of the extended hexadecimal floating-point number; the low-order sign and exponent of the extended operand are ignored.

[0029] One embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 1A. As an example, the computing environment is based on the z / Architecture® hardware architecture provided by International Business Machines Corporation (Armonk, New York). One embodiment of the z / Architecture hardware architecture is described in the publication “z / Architecture Principles of Operation,” IBM Publication No. SA22-7832-12, Thirteenth Edition, September 2019, which is incorporated herein by reference in its entirety. However, the z / Architecture hardware architecture is only one exemplary architecture, and other architectures or types of computing environments of International Business Machines Corporation or other entities or both may include and / or use one or more aspects of the present invention. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0030] 1A, computing environment 100 includes a computer system 102, shown, for example, in the form of a general-purpose computing device. Computer system 102 may include, but is not limited to, one or more processors or processing units 104 (e.g., central processing units (CPUs)), memory 106 (e.g., also referred to as system memory, main memory, primary storage, central storage, or storage), and one or more input / output (I / O) interfaces 108, coupled together via one or more buses or other connections 110 or both.

[0031] Bus 110 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures, including, by way of example only, Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnects (PCI).

[0032] The memory 106 may include a cache 112, such as a shared cache, which may be coupled to a local cache 114 of the processor 104, for example. Additionally, the memory 106 may include one or more programs or applications 116 and at least one operating system 118. An exemplary operating system includes the z / OS® operating system offered by International Business Machines Corporation (Armonk, New York). z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems offered by International Business Machines Corporation and / or other entities may also be used. The memory 106 may include one or more computer-readable program instructions 120, which may be configured to perform functions of embodiments of aspects of the present invention.

[0033] The computer system 102 may communicate with one or more external devices 130, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, for example, via the I / O interface 108. The data storage devices 134 may store one or more programs 136, one or more computer-readable program instructions 138, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0034] The computer system 102 may communicate, for example, via the I / O interface 108, with a network interface 132 that enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, to facilitate communication with other computing devices or systems.

[0035] Computer system 102 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, computer system 102 may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or an optical disk drive for reading from or writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components may be used with computer system 102, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0036] Computer system 102 may operate in numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, microcomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0037] In one example, a processor (e.g., processor 104) includes multiple functional components used to execute instructions. As shown in FIG. 1B , these functional components include, for example, an instruction fetch component 150 for fetching instructions to be executed, an instruction decode unit 152 for decoding the fetched instructions and obtaining operands for the decoded instructions, one or more instruction execution components 154 for executing the decoded instructions, a memory access component 156 for accessing memory to execute the instructions, if necessary, and a writeback component 158 ​​for providing results of the executed instructions. One or more of the components may access and / or use one or more registers 160 in instruction processing. Additionally, one or more of the components may include or have access to at least a portion of one or more other components used in performing multiplication and arithmetic (e.g., addition) operations and / or arithmetic-only operations of, for example, a multiply-add instruction (or other processing that may employ one or more aspects of the present invention) as described herein in accordance with one or more aspects of the present invention. The one or more other components may include, for example, multiplication component / arithmetic component (or one or more other components) 170.

[0038] In accordance with an aspect of the present invention, instructions, referred to herein as Multiply and Add instructions, are provided to perform at least a multiplication operation, an addition operation, a normalization operation, a rounding operation, and / or a truncation operation as part of executing an instruction. The instructions are configured to perform multiple operations, including, for example, a Multiply and Add instruction operation and an Add Only instruction operation, where a multiplication (e.g., by 1) is performed to increase the precision of the product used in the addition.

[0039] For example, multiplication of two operands results in a double-wide product, and by combining arithmetic operations in a single instruction, the arithmetic can involve a full double-wide product rather than a rounded or truncated product. As an example, multiplication of two six-digit hexadecimal operands results in a 12-digit hexadecimal product. If these were separate operations, the product would be truncated to six hexadecimal digits before the next operation. By using the full intermediate result, the combined operation becomes more accurate. In other words, for simple floating-point operations using truncation, an error of 0 to 1 ulp (unit of last place) is typically obtained. If there is a multiplication and truncation, the product will have an error of 1 ulp, and if there is an addition of the product to the addend, that will cause another 1 ulp of error, for a total error of 2 ulps. However, if the operations are one compound operation, only an error of 1 ulp is present. This is true for binary floating point, and the error is even worse for hexadecimal floating point.

[0040] As an example, hexadecimal floating-point addition is defined to use the exponent to align the fraction and maintain one guard digit. If the operand with a larger exponent contains leading zeros, one guard digit is not sufficient to obtain an accurate result. A hexadecimal floating-point multiply-add operation is defined to maintain accuracy of intermediate results before rounding. A more accurate addition is created by using a hexadecimal floating-point multiply-add operation with a multiplicand equal to 1.

[0041] An example is shown below. A=0.000123x×16^(8) B=0.987654x×16^(2) HFP addition 0.000123x×16^8 0.0000009x×16^8 with only one guard digit ____________________________________ 0.0001239x×16^8 intermediate result 0.123900x×16^5 normalized result

[0042] HFP Multiply and Accumulate 0.000123x×16^8 0.000000987654x×16^8 ____________________________________ 0.000123987654x×16^8 intermediate result 0.123987654x×16^5 normalization 0.123987x×16^5 result

[0043] The worst case of hexadecimal floating-point addition is when a 0 with a large exponent is added to a number, losing all precision. For example: A=0.000000x×16^63 B=0.ABCDEFx×16^56 ____________________________________ 0.000000x×16^63 A 0.0000000x×16^63 B is aligned to one guard digit 0.0000000x×16^63 Intermediate result 0.000000x × 16^0 results in a true zero The result is off by approximately 16^56, not including digits of precision. If this is done using hex floating-point Multiply-Add, the result is equal to B and is exact.

[0044] One embodiment of a multiply-add instruction used to perform the operations of a multiply-add instruction and / or an add-only instruction is described with reference to FIG. 2A . The instruction, in one example, is executed using a general-purpose processor (e.g., processor 104). In the description herein, specific locations of fields, specific fields, and / or specific sizes are indicated (e.g., specific bytes and / or bits). However, other locations, fields, and / or sizes may be provided. Furthermore, while setting bits to specific values ​​(e.g., 1 or 0) may be specified, this is merely an example. Bits may be set to different values, such as opposite or different values, in other examples. Many variations are possible.

[0045] In one example, a multiply-add instruction has an RRD format that indicates register and register operations along with an extended operation code (opcode) and additional registers. As shown in FIG. 2A , in one example, a multiply-add instruction 200 includes multiple fields, and the fields may have associated subscript numbers. The subscript numbers associated with a field of the instruction indicate the operand to which the field applies. For example, the subscript number 1 associated with register R1 indicates that the register specified using R1 contains the first operand, and so on. The length of the register operand is one register, e.g., 64 bits.

[0046] In one embodiment, the multiply-add instruction 200 includes at least an operation code (opcode) field 202 (e.g., bits 0-15) indicating a multiply-add operation, a first register (R1) field 204 (e.g., bits 16-19) used to specify at least one first register, a mask (M4) field 206 (e.g., bits 20-23), a second register (R2) field 210 (e.g., bits 28-31) used to specify at least one second register, and a third register (R3) field 208 (e.g., bits 24-27) used to specify at least one third register, each of which is described below. In one embodiment, each field is separate and independent of one another, although in other embodiments, two or more fields may be combined. More information regarding these fields is described below.

[0047] In one embodiment, the register (R1) field 204 is used to indicate at least one register containing a first operand, which is a value to be added in executing the instruction, and the location of the first operand (e.g., at least R1) stores the result of executing the instruction. The second operand is contained in at least one register specified using the register (R2) field 210 and is, for example, a hexadecimal floating-point number, and the third operand is contained in at least one register specified using the register (R3) field 208 and is, for example, a hexadecimal floating-point number.

[0048] In one example, one or more controls are used in executing the instruction. Exemplary controls are included in the M4 field 206. Referring to FIG. 2B, the M4 field 206 includes the following:

[0049] Add-only instruction 220: When this control (e.g., bit 0) is 0, the function performed is a multiply-add instruction. When this control is 1, the function performed is an add-only instruction, where a multiply-add is performed and the third operand is assumed to be 1.0. This operation is equivalent to adding with an infinity guard digit followed by normalization and rounding, with the rounding mode determined by the rounding mode control described below.

[0050] Rounding mode 222: If this control (e.g., bit 3) is 0, the normalized intermediate result is truncated to form the result. If this control is 1, the normalized intermediate result is rounded to the nearest value away from 0. The normalized intermediate result contains, for example, the 29, 15, or 7 most significant hexadecimal digits of the multiply-add result for the extended, long, and short formats, respectively, and includes one guard digit on the right. A 1 is added to the leftmost bit of the guard digit of the intermediate result, the carry is propagated to the left, and the guard digit is removed to generate the fractional part of the result. If the rounding intermediate result would cause a fractional overflow, the fractional part is shifted one hexadecimal position to the right and the exponent is incremented.

[0051] In one example, bits 1-2 are ignored and contain 0.

[0052] Another example of a format for a multiply-add instruction is described with reference to Figure 2C. In one embodiment, multiply-add instruction 250 has an RXF format that indicates register and indexed storage operations, an extended opcode field, and an additional register field. The multiply-add instruction 250 includes multiple fields, such as operation code (opcode) fields 252a, 252b (e.g., bits 0-7 and 40-47) that indicate at least a multiply-add operation, a first register (R1) field 262 (e.g., bits 32-35) used to specify at least one first register, a mask (M4) field 264 (e.g., bits 36-39) used to specify at least one third register, a third register (R3) field 254 (e.g., bits 8-11) used to specify at least one third register, and an index (X2) field 256 (e.g., bits 12-15), a base (B2) field 258 (e.g., bits 16-19), and a displacement (D2) field 260 (e.g., bits 20-31) used to specify the address of a second operand. For example, the contents of the general-purpose register specified by the X2 and B2 fields are added to the contents of the D2 field to form the address of the second operand. Each of the fields is described below. In one embodiment, each field is separate and independent of one another, although in other embodiments, two or more fields may be combined.

[0053] As described herein, in one embodiment, the register (R1) field 262 is used to indicate at least one register containing a first operand, which is a value to be added in executing the instruction, and the location of the first operand stores the result of executing the instruction. As previously mentioned, the second operand obtained from an address defined using the X2 field 256, the B2 field 258, and the D2 field 260 is, for example, a hexadecimal floating-point number, and the third operand is contained in at least one register specified using the register (R3) field 254 and is, for example, a hexadecimal floating-point number.

[0054] In one example, one or more controls are used in executing the instructions in one embodiment. Exemplary controls are included in the M4 field 264 and are described above with reference to FIG. 2B.

[0055] In execution of one embodiment of the multiply-add instruction (200, 250), the third operand (e.g., obtained as described below) is multiplied by the second operand (e.g., obtained using the R2 register or obtained from the address of the second operand) to obtain a product (also referred to herein as an intermediate product), and then the first operand (e.g., obtained using the R1 register) is added to this product. In one embodiment, in the operation of an add-only instruction (Add Only), if bit 0 of the M4 field 206, 264 (Add Only instruction 220) is, for example, 1, the operation is the addition of the second operand to the first operand. The value from the third operand's floating-point register is ignored (e.g., not read from the register and assumed to be a default value such as 1). The sum is placed in the location of the first operand.

[0056] The operation of the multiply-add instruction can be summarized as follows:

[0057] Op1=op3×op2+op1

[0058] The third and second hexadecimal floating-point operands are multiplied to form an intermediate product, and then the first operand is algebraically added to the intermediate product to form an intermediate result. The exponents and mantissas of the intermediate products and the intermediate results are maintained exactly. If the intermediate result is non-zero, it is normalized and truncated to the format of the operands before being placed in the position of the first operand. In one example, in an add-only instruction operation, if bit 3 (rounding mode 222) of the M4 field 206, 264 is 1, the intermediate result is normalized and rounded to the nearest value away from 0 to the format of the operands before being placed in the position of the first operand.

[0059] The rules of algebra determine the sign of the result unless the fractional part of the intermediate result is zero, in which case the result is forced to positive true zero.

[0060] If the exponent of the normalized result exceeds 127 and the fraction is not 0, a hexadecimal floating-point exponent overflow exception occurs. The operation is completed by making the exponent of the result 128 less than the correct value, and a hexadecimal floating-point exponent overflow program interrupt occurs. The result is normalized, and the sign and fraction remain correct.

[0061] If the normalized result is expressed using the correct exponent, hexadecimal floating-point exponent overflow is not recognized for intermediate values.

[0062] If the exponent of the normalized result is less than zero and the fraction is not zero, a hexadecimal floating-point underflow exception occurs. If the hexadecimal floating-point exponent underflow mask bit in a control register, such as the program status word, is 1, the operation completes by making the exponent of the result 128 greater than the correct value, and a hexadecimal floating-point exponent underflow program interrupt occurs. The result is normalized, and the sign and fraction remain correct. If the hexadecimal floating-point exponent underflow mask bit in a control register is 0, no program interrupt occurs; instead, the operation completes by making the result a positive true zero.

[0063] Hexadecimal floating-point exponent overflow is not recognized for input operands and intermediate values, provided the normalized result can be represented using the correct exponent.

[0064] Further details of one embodiment of processing based on execution of a multiply-add instruction in accordance with one or more aspects of the present invention are described with reference to Figures 3-4. In one example, a processor, such as general processor 104, is used to execute the instructions. As an example, processor hardware is used to execute the instructions. The hardware may be within or coupled to the processor for the purpose of receiving instructions from the processor, which may, for example, retrieve, decode, and set the instructions for execution on the hardware. Other variations are possible.

[0065] 3 , in one embodiment, an instruction, such as a multiply-add instruction, is first obtained (e.g., fetched, received, provided, etc.) (300) and executed (310). In one example, first and second operands are obtained (312). Additionally, in one embodiment, a control, referred to herein as an add-only instruction control 220, is obtained (314). If this control indicates that a multiply-add operation is to be performed (e.g., the add-only instruction control is set to 0) (316), a third operand is obtained (e.g., the third operand is read from one or more registers specified using R3) (318), and the second and third operands are multiplied to obtain a product (320). Alternatively, if this control indicates that an add-only instruction operation is to be performed (e.g., the add-only instruction control is set to 1) (316), it is assumed that the third operand is a value of 1 and that the one or more registers specified by R3 are not read. The second and third operands (eg, the third operand contains a default value of 1 in hexadecimal floating point) are multiplied (320) to obtain a product.

[0066] The first operand is added to this product to obtain an intermediate result 322. A result is obtained from the intermediate result 324, and this result is placed in the location of the first operand (e.g., one or more registers specified using R1) 326. In one example, rounding may be performed to obtain the result, as described herein.

[0067] Further details regarding obtaining a result from the intermediate result (324) are described with reference to FIG. 4. In one example, the exponent and mantissa of the intermediate product and the intermediate result are maintained exactly (400). If the intermediate result is non-zero (410), the intermediate result is normalized to provide a normalized result (420). Furthermore, a determination is made as to whether rounding is to be performed (430). As an example, this determination is made by checking the rounding mode control 222. If rounding is not performed, the normalized result is truncated to the format of the operand to provide a result placed in the position of the first operand (440). However, if rounding is performed (430), the normalized result is rounded, for example, to the nearest value away from zero, to the format of the operand to obtain a result placed in the position of the first operand (450). In one example, the rounding mode is used only for operations of the add-only instruction. In other examples, the rounding mode may be used in other operations.

[0068] Although various fields and registers of the multiply-add instruction have been described, one or more aspects of the present invention may use other more or fewer fields and / or registers, or other sized fields and / or registers, or combinations thereof, etc. Many variations are possible. For example, implicit registers may be used in place of explicitly specified registers and / or fields of the instruction, or explicitly specified registers and / or fields may be used in place of implicit registers and / or fields, or combinations thereof. Other variations are also possible.

[0069] As described herein, in one aspect, a single instruction (e.g., a single designed machine instruction (e.g., a multiply-add instruction) at a hardware / software interface) is provided to perform a multiplication operation, an addition operation, a normalization operation, a truncation operation, or a rounding operation, or a combination thereof. For example, the instruction is a hardware instruction defined in an instruction set architecture (ISA) that directly executes a multiply-add instruction, an add-only instruction, or both operations. The program complexity associated with performing the multiply-add operation is reduced. Furthermore, the performance of the operation (and therefore the processor) is improved. Execution of the hardware instruction reduces execution time and improves performance.

[0070] By performing at least the multiply-add operation (and optionally normalization, truncation, and / or rounding, and / or other operations) using a single instruction rather than multiple instructions, performance is improved by not requiring multiple passes through a hardware / software interface. Furthermore, by performing the operation as part of a single instruction, the operation does not require updating registers in the processor's register file (i.e., the array of processor registers used to store data between memory and functional units (e.g., floating-point processing units)) before completing the operation, and remains within the processing unit (e.g., floating-point processing unit) performing the operation. This improves execution time and reduces processor resource usage.

[0071] In accordance with one or more aspects, performing arithmetic (e.g., addition) using a multiply instruction that also performs the arithmetic as part of a single instruction increases precision, and using a single instruction rather than multiple instructions reduces complexity, improves performance, and reduces system resource usage. Additionally, by providing rounding modes as part of a single instruction, the error can be perturbed, in one example, to be either all in one direction or half the absolute error in both directions. The truncation error is 0 to +1 ulp, while the rounding error is -1 / 2 ulp to +1 / 2 ulp, where an ulp represents the weight of the last digit of the operand.

[0072] In one example herein, the arithmetic operation is addition, but in other examples, other arithmetic operations may be performed, including but not limited to subtraction. Many variations are possible.

[0073] One or more aspects of the present invention are closely related to computer technology and facilitate processing in computers and improve their performance. Using a single designed machine instruction to perform at least multiply-add operations, and optionally normalize, round, or truncate, or a combination thereof, improves performance within a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. Furthermore, using a single designed machine instruction to perform the multiply-add (and in one embodiment, normalize, round, or truncate the result, or a combination thereof, or perform other operations, or a combination thereof) improves performance within a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. The data and / or instructions may be used in many technical fields, such as computer processing, medical informatics, design, automotive technology, and manufacturing. By achieving optimization in performing arithmetic operations, these technical fields are improved by reducing execution time.

[0074] Further details of embodiments that facilitate processing within a computing environment as it relates to one or more aspects of the present invention are described with reference to FIGS. 5A-5C.

[0075] Referring to FIG. 5A , in one embodiment, an instruction is executed (500) by performing an operation selected from a plurality of operations configured for the instruction. In one example, executing the instruction includes determining a value of a selected operand (e.g., a third operand) of the instruction (502). Determining the value of the selected operand is based on control of the instruction (504), such as reading the selected operand of the instruction from the selected operand location to obtain the value of the selected operand (506) based on the control of the instruction including a first value, and using a default value as the value of the selected operand (508) based on the control of the instruction including a second value. This value and another selected operand (e.g., a second operand) of the instruction are multiplied to obtain a product (510). An arithmetic operation is performed using this product and the selected operand (e.g., the first operand) of the instruction to obtain an intermediate result (512). A result is obtained from the intermediate result (514) and placed in the selected location (516).

[0076] By performing multiplication and arithmetic operations using a single instruction, performance is improved and resource utilization is reduced. By performing multiplication and arithmetic operations using a single designed instruction, certain tasks such as multiplication and arithmetic operations can be performed much more efficiently than using a software paradigm. The multiplication and / or arithmetic operations are performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0077] By using a single instruction configured to perform multiple operations, performance is improved and resource utilization is reduced. By using a single designed instruction configured to perform multiplication and arithmetic operations or arithmetic-only operations, where multiplication is performed to provide greater precision for arithmetic operations, certain tasks such as multiplication and arithmetic operations can be performed much more efficiently than using a software paradigm. The multiplication and arithmetic operations are performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0078] Furthermore, in one example, performing arithmetic (e.g., addition) using a multiply instruction that also performs arithmetic improves precision, and using a single instruction rather than multiple instructions reduces complexity, improves performance, and reduces system resource usage. For example, multiplication of two operands results in a double-wide product; combining the arithmetic operations in a single instruction allows the arithmetic to involve a full double-wide product rather than a rounded or truncated product. As an example, multiplication of two six-digit hexadecimal operands results in a 12-digit hexadecimal product. If these were separate operations, the product would be truncated to six hexadecimal digits before the next operation. Using the full intermediate result makes the combined operation more accurate. In other words, simple floating-point operations using truncation typically result in an error of 0 to 1 ulp (the weight of the last digit). If there is a multiplication and truncation, the product will contain an error of 1 ulp, and if there is an addition of the product to the addend, that will introduce another 1 ulp of error, for a total error of 2 ulps. However, if the operation is one compound operation, there is only an error of 1 ulp. This is true for binary floating point; for hexadecimal floating point, the error is even worse.

[0079] In one example, using the default value as the value of the selected operand includes using the default value without reading the selected operand from the location (e.g., at least one register) of the selected operand (518), thereby improving system performance by eliminating the reading of one or more registers.

[0080] As an example, referring to FIG. 5B, the default value includes a value of 1 (520).

[0081] In one example, executing the instructions further includes determining whether rounding is to be performed (522) and, based on a determination that rounding is to be performed, performing the rounding on a version of the intermediate result to obtain a result (524). The version of the intermediate result includes, for example, a normalized result (526).

[0082] By using a single instruction to perform a multiplication operation, an arithmetic operation, rounding, and / or normalization operation, performance is improved and resource utilization is reduced. By using a single designed instruction to perform a multiplication operation, an arithmetic operation, rounding, and / or normalization operation, a particular task, such as a multiplication operation, an arithmetic operation, rounding, and / or normalization operation, can be performed much more efficiently than using a software paradigm. The multiplication operation, the arithmetic operation, rounding, and / or normalization operation is performed much faster, reducing execution time and improving performance of the processor and / or the overall system.

[0083] In one example, determining whether rounding is to be performed includes checking a rounding mode control of the instruction (528), and based on the rounding mode control being equal to a value of one, rounding is performed (530). Further, in one embodiment, by including a rounding mode control as part of a single instruction, the direction and magnitude of the error may be controlled. In one example, the error may be perturbed to be either all in one direction or half the absolute error in both directions. The error for truncation is 0 to +1 ulp, while the error for rounding is -1 / 2 ulp to +1 / 2 ulp.

[0084] In one example, obtaining the result includes normalizing the intermediate result to obtain a normalized result (532) and obtaining the result using the normalized result (534).

[0085] 5C , in one example, obtaining a result using the normalized result includes determining whether rounding is performed (540) and, based on determining that rounding is performed, rounding the normalized result to obtain a result (542). Further, in one example, based on determining that rounding is not performed, truncating the normalized result to obtain a result (544).

[0086] By using a single instruction to perform a multiplication operation, an arithmetic operation, a normalization operation, a rounding operation, or a truncation operation, or a combination thereof, performance is improved and resource utilization is reduced. By using a single designed instruction to perform a multiplication operation, an arithmetic operation, a normalization operation, a rounding operation, or a truncation operation, or a combination thereof, certain tasks, such as a multiplication operation, an arithmetic operation, a normalization operation, a rounding operation, or a truncation operation, or a combination thereof, can be performed much more efficiently than using a software paradigm. The multiplication operation, the arithmetic operation, the normalization operation, the rounding operation, or a truncation operation, or a combination thereof, is performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0087] As an example, the selected location includes at least one register specified by at least one field of the instruction (546).

[0088] In one example, the control is for an add-only instruction, and the arithmetic operation includes an add operation (548). Based on the control including a second value, the control indicates that the instruction is to perform an add-only operation, in which the other selected operand is multiplied by a predetermined value of 1 (550). Further, based on the control including the first value, the control indicates that the instruction is to perform a multiply-add operation, and that the other selected operand is to be multiplied by a value read from the selected operand location (552).

[0089] By performing a multiply-add operation using a single instruction, performance is improved and resource utilization is reduced. By performing a multiply-add operation using a single designed instruction, certain tasks such as multiply-add operations can be performed much more efficiently than using a software paradigm. The multiply-add operation is performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0090] By using a single instruction configured to perform multiple operations, performance is improved and resource utilization is reduced. By using a single designed instruction configured to perform a multiply-add instruction and / or an add-only instruction, where the multiplication is performed to provide greater precision for the addition operation but does not otherwise affect the sum, certain tasks, such as multiply-add operations, can be performed much more efficiently than using a software paradigm. The multiply-add operation is performed much faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0091] Additionally, in one example, performing arithmetic (e.g., addition) using a multiply instruction that also performs the arithmetic in a single instruction increases precision, and the use of a single instruction rather than multiple instructions reduces complexity, improves performance, and reduces system resource usage.

[0092] Other variations and embodiments are possible.

[0093] Aspects of the present invention may be used with many types of computing environments. Another example of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 6A. As an example, the computing environment of FIG. 6A is based on the z / Architecture® hardware architecture offered by International Business Machines Corporation (Armonk, New York). However, the z / Architecture hardware architecture is only one exemplary architecture. Additionally, computing environments may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other architectures from International Business Machines Corporation, or architectures from other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0094] In one example, computing environment 10 includes a central electronics complex (CEC) 11. Central electronics complex 11 includes multiple components, such as, for example, memory 12 (also called system memory, main memory, primary storage, central storage, or storage) coupled to one or more processors (also called central processing units (CPUs)) 13 and an input / output (I / O) subsystem 14.

[0095] I / O subsystem 14 may be part of or separate from the central electronics complex. I / O subsystem 14 directs the flow of information between main memory 12 and input / output control unit 15 and input / output (I / O) devices 16 coupled to the central electronics complex.

[0096] Many types of I / O devices may be used. One particular type is a data storage device 17. The data storage device 17 may store one or more programs 18, one or more computer-readable program instructions 19, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0097] Central electronics complex 11 can include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, central electronics complex 11 can include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as "hard drives"), magnetic disk drives for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or optical disk drives for reading from and writing to removable, non-volatile optical disks such as CD-ROMs, DVD-ROMs, or other optical media. It should be understood that other hardware and / or software components can be used in conjunction with central electronics complex 11, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0098] Additionally, central electronics complex 11 can operate in numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with central electronics complex 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0099] In one or more embodiments, central electronics complex 11 provides support for logical partitioning and / or virtualization. In one embodiment, as shown in FIG. 6B , memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of hypervisor 21 is the Processor Resource / System Manager (PR / SM™) offered by International Business Machines Corporation (Armonk, New York). As used herein, firmware includes, for example, processor microcode. Firmware includes, for example, hardware-level instructions and / or data structures used in implementing higher-level machine code. In one embodiment, firmware includes proprietary code that controls operating system access to the system's hardware, typically provided as microcode containing trusted software or microcode specific to the underlying hardware. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0100] Each logical partition 20 can function as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23, such as the z / OS® operating system provided by International Business Machines Corporation (Armonk, New York), or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire system, but in fact only a portion of it is available. While the z / OS operating system is provided as an example, other operating systems provided by International Business Machines Corporation, other companies, or both, may be used in accordance with one or more aspects of the present invention.

[0101] Memory 12 is coupled to CPU 13 (FIG. 6A), which is a physical processor resource that can be assigned to a logical partition. For example, logical partition 20 includes one or more logical processors, each of which represents all or a portion of physical processor resource 13 that can be dynamically assigned to a logical partition.

[0102] In yet another embodiment, the central electronics complex provides support for virtual machines (which may or may not support logical partitioning). As shown in FIG. 6C, memory 12 of central electronics complex 11 includes, for example, one or more virtual machines 26, a virtual machine manager (e.g., hypervisor 27) that manages the virtual machines, and processor firmware 28. One example of hypervisor 27 is the z / VM® hypervisor offered by International Business Machines Corporation (Armonk, New York). A hypervisor may be referred to as a host. z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0103] The central electronics complex's virtual machine support allows multiple virtual machines 26 to be run, each running a different program 29 and a guest operating system 30, such as the Linux® operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and run a different program. An operating system or application program running within a virtual machine appears to have access to the entire system, but in fact only a portion of it is available. While z / VM and Linux are provided as examples, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux® is used pursuant to a sublicense from the Linux Foundation (an exclusive licensee of Linus Torvalds, owner of the trademark worldwide).

[0104] Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 7A. In this example, computing environment 36 includes a native central processing unit (CPU) 37, memory 38, and one or more input / output devices and / or interfaces 39, coupled together, for example, via one or more buses 40 or other connections. By way of example, computing environment 36 may include a PowerPC® processor offered by International Business Machines Corporation (Armonk, New York), an HP Superdome with an Intel® Itanium® II processor offered by Hewlett-Packard Company (Palo Alto, California), or other machines based on architectures offered by International Business Machines Corporation, Hewlett-Packard Company, Intel Corporation, Oracle Corporation, or other companies, or combinations thereof. PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0105] The native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and / or one or more special purpose registers that are used during processing within the environment. These registers contain information that represents the state of the environment at any particular point in time.

[0106] Additionally, native central processing unit 37 executes instructions and code stored in memory 38. In one particular example, central processing unit executes emulator code 42 stored in memory 38. This code enables a computing environment configured with one architecture to emulate another architecture. For example, emulator code 42 enables machines based on architectures other than the z / Architecture hardware architecture (e.g., PowerPC processors, HP Superdome servers, etc.) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0107] Further details related to emulator code 42 are described with reference to FIG. 7B . Guest instructions 43 stored in memory 38 include software instructions (e.g., interrelated to machine instructions) developed to execute on an architecture other than that of native CPU 37. For example, guest instructions 43 may be designed to execute on a processor based on the z / Architecture hardware architecture, but are instead emulated on native CPU 37, which may be, for example, an Intel Itanium II processor. In one example, emulator code 42 includes an instruction fetch routine 44 for retrieving one or more guest instructions 43 from memory 38 and, optionally, providing local buffering of the retrieved instructions. Emulator code 42 also includes an instruction conversion routine 45 for determining the type of the retrieved guest instruction and for converting the guest instruction into one or more corresponding native instructions 46. This conversion includes, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform this function.

[0108] Additionally, emulator code 42 includes an emulation control routine 47 for causing execution of native instructions. Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulates one or more already-fetched guest instructions, and upon completion of such execution, return control to an instruction fetch routine to emulate the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 46 may include reading data from memory 38 into registers, storing data from registers back to memory, or performing some type of arithmetic or logical operation as determined by a translation routine.

[0109] For example, each routine is implemented in software that is stored in memory and executed by native central processing unit 37. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or some combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 41 or by using locations in memory 38. In an embodiment, guest instructions 43, native instructions 46, and emulator code 42 may reside in the same memory or may be distributed among different memory devices.

[0110] In accordance with one or more aspects of the present invention, an exemplary instruction that may be emulated is the multiply-add instruction described herein.

[0111] The computing environments described above are only examples of computing environments that can be used. Other environments may be used, including, but not limited to, non-partitioned, partitioned, cloud, or emulated environments, or combinations thereof, and embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are only examples.

[0112] Each computing environment can be configured to include one or more aspects of the present invention.

[0113] One or more aspects may relate to cloud computing.

[0114] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings presented herein is not limited to cloud computing environments. Embodiments of the present invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0115] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and for rapidly provisioning and releasing these resources with minimal administrative effort or interaction with a service provider. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0116] The features are as follows:

[0117] On-demand self-service: Cloud customers can unilaterally and automatically provision computing power, such as server time and network storage, as needed, without the need for human interaction with the service provider.

[0118] Wide network access: Cloud capabilities are available over the network and can be accessed using standard mechanisms, facilitating usage by heterogeneous thin- or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0119] Resource Pool: The provider's computing resources are pooled and offered to multiple consumers using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated according to demand. There is a sense of location independence; consumers typically have no control or knowledge regarding the exact location of the resources offered, although at a higher level of abstraction, they may be able to specify a location (e.g., country, state, or data center).

[0120] Rapid Elasticity: Cloud capacity can be quickly and elastically provisioned, in some cases automatically, to scale out quickly, and quickly released to scale in quickly. Capacity available for provisioning often appears to consumers as unlimited, available for purchase in any quantity at any time.

[0121] Metered Services: Cloud systems leverage metering capabilities to automatically control and optimize resource usage at an abstraction level appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0122] The service model is as follows:

[0123] SaaS (Software as a Service): The consumer is provided with the ability to use the provider's applications running on a cloud infrastructure. Those applications can be accessed from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or individual application features, except for the possibility of setting limited user-specific application configuration settings.

[0124] PaaS (Platform as a Service): The ability offered to a consumer is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of the application hosting environment.

[0125] Infrastructure as a Service (IaaS): The capability provided to a consumer is the provisioning of processing, storage, network, and other basic computing resources, upon which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, deployed applications, and in some cases, limited control over selected network components (e.g., host firewalls).

[0126] The deployment model is as follows:

[0127] Private Cloud: This cloud infrastructure is operated solely for the organization, can be managed by the organization or a third party, and can reside on-premise or off-premise.

[0128] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with shared interests (e.g., mission, security requirements, policy, and compliance considerations). It can be managed by these organizations or a third party and can reside on-premises or off-premises.

[0129] Public cloud: This cloud infrastructure is available for use by the general public or large industry organizations and is owned by an organization that sells cloud services.

[0130] Hybrid cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain distinct but are joined together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting to balance load between clouds).

[0131] A cloud computing environment is a service-oriented environment that emphasizes statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that contains a network of interconnected nodes.

[0132] Referring now to FIG. 8 , an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52 with which local computing devices used by cloud consumers (e.g., a personal digital assistant (PDA) or mobile phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N) can communicate. The nodes 52 may communicate with each other. The nodes 52 may be physically or virtually grouped in one or more networks (not shown), such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as previously described herein. This enables the cloud computing environment 50 to provide an infrastructure, platform, and / or SaaS that does not require cloud consumers to maintain resources on their local computing devices. The types of computing devices 54A-N shown in FIG. 8 are intended to be illustrative only, and it is understood that computing node 52 and cloud computing environment 50 can communicate with any type of computer-controlled device via any type of network and / or network-addressable connection (e.g., a connection using a web browser).

[0133] Referring now to Figure 9, a set of functional abstraction layers provided by cloud computing environment 50 (Figure 8) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 9 are intended to be illustrative only, and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0134] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0135] The virtualization layer 70 comprises an abstraction layer capable of providing virtual entities such as virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0136] By way of example, the management layer 80 may provide the following functions: Resource provisioning 81 dynamically procures computing and other resources used to execute tasks within the cloud computing environment; Metering and pricing 82 tracks costs as resources are utilized within the cloud computing environment and sends bills or invoices for the utilization of those resources; by way of example, those resources may include application software licenses; Security verifies the identity of cloud users and tasks and protects data and other resources; User portal 83 provides users and system administrators with access to the cloud computing environment; Service level management 84 allocates and manages cloud computing resources to meet required service levels; and Service Level Agreement (SLA) planning and execution 85 proactively prepares and procures cloud computing resources in accordance with SLAs in anticipation of future demand.

[0137] The Workload Layer 90 illustrates examples of functionality available in a cloud computing environment. Examples of workloads and functionality that may be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analysis processing 94, transaction processing 95, and multiply-add (or normalize, round, truncate, or a combination thereof) 96.

[0138] Aspects of the invention may be systems, methods, and / or computer program products, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to perform aspects of the invention.

[0139] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as being ephemeral signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0140] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof) that may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device.

[0141] Computer-readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0142] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0143] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to create a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium and capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for performing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0144] Computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process.

[0145] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may actually be realized as a single step, executed concurrently, executed substantially concurrently in a partially or fully overlapping manner in time, or executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks included in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of special-purpose hardware and computer instructions.

[0146] Additionally, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider that offers management of a customer's environment. For example, a service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from the customer, for example, under a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0147] In one aspect, an application may be deployed to perform one or more embodiments. As one example, deploying an application includes providing a computer infrastructure that functions to perform one or more embodiments.

[0148] As a further aspect, a computing infrastructure may be deployed that includes integrating computer readable code into a computing system, where the code in combination with the computing system is capable of executing one or more embodiments.

[0149] In yet another aspect, a process for integrating a computing infrastructure may be provided, comprising integrating computer-readable code into a computer system, the computer system comprising a computer-readable medium, the computer medium including one or more embodiments, the code in combination with the computer system capable of executing one or more embodiments.

[0150] Although various embodiments have been described above, they are merely examples. For example, computing environments of other architectures may be used to incorporate and / or use one or more aspects. Furthermore, different instructions or operations may be used. Furthermore, different types of registers and / or different registers may be used. Many variations are possible.

[0151] Various embodiments are described herein. Furthermore, many variations are possible without departing from the spirit of the embodiments of the present invention. It should be noted that each embodiment or feature described herein and variations thereof can be combined with any other embodiment or feature unless specifically inconsistent.

[0152] Additionally, other types of computing environments may be beneficial and may be used. By way of example, a data processing system may be used that includes at least two processors coupled directly or indirectly via a system bus to memory elements suitable for storing and / or executing program code. These memory elements may include, for example, local memory used during the actual execution of the program code, bulk storage, and cache memory for temporarily storing at least some program code to reduce the number of times the code must be retrieved from bulk storage during execution.

[0153] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other storage media) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the types of network adapters available.

[0154] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, indicate the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0155] Corresponding structures, materials, acts, and equivalents of all means or steps and functional elements within the scope of the claims below are intended to include any structure, material, or act for performing a function in combination with other claimed elements, if any, when specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain various aspects and practical applications, and to enable others skilled in the art to appreciate various embodiments with various modifications as may be suited to the particular use contemplated.

Claims

1. 1. A computer-implemented method comprising: Executing a single instruction to perform an operation selected from a plurality of operations configured for said instruction, said instruction including an opcode field and a mask field for specifying controls to be used in execution of said instruction, said executing said instruction comprising: determining a value of a selected operand of the instruction, the determining of the value being based on the control specified by the mask field of the instruction, the control being set by one control value of a plurality of control values ​​configured for the control, the one control value including a first value or a second value; reading the selected operand of the instruction from a selected operand location based on the control of the instruction including the first value to obtain the value of the selected operand; using a default value as the value of the selected operand based on the control of the instruction including the second value; said determining including: multiplying said value and another selected operand of said instruction to obtain a product; performing an arithmetic operation using the product and selected operands of the instruction to obtain an intermediate result; obtaining a result from the intermediate result; placing the result at a selected location; 11. A computer-implemented method comprising:

2. 2. The computer-implemented method of claim 1, wherein using the predetermined value as the value of the selected operand comprises using the predetermined value without reading the selected operand from the selected operand location, the selected operand location comprising at least one register.

3. The computer-implemented method of claim 1 or 2, wherein the predetermined value comprises a value of one.

4. executing the instructions, determining whether rounding is performed; based on a determination that the rounding operation is to be performed, performing the rounding operation on a version of the intermediate result to obtain the result; The computer-implemented method of claim 1 , further comprising:

5. The computer-implemented method of claim 4 , wherein the version of the intermediate result comprises a normalized result.

6. 5. The computer-implemented method of claim 4, wherein determining whether the rounding operation is to be performed comprises checking a rounding mode control of the instruction, and wherein the rounding operation is to be performed based on the rounding mode control being equal to a value of one.

7. Obtaining the result normalizing the intermediate result to obtain a normalized result; using the normalized result to obtain the result; 7. The computer-implemented method of claim 1, comprising:

8. using the normalized result to obtain the result; determining whether rounding is performed; based on a determination that the rounding operation is to be performed, rounding the normalized result to obtain the result; and truncating the normalized result to obtain the result based on a determination that the rounding is not performed.

9. 9. The computer-implemented method of claim 1, wherein the selected location comprises at least one register specified by at least one field of the instruction.

10. 10. The computer-implemented method of claim 1, wherein the control is an add-only control, the arithmetic operation includes an add operation, and based on the control including the second value, the control indicates that the instruction will perform an add-only operation in which the other selected operand is multiplied by the predetermined value of 1, and based on the control including the first value, the control indicates that the instruction will perform a multiply-add operation, and that the other selected operand is multiplied by the value read from the selected operand location.

11. A computer program product for causing a computer to execute the steps of the computer-implemented method according to any one of claims 1 to 10.

12. 1. A computer system comprising: Memory and a processor in communication with the memory; The memory stores the computer program of claim 11 , A system in which each of the procedures is executed by the processor to facilitate processing within a computing environment.

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