IEC protection of high frequency terminals

Abstract

An ESD trigger circuit is provided for protecting a pass transistor coupled to an integrated circuit terminal. The integrated circuit terminal is coupled to a voltage node through a diode. In response to an electrostatic shock at the integrated circuit terminal, the diode conducts charge to the voltage node, pulsing the voltage at the voltage node. The ESD trigger circuit responds to the voltage pulse by coupling the voltage node to the gate of the pass transistor.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of U.S. Patent Application No. 18 / 070,414, filed November 28, 2022, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes.

[0002] This application relates to electrostatic discharge (ESD) circuits for protecting terminals in accordance with International Electrotechnical Commission (IEC) standards, and more particularly to ESD circuits that provide IEC protection for high frequency terminals. [Background technology]

[0003] The fabrication of integrated circuits and their assembly into electronic devices typically occurs under controlled ESD conditions. Due to the ESD precautions taken during fabrication and assembly, the potential ESD stress from contact with technicians is relatively limited. To simulate this stress, the human body model (HBM) was developed. Due to the ESD precautions taken during fabrication and assembly, the stress from the HBM is not as severe as that developed by the International Electrotechnical Commission (IEC) to model the ESD stresses that may be applied to electronic devices by end users. Therefore, the voltage and current levels that integrated circuit terminals must withstand to meet IEC standards are significantly greater than the HBM levels.

[0004] To meet IEC standards, and therefore to accommodate such high levels of voltage and current, integrated circuit terminals are often coupled to robust ESD clamp circuits (sometimes referred to as ESD trigger circuits) capable of conducting increased amounts of charge from the integrated circuit terminal to a voltage node, such as ground or a power supply voltage rail. Clamp circuits that can safely accommodate IEC levels of charge typically load a significant amount of capacitance onto the integrated circuit. Such high capacitive loading by IEC clamp circuits can result in unacceptable bit error rates for high-speed (and therefore high-frequency) data signaling. Summary of the Invention [Means for solving the problem]

[0005] According to one aspect of the present disclosure, there is provided an electrostatic discharge (ESD) circuit including: an integrated circuit terminal; a pass transistor having a drain coupled to the integrated circuit terminal; a voltage node; a first ESD diode coupled between the integrated circuit terminal and the voltage node; and an ESD trigger circuit coupled between a gate of the pass transistor and the voltage node, the ESD trigger circuit configured to couple the gate of the pass transistor to the voltage node in response to an electrostatic shock of the integrated circuit terminal and to isolate the gate of the pass transistor from the voltage node in the absence of an electrostatic shock of the integrated circuit terminal.

[0006] According to another aspect of the present disclosure, there is provided a method of electrostatic discharge that includes the acts of receiving charge at a terminal of an integrated circuit from an electrostatic shock; conducting the charge from the terminal through a diode to a voltage node to pulse a voltage at the voltage node; and, in response to detecting the pulse in the voltage at the voltage node, coupling the voltage node to a gate of a pass transistor having a drain coupled to the terminal.

[0007] According to yet another aspect of the present disclosure, there is provided an electrostatic discharge (ESD) circuit including an integrated circuit terminal, a node for a high-speed data signal, a pass transistor coupled between the node for the high-speed data signal and the integrated circuit terminal, and an ESD trigger circuit configured to couple a power supply node for a power supply voltage to a gate of the pass transistor in response to a positive electrostatic shock to the integrated circuit terminal.

[0008] According to yet another aspect of the present disclosure, there is provided an electrostatic discharge (ESD) circuit including: an integrated circuit terminal; a node for a high-speed data signal; a pass transistor coupled between the node for the high-speed data signal and the integrated circuit terminal; and an ESD trigger circuit configured to couple a negative voltage node for a negative voltage to a gate of the pass transistor in response to a negative electrostatic shock to the integrated circuit terminal.

[0009] These and other advantageous features can be better understood through the following detailed description. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram of an integrated circuit including an ESD trigger circuit for pulsing voltages on the gate and bulk of a pass transistor coupled to an integrated circuit terminal, according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a circuit diagram of an integrated circuit having an ESD circuit for protecting an NMOS pass transistor according to one embodiment of the present disclosure. [Figure 3] FIG. 2 is a circuit diagram of an exemplary ESD circuit for protecting an NMOS pass transistor, according to one embodiment of the present disclosure. [Figure 4] FIG. 2 is a circuit diagram of an integrated circuit having an ESD circuit for protecting a PMOS pass transistor according to one embodiment of the present disclosure. [Figure 5] FIG. 2 is a circuit diagram of an exemplary ESD circuit for protecting a PMOS pass transistor, according to one embodiment of the present disclosure. [Figure 6] 1 is a flowchart of a method of operating an ESD circuit according to one embodiment of the present disclosure. [Figure 7] 1A-1C illustrate some exemplary electronic systems including ESD circuitry, according to an embodiment of the present disclosure.

[0011] Implementations of the present disclosure and their advantages are best understood by referring to the following detailed description, it being understood that like reference numerals are used to identify like elements shown in one or more of the figures. DETAILED DESCRIPTION OF THE INVENTION

[0012] The increased capacitive loading from the IEC clamp circuit is particularly problematic when the terminals of an integrated circuit are used not only to transmit (or receive) high-speed data during a high-speed data mode of operation, but also to transmit (or receive) audio signals during an audio mode of operation. A dual-mode integrated circuit 100 having both a high-speed data mode and an audio mode of operation is shown in FIG. 1. The integrated circuit 100 includes a differential pair of terminals formed by a universal serial bus (USB) data positive (DP) terminal and a data negative (DP) terminal. ESD diode D1 has its anode coupled to the DP terminal and its cathode coupled to a node of a power supply voltage Vdd. Similarly, ESD diode D2 has its anode coupled to a negative voltage node or rail of a negative voltage Vneg and its cathode coupled to the DP terminal. The DN terminal is protected by a similar pair of ESD diodes D3 and D4. The anode of diode D3 is coupled to the DN terminal, and its cathode is coupled to the power supply node. The anode of diode D4 is coupled to the negative voltage rail and its cathode is coupled to the DN terminal.

[0013] Diodes D1, D2, D3, and D4 protect terminals DP and DN from HBM-level charges but do not provide IEC ESD protection. To provide IEC ESD protection, integrated circuit 100 may include an ESD clamp circuit coupled to terminals DP and DN. As defined herein, an ESD clamp circuit capable of accommodating IEC amounts of electrostatically induced charge is referred to as an IEC clamp circuit. However, such an IEC clamp circuit loads terminals DP and DN with a capacitance of tens of picofarads, as described further herein. During a high-speed data operation mode, integrated circuit 100 may generate a DP signal (DPin) that couples via switch S1 and the DP terminal to an external device (not shown) that couples to the DP terminal via USB plug 105. Similarly, integrated circuit 100 may generate a DN signal (DNin) that couples via switch S3 and the DN terminal to an external device via USB plug 105. The bidirectional nature of the DP and DN terminals allows an external device to alternatively drive the DP and DN terminals such that the DPin and DNin signals are received signals rather than generated by integrated circuit 100.

[0014] During the audio mode of operation, integrated circuit 100 can generate a headphone right (HPHR) signal and a headphone left (HPHL) signal. Alternatively, these audio signals may be generated by another integrated circuit and sent to integrated circuit 100. The HPHR signal is coupled to the DP terminal via switch S2. Similarly, the HPHL signal is coupled to the DN terminal via switch S4. Switches S1 and S3 are open during the audio mode of operation. Similarly, switches S2 and S4 are open during the high-speed data mode of operation.

[0015] To pass both strong binary 1s and strong binary 0s, switches S1 and S3 can be constructed using transmission gates including both n-type metal-oxide-semiconductor (NMOS) and p-type metal-oxide-semiconductor (PMOS) pass transistors. Alternatively, switches S1 and S3 can be constructed using only a single pass transistor of either polarity. The pass transistor(s) used to construct switches S1 and S3 are off during audio operation mode and on during high-speed data mode. Switches S2 and S4 can also be constructed using pass transistors. Although the pass transistors forming switches S2 and S4 are off during high-speed data operation mode, these pass transistors and associated audio driver circuitry (not shown) load capacitance on the DP and DN terminals. This capacitive load may therefore become unsustainable if the DP and DN terminals couple to an IED clamp circuit.

[0016] To avoid capacitive loading from the ESD clamp circuit, integrated circuit 100 includes an ESD trigger circuit 110 that responds to electrostatic shock-induced charging of an integrated circuit terminal, such as the DP terminal or the DN terminal, by pulsing the voltages on the gate and bulk of a pass transistor that forms a switch coupled to the integrated circuit terminal. ESD trigger circuit 110 is sometimes referred to as an RC clamp circuit or an edge-triggered RC clamp circuit. Because ESD trigger circuit 110 does not couple to the DP terminal and the DN terminal, these terminals are not loaded with the capacitance of the IEC clamp circuit, and further, the pass transistor(s) coupled to the integrated circuit terminal are protected from IEC-level electrostatic shock-induced charging.

[0017] To better understand the function of ESD trigger circuit 110, an exemplary NMOS pass transistor M1 within integrated circuit 200 is shown in FIG. 2. Pass transistor M1 can be used to form switch S1 or S3, as described for integrated circuit 100. A plurality of audio pass transistors 210 form switches S2 and S4, as also described for integrated circuit 100. The drain of pass transistor M1 and the drain of audio pass transistor 210 (not shown) are both coupled to integrated circuit terminal DX. Integrated circuit terminal DX is a generic representation of either terminal DP or DN of integrated circuit 100. In this regard, the following description assumes that the high-speed data operating mode is the USB operating mode. However, it will be understood that the IEC ESD protection provided by the ESD trigger circuit disclosed herein may be applied to other types of high-speed data protocols.

[0018] In the audio mode of operation, the audio signal conducted through audio pass transistor 210 can be either positive or negative in voltage. To ensure that pass transistor M1 remains off during the audio mode in the presence of such a negative signal, controller 205 asserts the gate voltage of transistor M2, which is coupled between a negative voltage node for negative voltage Vneg and the gate of pass transistor M1. In this manner, the gate of pass transistor M1 is charged to the negative voltage Vneg during the audio mode of operation to ensure that pass transistor M1 does not conduct. During the high-speed data mode of operation, controller 205 switches off transistor M2 and switches on another transistor (not shown), which is coupled between the gate of pass transistor M1 and a power supply node for power supply voltage Vdd. Thus, pass transistor M1 is on during the high-speed data mode of operation, so that high-speed data signals can be conducted through pass transistor M1 to integrated circuit terminal DX. Transistor M3 is coupled between the bulk of pass transistor M1 and the negative voltage node. A controller, such as controller 205, controls the gate voltage of transistor M3 using the Vbulk control signal so that transistor M3 is on during audio mode and biases the bulk voltage Vbias of the pass transistor to the negative voltage Vneg.

[0019] While electrostatic shock-induced charging of the DX terminal can be either positive or negative, it can be shown that it is positive electrostatic charge that poses a danger to NMOS pass transistors, such as pass transistor M1. Conversely, it is negative electrostatic charge that poses a danger to PMOS pass transistors (not shown in FIG. 2 but described further herein). While ESD trigger circuit 110 is generic to the polarity of the pass transistor, in an exemplary implementation, there is a separate trigger circuit for protecting NMOS pass transistors compared to the trigger circuit for protecting PMOS pass transistors. In the case of pass transistor M1, NMOS pass transistor protection ESD trigger circuit 215 couples between a power supply node for power supply voltage Vdd and the gate of transistor M1. During normal operation (no electrostatic shock on the DX terminal), ESD trigger circuit 215 isolates the power supply node from the gate of pass transistor M1. However, in response to positive electrostatic charging of the DX terminal, ESD trigger circuit 215 couples the power supply node to the gate of transistor M1.

[0020] To provide additional ESD protection against positive electrostatic charge, the DX terminal couples to the power supply node through a Dpositive diode, which is a generic representation of either diode D1 or diode D3 of the integrated circuit 100. Similarly, to provide ESD protection against negative electrostatic charge, the DX terminal couples to the negative voltage node Vneg through a Vnegative diode, which is a generic representation of either diode D2 or diode D4 of the integrated circuit 100. In the presence of a positive electrostatic charge on the DX terminal, the Dpositive diode becomes forward biased, resulting in positive charge conduction to the power supply node. The ESD trigger circuit 215 responds to the resulting positive pulse of the power supply voltage Vdd by coupling the power supply node to the gate of transistor M1. This coupling through the ESD trigger circuit 215 also pulses the gate voltage of pass transistor M1 positive. Because transistor M2 is on, the pulse of the gate voltage of pass transistor M1 conducts through transistor M2, raising the negative voltage of the negative voltage Vneg. Because transistor M3 is also on during the audio mode of operation, pulsing the negative voltage Vneg positive also pulses the bulk voltage Vbulk of pass transistor M1 high. In this way, the gate-drain and gate-bulk voltages of pass transistor M1 are maintained at safe levels even if the DX terminal is suddenly exposed to an IEC-level positive static charge.

[0021] A positive electrostatic charge of IEC level on terminal DX can raise the voltage of terminal DX to approximately 10 V (albeit for a short time). It will be understood that this voltage value is exemplary and other values ​​may be used. Similarly, the negative voltage Vneg of −2 V is exemplary and can be changed in alternative embodiments. If the negative voltage Vneg is −2 V and terminal DX is charged to 10 V, the gate-drain voltage of pass transistor M1 is approximately −12 V in the absence of ESD trigger circuit 215. Such a relatively large gate-drain voltage could damage pass transistor M1. However, due to the protective action of ESD trigger circuit 215, the gate voltage also pulses high for a short time, such as to approximately 7.5 V. Therefore, the gate-drain voltage of pass transistor M1 is only approximately −2.5 V, which is easily tolerated. Similarly, conduction by ESD trigger circuit 215 can pulse the bulk voltage Vbulk of pass transistor M1 to approximately 5 V. Thus, the bulk-drain voltage of the pass transistor in response to a positive electrostatic shock is limited to approximately 5 V, which is also tolerated by pass transistor M1. Note that ESD trigger circuit 215 does not load the DX terminal; instead, it indirectly detects the pulsing of the DX terminal voltage by detecting the resulting pulsing of the power supply voltage Vdd. In this way, ESD trigger circuit 215 advantageously does not load any extra capacitance on the DX terminal. In contrast, conventional IEC clamp circuits load a significant amount of capacitance (e.g., tens of picofarads) on terminal DX. Therefore, ESD trigger circuit 215 is highly advantageous in providing IEC ESD protection without contributing any capacitive loading to the DX terminal. In this way, the DX terminal has an appropriately low level of capacitive loading for high-speed data signaling.

[0022] An exemplary circuit implementation 300 of the ESD trigger circuit 215 is shown in FIG. 3. However, it will be appreciated that numerous alternative implementations are possible for constructing an edge trigger circuit that functions to isolate the power supply node from the pass transistor gate during normal conditions and responds to a sudden increase in power supply voltage by coupling the pass transistor gate to the power supply node. The ESD trigger circuit 300 includes a low-pass filter, such as a low-pass RC filter formed by the series combination of a resistor R1 and a capacitor C1. The resistor R1 has a terminal coupled to a power supply node for the power supply voltage Vdd. Conversely, the capacitor C1 has a terminal coupled to a ground node Vss. Due to the low-pass filtering, a voltage Vfilter at a node 305 between the resistor R1 and the capacitor C1 is equal to the default (unaffected) value of the power supply voltage Vdd. The node 305 is coupled to the gate of a PMOS transistor P1, which has its source coupled to the power supply node. Thus, during normal operation, the transistor P1 is off. In response to a sudden increase in the power supply voltage Vdd, the voltage Vfilter decreases, switching on the transistor P1. The drain of transistor P1 is coupled to the ground node through resistor R2 in series with capacitor C2. Thus, the voltage at node 310 between resistor R2 and capacitor C2 increases in response to increases in power supply voltage Vdd. Node 310 is coupled to the gate of NMOS transistor M4, which has its source coupled to ground. Thus, transistor M4 switches on in response to pulsing of power supply voltage Vdd. The drain of transistor M4 is coupled to the power supply node through resistor R3. Switching on transistor M4 reduces its drain voltage. The drain of transistor M4 is coupled to PMOS transistor P2, which has its source coupled to the power supply node. Discharging the drain voltage of transistor M4 then switches on transistor P2. The drain of transistor P2 is coupled to a pass transistor gate, such as the gate of pass transistor M1 (not shown in FIG. 3), through PMOS transistor P3. Transistor P3 is biased into saturation by a bias voltage Vbias.Thus, in response to an electrostatic shock at terminal DX, the pass transistor gate is pulsed high by ESD trigger circuit 300. In this manner, the bulk and gate of the pass transistor protected by ESD trigger circuit 300 are pulsed high in voltage, as described for pass transistor M1.

[0023] As previously mentioned, the pass transistors may also be PMOS transistors. An exemplary PMOS pass transistor P4 in integrated circuit 400 is shown in FIG. 4. Pass transistor P4 may be used to form switch S1 or S3, as described for integrated circuit 100. Audio pass transistor 210 forms switches S2 and S4, as also described for integrated circuit 100. If these audio pass transistors 210 are PMOS transistors, they may be ESD protected in a manner similar to that described for pass transistor P4. The drains of pass transistor P4 and audio pass transistor 210 (not shown) are both coupled to integrated circuit terminal DX, which is a generic representation of either terminals DP and DN of integrated circuit 100. As noted above, it will be understood that the IEC ESD protection provided by the ESD trigger circuits disclosed herein may be applied to other types of high-speed data protocols besides USB.

[0024] To ensure that pass transistor P4 remains off during the audio mode, controller 405 grounds the gate voltage Vcontrol of PMOS transistor P5, which is coupled between the power supply node and the gate of pass transistor P4. In this manner, the gate of pass transistor P4 is charged to the power supply voltage Vdd during the audio mode of operation to ensure that pass transistor P4 does not conduct. During the high-speed data mode of operation, controller 405 switches off transistor P5 and switches on another transistor (not shown) coupled between the gate of pass transistor P4 and the ground node. Thus, pass transistor P4 is on during the high-speed data mode of operation, so that high-speed data signals can be conducted to integrated circuit terminal DX through pass transistor M4. PMOS transistor P6 is coupled between the bulk of pass transistor P4 and the power supply node. A controller such as controller 405 controls the gate voltage of transistor P6 using a Vbulk control signal so that transistor P6 is on during the audio mode and biases the bulk voltage Vbias of pass transistor P4 to the power supply voltage Vdd.

[0025] While electrostatic shock-induced charging of the DX terminal can be either positive or negative, it can be shown that it is negative electrostatic charge that poses a danger to PMOS pass transistors, such as pass transistor P4. As previously mentioned, ESD trigger circuit 110 is generic to the polarity of the pass transistor, but in an exemplary implementation, there is a separate trigger circuit for protecting NMOS pass transistors compared to the ESD trigger circuit for protecting PMOS pass transistors. For pass transistor M4, PMOS pass transistor protection ESD trigger circuit 415 couples between the negative voltage node and the gate of pass transistor P4. During normal operation (no electrostatic shock on the DX terminal), ESD trigger circuit 415 isolates the negative voltage node from the gate of pass transistor P4. However, in response to negative electrostatic charging of the DX terminal, ESD trigger circuit 415 couples the negative voltage node to the gate of pass transistor P4.

[0026] To provide additional ESD protection against negative electrostatic charge, the DX terminal couples to a negative voltage node through a Dnegative diode, which is a generic representation of either diode D2 or diode D4 of the integrated circuit 100. Similarly, to provide ESD protection against positive electrostatic charge, the DX terminal couples to a power supply node through a Dpositive diode, which is a generic representation of either diode D1 or diode D3 of the integrated circuit 100. In the presence of a negative electrostatic charge on the DX terminal, the Dnegative diode becomes forward biased, resulting in negative charge being conducted to the negative voltage node Vneg. The nominal value of the negative voltage may be −2 V; however, in the presence of a negative electrostatic charge on the DX terminal, the negative voltage may be pulled substantially more negative, such as approximately −10 V. It will be understood that such voltage values ​​are merely exemplary and may be higher or lower depending on the exact amount of negative electrostatic charge supplied to the DX terminal and the voltage of the negative voltage node. The trigger circuit 415 responds to the resulting negative pulse drive of the negative voltage node Vneg by coupling the negative voltage node to the gate of pass transistor P4. This coupling through the ESD trigger circuit 415 also pulses the gate voltage of pass transistor P4 negative. Because transistor P5 is on, the negative pulse on the gate voltage of pass transistor P4 conducts through transistor P5, negatively pulsing the power supply voltage Vdd. Because transistor P6 is on, the negative pulse on the DX terminal also pulses the bulk voltage Vbulk of pass transistor P4 negative. In this way, the gate-drain and gate-bulk voltages of pass transistor P4 are maintained at safe levels even if the DX terminal is suddenly exposed to an IEC-level negative static charge. As previously mentioned, an IEC-level negative static charge on terminal DX reduces the voltage at terminal DX to approximately −10 V (albeit for a short time). If the power supply voltage Vdd is 1 V, the gate-drain voltage of pass transistor P4 would be 11 V without the ESD trigger circuit 415. Such a relatively large gate-drain voltage could damage pass transistor P4. However, due to the protective action of the ESD trigger circuit 415, the gate voltage is also pulsed negative for a short period of time, such as to about -8V.Therefore, the gate-drain voltage of pass transistor P4 is only about 2 V, which is easily tolerated. Similarly, conduction by ESD trigger circuit 415 can pulse the bulk voltage Vbulk of pass transistor P4 negatively to about −6 V. Therefore, the bulk-drain voltage of pass transistor P4 in response to a negative electrostatic shock is limited to about 4 V, which is also tolerated by pass transistor P4. Note that ESD trigger circuit 415 does not load the DX terminal; instead, it indirectly detects the pulsing of the DX terminal voltage by detecting the resulting pulsing of the negative voltage Vneg. In this way, trigger circuit 415 advantageously does not load any extra capacitance on the DX terminal. In contrast, conventional IEC clamp circuits load a significant amount of capacitance (e.g., tens of picofarads) on terminal DX. Therefore, ESD trigger circuit 415 is highly advantageous in providing IEC-level ESD protection without contributing any significant capacitive loading to the DX terminal. In this way, the DX terminal has an appropriately low level of capacitive loading for high speed data signaling.

[0027] An exemplary circuit implementation 500 of the ESD trigger circuit 415 is shown in FIG. 5. However, it will be appreciated that numerous alternative implementations are possible to construct an edge-triggered RC clamp circuit that functions to isolate the power supply node from the pass transistor gate during normal conditions and responds to sudden increases in the power supply voltage by coupling the pass transistor gate to the power supply node. The ESD trigger circuit 500 includes a low-pass filter, such as a low-pass RC filter formed by the series combination of resistor R4 and capacitor C4. Resistor R4 has a terminal coupled to a negative voltage node for the negative voltage Vneg. Conversely, capacitor C4 has a terminal coupled to the ground node Vss. Due to the low-pass filtering, a voltage Vfilter at a node 505 between resistor R4 and capacitor C4 is equal to the default (undamaged) value of the negative power supply voltage. Node 505 is coupled to the gate of an NMOS transistor M5, which has its source coupled to the negative voltage node. Thus, during normal operation, transistor M5 is off. In response to the sudden decrease in the negative voltage Vneg, the gate-source voltage of transistor M5 rises, thereby switching on transistor M5 and discharging its drain voltage. The drain of transistor M5 is coupled to a high-pass filter formed by the series combination of capacitor C5 and resistor R5. A terminal of resistor R5 is coupled to the gate of a PMOS pass transistor (not shown) protected by ESD trigger circuit 500. A node 510 between resistor R5 and capacitor C5 is coupled to the gate of PMOS transistor P7, which has its source coupled to the gate of the PMOS pass transistor and its drain coupled to the ground node. Due to the high-pass filtering by capacitor C5 and resistor R5, the sudden decrease in the drain voltage of transistor M5 causes a sudden decrease in the voltage at node 510, thereby switching on transistor P7. Therefore, the gate voltage of the PMOS pass transistor is pulsed negative by ESD trigger circuit 500.

[0028] A method of operating an ESD circuit will now be described with reference to the flowchart shown in FIG. 6 . The method includes an operation 600 of receiving charge at a terminal of an integrated circuit from an electrostatic shock. Charging terminal DX of integrated circuit 200 or 400 or terminal DP or DN of integrated circuit 100 is an example of operation 600. The method also includes an operation 605 of conducting charge from the terminal through a diode to a voltage node to pulse the voltage of the voltage node. Conducting charge through a Dpositive diode in integrated circuit 200 to pulse the power supply voltage Vdd positively or conducting charge through a Dnegative diode in integrated circuit 400 to pulse the negative voltage Vneg negatively is an example of operation 605. The method further includes an operation 610 of coupling the voltage node to a gate of a pass transistor having a drain coupled to the terminal in response to detecting the pulse in the voltage of the voltage node. Coupling through ESD trigger circuit 300 or through ESD trigger circuit 500 is an example of operation 610.

[0029] The ESD circuits disclosed herein can be incorporated into any suitable mobile device or electronic system. For example, as shown in Figure 7, a cellular telephone 700, a laptop computer 705, and a tablet PC 710 can all include ESD circuits according to the present disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, can also be configured with ESD circuits constructed according to the present disclosure.

[0030] The disclosure is now summarized in the following series of clauses. Clause 1. An electrostatic discharge (ESD) circuit comprising: an integrated circuit terminal; a pass transistor having a drain coupled to an integrated circuit terminal; a voltage node; a first ESD diode coupled between the integrated circuit terminal and the voltage node; an ESD trigger circuit coupled between the gate of the pass transistor and the voltage node, the ESD trigger circuit configured to couple the gate of the pass transistor to the voltage node in response to an electrostatic shock of the integrated circuit terminal and to isolate the gate of the pass transistor from the voltage node in the absence of an electrostatic shock of the integrated circuit terminal; 1. An electrostatic discharge circuit comprising: Clause 2. The electrostatic discharge circuit of clause 1, wherein the pass transistor is an n-type metal-oxide-semiconductor (NMOS) pass transistor. Clause 3. The electrostatic discharge circuit of clause 1 or 2, wherein the voltage node is a power supply node for a power supply voltage. Clause 4. The electrostatic discharge circuit of any one of clauses 1 to 3, wherein the integrated circuit terminal is a data terminal for a universal serial bus (USB) interface. Article 5. a negative voltage node for a negative voltage; a second ESD diode coupled between the integrated circuit terminal and the negative voltage node; 4. The electrostatic discharge circuit of claim 3, further comprising: Article 6. a first transistor coupled between the negative voltage node and the gate of the pass transistor; a controller configured to switch on the first transistor to charge the gate of the pass transistor to the negative power supply voltage during an audio mode of operation; 6. The electrostatic discharge circuit of clause 5, further comprising: Article 7. a second transistor coupled between the negative voltage node and the bulk of the pass transistor, the controller further configured to switch on the second transistor during the audio mode of operation. Electrostatic discharge circuitry as described in clause 6. Clause 8. The electrostatic discharge circuit of clause 3, wherein the ESD trigger circuit includes a first PMOS transistor having a source coupled to the power supply node and a drain coupled to the gate of the pass transistor. Clause 9. The electrostatic discharge circuit of any one of clauses 1 to 9, wherein the ESD trigger circuit further comprises a low pass filter. Clause 10. The electrostatic discharge circuit of clause 1, wherein the pass transistor is a PMOS transistor. Clause 11. The electrostatic discharge circuit of clause 10, wherein the voltage node is a negative voltage node for a negative voltage. Article 12. 11. The electrostatic discharge circuit of clause 10, further comprising a second ESD diode coupled between the integrated circuit terminal and a power supply node for a power supply voltage. Article 13. a first PMOS transistor coupled between the gate of the pass transistor and the power supply node; a controller configured to switch on the first PMOS transistor during an audio mode of operation; 13. The electrostatic discharge circuit of claim 12, further comprising: Article 14. a second PMOS transistor coupled between the bulk of the pass transistor and the power supply node, the controller being further configured to switch on the second PMOS transistor during an audio mode of operation. Electrostatic discharge circuitry as described in clause 13. Clause 15. Electrostatic discharge method comprising: receiving charge at a terminal of the integrated circuit from an electrostatic shock; conducting charge from the terminal through the diode to the voltage node to pulse the voltage of the voltage node; In response to detecting a pulse in a voltage at the voltage node, coupling the voltage node to a gate of a pass transistor having a drain coupled to the terminal; A method comprising: Clause 16. The method of clause 15, wherein receiving charge at the terminal includes receiving positive charge, and conducting charge from the terminal through the diode to the voltage node includes conducting positive charge from the terminal to a power supply node for the power supply voltage. Clause 17. The method of clause 15, wherein receiving charge at the terminal includes receiving negative charge, and conducting charge from the terminal through the diode to the voltage node includes conducting negative charge from the terminal to a negative voltage node for the negative voltage. Clause 18. An electrostatic discharge (ESD) circuit comprising: an integrated circuit terminal; a node for high speed data signals; a pass transistor coupled between the node for the high speed data signal and the integrated circuit terminal; an ESD trigger circuit configured to couple a power supply node for a power supply voltage to a gate of the pass transistor in response to a positive electrostatic shock to the integrated circuit terminal; 1. An electrostatic discharge circuit comprising: Article 19. 20. The electrostatic discharge circuit of clause 18, further comprising a diode having an anode coupled to the integrated circuit terminal and a cathode coupled to the power supply node. Clause 20. The electrostatic discharge circuit of clause 18, wherein the integrated circuit terminal is an integrated circuit terminal for an integrated circuit contained within a cellular telephone. Clause 21. The electrostatic discharge circuit of clause 18, wherein the pass transistor is an NMOS pass transistor. Clause 22. An electrostatic discharge (ESD) circuit comprising: an integrated circuit terminal; a node for high speed data signals; a pass transistor coupled between the node for the high speed data signal and the integrated circuit terminal; an ESD trigger circuit configured to couple a negative voltage node for a negative voltage to the gate of the pass transistor in response to a negative electrostatic shock to the integrated circuit terminal; 1. An electrostatic discharge circuit comprising: Article 23. 23. The electrostatic discharge circuit of clause 22, further comprising a diode having an anode coupled to the negative voltage node and a cathode coupled to the integrated circuit terminal. Clause 24. The electrostatic discharge circuit of clause 22, wherein the pass transistor is a PMOS pass transistor.

[0031] It will be understood that numerous modifications, substitutions, and variations can be made in the materials, arrangements, constructions, and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, and since the specific implementations illustrated and described herein are merely a few examples, the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be given the full scope of the following appended claims and their functional equivalents.

Claims

1. 1. An electrostatic discharge (ESD) circuit, comprising: an integrated circuit terminal; a pass transistor having a drain coupled to the integrated circuit terminal; a voltage node; a first ESD diode coupled between the integrated circuit terminal and the voltage node; an ESD trigger circuit coupled between a gate of the pass transistor and the voltage node, the ESD trigger circuit configured to couple the gate of the pass transistor to the voltage node in response to an electrostatic shock of the integrated circuit terminal and to isolate the gate of the pass transistor from the voltage node in the absence of the electrostatic shock of the integrated circuit terminal; 1. An electrostatic discharge circuit comprising:

2. 2. The electrostatic discharge circuit of claim 1, wherein the pass transistor is an n-type metal-oxide-semiconductor (NMOS) pass transistor.

3. 3. The electrostatic discharge circuit of claim 2, wherein the voltage node is a power supply node for a power supply voltage.

4. 3. The electrostatic discharge circuit of claim 2, wherein the integrated circuit terminal is a data terminal for a Universal Serial Bus (USB) interface.

5. a negative voltage node for a negative voltage; a second ESD diode coupled between the integrated circuit terminal and the negative voltage node; 4. The electrostatic discharge circuit of claim 3, further comprising:

6. a first transistor coupled between the negative voltage node and the gate of the pass transistor; a controller configured to switch on the first transistor to charge the gate of the pass transistor to the negative power supply voltage during an audio mode of operation; 6. The electrostatic discharge circuit of claim 5, further comprising:

7. a second transistor coupled between the negative voltage node and a bulk of the pass transistor, the controller further configured to switch on the second transistor during the audio mode of operation.

7. The electrostatic discharge circuit of claim 6.

8. 4. The electrostatic discharge circuit of claim 3, wherein the ESD trigger circuit includes a first PMOS transistor having a source coupled to the power supply node and a drain coupled to the gate of the pass transistor.

9. 4. The electrostatic discharge circuit of claim 3, wherein the ESD trigger circuit further comprises a low pass filter.

10. 2. The electrostatic discharge circuit of claim 1, wherein the pass transistor is a PMOS transistor.

11. 11. The electrostatic discharge circuit of claim 10, wherein the voltage node is a negative voltage node for a negative voltage.

12. 11. The electrostatic discharge circuit of claim 10, further comprising a second ESD diode coupled between the integrated circuit terminal and a power supply node for a power supply voltage.

13. a first PMOS transistor coupled between the gate of the pass transistor and the power supply node; a controller configured to switch on the first PMOS transistor during an audio mode of operation; 13. The electrostatic discharge circuit of claim 12, further comprising:

14. a second PMOS transistor coupled between the bulk of the pass transistor and the power supply node, the controller further configured to switch on the second PMOS transistor during the audio mode of operation.

14. The electrostatic discharge circuit of claim 13.

15. 1. A method of electrostatic discharge comprising: receiving charge at a terminal of the integrated circuit from an electrostatic shock; conducting the charge from the terminal through a diode to a voltage node to pulse a voltage on the voltage node; responsive to detecting the pulsing of the voltage at the voltage node, coupling the voltage node to a gate of a pass transistor having a drain coupled to the terminal; A method comprising:

16. 16. The method of claim 15, wherein receiving the charge at the terminal comprises receiving a positive charge, and conducting the charge from the terminal through the diode to the voltage node comprises conducting the positive charge from the terminal to a power supply node for a power supply voltage.

17. 16. The method of claim 15, wherein receiving the charge at the terminal comprises receiving a negative charge, and conducting the charge from the terminal through the diode to the voltage node comprises conducting the negative charge from the terminal to a negative voltage node for a negative voltage.

18. 1. An electrostatic discharge (ESD) circuit, comprising: an integrated circuit terminal; a node for high speed data signals; a pass transistor coupled between the node and the integrated circuit terminal for the high speed data signal; an ESD trigger circuit configured to couple a power supply node for a power supply voltage to a gate of the pass transistor in response to a positive electrostatic shock to the integrated circuit terminal; 1. An electrostatic discharge circuit comprising:

19. 20. The electrostatic discharge circuit of claim 18, further comprising a diode having an anode coupled to the integrated circuit terminal and a cathode coupled to the power supply node.

20. 20. The electrostatic discharge circuit of claim 18, wherein the integrated circuit terminal is an integrated circuit terminal for an integrated circuit contained within a cellular telephone.

21. 20. The electrostatic discharge circuit of claim 18, wherein the pass transistor is an NMOS pass transistor.

22. 1. An electrostatic discharge (ESD) circuit, comprising: an integrated circuit terminal; a node for high speed data signals; a pass transistor coupled between the node and the integrated circuit terminal for the high speed data signal; an ESD trigger circuit configured to couple a negative voltage node for a negative voltage to the gate of the pass transistor in response to a negative electrostatic shock to the integrated circuit terminal; 1. An electrostatic discharge circuit comprising:

23. 23. The electrostatic discharge circuit of claim 22, further comprising a diode having an anode coupled to the negative voltage node and a cathode coupled to the integrated circuit terminal.

24. 23. The electrostatic discharge circuit of claim 22, wherein the pass transistor is a PMOS pass transistor.

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