Latch cross-coupling for stacked and stepped FETs.

Abstract

A semiconductor structure is presented that includes a first field effect transistor (FET) including a first device layer, a second FET including a second device layer, where the first device layer has a stepped portion relative to the second device layer, and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer. The first FET is stacked on top of the second FET. The second device layer is larger than the first device layer. The gate of the first FET is located above the first device layer having the stepped portion. (Figure 3)

Description

[Technical Field]

[0001] The present invention relates generally to semiconductor devices, and more particularly to constructing latch cross-couplings for stacked and stepped field effect transistors (FETs).

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric, conductive, and semiconducting layers of material above a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry has experienced rapid growth due to improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In large part, this improvement in integration density has resulted from shrinking semiconductor process nodes. Along with the increased demand for smaller size, higher speed, greater bandwidth, lower power consumption, and lower latency, chip layouts have become more complex and difficult to achieve in the production of semiconductor dies.

[0004] A device structure for a field effect transistor (FET) typically includes a source, a drain, and a gate electrode configured to switch the flow of carriers in a channel formed in a semiconductor body between the source and drain. When a control voltage above a specified threshold voltage is applied to the gate electrode, the flow of carriers in the channel between the source and drain generates a device output current.

[0005] The body and channel of a planar FET are located below the top surface of a substrate on which a gate electrode is supported. A fin-type field-effect transistor (FinFET) is a non-planar device structure for FETs that can be packed more densely within an integrated circuit than a planar FET. A FinFET includes a fin, heavily doped source / drain regions, and a gate electrode wrapping around the fin. During operation, a channel for carrier flow is formed within the fin between the source / drain regions. Compared to planar FETs, the arrangement between the gate structure and the fins improves control over the channel and reduces leakage current when the FinFET is in its "off" state. This, in turn, lowers the threshold voltage compared to planar FETs, resulting in improved performance and reduced power consumption.

[0006] Nanosheet FETs have been developed as an advanced type of FinFET that may allow for additional increases in packing density in integrated circuits (ICs). The body of a nanosheet FET includes multiple nanosheet channel layers stacked vertically in a three-dimensional array. Sections of gate stacks may surround individual nanosheet channel layers on all sides in a gate-all-around configuration. The nanosheet channel layers are first arranged in a layer stack with a sacrificial layer composed of a material (e.g., silicon-germanium) that can be selectively etched relative to the material (e.g., silicon) that constitutes the nanosheet channel layer. The sacrificial layer is etched and removed to release the nanosheet channel layer and provide space for the formation of the gate stack.

[0007] Gate-all-around field effect transistors (GAAFETs) (e.g., nanowire-type GAAFETs or nanosheet-type GAAFETs) have been developed to improve drive current and static electricity, as well as allow scaling of device size, increased device density, and reduced area consumption. A GAAFET includes an elongated nanofeature (e.g., a nanowire or nanosheet) extending laterally between source / drain regions, and a wrap-around gate structure wrapping around the nanofeature so that the nanofeature functions as a channel region.

[0008] Recently, complementary field-effect transistors (CFETs) have been developed to further increase on-chip device density and reduce area consumption. A CFET typically includes a pair of N-type and P-type GAAFETs stacked on top of each other and having a common gate structure, as opposed to being side-by-side with discrete gate structures. Specifically, a CFET includes an N-type GAAFET in one level, a P-type GAAFET in an adjacent level (e.g., above or below), and a common gate extending vertically across and wrapping around the stacked channel regions of the N-type and P-type GAAFETs. Typically, the source / drain regions of the lower-level GAAFET are electrically isolated from the source / drain regions of the upper-level GAAFET by one or more isolation layers. Such CFETs can be incorporated, for example, into a six-transistor (6T) static random access memory (SRAM) cell, one for each pair of pull-down and pull-up field-effect transistors. While using CFETs can increase on-chip device density and reduce area consumption, providing signal connections to the source / drain regions of lower-level GAAFETs (e.g., to realize cross-coupled connections in SRAM cells) can become quite complex. Summary of the Invention

[0009] According to an embodiment, a semiconductor structure is provided, the semiconductor structure including a first field effect transistor (FET) including a first device layer, a second FET including a second device layer, where the first device layer has a stepped portion relative to the second device layer, and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer.

[0010] According to another embodiment, a semiconductor structure is provided that includes a first field effect transistor (FET) including a first device layer, a second FET including a second device layer, and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer.

[0011] According to yet another embodiment, a semiconductor structure is provided, the semiconductor structure including a first field effect transistor (FET) including a first device layer, a second FET including a second device layer, the second device layer being larger than the first device layer, and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer.

[0012] In one preferred embodiment, the first FET is stacked on top of the second FET.

[0013] In another preferred embodiment, the second device layer is larger than the first device layer.

[0014] In yet another preferred embodiment, the first FET is a p-type FET and the second FET is an n-type FET.

[0015] In one preferred embodiment, the gate of the first FET is located above the first device layer having a stepped portion.

[0016] In another preferred embodiment, the gate of the first FET is located above both the first and second device layers.

[0017] In yet another preferred embodiment, the second FET includes a floating gate.

[0018] In yet another preferred embodiment, the floating gate is vertically aligned with the stepped portion of the first device layer.

[0019] In a preferred embodiment, the first device layer is centered relative to the second device layer.

[0020] In another preferred embodiment, the first device layer is positioned adjacent to the second device layer such that a surface of the first device layer is horizontally aligned with a surface of the second device layer.

[0021] In yet another preferred embodiment, the first device layer generally overlaps the second device layer.

[0022] In yet another preferred embodiment, the gate of the first FET is located above the first device layer having a double step structure.

[0023] In yet another preferred embodiment, the gate of the first FET is located above both the first and second device layers.

[0024] Advantages of the present invention include producing transistors that consume less power, have better performance, occupy less area on a wafer, and reduce costs in semiconductor manufacturing. Further advantages of the present invention include improving the latch cross-couple configuration or connection used in circuits. In conventional non-stacked transistors, the latch cross-couple connects the PC or gate layer of an NFET to the PC or gate layer of a PFET, resulting in a cross or "X" connection between them. This "X" connection between the PC or gate layers of a PFET and an NFET can be difficult, however. However, stacked FETs such as those presented herein, in which, for example, a PFET is stacked on top of an NFET, can advantageously alleviate such implementation challenges. In addition to being stacked, the PFET and NFET can also be advantageously stepped. The term "stepped" refers to a stepped structure in which one nanosheet (or FET) is wider than the other to advantageously create a step or ledge. For example, the first nanosheet stack (or FET) is advantageously wider than the second nanosheet stack (or FET), such that a stepped region or shelf is advantageously formed at the intersection of the first and second nanosheet stacks (or FETs).

[0025] It should be noted that exemplary embodiments are described with reference to different subject matter. In particular, some embodiments are described with reference to method-type claims, while other embodiments are described with reference to apparatus-type claims. However, those skilled in the art will appreciate from the above and following description that, unless otherwise notified, any combination of features belonging to one type of subject matter, as well as any combination between features relating to different subject matters, particularly between features of method-type claims and between features of apparatus-type claims, is considered to be described within this specification.

[0026] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0027] The present invention is provided in more detail in the following description of preferred embodiments with reference to the following drawings.

[0028] [Figure 1] 1 is a circuit diagram of a stacked field effect transistor (FET) according to an embodiment of the present invention.

[0029] [Figure 2] 1 is a top view of a semiconductor structure presenting a stacked and stepped FET structure according to an embodiment of the present invention;

[0030] [Figure 3] 3 is a cross-sectional view of the semiconductor structure of FIG. 2 showing a first FET and a second FET of a stacked and stepped FET structure according to an embodiment of the present invention.

[0031] [Figure 4] 1 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0032] [Figure 5] 1 is a top view of a semiconductor structure in which the top FET of a stacked and stepped FET structure includes a floating gate, according to an embodiment of the present invention.

[0033] [Figure 6] 6 is a cross-sectional view of the semiconductor structure of FIG. 5 showing the floating gate of the top FET according to an embodiment of the present invention.

[0034] [Figure 7] 1 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0035] [Figure 8] 1 is a top view of a semiconductor structure in which the stacked and stepped FET structure includes a double step stacked FET according to an embodiment of the present invention. FIG.

[0036] [Figure 9] 9 is a cross-sectional view of the semiconductor structure of FIG. 8 showing the first and second FETs of the stacked and stepped FET structure according to an embodiment of the present invention.

[0037] [Figure 10] 1 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0038] [Figure 11] 1 is a top view of a semiconductor structure in which a stacked and stepped FET structure includes a double step stacked FET with a smaller bottom transistor, according to an embodiment of the present invention. FIG.

[0039] [Figure 12] 12 is a cross-sectional view of the semiconductor structure of FIG. 11 showing the first and second FETs of a stacked and stepped FET structure with a smaller bottom FET according to an embodiment of the present invention.

[0040] [Figure 13] 1 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0041] [Figure 14] 1 is a top view of a semiconductor structure in which a stacked and stepped FET structure includes a double step stacked FET with a larger bottom transistor, according to an embodiment of the present invention. FIG.

[0042] [Figure 15] 15 is a cross-sectional view of the semiconductor structure of FIG. 14 showing the first and second FETs of a stacked and stepped FET structure with a larger bottom FET according to an embodiment of the present invention.

[0043] Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. DETAILED DESCRIPTION OF THE INVENTION

[0044] Embodiments in accordance with the present invention provide methods and devices for constructing latch cross-couplings for stacked and stepped field-effect transistors (FETs). The stacked FET includes a first device layer and a second device layer, where one of the device layers is advantageously shifted or tapered or stepped relative to the other device layer. The shifted or tapered device layer is advantageously shifted or tapered between the gates or "PCs" of the device. Electrical connections are advantageously made from the bottom gate to the top gate in the shifted or tapered device layer. A floating gate may also be used on the shifted or tapered device layer. In other embodiments, a double-step stacked FET is advantageously used. Also, one of the device layers is advantageously larger in size or larger than the other device layer.

[0045] Examples of semiconductor materials that can be used to form such structures include silicon (Si), germanium (Ge), silicon germanium alloy (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors, and / or II-VI compound semiconductors. III-V compound semiconductors are materials that contain at least one element from Group III of the periodic table of the elements and at least one element from Group V of the periodic table of the elements. II-VI compound semiconductors are materials that contain at least one element from Group II of the periodic table of the elements and at least one element from Group VI of the periodic table of the elements.

[0046] The present invention will be described in terms of a given example architecture; however, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may vary within the scope of the present invention. Note that for clarity, certain features may not be shown in every figure. This is not intended to be construed as a limitation of any particular embodiment, or of the scope of the illustrations, or claims.

[0047] FIG. 1 is a circuit diagram of a stacked field effect transistor (FET) according to an embodiment of the present invention.

[0048] Circuit 5 shows an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also shows a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked above the NFET portion. The PFET portion may have a stepped or tapered relationship to the NFET portion.

[0049] FIG. 2 is a top view of a semiconductor structure presenting a stacked and stepped FET structure according to an embodiment of the present invention.

[0050] The top view shows a top device layer 30T (Top Rx) having multiple sections 30, 32, 34, and a bottom device layer 40 (Bot Rx). The top device layer 30T may be referred to as a first device layer, and the bottom device layer 40 may be referred to as a second device layer. The multiple sections 30, 32, 34 of the top device layer 30T may advantageously be shifted and / or tapered and / or offset from one another.

[0051] A p-type transistor is shown stacked on an n-type transistor. For example, a first PFET 10 (P1) is stacked on a first NFET 20 (N1), a second PFET 12 (P2) is stacked on a second NFET 22 (N2), a third NFET 24 (N3) is stacked on a third PFET 14 (P3), and a fourth NFET 26 (N4) is stacked on a fourth PFET 16 (P4). The device gates "top PC" and "bottom PC" are also shown. The shifted or tapered device layers advantageously have a shifted or tapered shape between the device gates or "PCs." Electrical connections are advantageously made from the bottom gate to the top gate in the shifted or tapered device layers.

[0052] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is labeled "S" and circuit input pin 52 is labeled "SB." "S" stands for "Select" and "SB" stands for "Select Bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0053] As used herein, PC means shorter (<40 nanometers) gate photolithography layers, CB means longer (>40 nanometers) gate photolithography layers, CT means PC cut photolithography layers, and CA and CC mean source / drain open photolithography layers.

[0054] Thus, a first FET is presented including a first device layer, and a second FET is presented including a second device layer, where the first device layer has a stepped portion (or shifted or tapered configuration) relative to the second device layer. An electrical connection is made between the gate of the first FET and the gate of the second FET at the stepped portion of the first device layer. The first FET is stacked above the second FET. The second device layer is larger than the first device layer. The first FET is a p-type FET and the second FET is an n-type FET. In one embodiment, the gate of the first FET is located above the first device layer having the stepped portion. In another embodiment, the gate of the first FET is located above both the first and second device layers.

[0055] FIG. 3 is a cross-sectional view of the semiconductor structure of FIG. 2 showing a first FET and a second FET of a stacked and stepped FET structure according to an embodiment of the present invention.

[0056] 3 is a cross-sectional view along axis "X" showing the third PFET 14 (P3) and fourth PFET 16 (P4), as well as the first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A top device layer 30T extends across the third PFET 14 (P3) and fourth PFET 16 (P4). In particular, a section 34 of the top device layer 30T extends across the third PFET 14 (P3) and fourth PFET 16 (P4). A bottom device layer 40 extends across the first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Via 60 extends from circuit input pin 50 (“S”) to second NFET 22 (N2), and via 62 extends from circuit input pin 50 (“S”) to third PFET 14 (P3).

[0057] FIG. 4 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0058] Circuit 5 shows an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also shows a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked above the NFET portion. The PFET portion may have a stepped or tapered relationship to the NFET portion.

[0059] FIG. 5 is a top view of a semiconductor structure in which the top FET of a stacked and stepped FET structure includes a floating gate, according to an embodiment of the present invention.

[0060] The top view shows a top device layer 30T having multiple sections 30, 32, and 35, and a bottom device layer 42. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 42 may be referred to as a second device layer. The multiple sections 30, 32, and 35 of the top device layer 30T may advantageously be shifted and / or tapered and / or offset from one another. The section 35 of the top device layer 30T is larger, more extensive, or occupies a larger space than the sections 30 and 32. The bottom device layer 42 is also enlarged to accommodate the first NFET 20 (N1), the second NFET 22 (N2), the third NFET 24 (N3), and the fourth NFET 26 (N4), as well as the floating gate 70. Thus, the bottom device layer 42 of FIG. 5 is larger, more extensive, or occupies a larger space than the bottom device layer 40 of FIG. 2. The floating gate 70 is advantageously vertically aligned with the stepped portion of the top device layer 30T.

[0061] A p-type transistor is shown stacked on an n-type transistor. For example, a first PFET 10 (P1) is stacked on a first NFET 20 (N1), a second PFET 12 (P2) is stacked on a second NFET 22 (N2), a third NFET 24 (N3) is stacked on a third PFET 14 (P3), and a fourth NFET 26 (N4) is stacked on a fourth PFET 16 (P4). The device gates "top PC" and "bottom PC" are also shown. The shifted or tapered device layers are advantageously shifted or tapered between the device gates or "PCs." Electrical connections are advantageously made from the bottom gate to the top gate in the shifted or tapered device layers. A floating gate 70 is located between the PFET and NFET. In one example, floating gates 70 are shown between second NFET 22 (N2) and third NFET 24 (N3), and between second PFET 12 (P2) and third PFET 14 (P3).

[0062] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit output pin "Z" is located above floating gate 70.

[0063] Circuit input pin 50 is labeled "S" and circuit input pin 52 is labeled "SB." "S" stands for "Select" and "SB" stands for "Select Bar." Circuit input pin 50 extends across floating gate 70. Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0064] FIG. 6 is a cross-sectional view of the semiconductor structure of FIG. 5 showing the floating gate of the top FET according to an embodiment of the present invention.

[0065] 6 is a cross-sectional view along axis "X" showing the third PFET 14 (P3) and fourth PFET 16 (P4), as well as the first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A top device layer 30T extends across the third PFET 14 (P3) and fourth PFET 16 (P4). In particular, a section 35 of the top device layer 30T extends across the third PFET 14 (P3) and fourth PFET 16 (P4). A bottom device layer 42 extends across the first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). Via 60 extends from circuit input pin 50 (“S”) to second NFET 22 (N2), and via 62 extends from circuit input pin 50 (“S”) to third PFET 14 (P3).

[0066] Section 35 of top device layer 30T extends to a floating gate 70 located between second NFET 22 (N2) and third NFET 24 (N3). Section 35 is therefore stretched or enlarged to extend to floating gate 70.

[0067] FIG. 7 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0068] Circuit 5 shows an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also shows a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked above the NFET portion. The PFET portion may have a stepped or tapered relationship to the NFET portion.

[0069] FIG. 8 is a top view of a semiconductor structure in which the stacked and stepped FET structure includes a double step stacked FET, according to an embodiment of the present invention.

[0070] The top view shows a top device layer 30T having multiple sections 30, 32, 35, and a bottom device layer 42. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 42 may be referred to as a second device layer. The multiple sections 30, 32, 35 of the top device layer 30T may be aligned with one another (in contrast to the configurations of FIGS. 2 and 5). This may be referred to as a dual-step stacked FET configuration. The top device layer 30T is substantially or normally centered relative to the bottom device layer 42.

[0071] A p-type transistor is shown stacked on top of an n-type transistor. For example, a first PFET 10 (P1) is stacked on top of a first NFET 20 (N1), a second PFET 12 (P2) is stacked on top of a second NFET 22 (N2), a third NFET 24 (N3) is stacked on top of a third PFET 14 (P3), and a fourth NFET 26 (N4) is stacked on top of a fourth PFET 16 (P4). The device gates "top PC" and "bottom PC" are also shown.

[0072] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is labeled "S" and circuit input pin 52 is labeled "SB." "S" stands for "Select" and "SB" stands for "Select Bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0073] A cross-sectional view along the Y axis is also shown, which shows circuit input pin 50 connected to third PFET 14 (P3) by via 62 and circuit input pin 52 connected to third NFET 24 (N3) by via 64.

[0074] FIG. 9 is a cross-sectional view of the semiconductor structure of FIG. 8 showing the first and second FETs of a stacked and stepped FET structure according to an embodiment of the present invention.

[0075] 9 is a cross-sectional view along axis "X" showing third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A bottom device layer 42 extends across first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A via 60 extends from circuit input pin 50 ("S") to second NFET 22 (N2), and a via 62 extends from circuit input pin 50 ("S") to third PFET 14 (P3). The top device layer 30T is not visible, in contrast to FIGS. 3 and 6.

[0076] FIG. 10 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0077] Circuit 5 shows an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also shows a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked above the NFET portion. The PFET portion may have a stepped or tapered relationship to the NFET portion.

[0078] FIG. 11 is a top view of a semiconductor structure in which a stacked and stepped FET structure includes a double step stacked FET with a smaller bottom transistor, according to an embodiment of the present invention.

[0079] The top view shows a top device layer 30T having multiple sections 30, 32, 35, and a bottom device layer 44. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 44 may be referred to as a second device layer. The multiple sections 30, 32, 35 of the top device layer 30T may be aligned with one another (in contrast to the configurations of FIGS. 2 and 5). This may be referred to as a dual-step stacked FET configuration. Also, the bottom device layer 44 is thinner than the bottom device layer 42 of FIGS. 2 and 3. The top device layer 30T substantially entirely overlaps the bottom device layer 44.

[0080] A p-type transistor is shown stacked on top of an n-type transistor. For example, a first PFET 10 (P1) is stacked on top of a first NFET 20 (N1), a second PFET 12 (P2) is stacked on top of a second NFET 22 (N2), a third NFET 24 (N3) is stacked on top of a third PFET 14 (P3), and a fourth NFET 26 (N4) is stacked on top of a fourth PFET 16 (P4). The device gates "top PC" and "bottom PC" are also shown.

[0081] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is labeled "S" and circuit input pin 52 is labeled "SB." "S" stands for "Select" and "SB" stands for "Select Bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0082] A cross-sectional view along the Y-axis is also shown, showing circuit input pin 50 connected to third PFET 14 (P3) by via 62 and circuit input pin 52 connected to third NFET 24 (N3) by via 64. The difference from Figure 8 is that bottom device layer 44 is smaller, resulting in larger portions of first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4) being exposed. In addition, larger portions of third PFET 14 (P3) and fourth PFET 16 (P4) are exposed.

[0083] FIG. 12 is a cross-sectional view of the semiconductor structure of FIG. 11 showing the first and second FETs of a stacked and stepped FET structure with a smaller bottom FET according to an embodiment of the present invention.

[0084] 12 is a cross-sectional view along axis "X" showing third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A bottom device layer 44 extends across first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A via 60 extends from circuit input pin 50 ("S") to second NFET 22 (N2), and a via 62 extends from circuit input pin 50 ("S") to third PFET 14 (P3). The top device layer 30T is not visible, in contrast to FIGS. 3 and 6.

[0085] FIG. 13 is a circuit diagram of a stacked FET according to an embodiment of the present invention.

[0086] Circuit 5 shows an NFET circuit portion including a first NFET 20 (N1), a second NFET 22 (N2), a third NFET 24 (N3), and a fourth NFET 26 (N4). Circuit 5 also shows a PFET circuit portion including a first PFET 10 (P1), a second PFET 12 (P2), a third PFET 14 (P3), and a fourth PFET 16 (P4). The PFET portion is stacked above the NFET portion. The PFET portion may advantageously have a stepped or tapered relationship to the NFET portion.

[0087] FIG. 14 is a top view of a semiconductor structure in which a stacked and stepped FET structure includes a double step stacked FET with a larger bottom transistor, according to an embodiment of the present invention.

[0088] The top view shows a top device layer 30T having multiple sections 30, 32, 35 and a bottom device layer 46. The top device layer 30T may be referred to as a first device layer, and the bottom device layer 46 may be referred to as a second device layer. The multiple sections 30, 32, 35 of the top device layer 30T may be aligned with one another (in contrast to the configurations of FIGS. 2 and 5). This may be referred to as a dual-step stacked FET configuration. Additionally, the bottom device layer 46 extends along direction "A," which results in the top device layer 30T being non-centered with respect to the bottom device layer 46. Thus, the first device layer is positioned adjacent to the second device layer such that the surface of the first device layer is horizontally aligned with the surface of the second device layer.

[0089] A p-type transistor is shown stacked on top of an n-type transistor. For example, a first PFET 10 (P1) is stacked on top of a first NFET 20 (N1), a second PFET 12 (P2) is stacked on top of a second NFET 22 (N2), a third NFET 24 (N3) is stacked on top of a third PFET 14 (P3), and a fourth NFET 26 (N4) is stacked on top of a fourth PFET 16 (P4). The device gates "top PC" and "bottom PC" are also shown.

[0090] The letters "A" and "B" represent circuit input pins, while the letter "Z" represents a circuit output pin. Circuit input pin 50 is labeled "S" and circuit input pin 52 is labeled "SB." "S" stands for "Select" and "SB" stands for "Select Bar." Vias 60, 62 are shown connecting circuit input pin 50 to second NFET 22 (N2) and third PFET 14 (P3).

[0091] A cross-sectional view along the Y axis is also shown, showing circuit input pin 50 connected to third PFET 14 (P3) by via 62 and circuit input pin 52 connected to third NFET 24 (N3) by via 64. The difference from Figure 11 is that bottom device layer 46 is advantageously larger than bottom device layer 44 and is off-center from top device layer 30T.

[0092] FIG. 15 is a cross-sectional view of the semiconductor structure of FIG. 14 showing the first and second FETs of a stacked and stepped FET structure with a larger bottom FET according to an embodiment of the present invention.

[0093] 15 is a cross-sectional view along axis "X" showing third PFET 14 (P3) and fourth PFET 16 (P4), as well as first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A bottom device layer 46 extends across first NFET 20 (N1), second NFET 22 (N2), third NFET 24 (N3), and fourth NFET 26 (N4). A via 60 extends from circuit input pin 50 ("S") to second NFET 22 (N2), and a via 62 extends from circuit input pin 50 ("S") to third PFET 14 (P3). The top device layer 30T is not visible, in contrast to FIGS. 3 and 6.

[0094] In conclusion, exemplary embodiments of the present invention present methods and devices for constructing latch cross-couplings for stacked and stepped FETs. The stacked FET includes a first device layer and a second device layer, where one of the device layers is advantageously shifted or tapered or stepped relative to the other device layer. The shifted or tapered device layer is advantageously shifted or tapered between the gates or "PCs" of the device. Electrical connections are advantageously made from the bottom gate to the top gate in the shifted or tapered device layer. A floating gate is also used on the shifted or tapered device layer. In other embodiments, a double-step stacked FET is advantageously used. Also, one of the device layers is advantageously larger in size or larger than the other device layer.

[0095] Considering Figures 1-15, deposition is any process by which material is grown, coated, or otherwise transferred onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. As used herein, "depositing" may include any technique now known or later developed that is appropriate for the material to be deposited, including, but not limited to, for example, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), subatmospheric pressure CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), and ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), coating, evaporation.

[0096] As used herein, the term "process" includes depositing material or photoresist, patterning material or photoresist, exposing, developing, etching, cleaning, stripping, implanting, doping, stressing, layering, and / or removing as necessary in forming the described structures.

[0097] The present invention is described in terms of given example architectures; however, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may vary within the scope of the present invention.

[0098] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that it can be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0099] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical mechanism (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., over the Internet). The stored design is then converted into a format (e.g., GDSII) suitable for manufacturing photolithography masks, which typically contain multiple copies of the chip design to be formed on a wafer. The photolithography mask is utilized to define the areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0100] Methods such as those described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards or other input devices, and central processing units.

[0101] It should also be understood that material compounds are described in terms of the listed elements, e.g., SiGe. These compounds may contain different ratios of elements within the compound, e.g., SiGe may contain Si x Ge 1-x where x is less than or equal to 1, etc. Additionally, other elements may be included within the compound and still function in accordance with the present embodiments. Compounds with additional elements are referred to herein as alloys.

[0102] References herein to "one embodiment" or "an embodiment" of the present invention, as well as other variations thereof, mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," as well as any other variations thereof, appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0103] It should be understood that the use of any of the following terms " / ," "and / or," and "at least one of" is intended to encompass the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of both options (A and B), for example, "A / B," "A and / or B," and "at least one of A and B." As a further example, for "A, B, and / or C" and "at least one of A, B, and C," such language is intended to encompass the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of only the third listed option (C), or the selection of only the first and second listed options (A and B), or the selection of only the first and third listed options (A and C), or the selection of only the second and third listed options (B and C), or the selection of all three options (A, B, and C). This can be extended to many of the items listed, as would be readily apparent to one skilled in this and related arts.

[0104] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting to example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0105] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like are used herein for ease of description and may describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" such other elements or features. Thus, the term "below" can encompass both an orientation of above and below. A device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, when a layer is referred to as being "between" two layers, it will also be understood that it may be the only layer between the two layers, or that one or more intervening layers may also be present.

[0106] Terms such as "first," "second," etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element described below could be referred to as a second element without departing from the scope of the present concepts.

[0107] Having described preferred embodiments (intended to be illustrative, not limiting) of the methods and structures provided for constructing latch cross-couplings for stacked and stepped FETs, it should be noted that modifications and variations may be made by one skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments described and are within the scope of the invention as outlined by the appended claims. Having so described aspects of the invention with the detail and specificity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. a first field effect transistor (FET) including a first device layer; a second FET including a second device layer, wherein the first device layer has a stepped portion relative to the second device layer; and an electrical connection between the gate of the first FET and the gate of the second FET in the stepped portion of the first device layer; 1. A semiconductor structure comprising:

2. The semiconductor structure of claim 1 , wherein the first FET is stacked above the second FET.

3. The semiconductor structure of claim 1 , wherein the second device layer is larger than the first device layer.

4. 2. The semiconductor structure of claim 1, wherein the first FET is a p-type FET and the second FET is an n-type FET.

5. 2. The semiconductor structure of claim 1, wherein the gate of the first FET is located above the first device layer having the stepped portion.

6. 2. The semiconductor structure of claim 1, wherein the gate of the first FET is located above both the first and second device layers.

7. The semiconductor structure of claim 1 , wherein the second FET includes a floating gate.

8. 8. The semiconductor structure of claim 7, wherein said floating gate is vertically aligned with said stepped portion of said first device layer.

9. a first field effect transistor (FET) including a first device layer; a second FET including a second device layer; and an electrical connection between the gate of the first FET and the gate of the second FET in the stepped portion of the first device layer; 1. A semiconductor structure comprising:

10. 10. The semiconductor structure of claim 9, wherein the first FET is stacked above the second FET.

11. 10. The semiconductor structure of claim 9, wherein the second device layer is larger than the first device layer.

12. 12. The semiconductor structure of claim 11, wherein the first device layer is centered relative to the second device layer.

13. 12. The semiconductor structure of claim 11, wherein the first device layer is positioned adjacent to the second device layer such that a surface of the first device layer is horizontally aligned with a surface of the second device layer.

14. 10. The semiconductor structure of claim 9, wherein the first device layer generally overlaps the second device layer.

15. 10. The semiconductor structure of claim 9, wherein the gate of the first FET is located above the first device layer having a double step structure.

16. 10. The semiconductor structure of claim 9, wherein the gate of the first FET is located above both the first and second device layers.

17. a first field effect transistor (FET) including a first device layer; a second FET including a second device layer, wherein the second device layer is larger than the first device layer; and an electrical connection between the gate of the first FET and the gate of the second FET in the stepped portion of the first device layer; 1. A semiconductor structure comprising:

18. 20. The semiconductor structure of claim 17, wherein the first device layer is stepped relative to the second device layer.

19. 20. The semiconductor structure of claim 17, wherein the first FET is stacked above the second FET.

20. 20. The semiconductor structure of claim 17, wherein the gate of the first FET is located above the first device layer having a stepped portion.

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