Accurate programming of analog memory devices in an in-memory processing device having a crossbar array structure

Abstract

The present invention is directed, inter alia, to a method for programming memory elements of an in-memory computing (IMC) device. The IMC applies a SET signal to the K memory elements of each cell to set each of the K memory elements to a SET state and reads K conductance values ​​of the K memory elements in the SET state. The IMC adjusts the conductance value of at least one of the K memory elements based on the read K conductance values ​​and the target conductance value so that the summed conductance of the K memory elements of each cell matches the target conductance value. The IMC maximizes the number of the K memory elements in either their SET state or their zero-conductance nominal RESET state so that at most one of the K memory elements is not in either the SET state or the RESET state.

Description

[Technical Field]

[0001] [Background of the invention] The present invention relates generally to methods for programming analog memory elements of an in-memory computing device having a crossbar array structure, to a programmable system including such an in-memory computing device, and to related computer program products, and in particular to a programming method that maximizes the number of memory elements in either the SET or RESET state.

[0002] Artificial neural networks (ANNs), such as deep neural networks, have transformed the field of machine learning by providing unprecedented performance in solving cognitive tasks. ANN operations typically involve matrix-vector multiplications (MVMs). Such operations impose numerous challenges due to their repetition, as well as computational and memory requirements. Traditional computer architectures are based on the concept of von Neumann computing, in which processing power and data storage are partitioned into separate physical units. This architectural concept suffers from congestion and high power consumption, as data must be continuously transferred from memory units to control and computational units through physically constrained and costly interfaces. Summary of the Invention

[0003] According to a first aspect, the invention is embodied in a method for programming memory elements of an in-memory computing (IMC) device having a crossbar array architecture. That is, the IMC device includes N input lines and M output lines interconnected at nodes (i.e., junctions) defining N×M cells, where N≧2 and M≧2. The nodes include respective memory systems, which connect the input lines to the output lines. Each memory system includes a group of K memory elements arranged in parallel, where K≧2. That is, each cell of the N×M cells includes K memory elements.

[0004] The aim of the method is to program each cell given a target conductance value corresponding to a target weight value to be stored in each cell. Each cell is programmed by first setting K memory elements to a SET state. To this end, a SET signal is applied to the K memory elements of each cell. Subsequently, the K conductance values ​​of the K memory elements (now in the SET state) are read with a view to adjusting the electrical conductance of the cell. That is, the conductance value of at least one of the K memory elements is adjusted based on the K read conductance values ​​and the target conductance value. This is performed to match the summed conductance of the K memory elements of the cell to the target conductance value while maximizing the number of the K memory elements that are in either their SET state or their zero-conductance nominal RESET state, such that at most one of the K memory elements is not in either the SET state or the RESET state.

[0005] This allows for a reduction in inaccuracies due to intermediate conductance states across the array, which in turn leads to a significant reduction in programming errors and improved computational accuracy.

[0006] A preferred embodiment relies on determining a suitable subset of memory elements, i.e., the tuning procedure first includes determining a subset of K' memory elements based on the K read conductance values ​​and the target conductance value, where K'≦K. The latter is typically obtained by scaling the initial conductance values, i.e., by multiplying the initial weight values ​​by a scale factor determined according to the maximum cell conductance of the cells.

[0007] The subset is determined under the constraint that the summed conductance of the memory elements of this subset must match a target conductance value, subject to tolerances that can be removed by reprogramming at most one of the K' memory elements. The tuning itself is then achieved by (i) applying a RESET signal to any remaining memory elements (cells) that are not within the subset, setting such elements to their RESET state; and / or (ii) reprogramming at most one of the K' memory elements of the determined subset.

[0008] The subset may be determined, for example, as the subset with the smallest cardinality, i.e., the subset with the largest summed conductance value of the memory elements in their SET state. In addition, the memory element to be reprogrammed may advantageously be selected as the element with the smallest conductance among the memory elements of the determined subset, so as to minimize the number of memory elements in intermediate states.

[0009] Some scenarios may simply require reprogramming exactly one of the K' memory elements, while others may require only resetting the remaining memory elements, i.e., elements outside the determined subset. However, the most likely scenario is one that requires both applying a RESET signal to any remaining memory elements and reprogramming exactly one of the K' memory elements.

[0010] The proposed technique can be advantageously applied to multi-device cells in a differential configuration. That is, the memory system of each cell may include two groups of K memory elements, where K≧2 in each group (each cell then includes 2K memory elements). The two groups are in a differential configuration; they consist of a first group of K memory elements and a second group of K memory elements intended to store positive and negative weight values, respectively. The K memory elements are arranged in parallel in each of the two groups.

[0011] In this context, the method further comprises selecting a given group of the two groups according to the intended sign of the target weight to be stored in each cell. This is performed before and in consideration of the step of setting the memory elements to their SET state. The SET signal needs to be applied only to the K memory elements of the selected given group, resulting in each of the K memory elements of the given group being set to the SET state. However, 2K conductance values, consisting of the K conductance values ​​of the K memory elements in each of the two groups, are subsequently read. Finally, the adjustment procedure is performed by modifying one or more conductance values ​​in the given group. That is, the method adjusts the conductance value of at least one of the K memory elements of the given group based on the 2K read conductance values ​​and the target conductance value. The aim is to match the summed conductance of the cell's 2K memory elements to a target conductance value while maximizing the number of 2K memory elements that are in either their SET state or their zero-conductance nominal RESET state, such that at most one of the K memory elements in a given group is in neither the SET state nor the RESET state.

[0012] It should be noted that the conductance of at most one of the memory elements can be adjusted according to any suitable single-device programming method, such as an iterative programming method, a gradient-based algorithm, or a single-shot programming method, among others. Preferably, the K memory elements are first set to the SET state by programming the K memory elements according to a single-shot programming method. Similarly, the remaining memory elements, if any, are reset to the RESET state, preferably by programming such memory elements according to a single-shot programming method. For completeness, each cell is typically initialized by resetting all of its memory elements before applying a SET signal to the K memory elements or a group of K memory elements of the cell, selected according to their polarity.

[0013] According to another aspect, the present invention is embodied as a processing system. The system includes an IMC device having a crossbar array structure as described above. The memory elements are analog memory devices, such as phase-change memory devices, resistive random-access memory devices, and flash memory cell devices. Preferably, the memory elements are phase-change memory devices. The system further includes a programming unit connected to the IMC device. The programming unit is configured to program each cell according to the above method, i.e., by setting K memory elements of each cell to a SET state and then adjusting the conductance value of at least one of the K memory elements. Again, the aim is to match the summed conductance of the K memory elements of each cell to a target conductance value while maximizing the number of K memory elements in either the SET state or the RESET state, so that at most one of the K memory elements is in an intermediate state (i.e., not in either the SET state or the RESET state).

[0014] Preferably, the programming unit is connected to the IMC device via an input or output line of the IMC device and is adapted to adjust the conductance value of said at least one of the K memory elements by applying a voltage signal across the input or output line, respectively. In a variant, the programming unit may be connected to the IMC device via a further line, independent of the input or output line.

[0015] In an embodiment, the processing system further comprises a readout circuit connected at the output of the output line. A programming unit may, for example, be connected to the readout circuit and configured to adjust said conductance value according to a single-device programming method.

[0016] Again, each memory system may include two groups of K memory elements, possibly in a differential configuration, in which case the programming unit is further configured to select a given one of the two groups according to the intended sign of the target weight to be stored in the cell.

[0017] A final, but related, aspect of the invention relates to a computer program product for programming memory elements of an IMC device as described above, the program instructions being executable by processing means of a programming unit connectable to the IMC device so as to cause the programming unit to program each cell of the IMC device according to the method as described above. [Brief explanation of the drawings]

[0018] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in conjunction with the accompanying drawings, which are for clarity purposes only and together with the detailed description will facilitate an understanding of the invention by those skilled in the art.

[0019] [Figure 1] 1 schematically illustrates selected components of a hardware system including, among other things, an in-memory computing device having a crossbar array structure, as well as a programming unit for programming memory elements of the in-memory computing device, according to an embodiment.

[0020] [Figure 2] 1 is a plot that schematically represents the distribution of actual conductance values ​​of resistive memory devices in a crossbar array structure either in their SET state or in their RESET state.

[0021] [Figure 3] FIG. 3A illustrates a unit cell of a crossbar array structure according to an embodiment. FIG. 3B illustrates a unit cell of a crossbar array structure according to an embodiment. FIG. 3C illustrates a unit cell of a crossbar array structure according to an embodiment. FIG. 3D illustrates a unit cell of a crossbar array structure according to an embodiment. In each case, the cell includes two polarity groups in a differential configuration, where K resistive memory elements are arranged in parallel in each group; see FIG. 3A. FIGS. 3B-3D compare the distribution of conductance values ​​obtained across a typically 2×2 memory element cell by different methods, including a method according to the prior art (FIGS. 3B, 3C) and an embodiment (FIG. 3D). Specifically, FIGS. 3B and 3C illustrate conductance values ​​obtained according to an equal-fill approach and a max-fill approach (without according to an embodiment), while FIG. 3D illustrates conductance values ​​obtained according to one embodiment. The conductance values ​​obtained in FIG. 3D maximize the number of devices in either the SET or RESET state; only a single device is in an intermediate state.

[0022] [Figure 4]Figure 4A illustrates, in an embodiment, a step-by-step programming of a memory element of a unit cell such as that shown in Figure 3B. Figure 4B illustrates, in an embodiment, a step-by-step programming of a memory element of a unit cell such as that shown in Figure 3B. Figure 4C illustrates, in an embodiment, a step-by-step programming of a memory element of a unit cell such as that shown in Figure 3B. Figure 4D illustrates, in an embodiment, a step-by-step programming of a memory element of a unit cell such as that shown in Figure 3B. Figure 4E illustrates, in an embodiment, a step-by-step programming of a memory element of a unit cell such as that shown in Figure 3B.

[0023] [Figure 5] 1 is a flowchart illustrating high-level steps of a method for programming memory elements of an in-memory computing device having a crossbar array structure, according to an embodiment.

[0024] [Figure 6] Figure 6A illustrates a single-device programming scheme that can be used in embodiments. Figure 6B illustrates a single-device programming scheme that can be used in embodiments. Figure 6A assumes the use of a gradient-based programming method, while Figure 6B relies on an iterative programming scheme.

[0025] The accompanying drawings show simplified representations of devices or portions thereof, as may be involved in the embodiments, in which like or functionally similar elements are assigned the same reference numbers unless otherwise specified.

[0026] Methods, systems and computer program products embodying the present invention are now described by way of non-limiting examples. DETAILED DESCRIPTION OF THE INVENTION

[0027] One possibility for accelerating MVM is to use a dedicated hardware acceleration device, such as an in-memory computing device with a crossbar array structure. This type of circuit has input and output lines interconnected at intersections that define cells. The cells contain respective memory elements (or sets of memory elements) designed to store respective matrix coefficients. Such an architecture can map MVM simply and efficiently: vectors are encoded into signals that are applied to the input lines of the crossbar array, performing the MVM as a multiply-accumulate (MAC) operation. Weights can be updated by reprogramming the memory elements as needed to perform successive MVMs. Such in-memory computing devices break down the "memory wall" by combining computation and memory units into a single in-memory computing (IMC) unit.

[0028] Moreover, the use of analog memory devices in IMC units allows efficient execution of MVM operations by exploiting the analog storage capabilities of the IMC devices and Kirchhoff's laws of circuits. Another advantage of crossbar array structures is that they support matrix transpose operations, which can be utilized to train ANNs. More generally, the important computational primitives realized by such devices can also be used for other applications, such as solvers for systems of linear equations.

[0029] However, a key challenge is to achieve satisfactory computational accuracy, which is essentially determined by the accuracy with which target synaptic conductance values ​​can be mapped to synaptic elements, ie, analog memory elements.

[0030] For example, consider synaptic weights to be stored in a unit cell with two memristor devices in a differential configuration. That is, the memristor devices are intended to store positive and negative values, respectively. In such a configuration, the target weight value is typically set to a value that is greater than or equal to the value of the “positive” device (with conductance value G p ) or "negative" devices (set to have a conductance value G n The target weight is typically mapped to the conductance of only one memristor device, either the target weight or the value of the other device (which is set to have a nominal conductance value of zero). The other device is reset to the RESET state, which has a zero nominal conductance value. The target weight is typically mapped to a factor (called G max ) so that the full dynamic range of device conductance is utilized across the memory element of the cell.

[0031] The same approach can be extended to a unit cell containing two groups of K devices each, where the two groups are in a differential configuration and the K devices are connected in parallel in each group. Here, the weight values ​​are mapped to the conductances of the K devices in the group selected according to their polarity. The mapping can be done in several ways. One approach (called the "equal fill approach") is to use an arbitrarily chosen factor (G max ) and map all K devices to that value. Another approach (often called the "max-fill approach") is to scale the weights by K × G max , and set as many memory devices as possible to the value G while setting a single device to the conductance value corresponding to the residual difference. max The remaining devices, if any, are reset to zero conductance.

[0032] The most common approach to programming weights in a single device is the so-called "iterative programming" (ITP) scheme, whereby memory devices are individually read to determine the target conductance value (G target ) and measured value (G measured Correction pulses are applied to such devices to minimize the difference between the . The applied correction pulses are iteratively defined by a programming controller. The main drawback of this approach is that single-device readouts can be inaccurate and expensive to implement due to the high-precision analog-to-digital converters (ADCs) and the very long integration times required.

[0033] Another common single-device programming approach is the so-called "single shot programming" (SSP) approach, where the programming pulses are parametrically captured in a lookup table (LUT) that collects all information related to the programming curve. The main drawback of this approach is that the ideal programming curve (except for setting memory devices to their SET and RESET states) has inter- and intra-device variability. As a result, intermediate states cannot be accurately achieved in large arrays of memory devices.

[0034] With respect to multi-device unit cells, programming can be done by extending or combining the single-device programming schemes described above. For example, one may extend the ITP technique to all memory devices contained in the unit cell, looping over each device individually. Another possibility is to combine the SSP and ITP techniques, whereby the SSP technique can be used to initialize the memory devices by applying RESET and SET pulses. Subsequently, a sequential read-verify scheme can be used to program the memory devices, initially set to the RESET state, to either the SET state, the RESET state, or an intermediate state by applying SSP pulses. The aim is to increase the summed conductance value (G cell ) to G target Finally, the ITP scheme can be used to program memory devices that were initially set to the SET state to correct SSP programming errors, resulting in a residual conductance error (G error ) can be minimized.

[0035] The inventors discovered that known programming schemes inherently result in some inaccuracy in the programmed weight values, and therefore they devised a novel technique to more accurately program the analog memory elements of a crossbar array.

[0036] As the inventors have observed, in an in-memory computing (IMC) device with a crossbar array structure, there is a very wide distribution of actual conductance values ​​corresponding to the SET states of analog memory elements. The RESET states of analog memory elements are effectively non-conductive, so that noise and drift have little effect on computational accuracy. Furthermore, the SET states of analog memory elements may happen to be less "noisy" than intermediate states, even though they have larger conductance values. The noisiness of intermediate states means that their actual conductance values, once programmed, deviate measurably from their intended values, resulting in some noise across the array. Drift or programming inaccuracies may result in a deviation between the actual and intended conductance values.

[0037] Here, the scale factor G used to generate the conductance values ​​in the previous programming scheme is max is assumed to be the same for all memory devices in the array; this means that most of the SET conductance values ​​are actually G max It is further specified to be greater than the value 0. In practice, this means that it will not be possible to program most of the memory devices to their SET state.

[0038] As the inventors have recognized, devices max Not the value but their G set Programming the K memory elements to a value results in a significant reduction in programming errors and an increase in computational accuracy. They therefore devised a novel technique for programming the analog memory elements of a crossbar array device that maximizes the number of K memory elements in either the SET or RESET state, subject to at most one memory element being programmed to an intermediate state, as required for the cell to match a target conductance value corresponding to the target weight value.

[0039] The following description is structured as follows: Section 1 describes general embodiments and high-level variations; Section 2 describes particularly preferred embodiments; and Section 3 addresses technical implementation details. Note that the method and its variations are collectively referred to as "the method." All Sn references refer to method steps in the flowchart of FIG. 5, and numbered references relate to devices, components, and concepts involved in embodiments of the invention. 1. General embodiments and high-level variations

[0040] A first aspect of the present invention will now be described in detail, primarily with reference to Figures 1 and 5. This aspect relates to a method for programming analog memory elements 157 of an IMC device 15 having a crossbar array structure such as that shown in Figure 1.

[0041] That is, the IMC device 15 comprises N input lines 151 and M output lines 152, which are interconnected at intersections (i.e., junctions). The intersections thus define N×M cells 154, also called unit cells. The input and output lines are interconnected via a memory system 156. In principle, at least two input lines and two output lines are required to define an array (i.e., N≧2 and M≧2). However, in practice, the number of input lines 151 and output lines 152 is typically on the order of hundreds to thousands of lines. For example, 256×256, 512×512, or 1024×1024 arrays can be envisioned, although N does not necessarily have to equal M. The IMC device 15 may be intended for use as a neural processing device designed to implement, for example, M neurons at a time. Thus, the number of neurons may be equal to, for example, 256, 512, or 1024.

[0042] Examples of unit cells are shown in FIGS. 3A-4E. As shown schematically in FIG. 1, each intersection includes a respective memory system 156. As can be seen in FIGS. 3A-4E, each memory system 156 includes a group of K memory elements 157, which are arranged in parallel within the group. In practice, each cell may include two groups of K memory elements 157 each, for reasons that will become apparent later. Various connection schemes can be envisioned. Preferably, each input (respectively output) line is typically split into K or 2K conductors to appropriately connect to (respectively from) each memory element of each cell. Thus, each input (or output) line typically includes multiple parallel electrical conductors. Here, we assume that each cell includes a group of K memory elements, such that each cell 154 includes K memory elements.

[0043] The method aims to program each multi-device cell in turn (which corresponds to steps S20 to S80 in FIG. 5), as reflected in the loop from step S90 to step S10 in FIG. 5. Programming a cell means storing a target weight value in this cell. The target weight value can be converted into an electrical conductance value. Thus, the aim is to program the memory elements of this cell so that they produce a summed conductance value that matches the target conductance value corresponding to the target weight value to be stored in the cell. Because the weight values ​​are intended to be mapped to the conductance values ​​of the memory elements, the method applies only to analog memory devices and not to digital memory elements.

[0044] The target conductance value may be obtained, for example, by scaling the initial conductance value S60, i.e., by multiplying this initial weight value by a scale factor, where the weight value is typically normalized, i.e., distributed between 0 and 1 (or between −1 and 1, as will be explained later). Therefore, this factor (which we will call S maxThe scale factor S can be set according to the maximum cell conductance of the cell. The same procedure is applied to each cell. max converts the initial (typically normalized) weight values ​​into suitable conductance units. This scale factor typically depends on the saturation current of the ADC used at the output of the output line (not shown), which may further vary across different crossbar arrays and / or across output lines of the same crossbar array.

[0045] The K memory elements may first need to be initialized (step S20), for example, by resetting all K memory elements to a RESET state with a zero nominal conductance value. Next, a SET signal is applied to the K memory elements of the cell to set each memory element to the SET state. The true corresponding conductance values ​​are then read S50, thereby obtaining K conductance values ​​for each of the K memory elements. The actual conductance values ​​may differ slightly from their nominal values. Note that the same SET signal could conceivably be applied to all of the K elements. However, even when the same SET signal is applied, the K memory elements will adopt different conductance values.

[0046] The actual conductance values ​​of the memory elements in their SET states are then used to optimally program each cell's memory elements. That is, such conductance values, along with the target conductance value, are used to adjust the conductance value of one or more of the cell's K memory elements (S70-S80). At least one of the K memory elements typically needs to be adjusted unless, as will be explained later, its SET conductance value happens to coincide with the target value or the cell conductance is unable to adapt to the weight value. The memory elements are adjusted by resetting or otherwise changing the conductance of such memory elements. This adjustment (S80) effectively reprograms one or more of the memory elements. This is performed to match the combined conductance of the cell's K memory elements to the target conductance value while maximizing the number of the K memory elements in either their SET state or their nominal zero-conductance RESET state.

[0047] This maximization ultimately contingents on at most one of the K memory elements being in an intermediate state, i.e., not in either the SET or RESET state. Thus, although multiple memory elements may end up being reset in step S80, at most one element is adjusted S80 to be not in either the SET or RESET state. In other words, the summed conductance of the K memory elements ultimately decomposes as the sum of actual conductance values ​​corresponding to either the SET and / or RESET state, subject to at most one intermediate conductance value.

[0048] The underlying concept is to maximize the number of memory elements in either the SET or RESET state, because those states are the least noisy. Again, in this context, "noisy" means that actual conductance values ​​may deviate slightly from their intended (theoretical) values, whether due to drift or programming inaccuracies. Here, the multiplexing of such states across the crossbar creates noise around the ideal value. That being said, the SET state of a memory element is typically the least noisy state in terms of least weight noise and drift, while the RESET state is effectively non-conductive, so that noise and drift have little effect in that case.

[0049] Here, in the previous programming scheme, the scaling value G max is assumed to be the same for all memory elements in the array, and most of the SET conductance values ​​are G max As previously mentioned, this makes it impossible to accurately program most of the memory elements to their corresponding SET states. Therefore, as recognized by the inventors, it is desirable to program memory elements with a SET conductance value G set (G max Programming the memory elements in the array (rather than the SET state) can result in a significant reduction in programming errors and improved calculation accuracy. Therefore, rather than using the same single scaling value and assuming this value applies to all memory elements in the array, the method relies on the actual SET state conductance values ​​of the memory elements in the array to accurately match the target weight value. With this approach, at most one memory element per unit cell is in an intermediate (noisy) state, and the rest are in either a less noisy SET state or a less noisy RESET state. As a result, the proposed approach allows for a reduction in overall noise, benefiting calculation accuracy.

[0050] Compared to existing multi-device programming schemes, the present solution has the following advantages: First, as mentioned above, the present approach reduces weight and drift noise by maximizing the number of memory elements in the least noisy state, either SET or RESET. This maximization is contingent on there being at most one memory element per cell in an intermediate state. Second, the proposed approach allows achieving a more optimal weight mapping. For example, the method can allocate the smallest number of memory elements needed based on their true G set By utilizing a value, it can be selected a priori to match a given weight value, and this results in less energy and time overhead during programming, since only one programming is required after the conductance read.

[0051] Note that this approach also applies to memory elements in a non-differential configuration. That is, a multi-device unit cell may have a differential configuration, as in the embodiments described in detail below. The logic remains the same, except that the memory elements to be reprogrammed / reset belong to a polarity group selected according to a weight value. In general, however, each cell may contain one or two groups of K memory elements each. If the weight values ​​are normalized and distributed, for example, between 0 and 1, one group is sufficient. Relying on two groups of memory elements is useful if the weight values ​​are distributed, for example, between −1 and 1. In this context, the minimum number of elements in a group, K, is equal to 2, regardless of whether the group is in a differential or non-differential configuration.

[0052] All of this will now be described in detail with reference to embodiments of the present invention. First, various approaches can be envisioned to maximize the number of memory elements in the SET or RESET state. However, one conventional approach is to first determine a suitable subset of K memory elements of a cell (or in a group of K elements). In particular, the method may advantageously attempt to determine S70 a subset of K′ memory elements based on the target conductance value and the K conductance values ​​read in step S50, where K′≦K. This subset is determined such that the summed conductance of the K′ elements matches the target conductance value with a certain tolerance. However, this tolerance should be such that it can be removed by suitably reprogramming at most one of the K′ memory elements after performing the initial programming in step S40 to set the memory elements to the SET state.

[0053] Next, the adjustment step S80 may include resetting any remaining memory elements that are not within the determined subset. Such elements, if any, are reset by applying a RESET signal to set them to a RESET state of zero nominal conductance. Resetting any remaining memory elements outside the subset is one way of adjusting the conductance value of that element. Alternatively, or in addition, one of the K' memory elements may need to be reprogrammed, which will also adjust the conductance value of the memory element. The adjustment procedure S80, whether it involves resetting and / or reprogramming the memory element, is performed so that the sum of the actual conductance values ​​of all memory elements of the cell matches the target conductance value. Various scenarios can be envisioned. Examples of such scenarios are summarized in Tables I and II below.

[0054] Table I corresponds to the adjustment scenarios for cells of two memory elements (D1 and D2) arranged in parallel. The upper values ​​correspond to the conductance values ​​of the devices in the SET state (i.e., after step S40). The conductance values ​​of the elements belonging to the identified subset are underlined. The lower values ​​in brackets correspond to the adjusted conductance values ​​(as obtained after step S80). [Table 1] Table I: Example Coordination Scenarios for Two Memory Device Cells in Parallel

[0055] Table II corresponds to the tuning scenario for three memory element cells arranged in parallel. Again, the upper values ​​for devices D1, D2, and D3 correspond to the conductance values ​​of the devices in the SET state (after step S40), the conductance values ​​of the elements in the identified subset are underlined, and the lower values ​​(in brackets) correspond to the tuned conductance values ​​(after step S80). [Table 2] Table II: Example Tuning Scenarios for Three Memory Device Cells in Parallel

[0056] Note that the conductance values ​​shown in the above table and in FIGS. 3B-3D are chosen for illustrative purposes only; they are not meant to be realistic.

[0057] In the above table, it is assumed that the cell contains a single group of memory elements. However, the above scenario can be simply applied to a cell containing two groups of memory elements in a differential configuration; the tuning solution is then applied to the selected polarity group, as will be explained in more detail below.

[0058] In each of the above examples, a suitable subset of K' memory elements is identified, which is sufficient for the cell to store the desired weight value. In practice, this means that the summed conductance of the memory elements in this subset must be greater than or at least equal to the conductance value corresponding to the target weight to be stored in the cell. The remaining memory elements (outside the identified subset), if any, are then reset to a RESET state with a zero nominal conductance value, and at most one memory element is reprogrammed, e.g., using a conventional single-device programming scheme, with a view to bringing the summed conductance value of all memory elements in the cell as close as possible to the target conductance value.

[0059] The subset is preferably determined S70 as the minimum subset, i.e., the smallest possible subset in terms of cardinality, as in all of the scenarios presented in Tables I and II, except for scenario 3, where the selected subset does not have the smallest possible cardinality. In fact, the determined subset is equal to the initial group of two memory elements, and therefore is not even a proper (i.e., strict) subset of the initial group in this example. In that case, the memory elements are not reset to the RESET state. Rather, the programming strategy used in scenario 3 aims to maximize the number of memory elements that can be maintained in the SET state.

[0060] In all other scenarios, the selected subset is the subset with the smallest possible cardinality, i.e., the least-populated subset, consisting of the minimum number of memory elements required to store the target weight. Here, multiple possible subsets can potentially be specified for the same target conductance value, as in scenarios 6 through 8. However, the programming method can further distinguish between possible subsets by selecting memory elements with the largest summed conductance value in the SET state, as in scenario 7. In this case, the subset is determined to satisfy two conditions: (i) among all possible subsets of K memory elements that can a priori store the target weight, the optimal subset is determined as the subset with the smallest cardinality; and (ii) as in scenario 7, contrary to scenario 8, among all possible subsets with the same minimum cardinality, the summed conductance value of the memory elements in the subset must be the largest.

[0061] In practice, this can be achieved by first identifying the memory devices with the largest conductance values ​​in their SET state, and then, starting with the element with the highest conductance value, selecting the minimum number of memory elements required to match the target electrical conductance value.

[0062] The remaining memory elements K through K' of the cell (i.e., not within the determined subset) belong to the absolute complement of the identified smallest subset. In other words, the set formed by the elements of the cell is decomposed into two complementary subsets: the identified smallest subset and the complement formed by the remaining memory elements. The remaining elements K through K' are reset S80 by applying a RESET signal, as in scenarios 1, 2, and 4 through 8, thereby placing such elements in a RESET state with a zero nominal conductance value. Doing so increases the number of elements that end up in the RESET state, which reduces noise across the memory elements of the array.

[0063] In addition to the external reset, it is often necessary to reprogram exactly one of the K' memory elements of the determined subset in order for the cell to meet the target conductance. That is, the adjustment procedure S80 will most likely require reprogramming exactly one memory element so that this element is ultimately in neither the SET nor the RESET state, as in scenarios 2, 3, 7, and 8. Doing so limits the number of devices in intermediate states to at most one device per cell, which limits noise.

[0064] In some cases, as in scenarios 1, 4, 5, and 6, if the summed conductance value happens to match the target value, it is sufficient to reset the memory elements outside the determined subset without needing to reprogram any memory elements. However, such a situation is highly unlikely in practice. Rather, it is most likely necessary to both reset the remaining memory elements and reprogram exactly one of the K' memory elements.

[0065] As indicated above, steps S70-S80 may be performed to generally favor memory elements in either the SET state or the RESET state. Some strategies may favor the RESET state over the SET state to a certain extent, or conversely, favor the SET state over the RESET state. Which strategy is best depends on the memory element characteristics and, in fact, on the system 1 as a whole, taking into account peripheral circuitry. A strategy favoring the RESET state is desirable when memory elements in lower SET states also have less noise. If memory elements with larger SET states happen to have less noise, it may be better to strive to keep as many elements as possible in the SET state, reset the others, and reprogram at most one memory element to meet the target conductance value.

[0066] The memory element to be reprogrammed can be selected by default. It may be selected randomly from a subset of K' elements. However, as in scenarios 7 and 8, it is much preferable to select this element as the element from the subset with the lowest possible electrical conductance. As explained above, this results in a minimization of noise in the mid-range.

[0067] Any suitable single-device programming method can be used to set, reset, or reprogram a memory element. Examples of such methods include iterative programming (ITP) methods, gradient-based programming (GDP) algorithms, and single-shot programming (SSP) methods. ITP and SSP methods are described in the Background section. Examples of the use of ITP methods and gradient-based algorithms are described in Section 2 with reference to Figures 6A and 6B.

[0068] A single-device programming method can also be used to set and reset the memory elements. Preferably, K memory elements 157 are first set to their SET state by programming them according to the SSP method S40. The same method can also be used to reset the remaining memory elements S80. As mentioned in the Background section, a mixture of ITP and SSP methods can also be used. In all cases, the summed conductance value of the memory elements of the cell should ultimately match the target conductance value as closely as possible.

[0069] As noted, the present technique extends to multi-device cells including two groups of memory elements in a differential configuration. As shown in FIGS. 3A-4E, each cell 154 includes a respective memory system 156, which itself is decomposed into two groups 156p, 156n of K memory elements 157 (again, K≧2 in each group). Thus, each cell 154 now includes 2K memory elements arranged in parallel in two groups: a first group 156p of K memory elements and a second group 156n of K memory elements intended to store positive and negative weight values, respectively. Because the two groups 156p, 156n are arranged in a differential configuration, any weight value (whether positive or negative) can be read by reading the summed conductance value of the parallel memory elements 157.

[0070] The core principles previously described with reference to a single group of memory elements remain unchanged. However, now a given group must be selected S30 (see FIG. 5) according to the intended sign of the target weight to be stored in each cell. That is, positive and negative weight values ​​are stored in groups of corresponding polarity. Next, a SET signal needs to be applied S40 to only the K memory elements of the selected group, resulting in each of the K memory elements of the selected group being set to the SET state. Note that, although all conductance values ​​are read in step S50, all memory elements 157 are typically preferably initialized (e.g., reset) in step S20 before setting the selected memory elements to the SET state S40. Then, 2K conductance values ​​are read in step S50, i.e., the K conductance values ​​of the K memory elements in each of the two groups. The reason for doing so is that all conductance values ​​should preferably be taken into account for the final adjustment S80 of the summed conductance. That being said, it may be sufficient to read the conductance value of K only for elements set to the SET state, since other elements can be assumed to have zero conductance.

[0071] As before, the following steps S70-S80 are performed to adjust the conductance value of at least one of the selected group of K memory elements based on the 2K read conductance values ​​and the target conductance value. Note again that the aim is for the summed conductance of the 2K memory elements to match the target conductance value, with the actual conductance values ​​of the other (i.e., unselected) group of K memory elements being equal to or very close to zero. Consistent with the principles previously described, steps S70-S80 are performed to maximize the number of the 2K memory elements in either the SET state or the zero-conductance nominal RESET state, although one of the K memory elements in the selected polarity group may need to be set to an intermediate state (i.e., neither in the SET state nor the RESET state).

[0072] In other words, only the selected group of memory elements are set S40 and possibly reprogrammed S80. The RESET signal applied in step S80 may relate only to the selected group of memory elements. In a variant, the RESET signal may also be applied to other groups of memory elements, depending on the initialization protocol used.

[0073] Again, the method may advantageously attempt to determine a subset of the elements of K′, even if only within a selected polarity group. This subset may be If the target weight value is positive, |Σ i {S} G i p -Σ i=1 K G i n |≧|G target |or If the target weight value is negative, |Σ i=1 K G i p -Σ i {S} G i n |≧|Gtarget It may be decided to verify that |

[0074] In the above equation, {S} denotes the determined subset, and G i p denotes the conductance value of the i-th memory element of the first group 156p, and G i n represents the conductance value of the i-th memory element of the second group 156n, and G target is the target conductance value. However, the value G i n / p refers to the read conductance value of a memory element which can be in either the SET or RESET state depending on the sign of the target weight and the group of memory elements intended to store the weight value.

[0075] Further features of the method are described in Section 2.

[0076] Referring back to FIG. 1 , another aspect of the present invention will now be described in detail with respect to processing system 1. The system comprises, among other things, an IMC device 15 having a crossbar array structure, as previously described with reference to the present method. Memory elements 157 are analog memory devices that may be, among other things, phase-change memory (PCM) devices, resistive random-access memory (RRAM) devices, or flash memory cell devices. Using such devices, weight values ​​are mapped across the conductance range of the memory elements, as opposed to multiple binary devices representing different weight bits in digital storage. A preferred embodiment relies on PCM devices.

[0077] In addition to IMC device 15, system 1 includes a programming unit 19 connected to IMC device 15. Programming unit 19 may be connected to, among other things, input lines 151 of IMC device 15. However, programming unit 19 is typically independent of input unit 11, which is used to apply signals to input lines 151 to activate IMC device 15. Programming unit 19 is generally configured to program each cell 154 of device 15 according to the principles described above with reference to the present method. In particular, programming unit 19 is designed to enable setting, resetting, and adjusting the conductance value of the memory element of each cell 154 as needed to match the summed conductance of the memory elements of each cell to a target conductance value. Consistent with the present method, programming unit 19 does so by maximizing the number of memory elements in either the SET state or the RESET state (with a nominal zero conductance), subject to the constraint that at most one memory element is in neither the SET state nor the RESET state.

[0078] For example, the unit 19 may be adapted to adjust the conductance value of the memory element 157 by applying a suitable voltage signal across the input or output line, respectively 151, of the IMC device 15. In a variant, the programming unit 19 may be connected to the memory element via a separate connector. It should be noted that the processing system 1 typically comprises a readout circuit 16 connected at the output of the output line 152. The programming unit 19 may therefore be connected at its output to the readout circuit 16 so as to be able to adjust the conductance value of the memory element 157 according to the single-device programming method, as recalled above. The system 1 may also further comprise a processing unit 18 connected at the output of the IMC device 15, i.e., at the output of the readout circuit 16. This processing unit 18 may preferably be arranged as a near-memory processing unit. In that case, the programming unit 19 may advantageously be connected at the output of the near-memory processing unit 18 so as to enable closed-loop programming of the crossbar array structure 15. In a variant, the processing unit 18 and the programming unit 19 are implemented as one and the same unit, which may further include an input / output (I / O) controller, as suggested in Figure 1, and be configured to communicate with external devices or computers.

[0079] The memory system 156 of each cell 154 of the IMC device 15 preferably includes two groups 156p, 156n of K memory elements 157, the two groups 156p, 156n being in a differential configuration for reasons previously explained. In that case, the programming unit 19 must further be able to select a given group according to the sign of the target weight to be stored in each cell 154.

[0080] Once the weights have been programmed across the crossbar array 15, vector components can be injected into the crossbar array structure 15. More precisely, signals encoding an N component (i.e., N vector) vector can be applied via input unit 11 to N input lines 151 of the crossbar array structure 15, causing the crossbar array structure 15 to perform a multiply-accumulate (MAC) operation based on, for example, the N vectors and the N×M weights stored in device 15. The result of the MAC operation is that the values ​​encoded by the signals applied to the N input lines are each multiplied by a weight value.

[0081] Such MAC operations may be instances performed as part of running or training an ANN. A single crossbar array structure can typically implement one neural layer at a time. However, if the neural weights can be efficiently and accurately reprogrammed with each algorithm cycle, the crossbar array structure 15 can be operated cyclically in a closed loop so that the structure 15 implements multiple successively connected neural layers of an ANN. In a variant, multiple crossbar array structures 15 are cascaded to accomplish the same thing. The neural layer implemented by the crossbar array structure 15 can be any layer or portion of a layer of an ANN.

[0082] Whether or not intended for ANN applications, the optimal mapping of operations can be determined by processing unit 18 or an external processing unit (not shown), i.e., a unit distinct from core compute array 15. However, the processing unit is preferably merged with core IMC array 15 within system 1, as assumed in FIG. 1. In all cases, the processing unit can be used to determine the computation strategy (i.e., input vectors and block matrices and associate them). Corresponding matrix weight values ​​can then be passed to programming unit 19, which then appropriately programs the cells of array 15. In practice, programming unit 19 may include a programming controller. Like the input unit, the programming unit may include or be connected to a signal generator to apply pulses in accordance with the programming controller.

[0083] The system 1 shown in FIG. 1 comprises multiple devices (i.e., an IMC device 15, a readout circuit 16, a near memory processing unit 18, and a programming unit 19, which are connected to each other to form the system 1). The system 1 itself can be fabricated as a single apparatus or even a single device. In particular, the IMC device 15, the processing unit 18, and the programming unit 19 may all be fused together in the same chip, as assumed in FIG. 1. Thus, the system 1 may consist of a single device (e.g., a single chip) that fuses all necessary components. Thus, the system 1 may be conveniently used in a special-purpose infrastructure or network, for example, to service multiple simultaneous client requests. The entire system may be configured, for example, as a composable disaggregated infrastructure, which may further include other hardware acceleration devices, for example, application-specific integrated circuits (ASICs) and / or field-programmable gate arrays (FPGAs).

[0084] According to another aspect, the present invention may then be embodied as a computer program product for programming memory elements 157 of an IMC device 15, as previously described. The computer program product comprises a computer-readable storage medium having program instructions embodied thereon, the program instructions being executable by processing means of a programming unit 19, which may be coupled to the IMC device 15, to cause the programming unit 19 to program each cell 154 according to the principles described with reference to the present method. Section 3 provides further details.

[0085] The above embodiments have been briefly described with reference to the accompanying drawings and may be adapted to many variations. Several combinations of the above-described features may be considered. Examples are given in the following sections. 2. Particularly Preferred Embodiments 2.1 Preferred flow (Figure 5)

[0086] FIG. 5 shows a preferred (high-level) flow of steps for a method of programming memory elements 157 of an IMC device 15. The process begins at step S5. It iterates through the cells 154 of the IMC device 15. At step S10, the next cell is selected. At step S20, the memory elements are initialized, for example, by applying a RESET signal to all memory elements of the currently selected cell; however, the cells may be initialized once and then a new cell may be selected at step S10. At step S30, a given polarity group is selected according to the sign of a target weight value to be stored in that cell. The target weight value is used as an input to step S30. At step S40, a SET signal is applied to all memory elements of the selected polarity group, after which the conductance values ​​of the memory elements of the cells are read at step S50. Next, at step S70, a sufficient subset (e.g., a minimum subset) is determined based on the read conductance values ​​and the target conductance value corresponding to the target weight value. Note that the target conductance value is typically obtained by suitably scaling the target weight values, as described in Section 1 (S60). Once the suitable subset is determined (S70), one memory element is selected for intermediate programming, if necessary. This element is preferably selected as the subset element with the lowest conductance. The conductance of one or more memory elements is then adjusted (S80) as needed to match the summed conductance of the cell's memory elements to the target conductance value. Memory elements outside the determined subset are then reset. Additionally, at most one memory element of the subset is set to an intermediate state (neither in the SET state nor in the RESET state) to maximize the number of memory elements in either the SET state or the RESET state. If the current cell is the last cell (S90: Yes), the programming process stops at step S100. Otherwise (S90: No), the process proceeds to the next cell (S10). The process is repeated until all cells are suitably programmed. 2.2 Preferred Cell Architecture and Illustrative Examples (FIGS. 3A-3D)

[0087] FIG. 3A shows a preferred cell architecture, in which each memory system 156 includes two groups 156p, 156n of K memory elements 157, numbered 1 through K (K≧2), such that the cell contains 2K memory elements. The two groups 156p, 156n are in a differential configuration. The first group 156p is intended to store positive weight values, and the second group 156n is intended to store negative weight values. In each group, the K memory elements 157 are arranged in parallel. The parallel and differential configuration makes it possible to read all conductance values ​​in one step. The resulting conductance is equal to the sum of the conductance values ​​of the elements 157 in the first group minus the sum of the conductance values ​​of the elements in the second group, which produces the desired weight value.

[0088] 3B, 3C, and 3D compare different programming techniques, assuming a cell is composed of four resistively variable elements 157 with two memory elements per polarity group. The weight value (w) to be stored in the cell is equal to 0.8, and the SET values ​​of the two memory elements in the positive polarity group are G SET,D1 = 12μS and G SET,D2 = 14µS. The preferred scale factor S max Let us further assume that is equal to 20 μS, which means that the value G max = 10 μS (since K = 2).

[0089] The uniform fill method (Figure 3B) uses the conductance value w × G max = 8 μS to all memory elements, which requires repeatedly programming all devices in the selected group to an intermediate state, resulting in "noisy" values. max= 10 μS, and then program the remaining devices to a residual value (6 μS), but this has the same drawback: both memory elements are iteratively programmed to an intermediate state. In contrast, our approach (Figure 3D) first sets all memory elements to the SET state, and then iteratively programs device D1 (with the lowest SET conductance) so that it reaches the lowest residual conductance value (2 μS). This means that the SET state is set to w × G max State and G max Since the SET state is less noisy than the RESET state, it reduces noise compared to the uniform fill and max fill approaches. Note that the benefit of this approach increases as the number of memory elements per cell increases (K>2), since at most one memory element is in the intermediate state and all remaining elements are in either the SET or RESET state. 2.3 Step-by-step programming example (Figure 4A-4E)

[0090] 4A-4E illustrate the steps of programming a cell according to one embodiment, which aims to maximize the number of memory elements in the SET state. First, a preferred scale factor S max is selected, which converts the normalized weight values ​​into corresponding conductance values ​​(in conductance units). This step corresponds to step S60 in Figure 5. The factor S max depends on the saturation current of the ADC circuit at the output of the IMC tile 15. It may further vary across different IMC tiles and / or across output lines of the same tile. Second, the array is initialized by resetting all memory element devices (step S20 in FIG. 5). FIG. 4A shows the cells as obtained after this step. Third, all memory elements in the positive polarity group (i.e., corresponding to the polarity of the positive weight value to be programmed) are set to the SET state, see FIG. 4B. Fourth, the conductance values ​​of the memory elements are read.

[0091] |Σ i=1 K G ip -Σ i=1 K G i n |<|G target In the first scenario, i.e., the total conductance of the cell is insufficient to support the weight value, the memory elements remain unchanged, i.e., all memory elements corresponding to the polarity of the weight are left in their SET state.

[0092] In the second (more likely) scenario, the cell is programmed with a weight value, i.e., |Σ i=1 K G i p -Σ i=1 K G i n |≧|G target Therefore, the mapping can be determined by the following process: (i) For positive weight values, |Σ i {S} G i p -Σ i=1 K G i n |≧|G target For weight values ​​that are | or negative |Σ i=1 K G i p -Σ i {S} G i n |≧|G target Find the minimum set {S} of memory elements such that |; (II) reset all memory elements that are not in set {S}; (iii) Select the least conductive memory element of set {S} for further programming, i.e., select this memory element so that the cell will have the value G target It is further programmed in the following steps to reach

[0093] Several cases can be detailed. For example, FIG. 4C illustrates that once all other memory elements have been reset (step S80 in FIG. 5), it may be sufficient to adjust a single memory element (e.g., element 2) for the cell to match the target conductance value. Another example, FIG. 4D, relates to the case where the minimum subset required a priori to meet the target conductance value consists of elements 2 through K. However, the conductance of the memory element with the smallest SET conductance (element 2 in this example) needs to be adjusted, while the other elements of the subset can remain in their SET state. Note that element 1 is reset because it does not belong to the determined subset. The final case, FIG. 4E, corresponds to a scenario in which all memory elements in the positive polarity group need to be selected; the determined subset is not a strict subset of the relevant polarity group. In this case, all elements in the positive polarity group remain in their SET state, subject to element 2 being reprogrammed to an intermediate state.

[0094] A variety of single-device programming methods can be used to condition a single element identified for further programming, such as an iterative programming (ITP) scheme, a single-shot programming to intermediate values ​​(SSP) scheme, and a gradient-based (GDP) algorithm. Preferred implementations of the ITP and GDP schemes are described in the following subsections. 2.4 Single-Device Programming Method Example (Figure 6A, Figure 6B)

[0095] 6A shows a gradient descent-based (GDP) algorithm used to further program a single memory element selected for further programming. The programming algorithm (performed by programming unit 19) provides a programming mask to further program the selected single memory element; the aim is that by only reprogramming the selected element, the cell will reach a target conductance value G, given that the other memory elements either remain in the SET state or are reset to the RESET state. target Following this procedure, the GDP algorithm is executed, which may generate multiple iterations (t=1...T). The programming controller triggers the application of pulses to the IMC tiles 15 according to the programming mask. The GDP algorithm iteratively calculates the gradient of a loss function L that captures the quality of matrix-vector multiplication (MVM). The gradient is converted to pulse amplitude. Pulses with the obtained amplitude are then applied to the device marked by the previously obtained programming mask. The process repeats until a satisfactory loss, i.e., MVM quality, is achieved or a maximum number of iterations is reached.

[0096] 6B illustrates an ITP scheme utilized to further program a single memory element selected for further programming. Again, the programming algorithm provides a programming mask for further programming the single memory element. An iterative programming loop begins, which may again require multiple programming iterations (t=1...T). This loop uses the measured conductances of all K devices of each polarity measured via the single-device read method, calculated for the relevant unit cell (k,l), G target and

number

[0097] A computerized device may be suitably designed to implement embodiments of the present invention as described herein. In that regard, it may be appreciated that the methods described herein are largely non-interactive and automatic. The methods described herein may be implemented using software (e.g., firmware), hardware, or a combination thereof. In an exemplary embodiment, the methods described herein are implemented using software as an executable program executed by a suitable digital processing device. More generally, general-purpose digital computers such as personal computers, workstations, and the like may be used to implement embodiments of the present invention. However, it is preferred to rely on a programming unit 19 (and possibly a processing unit 18) integrated with the IMC device 15.

[0098] For example, when programming units 19 are in operation, their processors are configured to execute software (or simply instructions) stored in the memory of the units 19 to communicate data to and from the memory and to generally control the operation of the units 19 in accordance with the instructions or software. The methods described herein are read, in whole or in part, by the processor, typically buffered within the processor, and then executed. When the methods described herein are implemented in software, the methods can be stored on any computer-readable medium, such as storage, used by or in conjunction with any computer-related system or method.

[0099] Accordingly, the present invention may be a system, a method, and / or a computer program product at any possible level of technical detail. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention. The computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction-execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves having instructions recorded thereon, and any suitable combination of the foregoing.

[0100] As used herein, a computer-readable storage medium should not be construed as being a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through a fiber optic cable), or an electrical signal transmitted through a wire.

[0101] Computer readable program instructions for carrying out operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and procedural programming languages ​​such as the C programming language or similar programming languages.

[0102] While the present invention has been described with reference to a limited number of embodiments, variations, and accompanying drawings, it will be apparent to those skilled in the art that various modifications may be made and equivalents may be substituted without departing from the scope of the invention. In particular, features (such as devices or methods) described in a given embodiment, variation, or illustrated in a drawing may be combined with or substituted for other features in another embodiment, variation, or drawing without departing from the scope of the invention. Various combinations of the features described in connection with any of the above embodiments or variations may be contemplated as appropriate while remaining within the scope of the appended claims. In addition, many minor modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is not intended that the invention be limited to the particular embodiments disclosed; rather, the invention is intended to include all embodiments falling within the scope of the appended claims. In addition, many variations other than those expressly mentioned above are contemplated. For example, other types of memory elements may be envisioned.

Claims

1. 1. A method of programming memory elements of an in-memory computing device having a crossbar array structure including N input lines and M output lines interconnected at intersections defining N×M cells, wherein N≧2 and M≧2, the intersections each including a respective memory system including a group of K memory elements arranged in parallel, wherein K≧2, whereby each cell of the N×M cells includes K memory elements, the method comprising: programming each of said cells given a target conductance value corresponding to a target weight value to be stored in said each of said cells; The method comprises: applying a SET signal to the K memory elements of each cell to set each of the K memory elements to a SET state, and reading K conductance values ​​of the K memory elements in the SET state; and determining a conductance value of at least one of the K memory elements based on the read K conductance values ​​and the target conductance value; matching the summed conductance of the K memory elements of each cell to the target conductance value; Maximizing the number of the K memory elements that are in either their SET state or their zero conductance nominal RESET state such that at most one of the K memory elements is not in either the SET state or the RESET state. The stage of adjusting A method for providing the above.

2. Adjusting the conductance value of the at least one of the K memory elements comprises: determining a subset of the K′ memory elements whose summed conductance matches the target conductance value with a tolerance that can be removed by reprogramming at most one of the K′ memory elements based on the read K conductance values ​​and the target conductance value, where K′≦K; and applying a RESET signal to any remaining memory elements of each of the cells not within the subset to set the any remaining memory elements to their RESET state; The method of claim 1 further comprising:

3. 3. The method of claim 2, wherein adjusting the conductance value comprises reprogramming exactly one of the K' memory elements of the subset.

4. 3. The method of claim 2, wherein adjusting the conductance value comprises applying the RESET signal to any remaining memory elements.

5. Adjusting the conductance value of at least one of the K memory elements comprises: Conductance values ​​of at least two of the K memory elements of each cell are determined by: applying the RESET signal to any remaining memory elements; and reprogramming exactly one of the K' memory elements of the subset; The stage of adjusting by The method of claim 2 further comprising:

6. The method comprises: identifying one of the K' memory elements as the memory element having the smallest conductance among the memory elements of the determined subset; The method of claim 5 further comprising:

7. The method of claim 2 , wherein the subset is determined as the subset of smallest cardinality for which the summed conductance value of the memory elements in their SET state is greatest.

8. The method comprises: before adjusting the conductance value, scaling initial conductance values ​​to the target conductance values ​​by multiplying initial weight values ​​by a scale factor determined according to a maximum cell conductance of each of the cells; The method of claim 1 further comprising:

9. each of the respective memory systems includes two groups of K memory elements, such that each cell of the N×M cells includes 2K memory elements, where K≧2, the two groups being in a differential configuration, the two groups consisting of a first group of K memory elements and a second group of K memory elements intended to store positive and negative weight values, respectively, the K memory elements being in parallel in each of the two groups, the method further comprising, prior to the step of applying the SET signal: selecting a given one of the two groups according to an intended sign of the target weight to be stored in the cell, whereby the SET signal is applied to only the K memory elements of the given group to set each of the K memory elements of the given group to the SET state; reading 2K conductance values, consisting of K conductance values ​​of the K memory elements in each of the two groups; and adjusting, based on the 2K read conductance values ​​and the target conductance value, the conductance value of at least one of the K memory elements of the given group to match the summed conductance of the 2K memory elements of each cell to the target conductance value and to maximize the number of the 2K memory elements of each cell that are in either their SET state or a zero conductance nominal RESET state, such that at most one of the K memory elements of the given group is not in either the SET state or the RESET state. The method of claim 1 further comprising:

10. 10. The method of claim 1, wherein the conductance of the at most one of the memory elements is adjusted according to one of: an iterative programming method; a gradient-based algorithm; or a single-shot programming method.

11. 2. The method of claim 1, wherein the K memory elements are set to the SET state by programming the K memory elements according to a single-shot programming method.

12. 2. The method of claim 1, wherein the remaining memory elements are reset to the RESET state by programming the remaining memory elements according to a single-shot programming method.

13. 2. The method of claim 1, wherein, prior to the step of applying the SET signal, the K memory elements are initialized by resetting all of the K memory elements.

14. 1. A processing system for programming memory elements of an in-memory computing device having a crossbar array structure including N input lines and M output lines interconnected at intersections defining N×M cells, wherein N≧2 and M≧2, the intersections each including a respective memory system including a group of K memory elements arranged in parallel, wherein K≧2, whereby each cell of the N×M cells includes K memory elements, the processing system comprising a programming unit connected to the in-memory computing device, the programming unit configured to program the memory elements of an in-memory computing device given a target conductance value corresponding to a target weight value to be stored in each cell. applying a SET signal to the K memory elements of each cell to set each of the K memory elements to a SET state, and reading K conductance values ​​of the K memory elements in the SET state; and determining a conductance value of at least one of the K memory elements based on the read K conductance values ​​and the target conductance value; matching the summed conductance of the K memory elements of each cell to the target conductance value; Maximizing the number of the K memory elements that are in either their SET state or their zero conductance nominal RESET state such that at most one of the K memory elements is not in either the SET state or the RESET state. Adjust it so that a processing system configured to program each cell by:

15. 15. The processing system of claim 14, wherein the programming unit is connected to the in-memory computing device via the input lines or the output lines of the in-memory computing device and is adapted to adjust the conductance value of the at least one of the K memory elements by applying a voltage signal across the input lines or the output lines, respectively.

16. 15. The processing system of claim 14, wherein the processing system further comprises a readout circuit connected at an output of the output line, the programming unit further connected to the readout circuit, the programming unit configured to adjust the conductance value according to a single-device programming method.

17. 17. The processing system of claim 16, wherein each of the respective memory systems includes two groups of K memory elements, where K≧2, such that each cell of the N×M cells includes 2K memory elements, the two groups being in a differential configuration, the two groups consisting of a first group of K memory elements and a second group of K memory elements intended to store positive and negative weight values, respectively, the K memory elements being in parallel in each of the two groups, and the programming unit is further configured to select a given one of the two groups according to an intended sign of the target weight to be stored in the cell.

18. 15. The processing system of claim 14, wherein the memory element is one of a phase change memory device, a resistive random access memory device, and a flash memory cell device.

19. 20. The processing system of claim 18, wherein the memory element is a phase change memory device.

20. 1. A computer program product for programming memory elements of an in-memory computing device having a crossbar array structure including N input lines and M output lines interconnected at nodes defining N×M cells, wherein N≧2 and M≧2, said nodes having respective memory systems each including groups of K memory elements arranged in parallel, wherein K≧2, whereby each cell of said N×M cells comprises K memory elements, said computer program product comprising a computer readable storage medium embodied with program instructions, by processing means of a programming unit connectable to said in-memory computing device, for causing said programming unit to, given target conductance values ​​corresponding to target weight values ​​to be stored in each said cell: applying a SET signal to the K memory elements of each cell to set each of the K memory elements to a SET state, and reading K conductance values ​​of the K memory elements in the SET state; and determining a conductance value of at least one of the K memory elements based on the read K conductance values ​​and the target conductance value; matching the summed conductance of the K memory elements of each cell to the target conductance value; Maximizing the number of the K memory elements that are in either their SET state or their zero conductance nominal RESET state such that at most one of the K memory elements is not in either the SET state or the RESET state. Steps to adjust a computer program product executable to cause each said cell to be programmed by

21. The program instructions further comprise a step of adjusting the conductance value of the at least one of the K memory elements, determining a subset of the K' memory elements whose summed conductance matches the target conductance value with a tolerance that can be removed by reprogramming at most one of the K' memory elements based on the read K conductance values ​​and the target conductance value, where K'≦K; applying a RESET signal to any remaining memory elements of each of the cells not within the subset to set the any remaining memory elements to their RESET state; and reprogramming at most one of the K' memory elements of the subset; Execute one or each of the following:

21. A computer program product according to claim 20, designed to:

22. 22. The computer program product of claim 21, wherein the program instructions for adjusting the conductance value of the at least one of the K memory elements include reprogramming exactly one of the K′ memory elements of the subset.

23. 22. The computer program product of claim 21, wherein the program instructions that cause the conductance value to be adjusted include applying the RESET signal to any remaining memory elements.

24. 22. The computer program product of claim 21, wherein the program instructions for adjusting the conductance value of at least one of the K memory elements include adjusting the conductance values ​​of at least two of the K memory elements of each cell by applying the RESET signal to any remaining memory elements and reprogramming exactly one of the K′ memory elements of the subset.

25. The program instructions include: identifying said exactly one of said K' memory elements as the memory element having the smallest conductance among said memory elements of said determined subset.

25. The computer program product of claim 24, further comprising:

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