Thermoelectric cooling attachment structure

Abstract

In some embodiments, the device may have a thermoelectric cooler embedded or integrally formed in one or more chips arranged in a hybrid bonded device stack.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to novel packaging techniques for microelectronic devices, and more particularly to embedded cooling systems for device packaging and methods of fabricating the same.

[0002] [Citation of Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 435,145, filed December 23, 2022, and U.S. Provisional Patent Application No. 63 / 509,026, filed June 19, 2023, each of which is incorporated by reference in its entirety. [Background technology]

[0003] Energy consumption poses a very serious challenge for the future of large-scale computing, as global computing energy needs are growing at a rate considered unsustainable by most. Some models predict that the information, communications, and technology (ICT) ecosystem could exceed 20% of global electricity use by 2030, with direct electricity consumption by large computing centers accounting for more than one-third of that energy use. Cooling costs account for a significant portion of a computing center's energy needs, as even small increases in operating temperature can adversely affect the performance of microprocessors, memory devices, and other electronic components.

[0004] Heat dissipation in high-power-density chips is also a significant challenge due to increased power density and correspondingly increased heat flux, which contributes to high chip temperatures, resulting from improved chip performance, for example, through increased gate density and the use of multicore microprocessors. These high temperatures are undesirable because they degrade the chip's operational performance, efficiency, and reliability. Cooling systems used to maintain a chip at a desired operating temperature typically employ one or more heat-dissipating devices, such as thermal spreaders, heat pipes, cold pipes, or heat sinks, to remove heat. These heat-dissipating devices are thermally coupled to the chip using compliant, thermally conductive materials, such as thermal pastes, thermal adhesives, and thermal gap fillers. Thermal interface materials (TIMs) maintain thermal contact between the chip and the heat-dissipating device surfaces to facilitate heat transfer between them. Unfortunately, the thermal resistance of the thermal interface material, combined with the thermal resistance at the interface region, can impede heat transfer from the chip to the heat-dissipating device, undesirably reducing the cooling efficiency of the cooling system. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, there is a need in the art for improved energy efficient cooling systems and methods of manufacturing same. [Means for solving the problem]

[0006] The embodiments described herein provide an integrated cooling assembly embedded within a device package that shortens the thermal resistance path between the device and the heat sink and reduces thermal communication between devices within the same package.

[0007] In some embodiments, the device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate, the cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be disposed between the package cover and the second side of the cold plate, and one or more surfaces of the second side of the cold plate may be spaced apart from the package cover to form a coolant channel between the package cover and the cold plate. The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel.

[0008] In some embodiments, the device package may have an integrated cooling assembly, the integrated cooling assembly including a cold frame, a first HI device, and a second HI device. The cold plate may have a plurality of sidewalls surrounding an opening formed therethrough. The first and second HI devices may each have a first die and one or more second dies directly bonded to the first die. The first dies may be directly bonded to opposing sides of the cold frame, which forms a perimeter of a coolant channel between the first and second HI devices. Backsides of the second dies may face each other within the coolant channel.

[0009] In some embodiments, a method for connecting a device package includes direct-bonding a first substrate to a second substrate and singulating an integrated cooling assembly from the bonded substrates. The first substrate may include a semiconductor device, the second substrate may include a cold plate, and the integrated cooling assembly may be formed by bonding the cold plate to the semiconductor device. The method may include attaching a package cover to the cold plate and attaching the semiconductor device to the package substrate before or after attaching the package cover. The cold plate may have a first side directly bonded to the semiconductor device and a second side opposite the first side, and the second side may have one or more surfaces spaced apart from the package cover to form a coolant channel between the cold plate and the package cover.

[0010] Some embodiments of the present disclosure relate to a method. For example, in one embodiment, a device may include a first chip. The device may further include a second chip hybrid-bonded to the first chip. The device may further include a thermoelectric cooler (TEC) disposed between the first chip and the second chip.

[0011] Some embodiments of the present disclosure relate to a method. For example, in one embodiment, a device may include a first chip. The device may further include a second chip hybrid-bonded to the first chip. The device may further include a thermoelectric cooler (TEC) disposed between the first chip and the second chip, with a first portion of the TEC disposed within or below the bonding surface of the first chip and a second portion of the TEC disposed within or below the bonding surface of the second chip.

[0012] Some embodiments of the present disclosure relate to a method. For example, in one embodiment, a device may include a first chip. The device may further include a second chip hybrid-bonded to the first chip. The device may further include a thermoelectric cooler (TEC) disposed between the first chip and the second chip, the TEC having alternating n-type and p-type semiconductor pillars parallel to a bonding surface of the second chip.

[0013] Some embodiments of the present disclosure relate to a method. For example, in one embodiment, a 3DIC device can include a first chip. The 3DIC device can further include a second chip hybrid-bonded to the first chip. The device can further include one or more TEC devices hybrid-bonded to the first chip and in a juxtaposed arrangement with the second chip.

[0014] These and other objects and advantages of the present disclosure will become apparent from a consideration of the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 illustrates a device package with an external heat sink. [Figure 2A] FIG. 1 illustrates an exemplary system panel according to embodiments of the present disclosure. [Figure 2B] FIG. 1 illustrates an exemplary system panel according to embodiments of the present disclosure. [Figure 3A] 1 illustrates an exemplary device package according to embodiments of the present disclosure. [Figure 3B] 1 illustrates an exemplary device package according to embodiments of the present disclosure. [Figure 4A] 1 illustrates an exemplary integrated cooling assembly according to embodiments of the present disclosure. [Figure 4B] 1 illustrates an exemplary integrated cooling assembly according to embodiments of the present disclosure. [Figure 4C] 1 illustrates an exemplary integrated cooling assembly according to embodiments of the present disclosure. [Figure 5] 1 illustrates an exemplary multi-component device package according to embodiments of the present disclosure. [Figure 6] 1 illustrates an exemplary multi-component device package according to embodiments of the present disclosure. [Figure 7A] 1 illustrates an exemplary device package according to embodiments of the present disclosure. [Figure 7B] 1 illustrates an exemplary device package according to embodiments of the present disclosure. [Figure 8A] 1 illustrates an exemplary device package according to embodiments of the present disclosure. [Figure 8B] 1 illustrates an exemplary device package according to embodiments of the present disclosure. [Figure 9] 1 illustrates an exemplary device package according to embodiments of the present disclosure. [Figure 10A] 1A and 1B illustrate examples of device packages according to embodiments of the present disclosure. [Figure 10B] 1A and 1B illustrate examples of device packages according to embodiments of the present disclosure. [Figure 10C] 1A and 1B illustrate examples of device packages according to embodiments of the present disclosure. [Figure 11] 1A-1D illustrate a method for manufacturing a device package according to embodiments of the present disclosure. [Figure 12] 12A-12C illustrate an exemplary device package at different stages of the method of FIG. 11. [Figure 13] 1A and 1B are diagrams illustrating examples of devices with thermoelectric coolers. [Figure 14] 1A and 1B are diagrams illustrating examples of devices with thermoelectric coolers. [Figure 15A] 1A and 1B are diagrams illustrating examples of devices with thermoelectric coolers. [Figure 15B] 1A and 1B are diagrams illustrating examples of devices with thermoelectric coolers. [Figure 16]1A and 1B are diagrams illustrating examples of devices with thermoelectric coolers. DETAILED DESCRIPTION OF THE INVENTION

[0016] While the figures herein depict various embodiments of the present invention, these are by way of example only, and it will be recognized that additional or alternative structures, assemblies, systems, and methods may be implemented within the principles illustrated by this disclosure.

[0017] Embodiments herein provide an integrated cooling assembly embedded within a device package that shortens the thermal resistance path between the device and the heat sink, as well as reduces thermal communication between devices within the same package.

[0018] As used herein, the term "substrate" means and includes any workpiece, wafer, or article that provides a base material or support surface upon which components, elements, devices, assemblies, modules, systems, or features of the heat-generating devices, packaging components, and cooling assemblies described herein can be mounted or configured. The term substrate further includes a "semiconductor substrate" that provides a support material upon which or on which elements of a semiconductor device can be fabricated or attached and any material layers, features, and / or electronic devices formed thereon, in, or through.

[0019] As described below, semiconductor substrates herein generally have a "device side," e.g., a side (surface) carrying semiconductor device elements such as transistors, resistors, and capacitors, and a "back side" opposite the device side. The term "active side" should be understood to include the device-side surface of a substrate, and may also include the device-side surface of a semiconductor device and / or the surface of any material layers, device elements, or features formed thereon or extending outward therefrom, and / or any openings formed therein. Thus, it should be understood that the material forming the active side can vary depending on the device fabrication and assembly stage. Similarly, the term "non-active side" (opposite the active side) includes the non-active side of a substrate at any device fabrication stage, including the surface of any material layers, device elements, or features formed thereon or extending outward therefrom, and / or any openings formed therein. Thus, the terms "active side" and "non-active side" may include the respective surfaces of a semiconductor substrate at the start of device fabrication as well as any surfaces formed during material removal, e.g., after a substrate thinning operation. Depending on the device fabrication or assembly stage, the terms "active side" and "non-active side" may also be used to refer to surfaces of material layers or features formed on, in, or through a semiconductor substrate, whether or not the material layers or features are ultimately present in the fabricated or assembled device.

[0020] Spatial terms are used herein to describe relationships between various elements, such as substrates, heat-generating devices, cooling assembly components, device package components, and other features described below. Unless otherwise specified, terms such as "above," "over," "upper," "outward," "on," "below," "under," "below," and the like are generally defined with respect to the X, Y, and Z directions depicted in the drawings. Thus, it should be understood that spatial terms used herein encompass different orientations of the substrate and are not limited by the direction of gravity, unless otherwise specified. Unless otherwise specified, terms describing relationships between elements, such as "on," "embedded in," "coupled to," "connected by," "mounted to," and "bonded to," alone or in combination with spatial terms, include both relationships with intervening elements and direct relationships without intervening elements.

[0021] Unless otherwise specified, the term "cold plate" generally refers to a base plate or a stack of base plates directly bonded to one another, which may be bonded to a semiconductor device. The cold plate may have material layers and / or metal features formed within or on the surface of the base plate or stack of base plates that facilitate direct dielectric or hybrid bonding with the semiconductor device. The direct bonding method can transfer heat from the semiconductor device from the cold plate to a fluid flowing along it without the use of a thermal interface material. Unless otherwise specified, the device packages and cold plates described herein can be used with any desired fluid coolant, for example, a liquid-phase, gas-phase, and / or vapor-phase coolant. Thus, these terms should not be construed as limiting the coolant to any one fluid phase.

[0022] 1 is a schematic side view of a device package 10 and a heat sink 22 attached to the device package. The device package 10 typically includes a package substrate 12, a first device 14, a device stack 15, a heat spreader 18, and one or more first TIM layers 16 that thermally couple the first device 14 and the device stack 15 to the heat spreader 18. The device package 10 is thermally coupled to the heat sink 22 via a second TIM layer 20. The TIM layer is typically formed of a compliant material, such as a thermally conductive paste, grease, adhesive, or other thermally conductive material, such as a fusible metal alloy, e.g., solder, or a combination thereof. The TIM layer facilitates thermal contact between components in the device package and between the device package 10 and the heat sink 22.

[0023] 1 becomes increasingly problematic because the heat cannot be dissipated quickly enough to allow the device to operate at optimum power, thus reducing the energy efficiency of the device. Also problematic is the transfer of heat between devices within the package, as shown by heat transfer path 24, where heat may undesirably transfer from a first device 14, e.g., a CPU or GPU, with a high heat flux, to a device in the stack 15, e.g., a memory, with a low heat flux, through heat spreader 18.

[0024] For example, as shown in FIG. 1 , each package component and their respective interface boundaries have a corresponding thermal resistance (R1-R5). Here, R1 is the thermal resistance of the bulk semiconductor material of the first device 14, R3 and R5 are the thermal resistances of the first and second TIM layers 16 and 20, respectively, R4 is the thermal resistance of the heat spreader 18, and R2 represents the thermal resistance at the component interface region. In a typical cooling system, R3 and R5 may account for 80% or more of the cumulative thermal resistance of the heat transfer path 26, and R4 may account for 5% or more, while R1 of the first device 14 and R2 of the interface account for the remainder. Thus, embodiments herein provide an integrated cooling system embedded within a device package. The embedded cooling assembly shortens the thermal resistance path between the device and the heat sink and reduces thermal communication between devices in the same package, as described, for example, in connection with the following figures.

[0025] FIG. 2A is a schematic plan view of an example system panel 200 having multiple device packages 301. FIG. 2B shows a partial cross-sectional side view of a portion of the system panel 200. In this case, the system panel 200 includes a printed circuit board, in this case a PCB 202, multiple device packages 301 mounted on the PCB 202, and multiple coolant lines 208 fluidly coupling each of the device packages 301 to a coolant source. As envisioned, the coolant can be delivered to each of the device packages 301 in any desired fluid phase, e.g., liquid, vapor, gas, or combinations thereof, and such coolant can exit the device packages 301 in the same or different layers. In some embodiments, the coolant is delivered to the device packages 301 and returned therefrom as a liquid, and the coolant source 210 may include a heat exchanger or chiller to maintain the coolant at a desired temperature. In other embodiments, the coolant may be delivered to the device package 301 as a liquid, evaporated to a gas within the device package, and returned as a vapor to the coolant source 210. In these embodiments, the device package 301 may be fluidly coupled in parallel to the coolant source 210, which may have or further include a compressor (not shown) to condense the received vapor into liquid form.

[0026] As shown, each device package 301 is mounted within a socket 214 of the PCB 102 and is coupled to the socket using a plurality of pins 216 or other suitable coupling methods, such as solder bumps (not shown). The device package 301 may be seated within the socket 214 and secured to the PCB 202 using a mounting frame 206 and a plurality of fasteners 212, such as compression springs, configured to together exert a relatively uniform downward force on the upwardly facing edges of the device package 301. The uniform downward force ensures proper pin contact between the device package 301 and the socket 214.

[0027] Fig. 3A is a schematic exploded isometric view of device package 301. Fig. 3B is a schematic cross-sectional view of device package 301 taken along line A-A'. As main components, device package 301 includes package substrate 302, integrated cooling assembly 303, and package cover 308. Device package 301 further includes adhesive layer 322 for attaching integrated cooling assembly 304 to package cover 308 to form coolant channels 310 therebetween.

[0028] Typically, package substrate 302 is formed of a rigid material, such as an epoxy or resin-based laminate, that supports integrated cooling assembly 303 and package cover 308. Package substrate 302 typically has conductive features that electrically couple integrated cooling assembly 303 to PCB 102. Integrated cooling assembly 303 may include a semiconductor device, in this case device 304, mounted on package substrate 302 and a cold plate 306 bonded to device 304. In this case, device 304 has an active side 318 on or within which device components, such as transistors, resistors, and capacitors, are formed, and device 304 has an inactive back side 320 opposite active side 318. As shown, active side 318 is positioned adjacent to and facing package substrate 302. The active side 318 may be electrically coupled to the package substrate 302 using conductive bumps 319, which are encapsulated by a first underfill layer 321 disposed between the device 304 and the package substrate 302. The first underfill layer 321 may be comprised of a cured polymer resin or epoxy that provides mechanical support for the conductive bumps 319 and prevents thermal fatigue.

[0029] In this case, the cold plate 306 is attached to the device backside 320 without an intervening adhesive material, e.g., directly bonded to the device backside 320, such that the cold plate 306 and the device backside 320 are in direct thermal contact. In some embodiments, the cold plate 306 is attached to the device backside 320 using a direct dielectric bonding process. In other embodiments, the cold plate 306 is attached to the device backside 320 using a hybrid of a direct dielectric and direct metallic bond formed therebetween. For example, in some embodiments, one or both of the device backside 320 and the device-facing side of the cold plate 306 are comprised of a dielectric layer, e.g., a first dielectric layer 334A and a second dielectric layer 334B, and the cold plate 306 is directly bonded to the device backside 320 via a bond formed between the dielectric layers 334A and 334B. In some embodiments, the cold plate 306 is directly bonded to the device backside 320 using a hybrid bonding technique, with bonds formed between the dielectric layers 334A, 334B and between metal features disposed within the dielectric layers 334A, 334B, such as between the first metal pad 336A and the second metal pad 336B.

[0030] Suitable dielectrics for use as the dielectric layers 334A, 334B include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, metal oxides, metal nitrides, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, diamond-like carbon (DLC), or combinations thereof. In some embodiments, one or both of the dielectric layers 334A, 334B are formed of an inorganic dielectric, i.e., a dielectric substantially free of organic polymers. Typically, one or both of the layers 334A, 334B are deposited to a thickness greater than that of a native oxide, e.g., about 1 nm or more, 5 nm or more, 10 nm or more, 50 nm or more, 100 nm or more, or 200 nm or more. In some embodiments, one or both of the layers 334A, 334B are deposited to a thickness of 301 nm or less, e.g., 200 nm or less, 100 nm or less, or 50 nm or less.

[0031] Beneficially, direct bonding of the dielectric and (optionally) metallic surfaces eliminates the need for an intervening adhesive layer or thermal interface material (TIM) between the device 304 and the cold plate 306. Thus, the device package 301 can reduce the thermal resistance of the heat transfer path 326 compared to the heat transfer path 26 of the device package 10 shown in FIG. 1. In some embodiments, the cumulative thermal resistance of the path 326 is reduced by a factor of 50 or more compared to the thermal resistance of the heat transfer path 26. Methods for forming direct dielectric and hybrid bonds are described below.

[0032] As shown, the upwardly facing surface of cold plate 306 defines a cavity having a base surface 309 that forms the bottom of coolant channels 310 and sidewalls 311 that surround and project upwardly from the base surface. The upwardly facing surfaces of sidewalls 311 form a perimeter surface 313 that supports adhesive layer 322. Generally, when device package 301 is assembled, coolant channels 310 define a space between base surface 309 and package cover 308. Adhesive layer 322 attaches perimeter surface 313 to package cover 308, forming an impermeable barrier that prevents coolant delivered to coolant channels 310 from reaching and causing damage to active side 318 of device 304. In this case, adhesive layer 322 can be considered a decoupling adhesive that accommodates the difference in linear expansion between the dissimilar materials, thus accommodating the difference in CTE between package cover 308 and cold plate 306. In some embodiments, adhesive layer 322 comprises a decoupling membrane disposed between and attached to cold plate 306 and package cover 308.

[0033] In some embodiments, the cold plate 306 has a plurality of protruding features 324, such as fins, columns, or pillars, extending upward from the base surface 309. The protruding features 324 increase the surface area and facilitate laminar flow of fluid at the interface between the coolant and the cold plate 306, thereby increasing heat transfer therebetween. To further increase heat dissipation from the device, the protruding features 324 may be comprised of and / or formed from a thermally conductive metal, such as copper. Typically, the protruding features 324 are arranged in a repeating pattern. In some embodiments, the protruding features 324 may be arranged in a randomized pattern.

[0034] In some embodiments, the cold plate 306 is formed from a material having a coefficient of thermal expansion (CTE) that is approximately the same as the CTE of the bulk semiconductor substrate of the device 304. For example, in some embodiments, the device 304 may be formed on a single crystal silicon substrate, and the cold plate 306 may be made from a single crystal silicon or polycrystalline silicon substrate. Forming the cold plate 306 from a CTE-matched material (with respect to the bulk substrate material of the device 304) prevents undesired separation of the device 304 and the cold plate 306 throughout repeated thermal cycling.

[0035] In some embodiments, the cold plate 306 may be made from bulk substrate materials, including amorphous silicon materials, such as metals, metal alloys, ceramics, composites, and other low CTE materials suitable for bonding using the methods described below. For example, the cold plate 306 may be made from a bulk material selected from the group consisting of copper, aluminum, copper alloys (e.g., copper-molybdenum alloys and copper-tungsten alloys), iron-cobalt-nickel alloys (e.g., Kovar® available from Magellan Industrial Trading Co., Inc., South Norwalk, Connecticut, USA), iron-cobalt-nickel-silver alloys, iron-nickel alloys (e.g., Invar® superalloy available from Magellan), iron-nickel-silicon alloys, aluminum-silicon carbide, aluminum-silicon alloys, beryllium-beryllium oxide, beryllium composites, beryllium oxide composites, aluminum-graphite fibers, copper-graphite fibers, metal-diamond composites (e.g., aluminum-diamond composites and silver-diamond composites), metal oxides, metal nitrides, and combinations thereof. The non-silicon substrate material may be prepared to be bondable as described below, and may or may not include a dielectric layer deposited on the side facing the device to form a bonding surface.

[0036] The package cover 308 generally has one or more vertical or sloped sidewall portions 308A and a lateral portion 308B spanning and connected to the sidewall portions 308A. The sidewall portions 308A extend upward from the periphery of the package substrate 302 to enclose the device 304 and a cold plate 306 mounted thereon. The lateral portion 308B is attached to the cold plate 306 and is typically spaced from the cold plate 306 by a gap corresponding to the thickness of the adhesive layer 322. Coolant circulates through the coolant channels 310 through inlet / outlet openings 312 formed through the lateral portion 308B. Coolant lines may be attached to the device package 301 using threads formed in the sidewalls of the inlet / outlet openings 312 and / or connector features surrounding the openings 312 and extending upward from the surface of the lateral portion 308B.

[0037] Typically, the package cover 308 is formed of a semi-rigid or rigid material such that at least a portion of the downward force exerted by the mounting frame 106 (FIG. 2) on the package cover 308 is transferred to the support surface of the package substrate 302, but not to the cold plate 306 and underlying device 304. In some embodiments, the package cover 308 is made of a thermally conductive metal, such as aluminum or copper. In some embodiments, the package cover 308 functions as a heat spreader to redistribute heat from one or more electronic components within a multi-component device package, for example, as described below.

[0038] As described above, adhesive layer 322 thermally couples cold plate 306 to package cover 308 and, in combination, forms coolant channels 310. As shown, adhesive layer 322 is disposed between peripheral surface 313 of cold plate 306 and lateral portion 308B of package cover 308. In this case, cold plate 306 forms the lower or base surface and at least a portion of the coolant channel sidewalls of coolant channels 310, package cover 308 forms the upper surface of coolant channels 310, and adhesive layer 322 forms a seal between package cover 308 and peripheral surface 313 of cold plate 306. In other embodiments, adhesive layer 322 may be disposed between sidewall 311 of cold plate 306 and sidewall portion 308A of package cover 308. Generally, when device package 301 is assembled, adhesive layer 322 forms an impermeable barrier that prevents coolant delivered to coolant channels 310 from reaching and causing damage to active side 318 of device 304.

[0039] In some embodiments, the device package 301 further includes a second underfill layer 338 (shown in FIG. 3B ) disposed in a gap region located outside the coolant channels 310, e.g., between the package cover 308, the adhesive layer 322, and the package substrate 302. For example, the second underfill layer 338 may include a polymer or epoxy material extending upward from the package substrate 302 to encapsulate and / or surround at least a portion of the device 304, and in some embodiments, the cold plate 308. When used, the second underfill layer 338 can provide mechanical support that improves system reliability and extends the useful life of the device package 301. For example, the second underfill layer 338 can reduce mechanical stresses, such as stresses caused by vibration, mechanical and thermal shock, and / or fatigue caused by repeated thermal cycling, that may weaken interface bonds and / or electrical connections between components of the device package 301. In some embodiments, the second underfill layer 338 may be a thermally conductive material, such as a polymer or epoxy containing one or more thermally conductive additives, such as silver and / or graphite.

[0040] FIG. 4A is a schematic isometric view of an integrated cooling assembly 403 that reduces heat dissipation from high heat flux regions, or hot spot regions 408, of a device 304 compared to heat dissipation from adjacent regions. FIG. 4B is a schematic cross-sectional side view (taken along line B-B′ in FIG. 4A ) of the integrated cooling assembly 403 showing an embedded thermoelectric cooler, in this case a TEC 404, deposited over the device hot spot 408. FIG. 4C is an enlarged view of the TEC 404. Typically, the integrated cooling assembly 403 includes one or more TECs 404, each disposed within a corresponding cavity formed in a cold plate 406. Generally, each TEC 404 includes alternating n-type and p-type semiconductor pillars 410 and 412, which are electrically connected in series by a plurality of conductive plates 414. Each TEC 404 is coupled to a DC power source 416 such that when current flows therethrough, heat is transferred from a first side of the TEC 404 adjacent the hot spot region 408 to a second side of the TEC 404 adjacent the cold plate 406. Each TEC 404 may be secured to one or both of the device 304 and the cold plate 406 using direct bonding techniques described below.

[0041] In this case, power is delivered to the TEC 404 using metal interconnects and / or vias formed in, on, or through the device 304, such as the illustrated through-substrate vias (TSVs) 418. In some embodiments, power may be delivered to the TEC 404 using conductive features formed in or between the interfaces of the device 304 and the cold plate 406. In some embodiments, power may be delivered to the TEC 404 through conductive features, such as metal interconnects and vias formed in and / or through the cold plate 406.

[0042] In some embodiments, the number (component count) of protruding features, density, size, and / or shape of the protruding features 324 extending upward from the base surface 309 in the region above the TEC 404 is different than the surrounding regions of the base surface 309. For example, as shown in Figures 4A and 4B, the surface region 409 above the TEC 404 has fewer or no protrusions compared to adjacent regions of the base surface 309, which can increase the volumetric flow rate of coolant over and along the region 409, thereby increasing the relative heat transfer from the region 409.

[0043] 5 is a schematic side cross-sectional view of an example multi-component device package 501 having a cold plate 506 directly bonded to the backside surface of two or more devices. As shown, the device package 501 includes a package substrate 502, an interposer facilitating communication between, for example, device 304 and a device stack 604, an integrated cooling assembly 503, a package cover 308, and an adhesive layer 322. The integrated cooling assembly 503 may include multiple devices, which may be singulated, for example, device 304 and / or multiple devices, which may be arranged in a vertical device stack 504, and a cold plate 306 bonded to each of the device 304 and device stack 504. In some embodiments, the device 304 may comprise a processor, and the device stack 504 may comprise multiple memory devices. As shown, the device 304 and device stack 504 are arranged in a side-by-side array on the package substrate 302 and are electrically connected to the package substrate 302 using any suitable method. Cold plate 506 is attached to and directly bonded to the backside of device 304 and the backside of the topmost device in stack 504. In this case, cold plate 506 is sized to provide a bonding surface that can be attached to both device 304 and stack 504, but may otherwise be identical or substantially identical to other cold plates described herein. For example, cold plate 506 may include any one or combination of the features of the cold plates described in connection with other figures herein. In some embodiments, integrated cooling assembly 503 may include one or more TECs 404 ( FIG. 4B ) embedded between cold plate 506 and first device 904A and / or between cold plate 506 and device stack 504.

[0044] FIG. 6 is a schematic cross-sectional side view of an example multi-component device package 501, including an integrated cooling assembly 304 and a device stack 604, with heat transferred from the device stack 604 to the integrated cooling assembly 303 via a package cover 608. In this case, the device package 601 includes a package substrate 502, an integrated cooling assembly 303, one or more second devices (shown as device stack 604), and a package cover 608. Typically, the integrated cooling assembly 303 is bonded to the package cover 608 using an adhesive layer 322, thereby forming coolant channels 310 therebetween. The device stack 604 may be disposed on the package substrate 502 in a side-by-side arrangement within the device 304. As discussed above, heat generated by the device 304 is dissipated to a coolant, which circulates through the coolant channels, in this case, coolant channels 310, via inlet / outlet openings 312 formed through the package cover 608. The package cover 608 may be formed of a thermally conductive material, and the package cover functions as a thermal spreader. Heat generated by the device stack 604 is dissipated to a coolant through the package cover 608, which is thermally coupled to the device stack 604 through the use of a TIM layer 616. Advantageously, the cold plate 306 blocks the thermal path between the device 304 and the device stack 604 to prevent heat from transferring between the device 304 and the device stack 604. Thus, the device package 601 may be advantageously used to accommodate closely spaced devices on the interposer, such as high-power devices or memory stacks, while reducing latency and eliminating undesirable heat transfer between them.

[0045] In some embodiments, the device package 601 further includes a heat sink 608A disposed on a portion of the package cover 601 above the device stack 604. The heat sink 608A may be thermally coupled to the package cover 608 through the use of a TIM layer (not shown) or by direct bonding using methods described herein. In some embodiments, the device package 601 includes one or more TECs 404 and / or a second underfill layer 338, as described above.

[0046] 7A is a schematic cross-sectional side view of a device package 701 with an additional adhesive layer 322 applied between the package cover 308 and the inner surface 715 of the cold plate 706, and FIG. 7B is a schematic cross-sectional exploded isometric view of the integrated cooling assembly 703 and adhesive layer 722. As major components, the device package 701 includes a package substrate 302, an integrated cooling assembly 703, and a package cover 308. The integrated cooling assembly 703 includes a device 304 and a cold plate 706 directly bonded to the device 304 using an adhesive layer 722, and the adhesive layer 322 includes a first portion 722A provided on the periphery 313 and a second portion 722B provided on the inner surface 715 (the surface of the cold plate 706 located inward from the periphery 313). In this case, the first portion 722A forms an airtight seal between the cold plate 706 and the package cover 308 to define the perimeter of the coolant channel 710 between the cold plate 706 and the package cover 308. The second portion 722B attaches the inner surface 715 to a corresponding portion of the package cover 308 disposed thereon. The inner surface 715 may be disposed on a protrusion (as shown) extending upward from the base surface 309, or may constitute regions of the base surface 309. The additional attachment location provided by the second portion 722B substantially reduces or eliminates distortion of the package cover 308 due to the circulation of high-pressure coolant through the coolant channel 710. Thus, the additional attachment location can increase coolant flow rate, thereby increasing cooling efficiency. As envisioned, the additional attachment location provided by the second portion 722B of the adhesive layer 722 can be used with any of the device packages described herein.

[0047] 8A is a schematic cross-sectional side view of device package 801, with integrated cooling assembly 803 partially protruding into the underside of package cover 808 to provide additional structural support. FIG. 8B is a schematic exploded isometric view of integrated cooling assembly 803. As shown, integrated cooling assembly 803 includes device 304 and cold plate 806 directly bonded to device 304. Cold plate 806 includes multiple plates that are patterned and directly bonded to one another, shown in this case as first plate 812 and second plate 814 directly bonded to second plate 812. First plate 812 may be substantially similar to cold plates 306, 406, 506 described above, or may comprise any combination of the features of these cold plates. In this case, first plate 812 has base surface 309, protruding features 329, sidewalls 311, and perimeter surface 313 as described above in connection with cold plate 306. Second plate 814 has a plurality of sidewalls 311 aligned with and bonded to the sidewalls 311 of first plate 812. Blind openings formed in and / or protrusions extending downwardly from the inner surface of package cover 808 form well regions sized and shaped to receive upper portions of sidewalls 811. In some embodiments, sidewalls 311 form a rectangular annulus (as viewed in the Z direction), and well region 820 has a correspondingly shaped rectangular annulus.

[0048] In this case, integrated cooling assembly 803 may be attached to package cover 808 by adhesive layer 822 disposed in well region 820. Adhesive layer 822 forms an airtight seal between cold plate 806 and package cover 808 and surrounds an upper portion of sidewall 811 to define the perimeter of coolant channel 810. In some embodiments, adhesive layer 822 is formed from a compliant adhesive that, when compressed between package cover 808 and cold plate 806, forms an impermeable seal around the perimeter of coolant channel 810.

[0049] In some embodiments, the second plate 814 has one or more inner supports 815 (one shown) connecting the opposing sidewalls 811A and spaced apart from each of the sidewalls 811B. In such embodiments, a portion of the well region 820 may be sized and shaped to receive an upper portion of the inner support 815. The inner support 815 provides structural support for the second plate 814 and further secures the package cover 808 to the integral cooling assembly 803 during use. The additional attachment points provided by the inner supports 815 substantially reduce or eliminate distortion of the package cover 808 due to high-pressure coolant circulating through the coolant channels 810. Thus, the additional attachment points increase coolant flow rate and correspondingly increase cooling efficiency. As envisioned, device package features, such as the cold plate 806 and package cover 808 described above, may be advantageously used in combination with any other features of the device packages described herein.

[0050] 9 is a schematic cross-sectional side view of a device package 901 in which one or more cold plates 906 are positioned to partially cool a 3DIC device 904. The device package 901 includes, as its main components, an integrated cooling assembly 903 mounted on and electrically connected to a package substrate 302, and a package 908 mounted over the integrated cooling assembly 903. The integrated cooling assembly 903 includes a 3DIC device 904 including a first device 904A and one or more second devices 904B (one shown), and one or more cold plates 906. In this case, the first device 904A is mounted facing the package substrate 302, i.e., active side down, and the second device 904B is mounted on and bonded to a portion of the back side of the first device 904A. The first device 904A has multiple interconnects, such as through-substrate vias (TSVs) 918, formed between its active side and its rear side. In such an embodiment, the first device 904A and the second device 904B may be interconnected using the TSVs 918 and hybrid bonds formed between the active side of the second device 904B and the rear side of the first device 904A. In some embodiments, one or more second devices or device stacks 604 are directly bonded to and interconnected with the first device 904A using direct hybrid bonds.

[0051] In this case, a first device 904A is cooled using one or more cold plates 906 (two shown) disposed on and bonded to a backside of the first device 904A in a juxtaposed arrangement with a second device 904B. Each of the one or more cold plates 906 is attached to a package cover 908 using an adhesive layer 822, which forms an airtight seal between the periphery of the cold plate 906 and the package cover 908, thereby at least partially defining a coolant channel therebetween. Heat generated by the first device 904A is dissipated from the device package by coolant flowing through coolant channels 910 disposed thereon. In some embodiments, the second device 904B is thermally coupled to the package cover 908 using a TIM layer 616. In such an embodiment, the package cover 908 can function as a heat spreader, such that heat generated by the second device 904B is transferred to the coolant in the coolant channels 910 via a heat transfer path that includes the TIM layer 616 and the package cover 908.

[0052] FIG. 10A is a schematic side cross-sectional view of a device package 1001, in which a coolant channel 1010 is provided between a first HI device 1004A and a second HI device 1004B of an integrated cooling assembly 1003. FIG. 10B is a schematic cross-sectional view of the integrated cooling assembly 1003 taken along line CC' in FIG. 10A. In this case, the device package 1001A includes a package substrate 302, an integrated cooling assembly 1003 provided on the package substrate 302, and an optional package cover 1008 provided over the integrated cooling assembly 1003. The integrated cooling assembly 1003 forms a fluid chamber with the heterogeneous integration (HI) device 1004A, the second HI device 1004B, and a cold plate in the form of a frame, in this case a cold frame 1006 provided between the first HI device 1004A and the second HI device 1004B.

[0053] As a main component, the first HI device 1004A and / or the second HI device 1004B may include multiple heterogeneous integrated circuits connected to each other by hybrid bonding to form a heterogeneous integration. For example, the first HI device 1004A may include an interposer 1005A and multiple semiconductor devices 1007A (and / or device stacks) arranged in a side-by-side arrangement on the interposer 1005A. In this case, the semiconductor devices 1007A are interconnected via the interposer 1005A using hybrid bonds formed therebetween. The second device 1004B is a 3DIC integration including a base die 1005B and one or more second devices 1007B bonded to the base die 1005B, for example, by hybrid bonds, and a chiplet. In other embodiments, both devices are 2.5DIC or 3DIC integrated, or the relative portions of the first HI device 1004A and the second HI device 1004B can be swapped. In some embodiments, the interposer 1005A and / or the base die 1005B have a plurality of conductive features (not shown), such as bond pads, formed within their periphery.

[0054] The cold frame 1006 primarily includes sidewalls that form a polygonal annulus, e.g., a rectangular annulus, when viewed in the Z direction. In some embodiments, the cold frame 1006 may further include a plurality of vias 1018 (FIG. 10B) in the sidewalls that extend (in the Z direction) between opposite surfaces of the plate. The cold frame 1006 is aligned with and bonded to the periphery of the interposer and / or die 1005A, 1005B using hybrid bonding. As shown, the devices 1004A, 1004B and the bonded cold frame 1006 together form a coolant channel 1010, and the back surfaces of the devices 1007A, 1007B are disposed within the coolant channel 1010. A coolant fluid circulates through the coolant channels 1010 via inlet / outlet openings 1022 formed through opposing sidewalls of the cold frame 1006. In some embodiments, the device package 1001A may include a package cover 1008 disposed over the integrated cooling assembly 1003 and an adhesive or molding material 1038 disposed between the package cover 1008 and the integrated cooling assembly. In such embodiments, the coolant fluid may be delivered to the channels 1010 via the inlet / outlet openings 1012, openings formed in the molding material 1038, and openings 1022 formed through the plate sidewalls, each of which is aligned with or in fluid communication with one another.

[0055] In device package 1001A, integrated cooling assembly 1003 is disposed on package substrate 302 and is electrically connected by, for example, conductive bumps 319 disposed between the package substrate and interposer 1005A. A second device 1004B is in electrical communication with the package substrate through vias 1018 and hybrid bonds formed between interposer 1005A, cold frame 1006, and base die 1005B.

[0056] 10C is a schematic cross-sectional side view of a device package 1011, with coolant channels 1010 provided between a first HI device 1004A and a second HI device 1004B of an integrated cooling assembly 1003, the first HI device 1004A electrically connected to the first package substrate 302A, and the second HI device 1004B electrically connected to the second package substrate 302B. In such an embodiment, the device package 1011 may be provided between and connected to opposing PCBs (not shown).

[0057] FIG. 11 illustrates a method 1100 that can be used to fabricate the device packages described herein. FIG. 12 illustrates a device package 301 at different stages in the manufacturing process to illustrate aspects of the method 1100. At least some of the features of the device package 301 described below can be found with reference to FIG. 3 . However, it is contemplated that the method 1100 can be used to fabricate any of the device packages described herein. In block 1102, the method 1100 includes aligning a first substrate 1202 with a second substrate 1204, the first substrate 1202 having a plurality of die, e.g., devices 304, to be singulated, and the second substrate 1204 having a plurality of cold plates 306 to be singulated. The cold plates 306 may be formed from one or more base plates 924A, 924B (two are shown) according to any of the embodiments described above with reference to FIGS. 4-7. As shown, a first substrate 1202 has a plurality of devices 304 arranged in a rectangular array and spaced apart from one another by a plurality of scribe lines 1206 extending in the X and Y directions to form a grid pattern.

[0058] The first substrate 1202 may comprise a bulk material and multiple material layers disposed on the bulk material. The bulk material may include any semiconductor material suitable for fabricating semiconductor devices, such as silicon, silicon germanium, germanium, III-V semiconductor materials, II-VI semiconductor materials, or combinations thereof. For example, in some embodiments, the first substrate 1202 may comprise a monocrystalline wafer, such as a silicon wafer, multiple device components formed in or on the silicon wafer, and multiple interconnect layers formed on the multiple device components. In other embodiments, the substrate may include a reconstituted substrate, such as a substrate formed from multiple singulated devices embedded in a support material.

[0059] The bulk material of the first substrate 1202 may be thinned after the devices 304 are formed using one or more backgrinding, etching, and polishing operations to remove material from the backside. The first substrate 1202 may be thinned using a combination of polishing and etching processes to reduce the thickness (as viewed in the Z direction) to about 450 nm or less, e.g., about 301 nm or less, or about 150 nm or less. After thinning, the backside may be polished to a desired smoothness using a chemical mechanical polishing (CMP) process, and a dielectric layer may be deposited thereon. In some embodiments, the dielectric layer may be polished to a desired smoothness to prepare the substrate 1202 for a bonding process. In some embodiments, the method 1100 includes forming a plurality of metal features in the dielectric layer in preparation for a hybrid bonding process, for example, by using a damascene process.

[0060] In some embodiments, the active side is temporarily bonded to a carrier substrate (not shown) before or after the thinning process. In use, the carrier substrate provides support for the thinning operation and / or the thinned material to facilitate substrate handling during one or more of the following manufacturing operations described herein. In some embodiments, the second substrate 1204 is formed of multiple substrates (not shown), each of which is comprised of a single bulk material patterned to form multiple plates, e.g., first and second plates 806A, 806B, of the integrated cooling assembly 803 of FIG. 8B . Each of the multiple substrates may be of substantially the same size and shape as the first substrate 1202 in a top-down view (viewed in the Z direction), such that the interface surfaces are substantially coextensive with one another. In some embodiments, each of the substrates has a thickness (viewed in the Z direction) of about 0.5 mm to about 10 mm, about 1 mm to about 8 mm, about 1 mm to 6 mm, for example, about 0.5 mm or more, for example, about 1 mm or more, about 2 mm or more, about 10 mm or less, for example, about 8 mm or less, or about 6 mm or less.

[0061] In some embodiments, the second substrate 1204 is formed of a bulk material having substantially the same coefficient of linear thermal expansion (CTE) as the bulk material of the first substrate 1202, where CTE is the fractional change in length of the material per degree change measured over a desired temperature range. In some embodiments, the CTEs of the first and second substrates are matched such that the CTE of the second substrate 1204 is within about ±20% or less of the CTE of the first substrate 1202, e.g., within ±15% or less, within ±10% or less, or within about ±5% or less. In some embodiments, the CTEs are matched throughout a temperature range of about −60° C. to about 200° C., or about 60° C. to about 175° C. In one exemplary embodiment, the materials whose CTEs are matched each comprise silicon. For example, the bulk material of the first substrate 1202 may include monocrystalline silicon, and the bulk material of the second substrate 1204 may include monocrystalline silicon or may include polycrystalline silicon. In some embodiments, the method 1100 includes forming a dielectric layer, and optionally a plurality of metal features, on a bottom surface of the second substrate 1204.

[0062] At block 1104, the method 1100 includes direct bonding a plurality of cold plates 306 formed in the second substrate 1204 to a plurality of devices 304 in the first substrate 1202. As described above, the bonding surfaces may each comprise a dielectric layer, and direct bonding the first substrate 1202 and the second substrate 1204 includes forming a dielectric bond between the first dielectric layer 334A and the second dielectric layer 334B. Optionally, the first substrate 1202 and the second substrate 1204 may be direct bonded using a hybrid of dielectric and metallic bonds formed between metallic features.

[0063] Generally, direct bonding surfaces (surfaces of dielectric layers) involves pre-treating, aligning, and contacting the surfaces. Pre-treating the surfaces may include smoothing each surface to a wear surface roughness, e.g., 0.1-3.0 nm RMS, activating the surfaces to weaken or open chemical bonds in the dielectric, and terminating the surfaces with desired chemical species. Smoothing the surfaces may include polishing the substrates 1202, 1204 using a chemical mechanical polishing (CMP) process. Activating the surfaces and terminating them with desired chemical species may include exposing the surfaces to radical species formed in a plasma.

[0064] In some embodiments, a nitrogen-containing gas, such as N2, is used to form the plasma, and the terminating species include nitrogen and hydrogen. In some embodiments, a wet cleaning process may be used to activate the surfaces, for example, by exposing the surfaces to an aqueous ammonia solution. In some embodiments, a dielectric bond may be formed using a dielectric layer deposited on only one of the substrates 1202, 1204, but not both. In such embodiments, a direct dielectric bond may be formed by contacting a deposited dielectric layer of one substrate with a bulk material surface, such as a bulk semiconductor or polysilicon material surface, of the other substrate. In such embodiments, the bulk material surface may have a thin layer of native oxide or may be cleaned to be substantially free of native oxide prior to contact.

[0065] Forming a direct dielectric bond between the substrates at block 1104 involves directly contacting the pre-treated and aligned surfaces with each other at temperatures below 150°C, e.g., below 100°C, e.g., below 30°C, or at about room temperature, e.g., 20°C to 30°C. Without being bound by theory, it is believed that the hydrogen-terminated species diffuse from the bonding surface as an interface, and chemical bonds are formed between the remaining nitrogen species during the direct bonding process. In some embodiments, the direct bond is strengthened using an annealing process in which the substrates are heated to and maintained at a temperature of about 30°C or more and about 450°C or less, e.g., about 50°C or more and about 250°C or less, or about 150°C, for a duration of about 5 minutes or more, e.g., about 15 minutes. Typically, the bond will strengthen over time without the application of heat. Thus, in some embodiments, the method does not include heating the substrates.

[0066] In embodiments in which the substrates are bonded using a hybrid dielectric-metal bond, the method may further include planarizing or recessing the metal features below the field plane before contacting and bonding to the dielectric layer. After forming the dielectric bond, the substrates 1202, 1204 may be heated to a temperature of 150°C or greater and maintained at this elevated temperature for a duration of about 1 hour or greater, e.g., 8-24 hours, thereby forming a direct metallurgical bond between the metal features. Suitable direct dielectric-hybrid bonding technologies that can be used to practice aspects of the methods described herein include ZiBond® and DBI®, each of which is commercially available from Adeia Holding Corp., San Jose, California, USA.

[0067] At block 1106, the method 1100 includes singulating the plurality of integrated cooling assemblies 303 from the bonded substrate. Singulation after bonding imposes distinct structural properties on the integrated cooling assemblies 303 because the bonding surface of each cold plate 306 has the same perimeter as the backside of the device 304 bonded thereto. Thus, the sidewalls of the cold plate 306 are typically flush with the edges of the device 304 along their common perimeter. In some embodiments, the cold plates 306 are singulated from the second substrate 1204 using a process that cuts or separates the second substrate 1204 in a vertical plane, i.e., parallel to the Z-direction. In such embodiments, the sides of the cold plate 306 are substantially perpendicular to the backside of the device, i.e., the horizontal (X-Y) plane of the mounting interface between the device 304 and the cold plate 306. In some embodiments, a saw or laser dicing process is used to singulate the cold plate 306 .

[0068] At block 1108, the method includes coupling the integrated cooling assembly to the package substrate 302 and attaching the package cover 308 to the integrated cooling assembly 303 with an adhesive layer 322. In some embodiments, the method further includes at least partially encapsulating the integrated cooling assembly 303 with a second underfill layer 338.

[0069] The above-described method advantageously provides an embedded cold plate that eliminates and / or substantially reduces the thermal resistance path typically associated with cooling systems mounted externally to the device package. The cold plate may be attached to the semiconductor device using direct dielectric or direct hybrid dielectric-metal bonding methods. Such bonding methods may enable a relatively low thermal budget while substantially increasing bond strength compared to conventional silicon-to-silicon bonding methods, such as thermocompression bonding.

[0070] The cold plate and semiconductor device may be made of materials with matched CTEs, thereby eliminating the need for an intervening TIM layer. The cold plate and package cover may be formed of materials with mismatched CTEs and may be attached to one another using a compliant adhesive. The compliant adhesive accommodates the difference in linear expansion between the package cover and cold plate during repeated thermal cycling, thereby extending the useful life of the device package.

[0071] FIGS. 13, 14, and 15A and 15B illustrate the use of TEC devices, such as those described above with reference to FIGS. 4A-4C, in a bonded device stack. FIG. 13 is a cross-sectional view of a device stack having a first chip 1301, in this case active devices, and a second chip 1302 attached to the first chip 1301. The second chip 1302 may contain active or passive devices. The first chip 1301 and the second chip 1302 are directly bonded to each other without an intervening adhesive. In some embodiments, the first chip and the second chip are hybrid bonded to each other via direct bonds formed between metal features 1303 and the surrounding dielectric surface. The chips may be bonded active-side to active-side, active-side to passive or back-side, or passive or back-side to passive or back-side. As shown, the second chip 1302 has a TEC device 404 disposed within its active or backside surface. The TEC device may be disposed within an opening formed in the second chip 1302 or may be integrally formed therewith. In this case, the TEC device 404 is positioned such that heat is transferred vertically from the first side 420 to the second side 422 of the TEC, such that heat is transferred from the first chip 1301 to the second chip 1302.

[0072] Figure 14 is a cross-sectional view of a device stack having any of the features of Figure 13. In this case, TEC 1404, having any of the features of TEC 404, is arranged so that heat is transferred laterally from first side 420 to second side 422, or vice versa. In this case, each chip has at least one of n-type or p-type semiconductor pillars embedded or formed within their surface.

[0073] Figure 15 is a cross-sectional view of a device stack having any of the features of Figures 13 and 14, where n-type pillars 410 and p-type pillars 412 (shown in plan view in Figure 15) alternate across the surface of either a first chip 1501 or a second chip 1502. As shown in Figure 15, heat is transferred laterally from a first side 420 to a second side 422 of the TEC.

[0074] FIG. 16 is a cross-sectional view of a 2.5DIC or 3DIC device including a first chip 1601 and a TEC-equipped chip 1602 mounted in a side-by-side arrangement on a second chip 1604 (or package substrate, interposer, redistribution layer, or package substrate). Each TEC device is positioned to transfer heat to the surface of the second chip 1604 to which it is attached (or hybrid-bonded). Heat from the first chip 1601 can be dissipated through the TEC device 1602 via the second chip 1604 and / or through a heat sink 1608 (or heat spreader, heat pipe, or silicon dummy spreader) attached or directly bonded to the first chip. In some embodiments, the TEC device has a single chip enclosing the first chip, viewed from top to bottom. In some embodiments, the TEC chip is thermally coupled to the heat sink 1608 via a thermally conductive material 1606 disposed therebetween. In some embodiments, the first chip is a device stack, such as any one of the device stacks shown in Figures 13, 14, and 15A and 15B. As contemplated, any of the chips or devices described in Figures 13-16 may be active devices, passive dies, and / or reconfigurable dies. It is further contemplated that the device stacks of Figures 13-16 may be used in combination with any of the device package features described above.

[0075] The above embodiment sections are illustrative and not limiting of the present invention. Those skilled in the art will recognize that individual aspects of the cooling assemblies, device packages, and methods described herein may be omitted, modified, combined, and / or rearranged without departing from the scope of the present invention. The scope of protection of the present invention is defined solely by the following claims.

Claims

1. A device, a first chip; a second chip hybrid-bonded to the first chip; a thermoelectric cooler (TEC) disposed within the bonding surface of the first chip.

2. The device of claim 1 , wherein the TEC is located adjacent to a hot spot region of the second chip.

3. The device of claim 1 , wherein the TEC is powered via an interconnect provided through the first chip or the second chip.

4. The device of claim 1 , wherein the TEC transfers heat vertically from the second chip to the first chip.

5. A device, a first chip; a second chip hybrid-bonded to the first chip; a thermoelectric cooler (TEC) disposed between the first chip and the second chip, a first portion of the TEC disposed within or below a bonding surface of the first chip, and a second portion of the TEC disposed within or below a bonding surface of the second chip.

6. The device of claim 5 , wherein the TEC dissipates heat laterally from a first side of the TEC to a second side of the TEC.

7. A device, a first chip; a second chip hybrid-bonded to the first chip; a thermoelectric cooler (TEC) disposed within or below the bonding surface of the second chip, the TEC having alternating n-type and p-type semiconductor pillars positioned parallel to the bonding surface of the second chip.

8. The device of claim 7 , wherein the TEC dissipates heat laterally from a first side of the TEC to a second side of the TEC.

9. A 3DIC device, comprising: a first chip; a second chip hybrid-bonded to the first chip; A 3DIC device having one or more TEC devices hybrid bonded to the first chip and disposed in a side-by-side arrangement with the second chip.

10. The 3DIC device of claim 9 , wherein the one or more TEC devices laterally surround the first chip to form a frame around the second chip in a top-down view.

11. The 3DIC device of claim 9 further comprising a heat sink, said heat sink attached to a side of said second chip opposite said heat sink.

12. The 3DIC device of claim 11 , wherein the TEC device is thermally coupled to the heat sink via a thermal interface material disposed between the TEC device and the heat sink.

13. The 3DIC device of claim 9 , wherein the first chip comprises an active device, a passive device, a reconfigurable device, an interposer, a redistribution layer, or a package substrate.

14. The 3DIC device of claim 9 , wherein the one or more TEC devices each comprise a TEC disposed within a reconfigurable substrate.

15. The 3DIC device of claim 9, wherein the second chip comprises a device stack.

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