Photonic Programmable Interconnect Configuration

Abstract

Described herein are techniques for intra-chip communication within tiled photonic interposers. The photonic interposers may rely on a combination of optical and electrical lanes. For example, the photonic interposer may comprise a photonic integrated circuit (PIC) lithographically patterned with an array of photonic tiles, each photonic tile comprising an on-chip communication unit. The array of photonic tiles is arranged in rows and columns. Multiple electrical lanes arrange the on-chip communication units of the photonic tiles in different rows to electrically communicate with each other. Multiple optical lanes arrange the on-chip communication units of the photonic tiles in different columns to optically communicate with each other.

Description

[Background technology]

[0001] Computer systems include random access memory (RAM) for storing data and machine code. RAM is typically volatile memory, meaning that stored information is lost when power is removed. In modern implementations, the memory takes the form of integrated circuits. Each integrated circuit includes multiple memory cells. To allow access to the stored data and machine code, the memory is placed in electrical communication with the processor. Typically, these electrical communications are implemented as metal traces formed on a substrate on which the memory and processor reside. Summary of the Invention

[0002] Some embodiments relate to a photonic interposer, comprising a lithographically patterned optical integrated circuit (PIC) comprising an array of photonic tiles, each photonic tile comprising an on-chip communication unit, the array of photonic tiles being arranged in rows and columns; a plurality of electrical lanes arranging the on-chip communication units of photonic tiles in different rows to communicate electrically with each other; and a plurality of optical lanes arranging the on-chip communication units of photonic tiles in different columns to communicate optically with each other.

[0003] In some embodiments, the array comprises a first row of photonic tiles and a second row of photonic tiles adjacent to the first row, wherein the photonic tiles in the first row are of a first type and the photonic tiles in the second row are of a second type different from the first type.

[0004] In some embodiments, the second type of photonic tile is a mirror image of the first type of photonic tile. In some embodiments, the electrical lanes do not intersect the mid-plane of the photonic tiles in either the first row or the second row.

[0005] In some embodiments, the array comprises a first row of photonic tiles and a second row of photonic tiles adjacent to the first row, the photonic tiles in the first row being of the same type as the photonic tiles in the second row.

[0006] In some embodiments, the electrical lanes intersect the mid-plane of each of the photonic tiles in the first row. In some embodiments, the photonic interposer further comprises an analog repeater coupled to the electrical lanes and configured to transmit electrical signals across boundaries of adjacent tiles.

[0007] In some embodiments, each photonic tile of the PIC includes a plurality of photonic nodes optically coupled to the plurality of optical lanes, each photonic node including a controllable optical switch configured to selectively couple photonic tiles in the same row to each other.

[0008] In some embodiments, each photonic node further comprises a transceiver configured to perform electrical-to-optical conversion. In some embodiments, the photonic interposer further comprises a plurality of electronic dies disposed on the PIC, each electronic die coupled to a respective photonic tile in the array, and the electrical lanes and the optical lanes enabling communication between the plurality of dies.

[0009] In some embodiments, each photonic tile comprises a fiber coupler configured to connect to a respective optical fiber. Some embodiments relate to a photonic interposer comprising a lithographically patterned optical integrated circuit comprising an array of photonic tiles, each photonic tile comprising an on-chip communication unit, the array of photonic tiles being arranged in rows and columns; and a controller configured to control the on-chip communication units of the photonic tiles to electrically perform inter-tile communication between adjacent rows of the array, and to optically perform inter-tile communication between adjacent columns of the array.

[0010] Controlling the on-chip communication unit includes transferring data from source photonic tiles arranged in a first row and a first column to destination photonic tiles arranged in a second row and a second column, and transferring the data includes using the data to drive optical lanes coupling the source photonic tiles to intermediate photonic tiles arranged in the first row and the second column, and using the data to drive electrical lanes coupling the intermediate photonic tiles to the destination photonic tiles.

[0011] In some embodiments, forwarding the data further comprises performing optical-to-electrical conversion on the data at the intermediate photonic module. In some embodiments, controlling the on-chip communication unit includes transferring data from source photonic tiles arranged in a first row and a first column to destination photonic tiles arranged in a second row and a second column, and transferring the data includes using the data to drive optical lanes coupling the source photonic tiles to intermediate photonic tiles arranged in the second row and the first column, and using the data to drive optical lanes coupling the intermediate photonic tiles to the destination photonic tiles.

[0012] In some embodiments, controlling the on-chip communication unit includes transferring data from a first electronics die coupled to a first photonic tile to a second electronics die coupled to a second photonic tile.

[0013] In some embodiments, controlling the on-chip communication unit includes performing a memory read operation between a processor die coupled to the source photonic tile and a memory die coupled to the destination photonic tile.

[0014] Some embodiments relate to a method of controlling an optical integrated circuit comprising an array of photonic tiles, the array of photonic tiles arranged in rows and columns, the method including transferring data from a source photonic tile of the array arranged in a first row and a first column to a destination photonic tile of the array arranged in a second row and a second column, the transferring of data including using the data to drive optical lanes coupling the source photonic tile to an intermediate photonic tile of the array arranged in the first row and the second column, and using the data to drive electrical lanes coupling the intermediate photonic tile to the destination photonic tile.

[0015] In some embodiments, forwarding the data further comprises performing optical-to-electrical conversion on the data at the intermediate photonic module. In some embodiments, transferring the data enables a memory read operation between a processor die coupled to the source photonic tile and a memory die coupled to the destination photonic tile.

[0016] Various aspects and embodiments of the present application are described with reference to the following drawings. It should be appreciated that the drawings are not necessarily drawn to scale. Items that appear in more than one drawing are designated with the same reference numeral in the drawings in which they appear. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a perspective view illustrating a photonic interposer supporting multiple electronics dies, according to some embodiments. [Figure 2] FIG. 1 is a side view illustrating a photonic interposer supporting multiple electronics dies, according to some embodiments. [Figure 3] 1 illustrates a top view of a photonic interposer having multiple optical lanes and multiple electrical lanes, according to some embodiments. [Figure 4] 1 illustrates a top view of an example photonic tile, according to some embodiments. [Figure 5] FIG. 1B illustrates a top view of a photonic interposer patterned with eight photonic tiles of the same type, according to some embodiments. [Figure 6A] 1 is a circuit diagram illustrating a single-ended analog repeater according to some embodiments. [Figure 6B] 1 is a circuit diagram illustrating a differential analog repeater according to some embodiments. [Figure 7] 1A illustrates a top view of a photonic interposer patterned with four photonic tiles of a first type and four photonic tiles of a second type, according to some embodiments. [Figure 8] 1A and 1B are top views illustrating a photonic interposer that supports communication between multiple photonic tiles arranged diagonally relative to one another, according to some embodiments. [Figure 9] FIG. 10 is a top view illustrating another photonic interposer patterned with four photonic tiles of a first type and four photonic tiles of a second type, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0018] I. Overview Described herein is a technology for intra-chip communication within a tiled photonic interposer. The tiled photonic interposer is tiled in that it enables low-power, high-bandwidth communication and uses "photonic tiles" (also referred to herein as "photonic modules" or simply "tiles"). Each tile contains photonic circuitry that can be programmed based on the needs of a particular computer architecture. Essentially, each tile can function as a communication node within a computing system. Within each node may be one or more digital processor chips, one or more analog accelerators, one or more photonic accelerators, one or more memory chips, and one or more networking chips or other devices.

[0019] The present inventors have recognized and understood the challenges that limit the scalability of photonic interposers. While photonic interposers arranged in a one-dimensional manner (e.g., in 3x1 tile blocks, 5x1 tile blocks, 10x1 tile blocks, etc.) may be sufficient for some specific applications, arranging interposers in a two-dimensional manner (e.g., in 3x3 tile blocks, 5x3 tile blocks, 5x6 tile blocks, etc.) enables computer architectures that are not feasible in a one-dimensional manner, such as 2D hypertoroid architectures. However, the ability to deliver data in two dimensions in the optical domain is limited by the performance of waveguide intersections. A waveguide intersection is an optical structure that allows two waveguides to cross each other, ideally without affecting the integrity of the optical signal as it passes through the intersection. In practice, waveguide intersections are subject to insertion loss and crosstalk. Insertion loss (which can be considered a loss of optical power) occurs because a portion of the energy carried by an optical mode undergoes scattering generated by the non-uniform geometry of the intersection as it passes through the intersection. As a result, each time an optical signal passes through an intersecting waveguide, its power is reduced. This limits the total number of intersections an optical signal can pass through without incurring significant data loss. Similarly, crosstalk—the process by which some of the energy carried by an optical signal unintentionally couples into intersecting waveguides—can also degrade the performance of photonic networks.

[0020] While significant progress has been made to reduce insertion loss and crosstalk caused by waveguide intersections, some of these solutions require multiple levels of optical waveguides located in different planes of a substrate. For example, a waveguide intersection may include one waveguide located in a lower plane and extending along the x-axis, and another waveguide located in a higher plane and extending along the y-axis. Because the waveguides span different planes (similar to a bridge extending above a road), crosstalk and insertion loss are reduced. Unfortunately, requiring multiple levels of photonic waveguides located in different planes of a substrate presents its own challenges. First, it requires several etchable layers of semiconductor material, increasing manufacturing costs. Second, it requires a structure capable of vertically coupling light from one plane to another, which tends to be quite long and therefore takes up valuable space.

[0021] The inventors have developed a two-dimensional tiled photonic interposer that can deliver data to any location on the interposer without necessarily relying on waveguide intersections (although a small number of waveguide intersections may still be present). Instead, the photonic interposer developed by the inventors and described herein relies on a combination of optical and electrical lanes. Optical lanes transmit data in the optical domain and can include optical waveguides, optical couplers, optical switches, and free-space optical bridges, among other optical components. Electrical lanes, on the other hand, transmit data in the electrical domain via analog signals and can include electronic components such as conductive traces, vias, electronic switches, and analog repeaters.

[0022] In some embodiments, the photonic interposer is designed so that optical lanes extend in one direction and electrical lanes extend in an orthogonal direction. For example, optical lanes can couple tiles in the photonic interposer to other tiles in the same row, while electrical lanes can couple tiles to other tiles in the same column. Note that the names "column" and "row" should not be strictly interpreted to mean that columns always extend vertically (y-axis) and rows always extend horizontally (x-axis); vice versa is also possible. Enabling data traveling in orthogonal directions to use different carriers (optical vs. electrical) addresses the problem described above because it eliminates or at least reduces the reliance on optical crossovers.

[0023] II. Photonic Tile The photonic interposers described herein are engineered to limit manufacturing costs. These platforms can rely on the use of a common photomask set (or at least one common photomask) to fabricate multiple tiles. This approach reduces costs in two ways. First, it eliminates the additional costs incurred in procuring multiple different photomask sets. Second, it allows tiles to be manufactured using standard semiconductor contract manufacturing facilities, which require the use of the same photomask set (or at least one photomask) across an entire wafer. Designing tiles to share at least one photomask allows for the fabrication of multiple tiles on the same semiconductor wafer while leveraging standard, low-cost step-and-repeat manufacturing processes. Thus, in some embodiments, tiles are photolithographically patterned instantiations (shots) of a common template tile that are stitched together in a 1D or 2D arrangement. Some embodiments include two template tiles, such that each tile of the interposer is formed as either an instantiation of the first template tile or an instantiation of the second template tile. Tiles of different templates may, for example, alternate row by row, such that adjacent rows of tiles are of different types. In another example, the same template photonic tile is used throughout the photonic interposer, but tiles in adjacent rows are stamped as mirror image versions of each other. Tiles may be (for example) 24.8 mm x 32 mm in size and can support heterogeneous technologies (e.g., general-purpose processors, GPUs, DRAM / HBM stacks, or custom accelerators).

[0024] 1 illustrates an example of a computing system based on a photonic interposer with nine tiles arranged in three rows and three columns, according to one example. The computing system 10 includes a photonic interposer 20 patterned with nine photonic tiles 22. The photonic interposer 20 is implemented as a photonic integrated circuit (PIC), for example, using silicon photonics.

[0025] The photonic interposer supports one processor die (30) positioned in the center of the photonic interposer 20 and eight memory nodes surrounding the processor die. However, other computer architectures are possible. Some memory nodes include a single memory chip (see, e.g., memory die 32). Other memory nodes include stacked memories that include multiple vertically stacked memory dies (see, e.g., stacked memory 34), thus forming high-bandwidth memory (HBM). The dies are stacked on top of portions of the PIC that define the tiles. The dies can communicate with the underlying tiles electronically (e.g., using through-silicon vias, copper pillars, microbumps, ball grid arrays, or other electrical interconnects) and / or optically (e.g., using grating couplers, prisms, lenses, or other optical couplers).

[0026] As described in further detail below, tiles may be patterned to include possible components such as optical and electrical lanes, on-chip communication units, etc. These units selectively position the die of a particular node to communicate with any other die in the computing system using a combination of electrical and optical lanes depending on the relative positions of the source and destination tiles on the grid. For example, a read operation between a processor die 30 and stacked memory 34 may involve transferring data from the tile supporting the stacked memory 34 (the source tile) to the tile immediately to its right (the middle tile) using optical lanes, and transferring data from the middle tile to the tile supporting the processor die 30 (the destination tile) using electrical lanes.

[0027] 2 is a cross-sectional view of another exemplary photonic interposer. As shown, photonic tiles 22 are photolithographically formed as part of interposer 20. Each tile supports a respective electrical die (although a tile may support more than one die and / or some tiles may be unoccupied). Communication between the electronic dies occurs through the tiles of photonic interposer 20.

[0028] III. Communication Lanes 3 is a schematic top view illustrating a photonic interposer having multiple optical lanes and multiple electrical lanes, according to some embodiments. This example shows a photonic interposer having two rows and four columns of photonic tiles (although any other two-dimensional arrangement is possible). In this example, the rows extend in a direction parallel to the x-axis and the columns extend in a direction parallel to the y-axis. As described above, the tiles are photolithographically patterned onto a common photonic integrated circuit.

[0029] The tiles in the first row (labeled 0, 1, 2, and 3) communicate with each other via optical lanes 110. Similarly, the tiles in the second row (labeled 4, 5, 6, and 7) communicate with each other via another set of optical lanes 110. Photonic nodes 112 represent connection points from tiles to optical lanes. Each photonic node may include, for example, one or more programmable optical switches configured to direct optical signals to desired destinations. In addition, each photonic node may include a photonic transceiver configured to perform data conversion from the optical domain to the electrical domain and vice versa. Optical lanes may include optical waveguides monolithically integrated as part of a tile. Optical communication across the boundaries of adjacent tiles may be supported by continuous, uninterrupted waveguides or by free-space bridges. In some embodiments, there may be hundreds or thousands of optical lanes coupling tiles to each other.

[0030] Tiles in the same column (e.g., tiles 0 and 4) communicate with each other through electrical lanes 120, which may include conductive traces and, optionally, vias to support communication between multiple levels of conductive traces. Electronic nodes 122 represent connection points from tiles to the electrical lanes. Each electronic node may include, for example, analog drivers, analog repeaters, and / or one or more programmable electronic switches configured to direct electrical signals to desired destinations. In some embodiments, there may be hundreds or thousands of electrical lanes coupling tiles together.

[0031] In some embodiments, all tiles of photonic interposer 20 may be of the same type (e.g., all may be photolithographically patterned shots of the same reticle). In other embodiments, different tiles may be of different types. For example, a first row of tiles may be formed as multiple shots of the same template reticle, and a second row of tiles may be formed as multiple shots of the same template reticle, but mirrored (e.g., rotated 180 degrees). As a result, the second row is a mirror image of the first row. Alternatively, the second row of tiles may be formed as multiple shots of a different template reticle.

[0032] Allowing data traveling in orthogonal directions to use different carriers (optical vs. electrical) improves on photonic interposers, where data is carried optically in all directions, in that it eliminates or at least reduces the reliance on optical crossovers, which, as noted above, can limit the performance of an interposer because they introduce insertion loss and crosstalk.

[0033] FIG. 4 illustrates an example of a photonic die according to some embodiments. Photonic tile 22 includes an on-chip communication unit 204 configured to enable communication with other tiles of the PIC and an off-chip communication unit 202 configured to enable communication outside of the PIC. A fiber coupler 200 enables connection to an optical fiber for off-chip communication. In one example, the fiber coupler may be an edge coupler, and thus may be located at the edge of the tile, as shown in FIG. 4. In another example, the fiber coupler may be an out-of-plane coupler (e.g., a grating coupler), obviating the requirement that the coupler be located at the edge of the tile. The fiber coupler is coupled to the off-chip communication unit 202. Both the photonic node 112 and the electronic node 122 shown in FIG. 3 may be part of the on-chip communication unit 204. An optical waveguide 206 (which may form part of the optical lane described in connection with FIG. 3) may extend through (and away from) the on-chip communication unit 204.

[0034] FIG. 5 shows an example of a photonic interposer having eight reticles of the same type as shown in FIG. 4. In this example, because the on-chip communication units are located in the south region of the tiles, the electrical lanes connecting adjacent tiles are relatively long and may cross any mid-plane of the photonic tile (see, e.g., mid-plane 500). Here, the mid-plane represents an imaginary plane extending parallel to the x-axis and z-axis and cutting the tile into two equal halves. In some embodiments, the electrical lanes may be greater than 15 mm, greater than 20 mm, greater than 25 mm, or greater than 30 mm in length. Because these lanes are relatively long, attenuation may be significant. To reduce the negative effects of attenuation, analog repeaters may be used. The analog repeaters may be located at electronic nodes 122 (FIG. 3) and / or distributed along the length of the electrical lanes.

[0035] 6A and 6B are circuit diagrams illustrating examples of analog repeaters. Both repeaters connect a source node (which in this example includes a photodetector and a transimpedance amplifier) ​​to a destination node. The repeaters are distributed along the length of the electrical lane, thereby separating the electrical lane into multiple portions. The repeater in FIG. 6A is single-ended and includes complementary metal-oxide semiconductor (CMOS) inverter blocks. The repeater in FIG. 6B is differential and includes current-mode logic (CML) blocks. Given the nature of CML, the repeater in FIG. 6B can operate at higher frequencies than the repeater in FIG. 6A.

[0036] In the example photonic interposer of FIG. 7, electrical lanes are shortened by arranging tiles of different types in two rows. The top row is the same as the top row in FIG. 5. However, the bottom row is a mirror image of the first row. The second row of tiles is obtained by rotating the reticle 180 degrees. As a result, the on-chip communication units in the top row are located in the south region of the tiles, and the on-chip communication units in the bottom row are located in the north region of the tiles. This shortens the length of the electrical lanes. For example, the electrical lanes may be less than 20 mm, less than 15 mm, less than 10 mm, or less than 5 mm in length. In some embodiments, the electrical lanes do not intersect any midplane of the photonic tiles. Considering the shorter lanes, analog repeaters can be omitted, simplifying the interposer architecture and reducing costs.

[0037] FIG. 8 shows how communication between tiles diagonally arranged from each other (in different rows and columns) can occur in some embodiments. In this example, tile 0 would send data to tile 7. First, data can be transferred from the source photonic tile (tile 0) to the intermediate photonic tile (tile 3) using optical lanes. Then, data can be transferred from the intermediate photonic tile (tile 3) to the destination photonic tile (tile 7) using electrical lanes. At the intermediate tile, the data is converted from optical to electrical. Alternatively, data can first be transferred electrically from the source tile to another intermediate tile, and then optically to the destination tile. In this case, the data is converted from electrical to optical at the intermediate tile.

[0038] Figure 9 shows another example of a photonic interposer with two different types of tiles. Unlike the example of Figure 7, the tiles in the second row are not simply mirror images of the tiles in the first row, but rather are formed from an entirely different template reticle. In other words, the reticles are alternately stitched together row by row.

[0039] IV. Additional Remarks Similarly, as described, some aspects may be embodied as one or more methods. Acts performed as part of a method may be ordered in any suitable manner. Thus, although shown as sequential acts in an exemplary embodiment, embodiments may be constructed in which acts are performed in a different order than described, which may include performing some acts simultaneously.

[0040] It should be understood that all definitions defined and used herein are directed to dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms. As used in the specification and claims herein, the indefinite articles "a" and "an" should be understood to mean "at least one," unless expressly indicated otherwise.

[0041] As used in the specification and claims herein, the term "and / or" should be understood to mean "either or both" of the conjoined elements, i.e., elements that may be present conjunctively or disjunctively.

[0042] As used herein in the specification and claims, the phrase "at least one" in connection with a list of one or more elements should be understood to mean at least one element selected from any one or more of the listed elements, and does not necessarily include at least one of every element specifically listed within the list of elements, nor does it exclude any combination of elements within the list of elements. This definition also allows for the optional presence of elements other than those specifically identified within the list of elements to which the phrase "at least one" refers, whether related to the specifically identified elements or not.

[0043] The terms "approximately" and "about" may be used to mean, in some embodiments, within ±20% of a target value, in some embodiments, within ±10% of a target value, in some embodiments, within ±5% of a target value, and even in some embodiments, within ±2% of a target value. The terms "approximately" and "about" may include the target value.

Claims

1. A photonic interposer, comprising: a lithographically patterned photonic integrated circuit (PIC) comprising an array of photonic tiles, each photonic tile comprising an on-chip communication unit, the array of photonic tiles being arranged in rows and columns; a plurality of electrical lanes that arrange the on-chip communication units of the photonic tiles of different rows in electrical communication with each other; a plurality of optical lanes that arrange the on-chip communication units of the photonic tiles of different rows so as to be in optical communication with each other; A photonic interposer comprising:

2. 2. The photonic interposer of claim 1, wherein the array comprises a first row of photonic tiles and a second row of photonic tiles adjacent to the first row, the photonic tiles in the first row being of a first type and the photonic tiles in the second row being of a second type different from the first type.

3. The photonic interposer of claim 2 , wherein the second type of photonic tiles are mirror images of the first type of photonic tiles.

4. The photonic interposer of claim 2 , wherein the electrical lanes do not intersect the mid-plane of the photonic tiles in either the first row or the second row.

5. 2. The photonic interposer of claim 1, wherein the array comprises a first row of photonic tiles and a second row of photonic tiles adjacent to the first row, the photonic tiles in the first row being of the same type as the photonic tiles in the second row.

6. The photonic interposer of claim 5 , wherein the electrical lanes intersect the mid-plane of each of the photonic tiles in the first row.

7. The photonic interposer of claim 5 , further comprising an analog repeater coupled to the electrical lanes and configured to transmit electrical signals across boundaries of adjacent tiles.

8. 2. The photonic interposer of claim 1, wherein each photonic tile of the PIC includes a plurality of photonic nodes optically coupled to the plurality of optical lanes, and each photonic node includes a controllable optical switch configured to selectively couple photonic tiles in the same row to each other.

9. The photonic interposer of claim 8 , wherein each photonic node further comprises a transceiver configured to perform electrical-to-optical conversion.

10. 10. The photonic interposer of claim 1, further comprising a plurality of electronic dies disposed on the PIC, each electronic die coupled to a respective photonic tile in the array, and the electrical and optical lanes enabling communication between the plurality of dies.

11. The photonic interposer of claim 1 , wherein each photonic tile comprises a fiber coupler configured to connect to a respective optical fiber.

12. A photonic interposer, comprising: a lithographically patterned integrated optical circuit comprising an array of photonic tiles, each photonic tile comprising an on-chip communication unit, the array of photonic tiles being arranged in rows and columns; a controller configured to control the on-chip communication units of the photonic tiles to electrically perform inter-tile communication between adjacent rows of the array, and configured to optically perform inter-tile communication between adjacent columns of the array; A photonic interposer comprising:

13. 13. The photonic interposer of claim 12, wherein controlling the on-chip communication units includes transferring data from source photonic tiles arranged in a first row and a first column to destination photonic tiles arranged in a second row and a second column, and transferring the data includes: using the data to drive optical lanes coupling the source photonic tile to intermediate photonic tiles arranged in the first row and the second column; and using the data to drive electrical lanes coupling the intermediate photonic tile to the destination photonic tile.

14. The photonic interposer of claim 13 , wherein said transferring said data further comprises performing optical-to-electrical conversion on said data at said intermediate photonic module.

15. 14. The photonic interposer of claim 13, wherein controlling the on-chip communication unit includes performing a memory read operation between a processor die coupled to the source photonic tile and a memory die coupled to the destination photonic tile.

16. 13. The photonic interposer of claim 12, wherein controlling the on-chip communication units includes transferring data from source photonic tiles arranged in a first row and a first column to destination photonic tiles arranged in a second row and a second column, and transferring the data includes: using the data to drive electrical lanes coupling the source photonic tile to intermediate photonic tiles disposed in the second row and the first column; and using the data to drive optical lanes coupling the intermediate photonic tile to the destination photonic tile.

17. 13. The photonic interposer of claim 12, wherein controlling the on-chip communication unit includes transferring data from a first electronic die coupled to a first photonic tile to a second electronic die coupled to a second photonic tile.

18. 1. A method of controlling an optical integrated circuit comprising an array of photonic tiles, the array of photonic tiles being arranged in rows and columns, the method comprising: transferring data from source photonic tiles of the array arranged in a first row and a first column to destination photonic tiles of the array arranged in a second row and a second column, wherein said transferring data comprises: using the data to drive optical lanes that couple the source photonic tile to intermediate photonic tiles of the array arranged in the first row and the second column; and using said data to drive electrical lanes coupling said intermediate photonic tile to said destination photonic tile.

19. 20. The method of claim 18, wherein forwarding the data further comprises performing optical-to-electrical conversion on the data at the intermediate photonic module.

20. 20. The method of claim 18, wherein the transferring of data enables a memory read operation between a processor die coupled to the source photonic tile and a memory die coupled to the destination photonic tile.

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