Bidirectional bipolar junction transistor devices from bonded wide and thick wafers.

Abstract

A thin bidirectional bipolar junction transistor (BJT) device and a method for fabricating a thin bidirectional BJT device are provided. The method includes forming a first base region and a first emitter / collector region on a first side of a first thick semiconductor wafer. The method also includes removing a portion of the first thick semiconductor wafer to create a first thin semiconductor wafer. The method further includes forming a second base region and a second emitter / collector region on a second side of the first thin semiconductor wafer opposite the first side. The method also includes fabricating a second thin semiconductor wafer. The method further includes bonding the first thin semiconductor wafer to the second thin semiconductor wafer.

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 386,598, entitled "SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME," filed December 8, 2022, which is incorporated herein by reference as if reproduced in full below. [Background technology]

[0002] A bidirectional bipolar junction transistor (or "BJT") is a junction transistor constructed with a base and collector-emitter on one side of a semiconductor wafer and a separate, isolated base and collector-emitter on the other side of the semiconductor wafer. When properly configured by an external driver, current can selectively flow through a bidirectional BJT in either direction. Whether the collector-emitter is considered a collector (e.g., current flowing into a bidirectional bipolar junction transistor) or an emitter (e.g., current flowing out of a bidirectional bipolar junction transistor) depends on the applied external voltage and, therefore, the direction of current flow through the bidirectional BJT. Summary of the Invention

[0003] The collector-emitter voltage drop (or “V”) during current flow between the collector and emitter in a bidirectional BJT with a double-sided base. CEon ”) occurs. This voltage drop results in power loss. Reducing this voltage drop reduces power loss and improves efficiency. For example, a lower voltage drop can be achieved by placing the collector-emitter closer to each other within the semiconductor wafer. However, fabricating bidirectional BJT devices with thin semiconductor wafers can complicate mass production. Therefore, the present disclosure provides, among other things, thin bidirectional BJT devices and methods of fabricating thin bidirectional BJT devices that include thick semiconductor wafers that are processed and ground into thin semiconductor wafers and then bonded using a thin wafer bonding process.

[0004] The present disclosure provides a method for fabricating a thin bidirectional bipolar junction transistor device. The method includes forming a first base region and a first emitter / collector region on a first side of a first thick semiconductor wafer. The method also includes removing a portion of the first thick semiconductor wafer to create a first thin semiconductor wafer. The method further includes forming a second base region and a second emitter / collector region on a second side of the first thin semiconductor wafer opposite the first side. The method also includes creating a second thin semiconductor wafer. The method further includes bonding the first thin semiconductor wafer to the second thin semiconductor wafer.

[0005] The present disclosure also provides a method for fabricating a thin bidirectional bipolar junction transistor device. The method includes activating dopants of a first conductivity type and dopants of a second conductivity type introduced into different regions of a first side of a first semiconductor wafer using a diffusion process. The method also includes reducing a thickness of the first semiconductor wafer by removing a portion of the first semiconductor wafer from a second side of the first semiconductor wafer opposite the first side of the first semiconductor wafer. The method further includes activating dopants of the first conductivity type and dopants of the second conductivity type introduced into different regions of the second side of the first semiconductor wafer without a diffusion process. The method also includes activating dopants of the first conductivity type and dopants of the second conductivity type introduced into different regions of the first side of a second semiconductor wafer using a diffusion process. The method further includes reducing a thickness of the second semiconductor wafer by removing a portion of the second semiconductor wafer from a second side of the second semiconductor wafer opposite the first side of the second semiconductor wafer. The method also includes activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the second side of the second semiconductor wafer without a diffusion process. The method further includes bonding the first semiconductor wafer to the second semiconductor wafer.

[0006] The present disclosure further provides, in one implementation, a thin bidirectional bipolar junction transistor device including a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first front-side junction having a first base region and a first emitter / collector region on a first side of the first semiconductor wafer. The first semiconductor wafer also includes a first back-side junction having a second base region and a second emitter / collector region on a second side of the first semiconductor wafer opposite the first side of the first semiconductor wafer. The first back-side junction is thinner than the first front-side junction. The second semiconductor wafer includes a second front-side junction having a third base region and a third emitter / collector region on the first side of the second semiconductor wafer. The second semiconductor wafer also includes a second back-side junction having a fourth base region and a fourth emitter / collector region on a second side of the second semiconductor wafer opposite the first side of the second semiconductor wafer. The second backside junction is thinner than the second frontside junction. The second side of the first semiconductor wafer is bonded to the second side of the second semiconductor wafer. [Brief explanation of the drawings]

[0007] For a detailed description of example embodiments, reference will now be made to the accompanying drawings. [Figure 1] 1 is a schematic cross-sectional view of an example of a low-profile bidirectional BJT device according to some implementations. [Figure 2] FIG. 1 is a flow diagram of an example method for fabricating a thin bidirectional BJT device from a thick semiconductor wafer, according to some implementations. [Figure 3] 1 is a schematic cross-sectional view of a thick semiconductor wafer having a front-side PN junction, according to some implementations. [Figure 4] 1 is a schematic cross-sectional view of a thinned semiconductor wafer having a front-side PN junction, according to some implementations. [Figure 5] 1 is a schematic cross-sectional view of a thinned semiconductor wafer having a front-side PN junction and a back-side PN junction, according to some implementations. [Figure 6]1 shows an example plot of leakage current versus breakdown voltage for a thin semiconductor wafer according to some implementations. [Figure 7] 1 shows a plot illustrating an example of leakage current versus breakdown voltage for a low-profile bidirectional BJT device according to some implementations. [Figure 8] 1 shows example plots of collector-emitter current versus collector-emitter voltage for thick and thin bidirectional BJT devices according to some implementations. DETAILED DESCRIPTION OF THE INVENTION

[0008] definition Various terms are used to refer to particular system components. Different companies may refer to components by different names, and this document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms "including" and "having" are used open-endedly and, therefore, should be interpreted to mean "including, but not limited to." Also, the term "couple" is intended to mean either an indirect connection or a direct connection. Thus, when a first device couples to a second device, the connection may be by a direct connection or by an indirect connection via other devices and connections.

[0009] The "collector-emitter" of a bipolar junction transistor means the region of the bipolar junction transistor through which the primary load current flows. For purposes of this specification and claims, the designation as collector-emitter is unrelated to the underlying device physics within the bipolar junction transistor. For example, in the case of a double-sided double-base PNP transistor, the primary load current may flow from the upper P-type region, through the bulk N-type region, and out the lower P-type region; when so used, both the upper and lower P-type regions are considered collector-emitters. However, in other cases, such as those described in co-pending and commonly owned U.S. Provisional Application No. 63 / 382,924, entitled "Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor," filed November 9, 2022, the main load current can flow from the upper N-type region through the bulk N-type region and then through the lower N-type region, and when so used, the upper and lower N-type regions are considered collector-emitter.

[0010] The "base" of a bipolar junction transistor refers to the region of the bipolar junction transistor through which a control current flows, the control current being distinct from the primary load current. For purposes of this specification and claims, the designation as a base is independent of the underlying device physics within the bipolar junction transistor. For example, in the case of a double-sided double-base PNP transistor, the control current can flow into either the upper N-type region or the lower N-type region, and when so used, the upper and lower N-type regions are considered the base. However, in other cases, such as those described in the above-mentioned co-pending and commonly owned U.S. Provisional Application No. 63 / 382,924, the control current can flow into either the upper P-type region or the lower P-type region, and when so used, both the upper and lower P-type regions are considered the base.

[0011] With respect to an electrical device (whether stand-alone or part of an integrated circuit), the terms "input" and "output" refer to electrical connections to the electrical device and should not be interpreted as verbs requiring an action. For example, a differential amplifier, such as an operational amplifier, may have a first differential input and a second differential input; these "inputs" define electrical connections to the operational amplifier and should not be interpreted as requiring inputting a signal into the operational amplifier.

[0012] The following description is directed to various implementations of the present invention. While one or more of these implementations may be preferred, the disclosed implementations should not be construed or otherwise used as limiting the scope of the present disclosure, including the claims. Moreover, those skilled in the art will appreciate that the following description has broad applicability, and the description of any implementation is intended merely to exemplify that implementation and is not intended to imply that the scope of the present disclosure, including the claims, is limited to that implementation.

[0013] Various examples are directed to thin bidirectional bipolar junction transistor (or "BJT") devices and methods for fabricating thin bidirectional BJT devices. More specifically, various examples are directed to thin bidirectional BJT devices fabricated from thick, large-diameter wafers. Even more specifically, various examples are directed to thin bidirectional BJT devices fabricated using thin-wafer bonding processes. This specification first refers to an example completed thin bidirectional BJT device to orient the reader.

[0014] 1 is a schematic cross-sectional view of an example of a thin bidirectional BJT device 100 according to some implementations of the present disclosure. The thin bidirectional BJT device 100 shown in FIG. 1 includes an upper thinned semiconductor wafer 102 and a lower thinned semiconductor wafer 104. The designations "upper" and "lower" are arbitrary and should not be construed as requiring a particular physical layout.

[0015] The top thin semiconductor wafer 102 shown in FIG. 1 includes a drift region 106, an outer base region 108, an outer emitter / collector region 110, an inboard base region 112, and an inner emitter / collector region 114. The outer base region 108 and the outer emitter / collector region 110 are formed on a front side 116 of the top thin semiconductor wafer 102 as shown in FIG. 1. The inboard base region 112 and the inner emitter / collector region 114 are formed on a back side 118 of the top thin semiconductor wafer 102 as shown in FIG. 1. The top thin semiconductor wafer 102 shown in FIG. 1 also includes metal pads 120, 122, 124, and 126. The metal pad 120 is bonded to the outer base region 108. The metal pad 122 is bonded to the outer emitter / collector region 110. The metal pad 124 is bonded to the inboard base region 112. A metal pad 126 is coupled to the inner emitter / collector region 114 .

[0016] The lower thin semiconductor wafer 104 shown in FIG. 1 includes a drift region 128, an outer base region 130, an outer emitter / collector region 132, an inboard base region 134, and an inner emitter / collector region 136. With respect to the regions of the lower thin semiconductor wafer 104, this specification uses the terms “inner” and “outer” as a naming convention to reduce confusion with similarly located regions in the upper thin semiconductor wafer 102. The outer base region 130 and the outer emitter / collector region 132 are formed on a front surface 138 of the lower thin semiconductor wafer 104, as shown in FIG. 1. The inboard base region 134 and the inner emitter / collector region 136 are formed on a back surface 140 of the lower thin semiconductor wafer 104, as shown in FIG. 1. The lower thin semiconductor wafer 104 shown in FIG. 1 also includes metal pads 142, 144, 146, and 148. The metal pad 142 is coupled to the outer base region 130. Metal pad 144 is coupled to outer emitter / collector region 132. Metal pad 146 is coupled to inner base region 134. Metal pad 148 is coupled to inner emitter / collector region 136.

[0017] In some implementations, the drift regions 106 and 128 comprise a semiconductor material such as silicon carbide (i.e., “SiC”) or gallium nitride (i.e., “GaN”). With SiC, there are limitations on how thick the drift regions can be. Notably, unlike silicon, chemical vapor deposition (i.e., “CVD”) methods can be used to form lightly doped drift regions. CVD methods are time-consuming, and increasing the thickness of the epitaxy layer while maintaining sufficient quality can be a technical challenge. Furthermore, costs rise sharply as the epitaxy layer becomes thicker. However, by bonding two thin semiconductor wafers as described herein, a thin bidirectional BJT device formed in SiC can have a higher quality and lower cost drift region than SiC devices fabricated using other methods. In some implementations, the drift regions 106 and 128 can be P-type semiconductors, as shown in FIG. 1 . In an alternative implementation, the drift regions 106 and 128 can be N-type semiconductors.

[0018] The backside 118 of the top thin semiconductor wafer 102 is bonded to the backside 140 of the bottom thin semiconductor wafer 104. For example, as shown in FIG. 1 , metal pad 124 may be electrically coupled to metal pad 146, and metal pad 126 may be electrically coupled to metal pad 148.

[0019] As mentioned above, in bidirectional BJT devices, a lower collector-emitter voltage drop (i.e., “V CEon" can be achieved. One approach to doing so is to reduce the thickness of the semiconductor wafer relative to the surface where the collector-emitter is fabricated. This approach is feasible for smaller diameter semiconductor wafers, such as 4-inch and 6-inch wafers. However, as the wafer diameter increases, the risk of the wafer breaking during fabrication also increases. For example, semiconductor wafers having an 8-inch or 12-inch diameter but that are too thin can suffer from significantly increased breakage rates. Due to the risk of breakage, certain semiconductor foundries require a minimum wafer thickness, such as at least 500 micrometers for 6-inch wafers and at least 750 micrometers for 8-inch wafers.

[0020] Larger semiconductor wafer diameters allow for lower cost per bidirectional BJT device and faster production rates, but the increased thickness required increases V CEon However, by grinding two thick semiconductor wafers into two thin semiconductor wafers and then bonding the two thin semiconductor wafers together, a smaller thickness (and therefore a lower V CEon ) can be achieved. FIG. 2 is a flow diagram of an example method 200 for fabricating a thin bidirectional BJT device from a thick semiconductor wafer, according to some implementations. For simplicity of explanation, method 200 is described as a series of processes. However, processes according to the present disclosure may be performed in various orders and / or simultaneously and / or with other operations not presented and described herein. For example, the processes shown in method 200 of FIG. 2 may be performed in combination with any other processes of any other method disclosed herein. Also, not all illustrated processes are required to implement method 200 in accordance with the disclosed subject matter. Additionally, one skilled in the art will understand and appreciate that method 200 may instead be represented as a series of interrelated states via a state diagram or event diagram.

[0021] At block 202, a first base region and a first emitter / collector region are formed on a first surface of a first thick semiconductor wafer. In some implementations, the first thick semiconductor wafer has a thickness of about 750 micrometers and a diameter of about 8 inches. In other implementations, the first thick semiconductor wafer has a thickness of about 1,000 micrometers and a diameter of about 12 inches. FIG. 3 is a schematic cross-sectional view of an example thick semiconductor wafer 300 having an extrinsic base region 108 and an extrinsic emitter / collector region 110 formed on a front surface 302 of the thick semiconductor wafer 300. The extrinsic base region 108 and the extrinsic emitter / collector region 110 are made from dopants of opposite conductivity types to form a PN junction on the front surface 302 of the thick semiconductor wafer 300. For example, as shown in FIG. 3, a P-type dopant is introduced into a portion of the front surface 302 of the thick semiconductor wafer 300 to form the extrinsic base region 108. 3, N-type dopants are introduced into different portions of the front side 302 of the thick semiconductor wafer 300 to form outer emitter / collector regions 110. In some implementations, the outer base regions 108 may be formed using N-type dopants, and the outer emitter / collector regions 110 may be formed using P-type dopants. The P-type and N-type dopants in the outer base regions 108 and outer emitter / collector regions 110 are activated using a diffusion process. For example, the P-type and N-type dopants in the outer base regions 108 and outer emitter / collector regions 110 may be activated in a furnace process.

[0022] In some implementations, the outer base region 108 and the outer emitter / collector region 110 are metallized after their formation. For example, as shown in FIG. 3, a metal pad 120 may be formed on the outer base region 108 and a metal pad 122 may be formed on the outer emitter / collector region 110.

[0023] Returning to FIG. 2 , at block 204, a portion of the first thick semiconductor wafer is removed to create a first thin semiconductor wafer. For example, a portion of the thick semiconductor wafer 300 (shown in FIG. 3 by the dashed box 304) may be removed from the backside 306 of the thick semiconductor wafer 300 to create the top thin semiconductor wafer 102 as shown in FIG. 4 . In some implementations, the backside 306 of the thick semiconductor wafer 300 may be ground (e.g., using a Taiko process) to create the top thin semiconductor wafer 102. In some implementations, the thickness of the top thin semiconductor wafer 102 may be in a range from about 80 micrometers to about 110 micrometers.

[0024] Returning to FIG. 2 , in block 206, a second base region and a second emitter / collector region are formed on a second surface of the first thin semiconductor wafer opposite the first surface. For example, FIG. 5 is a schematic cross-sectional view of the top thin semiconductor wafer 102 having the intrinsic base region 112 and the intrinsic emitter / collector region 114 formed on the back surface 118 of the top thin semiconductor wafer 102. Note that the top thin semiconductor wafer 102 shown in FIG. 5 is inverted upside down compared to the top thin semiconductor wafer 102 shown in FIG. 4 . The intrinsic base region 112 and the intrinsic emitter / collector region 114 are made of dopants of opposite conductivity types to form a PN junction on the back surface 118 of the top thin semiconductor wafer 102. For example, as shown in FIG. 5 , a P-type dopant may be introduced into a portion of the back surface 118 of the top thin semiconductor wafer 102 to form the intrinsic base region 112. 5, N-type dopants may be introduced into different portions of the backside 118 of the top thin semiconductor wafer 102 to form inner emitter / collector regions 114. In some implementations, the inner base regions 112 may be formed using N-type dopants, and the inner emitter / collector regions 114 may be formed using P-type dopants. In some implementations, photolithography may be used to form P and N photopatterns before the P and N-type dopants are implanted (e.g., similar to the process used to fabricate reverse-conducting insulated gate bipolar transistors).

[0025] Because the top thin semiconductor wafer 102 is a thin wafer, the P-type and N-type dopants in the intrinsic base region 112 and the intrinsic emitter / collector region 114 may not be activated by a diffusion process. Rather, in some implementations, the P-type and N-type dopants in the intrinsic base region 112 and the intrinsic emitter / collector region 114 may be activated by a laser annealing process or a hot plasma process.

[0026] In some implementations, the intrinsic base region 112 and the intrinsic emitter / collector region 114 are metallized after their formation. For example, as shown in FIG. 5 , a metal pad 124 may be formed on the intrinsic base region 112, and a metal pad 126 may be formed on the intrinsic emitter / collector region 114.

[0027] 5, the PN junction on the backside 118 of the top thin semiconductor wafer 102 is thinner than the PN junction on the front side 116 of the top thin semiconductor wafer 102. For example, the PN junction on the backside 118 may be approximately 3 micrometers thick, and the PN junction on the front side 116 may be approximately 10 micrometers thick. Thus, the breakdown voltage of the top thin semiconductor wafer 102 may be configured to be approximately half the target breakdown voltage of the thin bidirectional BJT device 100. For example, if the target breakdown voltage of the thin bidirectional BJT device 100 is approximately 1,200 volts, the breakdown voltage of the top thin semiconductor wafer 102 may be approximately 600 volts.

[0028] 2, a second thin semiconductor wafer is fabricated at block 208. In some implementations, the second thin semiconductor wafer may be fabricated similarly to the first thin semiconductor wafer described above with respect to blocks 202, 204, and 206. For example, the second thin semiconductor wafer may have a structure similar to the lower thin semiconductor wafer 104 described above with respect to FIG.

[0029] At block 210, the first thin semiconductor wafer is bonded to the second thin semiconductor wafer. For example, as shown in FIG. 1 , the backside 118 of the top thin semiconductor wafer 102 can be bonded to the backside 140 of the bottom thin semiconductor wafer 104. In some implementations, the metal pad of the PN junction on the backside 118 of the top thin semiconductor wafer 102 is electrically coupled to the metal pad of the PN junction on the backside 140 of the bottom thin semiconductor wafer 104. For example, as shown in FIG. 1 , the metal pad 124 of the inboard base region 112 of the top thin semiconductor wafer 102 is electrically coupled to the metal pad 146 of the inboard base region 134 of the bottom thin semiconductor wafer 104, and the metal pad 126 of the inboard emitter / collector region 114 of the top thin semiconductor wafer 102 is electrically coupled to the metal pad 148 of the inboard emitter / collector region 136 of the bottom thin semiconductor wafer 104.

[0030] The bonded metal pads themselves may increase the inductance of the low-profile bidirectional BJT device 100 relative to other semiconductor devices that do not have such bonded metal pads. However, the additional inductance is small. For example, at 1 megahertz, 1 centimeter of 1-millimeter copper wire has an inductance of approximately 6 nanohenries, and 10 centimeters has an inductance of approximately 105 nanohenries, each of which is greater than that incorporated into the low-profile bidirectional BJT device disclosed herein. Also, a 500-micrometer diameter aluminum-copper alloy metal pad with a thickness of 4 micrometers may have an inductance of approximately 0.005 nanohenries. Further reduction in inductance may result from increasing the area of ​​the metallization (i.e., the area of ​​the metal pad) and reducing its thickness. For example, an aluminum-copper alloy metal pad with a thickness of 2 micrometers and a width of 1,000 micrometers may have a smaller inductance.

[0031] Figure 6 shows an example plot of leakage current versus breakdown voltage for a thin semiconductor wafer about 90 micrometers thick. Figure 6 shows that the breakdown voltage of the thin semiconductor wafer is greater than 0.6 kilovolts. A breakdown voltage of 0.6 kilovolts can be achieved by optimizing the preliminary wafer thickness and implant and activation process conditions.

[0032] Figure 7 shows an example plot of leakage current versus breakdown voltage for a thin bidirectional BJT device approximately 180 micrometers thick. Figure 7 shows that the breakdown voltage of the thin bidirectional BJT device is greater than 1.4 kilovolts.

[0033] FIG. 8 shows the collector-emitter voltage (i.e., “V”) for a 250 micrometer bidirectional BJT device fabricated using conventional techniques and a thin bidirectional BJT device disclosed herein. CE ”) to the collector-emitter current (i.e., “I CE 8 shows an example plot of a thin bidirectional BJT device. FIG. 8 shows that the collector-emitter voltage drop of the thin bidirectional BJT device is lower (about 30% lower) than the collector-emitter voltage drop of the thick bidirectional BJT device. This lower collector-emitter voltage drop of the thin bidirectional BJT device allows such devices to be produced in higher volumes on larger semiconductor wafers.

[0034] The thin bidirectional BJT devices disclosed herein can be electrically coupled to an external driver (e.g., drive circuit), such as that disclosed in U.S. Patent No. 11,411,557. Other drive circuits may also be used.

[0035] Although many of the electrical connections in the drawings are shown as direct couplings with no intervening devices, and are not explicitly stated as such in the description above, this paragraph nevertheless serves as the antecedent basis for referring to the electrical connections in the claims as "direct couplings" with respect to the electrical connections with no intervening devices shown in the drawings.

[0036] The above description is intended to be illustrative of the principles and various implementations of the present invention. Numerous modifications and variations will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such modifications and variations.

[0037] term

[0038] Item 1. A method for fabricating a thin bidirectional bipolar junction transistor device, comprising: forming a first base region and a first emitter / collector region on a first side of a first thick semiconductor wafer; removing a portion of the first thick semiconductor wafer to produce a first thin semiconductor wafer; forming a second base region and a second emitter / collector region on a second side of the first thinned semiconductor wafer opposite the first side; preparing a second thin semiconductor wafer; bonding the first thin semiconductor wafer to the second thin semiconductor wafer; How to have that.

[0039] Item 2. The manufacturing of the second thin semiconductor wafer further includes: forming a third base region and a third emitter / collector region on a third side of the second thick semiconductor wafer; removing a portion of the second thick semiconductor wafer to produce the second thin semiconductor wafer; forming a fourth base region and a fourth emitter / collector region on a fourth side of the second thinned semiconductor wafer opposite the third side; The method of any of the preceding paragraphs, including:

[0040] Item 3. The bonding of the first thin semiconductor wafer to the second thin semiconductor wafer further comprises: electrically coupling a metal pad of the second base region to a metal pad of the fourth base region; electrically coupling a metal pad of the second emitter / collector region to a metal pad of the fourth emitter / collector region; The method of any of the preceding paragraphs, including:

[0041] Item 4. The method of any item herein, wherein removing the portion of the first thick semiconductor wafer further comprises grinding the second surface of the first thick semiconductor wafer.

[0042] Item 5. The method of any item herein, wherein forming the first base region and the first emitter / collector region on the first surface of the first thick semiconductor wafer further includes activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the first surface of the first thick semiconductor wafer using a diffusion process, and forming the second base region and the second emitter / collector region on the second surface of the first thin semiconductor wafer further includes activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the second surface of the first thin semiconductor wafer without the diffusion process.

[0043] Item 6. The method of any item herein, wherein activating the first conductivity type dopant and the second conductivity type dopant introduced into the different regions of the second surface of the first thin semiconductor wafer without a diffusion process further includes activating the first conductivity type dopant and the second conductivity type dopant introduced into the different regions of the second surface of the first thin semiconductor wafer using a laser annealing process or a hot plasma process.

[0044] Item 7. The method of any of the items herein, wherein the thickness of the first thick semiconductor wafer is 750 micrometers or more, and the thickness of the first thin semiconductor wafer is within the range of about 80 micrometers to about 110 micrometers.

[0045] Item 8. A method for fabricating a thin bidirectional bipolar junction transistor device, comprising: activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the first surface of the first semiconductor wafer using a diffusion process; reducing a thickness of the first semiconductor wafer by removing a portion of the first semiconductor wafer from a second side of the first semiconductor wafer opposite the first side of the first semiconductor wafer; activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the second surface of the first semiconductor wafer without the diffusion process; activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the first surface of the second semiconductor wafer using the diffusion process; reducing a thickness of the second semiconductor wafer by removing a portion of the second semiconductor wafer from a second side of the second semiconductor wafer opposite the first side of the second semiconductor wafer; activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the second surface of the second semiconductor wafer without the diffusion process; bonding the first semiconductor wafer to the second semiconductor wafer; How to have that.

[0046] Item 9. The method of any item herein, wherein activating the first conductivity type dopant and the second conductivity type dopant introduced into the different regions of the second surface of the first semiconductor wafer without a diffusion process further includes activating the first conductivity type dopant and the second conductivity type dopant introduced into the different regions of the second surface of the first semiconductor wafer using a laser annealing process or a hot plasma process.

[0047] Item 10. The method of any item herein, further comprising: the diffusion process comprising a furnace process.

[0048] Item 11. The method of any item herein, wherein removing the portion of the first semiconductor wafer further comprises grinding the second surface of the first semiconductor wafer.

[0049] Item 12. The method of any item herein, wherein bonding the first semiconductor wafer to the second semiconductor wafer further comprises bonding the second side of the first semiconductor wafer to the second side of the second semiconductor wafer.

[0050] Item 13. The method of any of the items herein, wherein the thickness of the first semiconductor wafer before removing the portion of the first semiconductor wafer is approximately 750 micrometers, and the thickness of the first semiconductor wafer after removing the portion of the first semiconductor wafer is within a range of approximately 80 micrometers to approximately 110 micrometers.

[0051] Item 14. A first semiconductor wafer, a first front-side junction including a first base region and a first emitter / collector region on a first surface of the first semiconductor wafer; and a first semiconductor wafer including a first backside junction including a second base region and a second emitter / collector region on a second side of the first semiconductor wafer opposite the first side of the first semiconductor wafer, the first backside junction being thinner than the first frontside junction; a second semiconductor wafer; a second front side junction including a third base region and a third emitter / collector region on the first surface of the second semiconductor wafer; and a second semiconductor wafer including a second backside junction including a fourth base region and a fourth emitter / collector region on a second side of the second semiconductor wafer opposite the first side of the second semiconductor wafer, the second backside junction being thinner than the second frontside junction; and the second surface of the first semiconductor wafer is bonded to the second surface of the second semiconductor wafer; Thin bidirectional bipolar junction transistor device.

[0052] Item 15. The thin bidirectional bipolar junction transistor device of any item herein, wherein the metal pad of the second base region is electrically coupled to the metal pad of the fourth base region, and the metal pad of the second emitter / collector region is electrically coupled to the metal pad of the fourth emitter / collector region.

[0053] Item 16. The thin bidirectional bipolar junction transistor device of any item herein, wherein the first semiconductor wafer and the second semiconductor wafer each have a thickness within a range of about 80 micrometers to about 110 micrometers.

[0054] Item 17. The thin bidirectional bipolar junction transistor device of any item herein, wherein the first semiconductor wafer and the second semiconductor wafer each have a diameter of 8 inches or greater.

[0055] Item 18. The thin bidirectional bipolar junction transistor device of any item herein, wherein the combined thickness of the first semiconductor wafer and the second semiconductor wafer is within the range of about 160 micrometers to about 220 micrometers.

[0056] Item 19. The thin bidirectional bipolar junction transistor device of any item herein, further comprising: the first semiconductor wafer and the second semiconductor wafer each comprising silicon carbide.

[0057] Item 20. The thin bidirectional bipolar junction transistor device of any item herein, further comprising: the first semiconductor wafer and the second semiconductor wafer each comprising gallium nitride.

Claims

1. 1. A method for fabricating a thin bidirectional bipolar junction transistor device, comprising: forming a first base region and a first emitter / collector region in a first surface of the first thick semiconductor wafer; removing a portion of the first thick semiconductor wafer to produce a first thin semiconductor wafer; forming a second base region and a second emitter / collector region on a second side of the first thinned semiconductor wafer opposite the first side; preparing a second thin semiconductor wafer; bonding the first thin semiconductor wafer to the second thin semiconductor wafer; How to have that.

2. Producing the second thinned semiconductor wafer further includes: forming a third base region and a third emitter / collector region on a third side of the second thick semiconductor wafer; removing a portion of the second thick semiconductor wafer to produce the second thin semiconductor wafer; forming a fourth base region and a fourth emitter / collector region on a fourth surface of the second thinned semiconductor wafer opposite the third surface; The method of claim 1 , comprising:

3. Bonding the first thin semiconductor wafer to the second thin semiconductor wafer further comprises: electrically coupling a metal pad of the second base region to a metal pad of the fourth base region; electrically coupling a metal pad of the second emitter / collector region to a metal pad of the fourth emitter / collector region; The method of claim 2 , comprising:

4. 2. The method of claim 1, wherein removing the portion of the first thick semiconductor wafer further comprises grinding the second side of the first thick semiconductor wafer.

5. 2. The method of claim 1, wherein forming the first base region and the first emitter / collector region in the first side of the first thick semiconductor wafer further comprises activating dopants of a first conductivity type and dopants of a second conductivity type introduced in different regions of the first side of the first thick semiconductor wafer using a diffusion process, and forming the second base region and the second emitter / collector region in the second side of the first thin semiconductor wafer further comprises activating dopants of the first conductivity type and dopants of the second conductivity type introduced in different regions of the second side of the first thin semiconductor wafer without the diffusion process.

6. 6. The method of claim 5, wherein activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into the different regions of the second side of the first thin semiconductor wafer without a diffusion process further comprises activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into the different regions of the second side of the first thin semiconductor wafer using a laser annealing process or a hot plasma process.

7. 10. The method of claim 1, wherein the thickness of the first thick semiconductor wafer is 750 micrometers or greater, and the thickness of the first thin semiconductor wafer is in the range of about 80 micrometers to about 110 micrometers.

8. 1. A method for fabricating a thin bidirectional bipolar junction transistor device, comprising: activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the first surface of the first semiconductor wafer using a diffusion process; reducing a thickness of the first semiconductor wafer by removing a portion of the first semiconductor wafer from a second side of the first semiconductor wafer opposite the first side of the first semiconductor wafer; activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the second surface of the first semiconductor wafer without the diffusion process; activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the first surface of the second semiconductor wafer using the diffusion process; reducing a thickness of the second semiconductor wafer by removing a portion of the second semiconductor wafer from a second side of the second semiconductor wafer opposite the first side of the second semiconductor wafer; activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into different regions of the second surface of the second semiconductor wafer without the diffusion process; bonding the first semiconductor wafer to the second semiconductor wafer; How to have that.

9. 9. The method of claim 8, wherein activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into the different regions of the second side of the first semiconductor wafer without a diffusion process further comprises activating the dopants of the first conductivity type and the dopants of the second conductivity type introduced into the different regions of the second side of the first semiconductor wafer using a laser annealing process or a hot plasma process.

10. The method of claim 8 , further comprising: the diffusion process comprising a furnace process.

11. 9. The method of claim 8, wherein removing the portion of the first semiconductor wafer further comprises grinding the second side of the first semiconductor wafer.

12. 9. The method of claim 8, wherein bonding the first semiconductor wafer to the second semiconductor wafer further comprises bonding the second side of the first semiconductor wafer to the second side of the second semiconductor wafer.

13. 9. The method of claim 8, wherein a thickness of the first semiconductor wafer before removing the portion of the first semiconductor wafer is about 750 micrometers, and a thickness of the first semiconductor wafer after removing the portion of the first semiconductor wafer is in a range from about 80 micrometers to about 110 micrometers.

14. a first semiconductor wafer; a first front-side junction including a first base region and a first emitter / collector region on a first surface of the first semiconductor wafer; and a first semiconductor wafer including a first backside junction including a second base region and a second emitter / collector region on a second side of the first semiconductor wafer opposite the first side of the first semiconductor wafer, the first backside junction being thinner than the first frontside junction; a second semiconductor wafer; a second front-side junction including a third base region and a third emitter / collector region on the first surface of the second semiconductor wafer; and a second semiconductor wafer including a second backside junction including a fourth base region and a fourth emitter / collector region on a second side of the second semiconductor wafer opposite the first side of the second semiconductor wafer, the second backside junction being thinner than the second frontside junction; and the second surface of the first semiconductor wafer is bonded to the second surface of the second semiconductor wafer; Thin bidirectional bipolar junction transistor device.

15. 15. The thin bidirectional bipolar junction transistor device of claim 14, wherein a metal pad of the second base region is electrically coupled to a metal pad of the fourth base region, and a metal pad of the second emitter / collector region is electrically coupled to a metal pad of the fourth emitter / collector region.

16. 15. The thin bidirectional bipolar junction transistor device of claim 14, wherein the first semiconductor wafer and the second semiconductor wafer each have a thickness within a range from about 80 micrometers to about 110 micrometers.

17. 15. The thin bidirectional bipolar junction transistor device of claim 14, wherein the first semiconductor wafer and the second semiconductor wafer each have a diameter of 8 inches or greater.

18. 15. The thin bidirectional bipolar junction transistor device of claim 14, wherein the combined thickness of the first semiconductor wafer and the second semiconductor wafer is in the range of about 160 micrometers to about 220 micrometers.

19. 15. The thin bidirectional bipolar junction transistor device of claim 14, further comprising: said first semiconductor wafer and said second semiconductor wafer each comprising silicon carbide.

20. 15. The thin bidirectional bipolar junction transistor device of claim 14, further comprising: said first semiconductor wafer and said second semiconductor wafer each comprising gallium nitride.

Images