Semiconductor module

Abstract

To suppress the occurrence of parallel oscillation when a plurality of switching elements are simultaneously operated.SOLUTION: The first lower arm transistor 11L and the second lower arm transistor 12L are connected in parallel to each other. The parallel resonance circuit of the first lower arm transistor 11L and the second lower arm transistor 12L has a first pole frequency ω p1, a second pole frequency ω p1 higher than the first pole frequency ω p2, and a zero point frequency ω z. The absolute values of the phase delay at the second pole frequency ω p2 and the zero point frequency ω z are set to be smaller than 180 °.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor module. [Background technology]

[0002] Patent Document 1 discloses a power module in which a half-bridge circuit is formed by a plurality of first switching elements and a plurality of second switching elements. The plurality of first switching elements are connected in parallel with each other. The plurality of second switching elements are connected in parallel with each other. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-79670

[0004] [overview] When a plurality of switching elements connected in parallel are operated simultaneously, it is required to suppress the occurrence of parallel oscillation.

[0005] A semiconductor module according to an embodiment of the present disclosure includes a first transistor and a second transistor connected in parallel to each other, and a parallel resonant circuit of the first transistor and the second transistor has a first pole frequency ω p1 and the first pole frequency ω p1 Second pole frequency ω higher than p2 and the zero point frequency ω z and the second pole frequency ω p2 and the zero point frequency ω z The absolute value of the phase delay between the two is set to be smaller than 180°. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view showing an example of the internal configuration of an illustrative semiconductor module according to the first embodiment. [Figure 2]FIG. 2 is a schematic cross-sectional view of the semiconductor module taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor module taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic equivalent circuit diagram of the semiconductor module of FIG. [Figure 5] FIG. 5 is a schematic circuit diagram showing an inductance component between a first transistor and a second transistor connected in parallel in the semiconductor module of FIG. [Figure 6] FIG. 6 is an equivalent circuit diagram of parallel oscillation in the semiconductor module of FIG. [Figure 7] FIG. 7 is a Bode diagram showing the relationship between gain and frequency in the equivalent circuit diagram of FIG. [Figure 8] FIG. 8 is a Bode diagram showing the relationship between phase and frequency in the equivalent circuit diagram of FIG. [Figure 9] FIG. 9 is a schematic plan view of a simplified semiconductor module for evaluation purposes relative to the semiconductor module of FIG. [Figure 10] FIG. 10 is a schematic equivalent circuit diagram of the semiconductor module of FIG. [Figure 11] FIG. 11 is a graph showing the transition of the gate-source voltage at turn-off when the ratio (ωp2 / ωz) of the second pole frequency ωp2 to the zero-point frequency ωz in the semiconductor module of FIG. [Figure 12] FIG. 12 is a graph showing the transition of the gate-source voltage at the time of turn-off in the semiconductor module of FIG. 9 when the ratio (ωp2 / ωz) is 0.375. [Figure 13] FIG. 13 is a graph showing the transition of the gate-source voltage at the time of turn-off in the semiconductor module of FIG. 9 when the ratio (ωp2 / ωz) is 0.55. [Figure 14] FIG. 14 is a schematic plan view of a semiconductor module according to an exemplary embodiment of the second embodiment. [Figure 15] FIG. 15 is a schematic circuit diagram of the semiconductor module of FIG.

[0007] [Detailed explanation] Hereinafter, several embodiments of a semiconductor module according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] First Embodiment [Semiconductor module schematic configuration] 1 to 4 show an example of the configuration of a semiconductor module 10 according to the first embodiment. FIG. 1 schematically shows the planar structure of the semiconductor module 10. FIG. 2 schematically shows the cross-sectional structure of the semiconductor module 10 taken along line F2-F2 in FIG. 1. FIG. 3 schematically shows the cross-sectional structure of the semiconductor module 10 taken along line F3-F3 in FIG. 1. FIG. 4 is a circuit diagram showing the inductance components of the semiconductor module 10.

[0012] As shown in FIG. 1, the semiconductor module 10 includes a first upper arm transistor 11U, a second upper arm transistor 12U, a first lower arm transistor 11L, and a second lower arm transistor 12L. The first upper arm transistor 11U and the second upper arm transistor 12U are connected in parallel to each other. The first lower arm transistor 11L and the second lower arm transistor 12L are connected in parallel to each other. The first upper arm transistor 11U and the second upper arm transistor 12U are connected in series to the first lower arm transistor 11L and the second lower arm transistor 12L. In other words, the semiconductor module 10 includes a half-bridge circuit configured by the upper arm transistors 11U and 12U and the lower arm transistors 11L and 12L. Here, the first lower arm transistor 11L is an example of a “first transistor,” and the second lower arm transistor 12L is an example of a “second transistor.”

[0013] Each of the transistors 11U, 11L, 12U, and 12L may be, for example, a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET). Note that each of the transistors 11U, 11L, 12U, and 12L may be, instead of a SiC MOSFET, a SiMOSFET, an IGBT (Insulated Gate Bipolar Transistor), or a gallium nitride (GaN) transistor.

[0014] As shown in FIGS. 1 to 3, each of the transistors 11U, 11L, 12U, and 12L has a flat plate shape with its thickness direction aligned in the Z direction. Each of the transistors 11U, 11L, 12U, and 12L includes a first element surface and a second element surface opposite the first element surface. The first upper arm transistor 11U includes a first gate electrode GU1 and a first source electrode SU1 provided on the first element surface, and a first drain electrode DU1 provided on the second element surface. The second upper arm transistor 12U includes a second gate electrode GU2 and a second source electrode SU2 provided on the first element surface, and a second drain electrode DU2 provided on the second element surface. The first lower arm transistor 11L includes a first gate electrode GL1 and a first source electrode SL1 provided on the first element surface, and a first drain electrode DL1 provided on the second element surface. The second lower arm transistor 12L includes a second gate electrode GL2 and a second source electrode SL2 provided on the first element surface, and a second drain electrode DL2 provided on the second element surface.

[0015] The semiconductor module 10 includes a flat substrate 20 with its thickness direction aligned in the Z direction. In one example, the substrate 20 has a rectangular shape with its short side aligned in the X direction and its long side aligned in the Y direction when viewed from the Z direction. The substrate 20 includes a first substrate surface 21 on which the transistors 11U, 11L, 12U, and 12L are mounted, and a second substrate surface 22 opposite the first substrate surface 21. The substrate 20 includes first to fourth substrate side surfaces 23 to 26 as four substrate side surfaces connecting the first substrate surface 21 and the second substrate surface 22. The first substrate side surface 23 and the second substrate side surface 24 constitute both end surfaces of the substrate 20 in the X direction. The third substrate side surface 25 and the fourth substrate side surface 26 constitute both end surfaces of the substrate 20 in the Y direction. The substrate 20 may be, for example, a glass epoxy substrate. Alternatively, a substrate having higher heat dissipation performance than a glass epoxy substrate, such as alumina, may be used as the substrate 20. Furthermore, the shape of the substrate 20 in plan view can be changed arbitrarily.

[0016] The semiconductor module 10 includes a first power supply wiring 30, a second power supply wiring 40, an output wiring 50, a first gate wiring 61, and a second gate wiring 62 provided on a first substrate surface 21. The first power supply wiring 30, the second power supply wiring 40, the output wiring 50, the first gate wiring 61, and the second gate wiring 62 are made of a conductive material such as aluminum (Al), copper (Cu), or silver (Ag). In one example, the first power supply wiring 30, the second power supply wiring 40, the output wiring 50, the first gate wiring 61, and the second gate wiring 62 are each made of a conductive material containing Cu.

[0017] Here, the first power supply wiring 30 is an example of a "drain wiring" corresponding to each of the upper arm transistors 11U and 12U, the output wiring 50 is an example of a "source wiring" corresponding to each of the upper arm transistors 11U and 12U, and the first gate wiring 61 is an example of a "gate wiring" corresponding to each of the upper arm transistors 11U and 12U. Also, each output wiring 50 is an example of a "drain wiring" corresponding to each of the lower arm transistors 11L and 12L, the second power supply wiring 40 is an example of a "source wiring" corresponding to each of the lower arm transistors 11L and 12L, and the second gate wiring 62 is an example of a "gate wiring" corresponding to each of the lower arm transistors 11L and 12L.

[0018] The first power supply wiring 30 and the output wiring 50 are arranged side by side in the Y direction. The first power supply wiring 30 is arranged closer to the third substrate side surface 25 than the output wiring 50. The first power supply wiring 30 constitutes input wiring of the inverter circuit of the semiconductor module 10. The first power supply wiring 30 is electrically connected to the positive electrode of a DC power supply (not shown). Therefore, a current is supplied to the first power supply wiring 30 from the DC power supply. A first upper arm transistor 11U and a second upper arm transistor 12U are mounted on the first power supply wiring 30. More specifically, both the first upper arm transistor 11U and the second upper arm transistor 12U are joined to the first power supply wiring 30 by a conductive bonding material SD. As a result, both the first drain electrode DU1 of the first upper arm transistor 11U and the second drain electrode DU2 of the second upper arm transistor 12U are electrically connected to the first power supply wiring 30.

[0019] The first power supply wiring 30 includes an element mounting portion 31 on which the transistors 11U and 12U are mounted, and a terminal connection portion 32 extending from the element mounting portion 31 toward the third substrate side surface 25 when viewed from the Z direction.

[0020] The element mounting portion 31 has a rectangular shape with its long sides extending in the X direction and its short sides extending in the Y direction when viewed from the Z direction. The first upper arm transistor 11U and the second upper arm transistor 12U are arranged at the same position in the Y direction and spaced apart from each other in the X direction. An opening 33 is provided in a portion of the element mounting portion 31 closer to the third substrate side surface 25 than the transistors 11U and 12U when viewed from the Z direction. A first gate wiring 61 is provided within the opening 33 when viewed from the Z direction. The first gate wiring 61 is arranged spaced apart from the element mounting portion 31. The first gate wiring 61 has a strip shape extending in the X direction when viewed from the Z direction. The first gate wiring 61 is arranged to face the transistors 11U and 12U in the Y direction when viewed from the Z direction. The shape of the element mounting portion 31 when viewed from the Z direction can be changed as desired.

[0021] The first gate electrode GU1 of the first upper arm transistor 11U and the second gate electrode GU2 of the second upper arm transistor 12U are each electrically connected to a first gate wiring 61 by a gate wire WGU. A first gate terminal TG1 is provided at the center of the first gate wiring 61 in the X direction. Therefore, both the first gate electrode GU1 and the second gate electrode GU2 are electrically connected to the first gate terminal TG1 via the gate wire WGU and the first gate wiring 61.

[0022] Here, the gate wire WGU connected to the first gate electrode GU1 is an example of a "first gate connecting member" corresponding to the first upper arm transistor 11U, and the gate wire WGU connected to the second gate electrode GU2 is an example of a "second gate connecting member" corresponding to the second upper arm transistor 12U.

[0023] The terminal connection portion 32 is provided in the element mounting portion 31, closer to the second substrate side surface 24. The terminal connection portion 32 is provided at a distance in the Z direction from the first substrate surface 21 of the substrate 20. In one example, the terminal connection portion 32 is provided integrally with the element mounting portion 31. A power supply terminal TP (see FIG. 4) is connected to the terminal connection portion 32. Although not shown in FIG. 1, the power supply terminal TP is provided so as to protrude in the Y direction from the third substrate side surface 25 of the substrate 20 when viewed from the Z direction. The power supply terminal TP constitutes an external terminal that is electrically connected to an external electronic device when the semiconductor module 10 is mounted in the electronic device.

[0024] The output wiring 50 constitutes the output wiring of the inverter circuit of the semiconductor module 10. The first lower arm transistor 11L and the second lower arm transistor 12L are mounted on the output wiring 50. More specifically, both the first lower arm transistor 11L and the second lower arm transistor 12L are joined to the output wiring 50 by a conductive bonding material SD. As a result, both the first drain electrode DL1 of the first lower arm transistor 11L and the second drain electrode DL2 of the second lower arm transistor 12L are electrically connected to the output wiring 50.

[0025] The first source electrode SU1 of the first upper arm transistor 11U and the second source electrode SU2 of the second upper arm transistor 12U are each electrically connected to the output wiring 50 by a source wire WSU. The first source electrode SU1 and the second source electrode SU2 are electrically connected to each other by another source wire WSU. Therefore, both the first source electrode SU1 and the second source electrode SU2 are electrically connected to the first drain electrode DL1 of the first lower arm transistor 11L and the second drain electrode DL2 of the second lower arm transistor 12L via the output wiring 50. Here, the source wire WSU is an example of a "source connecting member" corresponding to each upper arm transistor 11U, 12U.

[0026] The output wiring 50 includes an element mounting portion 51 on which the transistors 11L and 12L are mounted, and a terminal connection portion 52 that extends from the element mounting portion 51 toward the fourth substrate side surface 26 when viewed from the Z direction.

[0027] The element mounting portion 51 has a rectangular shape with its long sides extending in the X direction and its short sides extending in the Y direction when viewed from the Z direction. The element mounting portion 51 is arranged alongside the element mounting portion 31 of the first power supply wiring 30 in the Y direction. The first lower arm transistor 11L and the second lower arm transistor 12L are arranged at the same position in the Y direction and spaced apart from each other in the X direction. An opening 53 is provided in a portion of the element mounting portion 51 closer to the fourth substrate side surface 26 than the transistors 11L and 12L when viewed from the Z direction. A second gate wiring 62 is provided within the opening 53 when viewed from the Z direction. The second gate wiring 62 is spaced apart from the element mounting portion 51. The second gate wiring 62 has a strip shape extending in the X direction when viewed from the Z direction. The second gate wiring 62 is arranged to face the transistors 11L and 12L in the Y direction when viewed from the Z direction. The shape of the element mounting portion 51 when viewed from the Z direction can be changed as desired.

[0028] The first gate electrode GL1 of the first lower arm transistor 11L and the second gate electrode GL2 of the second lower arm transistor 12L are each electrically connected to the second gate wiring 62 by a gate wire WGL. A second gate terminal TG2 is provided at the center of the second gate wiring 62 in the X direction. Therefore, both the first gate electrode GL1 and the second gate electrode GL2 are electrically connected to the second gate terminal TG2 via the gate wire WGL and the second gate wiring 62. Here, the gate wire WGL connected to the first gate electrode GL1 is an example of a "first gate connecting member" corresponding to the first lower arm transistor 11L, and the gate wire WGL connected to the second gate electrode GL2 is an example of a "second gate connecting member" corresponding to the second lower arm transistor 12L.

[0029] The terminal connection portion 52 extends from the center of the element mounting portion 51 in the X direction toward the fourth substrate side surface 26 when viewed from the Z direction. The terminal connection portion 52 is provided integrally with the element mounting portion 51. An output terminal TO (see FIG. 4) is connected to the terminal connection portion 52. Although not shown in FIG. 1, the output terminal TO is provided so as to protrude in the Y direction from the fourth substrate side surface 26 of the substrate 20 when viewed from the Z direction. The output terminal TO constitutes an external terminal that is electrically connected to an external electronic device when the semiconductor module 10 is mounted on the electronic device.

[0030] The second power supply wiring 40 constitutes ground wiring for the inverter circuit of the semiconductor module 10. When viewed from the Z direction, the second power supply wiring 40 is provided so as to surround the element mounting portion 31 of the first power supply wiring 30 from both sides in the X direction and from the third substrate side surface 25 side in the Y direction. The second power supply wiring 40 includes a first connection wiring 41, a second connection wiring 42, a linking wiring 43, and a terminal connection portion 44. Here, the first connection wiring 41 is an example of a "first wiring portion" corresponding to each of the lower arm transistors 11L, 12L, and the second connection wiring 42 is an example of a "second wiring portion" corresponding to each of the lower arm transistors 11L, 12L.

[0031] The first connection wiring 41 is disposed closer to the first substrate side surface 23 than the element mounting portion 31. The first connection wiring 41 has a strip shape extending in the Y direction. The first connection wiring 41 extends to a position facing the element mounting portion 51 of the output wiring 50 when viewed from the X direction.

[0032] The second connection wiring 42 is disposed closer to the second substrate side surface 24 than the element mounting portion 31. The second connection wiring 42 has a strip shape extending in the Y direction. The second connection wiring 42 extends to a position facing the element mounting portion 51 of the output wiring 50 when viewed from the X direction.

[0033] The connecting wiring 43 is a wiring that connects the first connecting wiring 41 and the second connecting wiring 42. The connecting wiring 43 is arranged closer to the third substrate side surface 25 than the element mounting portion 31. The connecting wiring 43 is strip-shaped and extends in the X direction. When viewed from the Z direction, the connecting wiring 43 includes a portion that overlaps with the terminal connecting portion 32 of the first power supply wiring 30. The connecting wiring 43 is arranged closer to the first substrate surface 21 than the terminal connecting portion 32 in the Z direction.

[0034] The terminal connection portion 44 extends from the connecting wiring 43 toward the third substrate side surface 25. When viewed from the Z direction, the terminal connection portion 44 is arranged side by side in the X direction with the terminal connection portion 32 of the first power supply wiring 30. The terminal connection portion 44 is arranged closer to the first substrate side surface 23 than the terminal connection portion 32. A ground terminal TN (see FIG. 4) is connected to the terminal connection portion 44. Although not shown in FIG. 1, the ground terminal TN is provided so as to protrude in the Y direction from the third substrate side surface 25 of the substrate 20 when viewed from the Z direction. The ground terminal TN constitutes an external terminal that is electrically connected to an external electronic device when the semiconductor module 10 is mounted on the electronic device.

[0035] The first source electrode SL1 of the first lower arm transistor 11L and the second source electrode SL2 of the second lower arm transistor 12L are electrically connected to the second power supply wiring 40 by source wires WSL, respectively. More specifically, both the first source electrode SL1 and the second source electrode SL2 are connected to both the first connection wiring 41 and the second connection wiring 42 of the second power supply wiring 40 by the source wires WSL. When viewed from the Z direction, the source wires WSL extend in the X direction and are connected to the first connection wiring 41, the first source electrode SL1, the second source electrode SL2, and the second connection wiring 42. Here, the source wires WSL are an example of a "source connecting member" corresponding to each of the lower arm transistors 11L, 12L.

[0036] FIG. 4 is a schematic equivalent circuit diagram of the semiconductor module 10, showing the inductance components of the conductive paths in the semiconductor module 10. The inductance components of the conductive paths include inductance components due to wiring and wires. More specifically, the semiconductor module 10 includes first to ninth source inductances s1 to s9, first to seventh drain inductances d1 to d8, and first to eighth gate inductances g1 to g8. In the following description, for the components of the semiconductor module 10, please refer to the components of the semiconductor module 10 shown in FIGS. 1 to 3.

[0037] The first source inductance s1 represents the inductance component of the source wire WSU connecting the first source electrode SU1 of the first upper arm transistor 11U and the second source electrode SU2 of the second upper arm transistor 12U. The second source inductance s2 represents the inductance component of the conductive path between the first source electrode SU1 and the first drain electrode DL1 of the first lower arm transistor 11L. This inductance component represents the sum of the inductance component of the source wire WSU connecting the first source electrode SU1 of the first upper arm transistor 11U and the output wiring 50 and the inductance component of the conductive path between the source wire WSU of the output wiring 50 and the first drain electrode DL1 of the first lower arm transistor 11L. The third source inductance s3 represents the sum of the inductance component of the source wire WSU connecting the second source electrode SU2 and the output wiring 50 and the inductance component of the conductive path between the source wire WSU of the output wiring 50 and the second drain electrode DL2 of the second lower arm transistor 12L.

[0038] The fourth source inductance s4, the fifth source inductance s5, and the ninth source inductance s9 represent inductance components of the source wire WSL connecting the first source electrode SL1 of the first lower arm transistor 11L, the second source electrode SL2 of the second lower arm transistor 12L, and the first connection wiring 41 and the second connection wiring 42 of the second power supply wiring 40. More specifically, the fourth source inductance s4 represents the inductance component of a portion of the source wire WSL connecting the first source electrode SL1 and the second source electrode SL2. The fifth source inductance s5 represents the inductance component of a portion of the source wire WSL connecting the first source electrode SL1 and the first connection wiring 41. The ninth source inductance s9 represents the inductance component of a portion of the source wire WSL connecting the second source electrode SL2 and the second connection wiring 42.

[0039] The sixth source inductance s6, the seventh source inductance s7, and the eighth source inductance s8 represent the inductance components of the second power supply wiring 40. The sixth source inductance s6 represents the sum of the inductance component of the first connection wiring 41 of the second power supply wiring 40 and the inductance component of the conductive path between the first connection wiring 41 and the terminal connection portion 44 of the linking wiring 43. The seventh source inductance s7 represents the inductance component of the terminal connection portion 44. The eighth source inductance s8 represents the sum of the inductance component of the second connection wiring 42 of the second power supply wiring 40 and the inductance component of the conductive path between the second connection wiring 42 and the terminal connection portion 44 of the linking wiring 43.

[0040] The first drain inductance d1 represents the inductance component of the conductive path connecting the first drain electrode DU1 of the first upper arm transistor 11U and the second drain electrode DU2 of the second upper arm transistor 12U in the element mounting portion 31 of the first power supply wiring 30. The second drain inductance d2 represents the inductance component of the conductive path between the first drain electrode DU1 and the terminal connecting portion 32 in the element mounting portion 31. The third drain inductance d3 represents the inductance component of the conductive path between the second drain electrode DU2 and the terminal connecting portion 32 in the element mounting portion 31. The fourth drain inductance d4 represents the inductance component of the terminal connecting portion 32.

[0041] The fifth drain inductance d5 represents the inductance component of the conductive path between the first drain electrode DL1 of the first lower arm transistor 11L and the second drain electrode DL2 of the second lower arm transistor 12L in the element mounting portion 51 of the output wiring 50. The sixth drain inductance d6 represents the inductance component of the conductive path between the first drain electrode DL1 of the element mounting portion 51 and the terminal connecting portion 52. The seventh drain inductance d7 represents the inductance component of the conductive path between the second drain electrode DL2 of the element mounting portion 51 and the terminal connecting portion 52. The eighth drain inductance d8 represents the inductance component of the terminal connecting portion 52.

[0042] The first gate inductance g1 represents the inductance component of the gate wire WGU connecting the first gate electrode GU1 of the first upper arm transistor 11U and the first gate wiring 61. The second gate inductance g2 represents the inductance component of the first gate wiring 61 between the gate wire WGU and the first gate terminal TG1. The fourth gate inductance g4 represents the inductance component of the gate wire WGU connecting the second gate electrode GU2 of the second upper arm transistor 12U and the first gate wiring 61. The third gate inductance g3 represents the inductance component of the first gate wiring 61 between the gate wire WGU connected to the second gate electrode GU2 and the first gate terminal TG1.

[0043] The fifth gate inductance g5 represents the inductance component of the gate wire WGL connecting the first gate electrode GL1 of the first lower arm transistor 11L and the second gate wiring 62. The sixth gate inductance g6 represents the inductance component of the second gate wiring 62 in a portion between the gate wire WGL and the second gate terminal TG2. The eighth gate inductance g8 represents the inductance component of the gate wire WGL connecting the second gate electrode GL2 of the second lower arm transistor 12L and the second gate wiring 62. The seventh gate inductance g7 represents the inductance component of the second gate wiring 62 in a portion between the gate wire WGL connected to the second gate electrode GL2 and the second gate terminal TG2.

[0044] FIG. 5 shows a schematic equivalent circuit illustrating the inductance component between the first lower arm transistor 11L and the second lower arm transistor 12L connected in parallel in the semiconductor module 10 shown in FIG.

[0045] The semiconductor module 10 includes a drain conduction path RD electrically connecting the first drain electrode DL1 and the second drain electrode DL2, a source conduction path RS electrically connecting the first source electrode SL1 and the second source electrode SL2, and a gate conduction path RG electrically connecting the first gate electrode GL1 and the second gate electrode GL2. The drain conduction path RD has a drain inductance L dd The source conduction path RS includes a source inductance L ss The gate conduction path RG includes a gate inductance L as a parasitic inductance of the gate conduction path RG. gg Includes.

[0046] For example, the gate inductance L gg is the sum of the fifth to eighth gate inductances g5 to g8 (g5+g6+g7+g8). The source inductance Lss is the combined inductance (s4 / / (s5+s6+s8+s9)) of the fourth source inductance s4 and the fifth, sixth, eighth, and ninth source inductances s5, s6, s8, and s9 in parallel. This combined inductance L ss L ss It can also be expressed as: = s4·(s5+s6+s8+s9) / (s4+s5+s6+s8+s9). Drain inductance L dd is a combined inductance (d5 / / (s1+s2+s3)) of the fifth drain inductance d5 and the first to third source inductances s1 to s3 in parallel. This combined inductance L dd L dd It can also be shown as =d5·(s1+s2+s3) / (d5+s1+s2+s3).

[0047] FIG. 6 shows an equivalent circuit of parallel oscillation in the semiconductor module 10 shown in FIG. 6 shows, as an example, the parasitic resistance and parasitic capacitance components of the first lower arm transistor 11L or the second lower arm transistor 12L. Note that in the semiconductor module 10, parallel oscillation may also occur in the first upper arm transistor 11U and the second upper arm transistor 12U. Therefore, the equivalent circuit of parallel oscillation in the semiconductor module 10 may be represented by the parasitic resistance and parasitic capacitance components of the first upper arm transistor 11U or the second upper arm transistor 12U. In the following, the parasitic resistance and parasitic capacitance components of the first lower arm transistor 11L or the second lower arm transistor 12L will be used for explanation.

[0048] The semiconductor module 10 has a drain-source resistance R as a parasitic resistance component of the first lower arm transistor 11L or the second lower arm transistor 12L. ds and gate resistance R g The semiconductor module 10 includes a drain-source capacitance C as a parasitic capacitance component of the first lower arm transistor 11L or the second lower arm transistor 12L. ds , gate-drain capacitance C gd , and the gate-source capacitance C gs Includes.

[0049] The semiconductor module 10 also includes a current source 101. The current source 101 generates a gate-source voltage V gs_i Based on the drain-source current I ds In FIG. 6, the transconductance of the first lower arm transistor 11L or the second lower arm transistor 12L is referred to as "transconductance g m In this case, the drain-source current I ds is the transconductance g m and gate-source voltage V gs_i Multiplication of (Ids=g m ·V gs_i )

[0050] As shown in Figure 6, the drain-source resistance R ds , drain-source capacitance C ds , and the gate-source capacitance C gs is connected in parallel with the current source 101. The gate resistor R g and gate-drain capacitance C gd are connected in series with the gate resistor R g Of which, the gate-drain capacitance C gd The first terminal connected to the gate-source capacitance C gs The first terminal of the gate-source capacitance C gs The second terminal of the ss That is, the gate-source capacitance C gs is electrically connected to the source of the first lower arm transistor 11L or the second lower arm transistor 12L. g The second terminal of the gg The drain inductance L dd is the drain-source capacitance C ds , drain-source resistance R ds , and gate-drain capacitance C gd In this way, the drain-source capacitance C ds , drain-source resistance R ds , and gate-drain capacitance C gd is electrically connected to the drain of the first lower arm transistor 11L or the second lower arm transistor 12L.

[0051] In the semiconductor module 10 shown in FIG. gs The voltage between the terminals is the gate-source voltage V gs_o When the gate-source voltage V gs_i to gate-source voltage V gs_o The open-loop characteristics up to are shown by the Bode diagrams of Figures 7 and 8. Here, the open-loop characteristics include the gain characteristics and the phase characteristics. gs_iindicates the voltage input to the current source 101. The gate-source voltage V gs_o indicates the voltage generated by the propagation of the output current of the current source 101.

[0052] FIG. 7 is a graph showing the relationship between frequency (Hz) and gain. FIG. 8 is a graph showing the relationship between frequency (Hz) and phase. The phase in FIG. 8 is a graph showing the relationship between gate-source voltage V gs_i and gate-source voltage V gs_o is the phase difference between

[0053] 7 and 8, the open loop characteristics can be divided into first to fourth regions R1 to R4 in terms of frequency range. These first to fourth regions R1 to R4 are divided into four regions R1 to R4, each having a first pole frequency ω p1 , second pole frequency ω p2 , and the zero frequency ω z More specifically, the first region R1 is divided by the first pole frequency ω p1 The second region R2 is the region where the first pole frequency ω p1 The second pole frequency ω p2 The third region R3 is the region where the second pole frequency ω p2 above zero frequency ω z The fourth region R4 is the zero-point frequency ω z where the first pole frequency ω p1 , second pole frequency ω p2 , and the zero frequency ω z Each of the curves indicates a frequency at an inflection point of the gain characteristic shown in FIG.

[0054] As shown in FIG. 7, the first region R1 has a frequency of the first pole frequency ω p1 The second region R2 is the region where the gain increases as the frequency approaches the first pole frequency ω p1 to the second pole frequency ω p2 This is the region where the gain decreases as the frequency approaches the first pole frequency ω p1 is the frequency at which the gain changes from increasing to decreasing. The third region R3 is the second pole frequency ω p2 to the zero-point frequency ω zThe gain decreases as the frequency approaches the second pole frequency ω. The degree of decrease in the gain in the third region R3 is greater than the degree of decrease in the gain in the second region R2. p2 is the frequency at which the degree of gain reduction is changed. The fourth region R4 is the frequency at which the zero-point frequency ω z The gain decreases as the frequency increases from the zero point frequency ω. The degree of decrease in the gain in the fourth region R4 is smaller than the degree of decrease in the gain in the third region R3. z is the frequency at which the degree of gain reduction is changed.

[0055] As shown in FIG. 8, the phase is a positive value in the first region R1 and a negative value in the second to fourth regions R2 to R4. When the phase is a negative value, it can be said that a phase lag occurs. The phase is a function of the first pole frequency ω p1 In both the second region R2 and the fourth region R4, the phase is a negative value (phase lag), but its absolute value is smaller than 180°. On the other hand, in the third region R3, the absolute value of the phase lag is greater than 180°. In other words, the absolute value of the phase lag is greater than 180° at the frequency where the gain is zero. Here, in the example of FIG. 8, at the second pole frequency ω p2 and the zero frequency ω z The absolute value of the phase delay is 180°.

[0056] The transfer function G(s) of the parallel resonant circuit shown in FIG. 6 can be expressed by the following equation:

[0057]

number

[0058] Here, "K" is the differential coefficient, and "ζ p1 "," "ζ p2 ", and "ζ z " are the first pole damping coefficient, the second pole damping coefficient, and the zero damping coefficient, respectively. "s" is the Laplace operator.

[0059] And the first pole frequency ω p1 , second pole frequency ω p2 , and the zero frequency ω z can be expressed by the following equations. Also, the first pole damping coefficient ζ p1 , the second pole damping coefficient ζ p2 , and zero damping coefficient ζ z can be expressed by the following equations:

[0060]

number

[0061]

number

[0062]

number

[0063]

number

[0064]

number

[0065]

number

[0066] Here, L in the above formula gg / / L ss L gg L ss / (L gg +L ss ) in the above formula. ss / / L gg L ss L gg / (L ss +L ggBased on these, the first pole frequency ω p1 , second pole frequency ω p2 , and the zero frequency ω z can be calculated.

[0067] 7 and 8, as described above, if the gain becomes equal to or greater than zero when the absolute value of the phase delay becomes equal to or greater than 180° in the third region R3, the first lower arm transistor 11L and the second lower arm transistor 12L will oscillate in parallel in the third region R3. Therefore, parallel oscillation can be suppressed by reducing the third region R3. In other words, in order to suppress parallel oscillation, the second pole frequency ω p2 and zero-point frequency ω z Based on this viewpoint, the second pole frequency ω p2 and zero-point frequency ω z The relationship between these can be expressed by the following equation:

[0068]

number

[0069] The zero frequency ω in the above equation z Second pole frequency ω p2 The ratio (ω p2 / ω z ) approaches 1, the third region R3 becomes smaller. On the other hand, even if the third region R3 does not disappear completely, the second pole frequency ω p2 and the zero frequency ω z If the absolute value of the phase delay in is smaller than 180°, parallel oscillation can be suppressed.

[0070] (Simulation of parallel oscillation) 9 to 13 show the ratio (ω p2 / ω z9 shows a simulation model of the semiconductor module 10. FIG. 10 shows the relationship between the inductance of the semiconductor module 10 shown in FIG. 9. FIGS. 11 to 13 show the relationship between the ratio (ω p2 / ω z ) when changing the gate-source voltage V gs This shows the trend of

[0071] The semiconductor module 10 shown in FIGS. 9 and 10 has the configuration of the semiconductor module 10 shown in FIGS. 1 and 4, which is different from the configuration of the semiconductor module 10 shown in FIGS. 1 and 4 in that the ratio (ω p2 / ω z This is a simplified simulation model for evaluating the

[0072] FIG. 9 shows a model for evaluating the configuration of the first lower arm transistor 11L and the second lower arm transistor 12L shown in FIG. 1. When the first lower arm transistor 11L and the second lower arm transistor 12L are switched, the first upper arm transistor 11U and the second upper arm transistor 12U (both see FIG. 1) perform rectification operations. For this reason, as shown in FIG. 9, the first upper arm transistor 11U and the second upper arm transistor 12U connected in parallel in the semiconductor module 10 are shown as Schottky barrier diodes SBD. The anode of the Schottky barrier diode SBD is electrically connected to the output wiring 50 by a wire WR. The cathode of the Schottky barrier diode SBD is electrically connected to the first power supply wiring 30. Accordingly, the shape of the first power supply wiring 30 is simplified. Furthermore, the first gate wiring 61 (see FIG. 1) is omitted.

[0073] The shapes of the second power supply wiring 40 and the output wiring 50 have also been changed. The second power supply wiring 40 is formed in a T-shape when viewed from the Z direction. The second power supply wiring 40 is arranged side by side with the output wiring 50 in the Y direction. The second power supply wiring 40 is arranged on the opposite side of the output wiring 50 from the first power supply wiring 30 in the Y direction.

[0074] In the output wiring 50, the shape of the element mounting portion 51 is different so that the second gate wiring 62 is disposed between the first lower arm transistor 11L and the second lower arm transistor 12L in the X direction. The transistors 11L, 12L are mounted on the element mounting portion 51 with their gate electrodes GL1, GL2 oriented so as to be located near the second gate wiring 62.

[0075] The terminal connection portion 52 of the output wiring 50 is arranged next to the first power supply wiring 30 in the Y direction. A wire WR connected to the anode of the Schottky barrier diode SBD is connected to the terminal connection portion 52. The terminal connection portion 52 is also connected to the output terminal TO.

[0076] The first connection wiring 41 of the second power supply wiring 40 is arranged at the same position in the X direction as the first lower arm transistor 11L. The second connection wiring 42 is arranged at the same position in the X direction as the second lower arm transistor 12L. These connection wirings 41, 42 extend in the X direction when viewed from the Z direction. The linking wiring 43 is provided between the first connection wiring 41 and the second connection wiring 42 in the X direction. The terminal connection portion 44 extends from the linking wiring 43 toward the fourth substrate side surface 26. The ground terminal TN is connected to the terminal connection portion 44.

[0077] 10, the conduction path of the first lower arm transistor 11L and the second lower arm transistor 12L connected in parallel in the semiconductor module 10 includes first to third drain inductances de1 to de3, first to fifth source inductances se1 to se5, a first gate inductance ge1, and a second gate inductance ge2. Note that, in the following, for the components of the semiconductor module 10, please refer to the components of the semiconductor module 10 shown in FIG.

[0078] The first drain inductance de1 represents the inductance component of the conductive path between the first drain electrode DL1 of the first lower arm transistor 11L in the element mounting portion 51 and the terminal connecting portion 52. The second drain inductance de2 represents the inductance component of the conductive path between the second drain electrode DL2 of the second lower arm transistor 12L in the element mounting portion 51 and the terminal connecting portion 52. The third drain inductance de3 represents the inductance component of the terminal connecting portion 52.

[0079] The first source inductance se1 represents the inductance component of the source wire WSL connecting the first source electrode SL1 of the first lower arm transistor 11L and the first connection wiring 41 of the second power supply wiring 40. The second source inductance se2 represents the inductance component of the conductive path between the source wire WSL and the terminal connection portion 44 of the first connection wiring 41 and the linking wiring 43. The fourth source inductance se4 represents the inductance component of the source wire WSL connecting the second source electrode SL2 of the second lower arm transistor 12L and the second connection wiring 42. The third source inductance se3 represents the inductance component of the conductive path between the source wire WSL connected to the second connection wiring 42 and the terminal connection portion 44 of the second connection wiring 42 and the linking wiring 43. The fifth source inductance se5 represents the inductance component of the terminal connection portion 44.

[0080] The first gate inductance ge1 represents the inductance component of the gate wire WGL connecting the first gate electrode GL1 of the first lower arm transistor 11L and the second gate wiring 62. The second gate inductance ge2 represents the inductance component of the gate wire WGL connecting the second gate electrode GL2 of the second lower arm transistor 12L and the second gate wiring 62. It is assumed that the inductance component of the second gate wiring 62 is negligibly small compared to the gate inductances ge1 and ge2.

[0081] Next, the ratio (ω p2 / ω zThe simulation results when the gate-source voltage V gs and the gate-source voltage V of the second lower arm transistor 12L. gs 11 to 13, the gate-source voltage V of the first lower arm transistor 11L fluctuates in the same manner, although the phases are shifted. gs The figure shows the trends in the following.

[0082] Figure 11 shows the ratio (ω p2 / ω z ) is 0.3, the gate-source voltage V gs As can be seen from FIG. 11, the gate-source voltage V gs is oscillating abnormally. Therefore, the ratio (ω p2 / ω z ) is 0.3, a very large parallel oscillation occurs when the transistors 11L and 12L are turned off.

[0083] Figure 12 shows the ratio (ω p2 / ω z 12 shows the transition of the gate-source voltage Vgs of the first lower arm transistor 11L when the gate-source voltage Vgs of the first lower arm transistor 11L is 0.375. gs However, the amplitude of the oscillation is proportional to the ratio (ω p2 / ω z ) is smaller than when it is 0.3. Therefore, the ratio (ω p2 / ω z When the ratio (ω) is 0.375, parallel oscillation occurs when the transistors 11L and 12L are turned off, but the amplitude is small. p2 / ω z ) is 0.375, the ratio (ω p2 / ω z ) is 0.3, it can be said that parallel oscillation when the transistors 11L and 12L are turned off is suppressed.

[0084] Figure 13 shows the ratio (ω p2 / ω z ) is 0.55, the gate-source voltage V gs As can be seen from FIG. 13, the gate-source voltage V gs is not oscillating. Therefore, the ratio (ω p2 / ω z When the ratio (ω) is 0.55, no parallel oscillation occurs when the transistors 11L and 12L are turned off. p2 / ω z ) is greater than 0.3, parallel oscillation can be suppressed when the transistors 11L and 12L are turned off. Note that, although the parallel oscillation when the transistors 11L and 12L are turned off has been described in FIGS. 11 to 13, the ratio (ω p2 / ω z ) is greater than 0.3, parallel oscillation can be suppressed.

[0085] In this way, the semiconductor module 10 is p2 / ω z ) is configured to be greater than 0.3, the amplitude of parallel oscillation when the transistors 11L and 12L are turned off and on can be reduced. p2 / ω z ) is 0.55 or more, parallel oscillation can be suppressed when the transistors 11L and 12L are turned off and on.

[0086] That is, the semiconductor module 10 has a second pole frequency ω p2 and zero-point frequency ω z By configuring the absolute value of the phase delay between the transistors 11L and 12L to be smaller than 180°, parallel oscillation can be suppressed when the transistors 11L and 12L are turned off and on.

[0087] In the semiconductor module 10, the second pole frequency ω p2 and zero-point frequency ω z The capacitance ratio (C dg / C ds ), gate inductance L gg , drain inductance L dd , and the source inductance L ss That is, in the semiconductor module 10, the capacitance ratio (C dg / C ds ), gate inductance L gg , drain inductance L dd , and the source inductance L ss The second pole frequency ω can be adjusted by adjusting at least one of p2 and zero-point frequency ω z The absolute value of the phase delay between the source inductance L and the source inductance L can be made smaller than 180°. ss By changing the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the first and second inputs can be made smaller than 180°.

[0088] In one example, in the semiconductor module 10, the ratio (ω p2 / ω z The configuration and size of each of the transistors 11U, 12U, 11L, and 12L, the length, diameter, and number of the gate wires WGU and WGL, the shape and size of the first power supply wiring 30, the second power supply wiring 40, and the output wiring 50, and the length, diameter, and number of the source wires WSU and WSL are determined so that the capacitance ratio (C dg / C ds ), gate inductance L gg , drain inductance L dd, and the source inductance L ss By adjusting at least one of the ratios (ω p2 / ω z ) can be greater than 0.3 or can be 0.55 or greater.

[0089] As an example, in the semiconductor module 10, the source inductance L ss By changing the ratio (ω p2 / ω z ) is greater than 0.3 or 0.55 or greater. In the semiconductor module 10, the wire diameter, length, and number of the source wires WSL can be configured to satisfy the ratio (ω p2 / ω z ) is configured to be greater than 0.3 or to be 0.55 or greater. In the semiconductor module 10 of the first embodiment, there is one source wire WSL, but the ratio (ω p2 / ω z ) is greater than 0.3 or 0.55 or greater. In this case, the plurality of source wires WSL extend in the X direction. The plurality of source wires WSL are arranged side by side in the Y direction. Here, the X direction is an example of the "first direction." The Y direction is an example of the "second direction."

[0090] [Effects of the first embodiment] (1-1) The semiconductor module 10 includes a first lower arm transistor 11L and a second lower arm transistor 12L connected in parallel to each other. A parallel resonant circuit of the first lower arm transistor 11L and the second lower arm transistor 12L has a first pole frequency ω p1 and the first pole frequency ω p1 Second pole frequency ω higher than p2 and the zero point frequency ω z and the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the two is set to be smaller than 180°.

[0091] With this configuration, the second pole frequency ω p2 and zero-point frequency ω z Since the absolute value of the phase delay between the first lower arm transistor 11L and the second lower arm transistor 12L is smaller than 180°, parallel oscillation can be suppressed when the first lower arm transistor 11L and the second lower arm transistor 12L are turned on and off.

[0092] (1-2) The parasitic inductance of the conductive path between the first source electrode SL1 of the first lower arm transistor 11L and the second source electrode SL2 of the second lower arm transistor 12L is defined as the source inductance L ss Then, the second pole frequency ω p2 is the source inductance L ss The source inductance L is a parameter that changes depending on the ss is the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the two is set to be smaller than 180°.

[0093] According to this configuration, the source inductance L ss By changing the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the first lower arm transistor 11L and the second lower arm transistor 12L can be made smaller than 180°, thereby making it possible to suppress the occurrence of parallel oscillation when the first lower arm transistor 11L and the second lower arm transistor 12L are turned on and off.

[0094] (1-3) Zero point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3. According to this configuration, the ratio (ω p2 / ω z Since the semiconductor module 10 is configured so that the ratio (ω p2 / ω z) is less than 0.3, the occurrence of parallel oscillation can be suppressed when the first lower arm transistor 11L and the second lower arm transistor 12L are turned on and off.

[0095] (1-4) Zero point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or greater. According to this configuration, the ratio (ω p2 / ω z ) is 0.55 or more, the occurrence of parallel oscillation can be reduced to substantially zero when the first lower arm transistor 11L and the second lower arm transistor 12L are turned on and off.

[0096] (1-5) The semiconductor module 10 includes a source wire WSL connected to the first source electrode SL1 of the first lower arm transistor 11L and the fourth source electrode SL4 of the second lower arm transistor 12L. The source wire WSL has a capacitance of 1.5 V at a ratio (ω p2 / ω z ) is greater than 0.3.

[0097] According to this configuration, the source inductance L ss can be easily changed by changing the length, diameter, and number of source wires WSL. Therefore, by changing the length, diameter, and number of source wires WSL, the ratio (ω p2 / ω z ) can be easily adjusted to be greater than 0.3. This allows the ratio (ω p2 / ω z ) is greater than 0.3, the source inductance L ssTherefore, parallel oscillation of the semiconductor module 10 can be easily suppressed without making any major design changes.

[0098] (1-6) The semiconductor module 10 includes a source wire WSL connected to the first source electrode SL1 of the first lower arm transistor 11L and the fourth source electrode SL4 of the second lower arm transistor 12L. The source wire WSL has a capacitance of 1.5 V at a ratio (ω p2 / ω z The wires are connected to the first source electrode SL1, the second source electrode SL2, and the second power supply wiring 40 with lengths, wire diameters, and numbers that satisfy the relationship that the difference between the first source electrode SL1, the second source electrode SL2, and the second power supply wiring 40 is 0.55 or more.

[0099] According to this configuration, the source inductance L ss can be easily changed by changing the length, diameter, and number of source wires WSL. Therefore, by changing the length, diameter, and number of source wires WSL, the ratio (ω p2 / ω z ) to be 0.55 or more. This makes it possible to adjust the ratio (ω p2 / ω z ) is 0.55 or more, the source inductance L ss Therefore, parallel oscillation of the semiconductor module 10 can be easily suppressed without making any major design changes.

[0100] Second Embodiment The configuration of the semiconductor module 10 of the second embodiment will be described with reference to Figures 14 and 15. The semiconductor module 10 of the second embodiment differs from the semiconductor module 10 of the first embodiment mainly in the number of upper arm transistors and the number of lower arm transistors. In the following, components common to the components of the semiconductor module 10 of the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0101] 14 is a schematic diagram showing the planar structure of the semiconductor module 10 of the second embodiment, and FIG. 15, the semiconductor module 10 includes first to fourth upper arm transistors 11U to 14U connected in parallel to each other as an upper arm circuit, and first to fourth lower arm transistors 11L to 14L connected in parallel to each other as a lower arm circuit. Here, in the second embodiment, the first lower arm transistor 11L is an example of a "first transistor," and the second lower arm transistor 12L or the fourth lower arm transistor 14L is an example of a "second transistor."

[0102] The first to fourth drain electrodes DU1 to DU4 of the first to fourth upper arm transistors 11U to 14U are electrically connected to each other and to a power supply terminal TP. The first to fourth source electrodes SU1 to SU4 of the first to fourth upper arm transistors 11U to 14U are electrically connected to each other and to an output terminal TO. The first to fourth gate electrodes GU1 to GU4 of the first to fourth upper arm transistors 11U to 14U are electrically connected to each other and to a first gate terminal TG1.

[0103] The first to fourth drain electrodes DL1 to DL4 of the first to fourth lower arm transistors 11L to 14L are electrically connected to each other and to the first to fourth source electrodes SU1 to SU4 of the first to fourth upper arm transistors 11U to 14U. The first to fourth drain electrodes DL1 to DL4 are electrically connected to the output terminal TO. The first to fourth source electrodes SL1 to SL4 of the first to fourth lower arm transistors 11L to 14L are electrically connected to each other and to the ground terminal TN. The first to fourth gate electrodes GL1 to GL4 of the first to fourth lower arm transistors 11L to 14L are electrically connected to each other and to the second gate terminal TG2.

[0104] 14, similar to the semiconductor module 10 of the first embodiment (see FIG. 1), the semiconductor module 10 includes a substrate 20, and a first power supply wiring 30, a second power supply wiring 40, and an output wiring 50 provided on a first substrate surface 21 of the substrate 20. The configurations of the substrate 20, the first power supply wiring 30, the second power supply wiring 40, and the output wiring 50 are similar to those of the semiconductor module 10 shown in FIG. 1, and therefore description thereof will be omitted.

[0105] Here, the first power supply wiring 30 is an example of a "drain wiring" corresponding to each of the upper arm transistors 11U and 12U, the output wiring 50 is an example of a "source wiring" corresponding to each of the upper arm transistors 11U and 12U, and the first gate wiring 61 is an example of a "gate wiring" corresponding to each of the upper arm transistors 11U and 12U. Also, the output wiring 50 is an example of a "drain wiring" corresponding to each of the lower arm transistors 11L and 12L, the second power supply wiring 40 is an example of a "source wiring" corresponding to each of the lower arm transistors 11L and 12L, and the second gate wiring 62 is an example of a "gate wiring" corresponding to each of the lower arm transistors 11L and 12L.

[0106] The first to fourth upper arm transistors 11U to 14U are mounted on an element mounting portion 31 of the first power supply wiring 30. The first to fourth upper arm transistors 11U to 14U are joined to the element mounting portion 31 by a conductive bonding material SD, similar to the semiconductor module 10 of the first embodiment. As a result, the first to fourth drain electrodes DU1 to DU4 of the first to fourth upper arm transistors 11U to 14U are electrically connected to the first power supply wiring 30. The first to fourth upper arm transistors 11U to 14U are arranged at the same positions as one another in the Y direction and side by side in the X direction.

[0107] The first to fourth gate electrodes GU1 to GU4 of the first to fourth upper arm transistors 11U to 14U are connected to the first gate wiring 61 by gate wires WGU. The first to fourth source electrodes SU1 to SU4 of the first to fourth upper arm transistors 11U to 14U are connected to one another by source wires WSU extending in the X direction when viewed from the Z direction. Each of the first to fourth source electrodes SU1 to SU4 is connected to the output wiring 50 by a source wire WSU extending in the Y direction when viewed from the Z direction. As a result, each of the first to fourth source electrodes SU1 to SU4 is electrically connected to the output wiring 50.

[0108] The first to fourth lower arm transistors 11L to 14L are mounted on an element mounting portion 51 of an output wiring 50. The first to fourth lower arm transistors 11L to 14L are joined to the element mounting portion 51 by a conductive bonding material SD, similar to the semiconductor module 10 of the first embodiment. As a result, the first to fourth drain electrodes DL1 to DL4 of the first to fourth lower arm transistors 11L to 14L are electrically connected to the output wiring 50. Therefore, the first to fourth drain electrodes DL1 to DL4 are electrically connected to the first to fourth source electrodes SU1 to SU4 of the first to fourth upper arm transistors 11U to 14U via the output wiring 50.

[0109] The first to fourth gate electrodes GL1 to GL4 of the first to fourth lower arm transistors 11L to 14L are connected to the second gate wiring 62 by gate wires WGL, respectively. The first to fourth source electrodes SU1 to SU4 of the first to fourth lower arm transistors 11L to 14L are connected to one another and to the first connection wiring 41 and the second connection wiring 42 of the second power supply wiring 40 by source wires WSL extending in the X direction when viewed from the Z direction. As a result, the first to fourth source electrodes SU1 to SU4 are electrically connected to the second power supply wiring 40. Here, in the second embodiment, the first connection wiring 41 is an example of a "first wiring portion," and the second connection wiring 42 is an example of a "second wiring portion."

[0110] The semiconductor module 10 of the second embodiment has a second pole frequency ω p2 and zero-point frequency ω zThe semiconductor module 10 of the second embodiment is configured so that the absolute value of the phase delay between the p2 / ω z ) is configured to be greater than 0.3. The semiconductor module 10 of the second embodiment is configured such that, for example, the ratio (ω p2 / ω z ) is configured to be 0.55 or greater.

[0111] In the semiconductor module 10 of the second embodiment, similarly to the semiconductor module 10 of the first embodiment, the second pole frequency ω p2 and zero-point frequency ω z The capacitance ratio (C dg / C ds ), gate inductance L gg , drain inductance L dd , and the source inductance L ss That is, in the semiconductor module 10 of the second embodiment, the capacitance ratio (C dg / C ds ), gate inductance L gg , drain inductance L dd , and the source inductance L ss The second pole frequency ω can be adjusted by adjusting at least one of p2 and zero-point frequency ω z The absolute value of the phase delay between the source inductance L and the source inductance L can be made smaller than 180°. ss By changing the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the first and second inputs can be made smaller than 180°.

[0112] As an example, in the semiconductor module 10 of the second embodiment, the ratio (ω p2 / ω zThe configuration and size of each of the transistors 11U to 14U, 11L to 14L, the length, diameter, and number of the gate wires WGU, WGL, the shape and size of the first power supply wiring 30, the second power supply wiring 40, and the output wiring 50, and the length, diameter, and number of the source wires WSU, WSL are determined so that the capacitance ratio (C dg / C ds ), gate inductance L gg , drain inductance L dd , and the source inductance L ss By adjusting at least one of the ratios (ω p2 / ω z ) can be greater than 0.3 or can be 0.55 or greater.

[0113] As an example, in the semiconductor module 10 of the second embodiment, similarly to the semiconductor module 10 of the first embodiment, the source inductance L ss By changing the second pole frequency ω p2 and zero-point frequency ω z In the semiconductor module 10 of the second embodiment, the wire diameter, length, and number of the source wires WSL can be configured so as to satisfy the ratio (ω p2 / ω z ) is greater than 0.3 or is 0.55 or greater. In the semiconductor module 10 of the second embodiment, the ratio (ω p2 / ω z ) is greater than 0.3 or 0.55 or greater. In this case, the plurality of source wires WSL extend in the X direction. The plurality of source wires WSL are arranged side by side in the Y direction.

[0114] <Ratio(ω p2 / ω z ) Adjustment Method> Next, using the semiconductor module 10 of the second embodiment, the ratio (ω p2 / ω z An example of a method for adjusting the capacitance ratio (C gd / C ds ) is set to 0.1, the wire diameter of the gate wire WGL is set to 150 μm, and the wire diameter of the source wire WSL is set to 400 μm. The size of the first to fourth lower arm transistors 11L to 14L in plan view is 5×5 (mm).

[0115] Ratio (ω p2 / ω z ) is the capacitance ratio (C gd / C ds ) and gate inductance L gg , source inductance L ss , and the drain inductance L dd where the capacity ratio (C gd / C ds ) = 0.1, so the gate inductance L gg , source inductance L ss , and the drain inductance L dd By adjusting at least one of the ratios (ω p2 / ω z ) can be adjusted to the desired value.

[0116] Gate inductance L gg and the source inductance L ss The drain inductance L is calculated by adding the parasitic inductance of the wire and the parasitic inductance of the wiring pattern. dd is calculated from the parasitic inductance of the wiring pattern. Here, the parasitic inductance Lw of the wire is calculated using the following equation, and the parasitic inductance Lc of the wiring pattern is calculated using the following equation.

[0117]

number

[0118] Note that "L" is the length of the wire and "a" is the radius of the wire.

[0119]

number

[0120] Here, "L" is the length of the wiring pattern, "w" is the width of the wiring pattern, and "t" is the thickness of the wiring pattern. Here, parallel oscillation of the semiconductor module 10 is likely to occur between transistors with low phase margins among the first to fourth lower arm transistors 11L to 14L. The condition for a low phase margin is when the gate inductance L gg is small, or the source inductance L ss and the drain inductance L dd The gate inductance L gg The source inductance L is small between adjacent transistors among the first to fourth lower arm transistors 11L to 14L. ss and the drain inductance L dd becomes large between the first lower arm transistor 11L and the fourth lower arm transistor 14L.

[0121] First, between adjacent transistors among the first to fourth lower arm transistors 11L to 14L, the gate inductance L between the first lower arm transistor 11L and the second lower arm transistor 12L is gg , drain inductance L dd , and the source inductance L ss The calculation of is explained below.

[0122] Gate inductance L between the first lower arm transistor 11L and the second lower arm transistor 12L ggis the sum of the parasitic inductance of both the gate wire WGL connected to the first lower arm transistor 11L and the gate wire WGL connected to the second lower arm transistor 12L, and the parasitic inductance of the portion of the second gate wiring 62 between the two gate wires WGL.

[0123] Here, the length of the gate wire WGL is 7 mm in the semiconductor module 10. The width of the second gate wiring 62 is 2 mm, and the distance between two gate wires WGL of the second gate wiring 62 is 7 mm.

[0124] Parasitic inductance L of one gate wire WGL w_gg_1 is obtained from the above formula. L w_gg_1 ≒ 0.2 × 7 × (ln(2 × 7 / 0.075)-1) ≒ 5.921 (nH / piece).

[0125] The parasitic inductance L of the second gate wiring 62 c_gg is obtained from the above formula. L c_gg ≒ 0.2 × 7 × (ln(2 × 7) / (2 × 0.07)) + 0.2235 × (2 + 0.07) / 7 + 0.5 ≒ 3.469 (nH).

[0126] Therefore, the gate inductance L gg L gg =5.921×2+3.469=15.311(nH). The drain inductance L between the first lower arm transistor 11L and the second lower arm transistor 12L dd is calculated from the parasitic inductance of the portion of the output wiring 50 between the first lower arm transistor 11L and the second lower arm transistor 12L. dd is obtained from the above formula. L dd ≒ 0.2 × 2 × (ln(2 × 2) / (5 × 0.07)) + 0.2235 × (5 + 0.07) / 2 + 0.5 ≒ 0.332 (nH).

[0127] Here, the length of the portion of the output wiring 50 between the first lower arm transistor 11L and the second lower arm transistor 12L is set to 2 mm, and the width is set to 5 mm. Source inductance L ss is the sum of the parasitic inductance of the source wire WSL connected to the first lower arm transistor 11L and the source wire WSL connected to the second lower arm transistor 12L, and the parasitic inductance between the above two source wires WSL of the second power supply wiring 40 and the ground terminal TN.

[0128] Here, the length of the source wire WSL between the first lower arm transistor 11L and the second lower arm transistor 12L is 7 mm. The total length of the connection portion of the source wire WSL between the first lower arm transistor 11L and the first connection wiring 41 and the connection portion of the second lower arm transistor 12L and the second connection wiring 42 is 38 mm. The width (dimension in the X direction) of each of the first connection wiring 41, the second connection wiring 42, and the linking wiring 43 of the second power supply wiring 40 is 5 mm, and the length of the second power supply wiring 40 from both ends of the source wire WSL in the X direction to the terminal connection portion 44 is 120 mm.

[0129] The parasitic inductance L of the source wire WSL between the first lower arm transistor 11L and the second lower arm transistor 12L w_ss_1 is obtained from the above formula. L w_ss_1 ≒ 0.2 × 7 × (ln(2 × 7 / 0.2)-1) ≒ 4.548 (nH / piece).

[0130] The total parasitic inductance L of the connection part of the source wire WSL between the first lower arm transistor 11L and the first connection wiring 41 and the connection part of the source wire WSL between the second lower arm transistor 12L and the second connection wiring 42 is w_ss_2 is obtained from the above formula. L w_ss_2 ≒ 0.2 × 38 × (ln(2 × 38 / 0.2)-1) ≒ 37.545 (nH / piece).

[0131] The parasitic inductance L of the second power supply wiring 40c_ss is obtained from the above formula. L c_ss ≒ 0.2 × 120 × (ln(2 × 120) / (5 × 0.07)) + 0.2235 × (5 + 0.07) / 120 + 0.5 ≒ 104.802 (nH).

[0132] Here, as an example, in the semiconductor module 10, the ratio (ω p2 / ω z A method for setting the value of the parasitic inductance L between the first lower arm transistor 11L and the second lower arm transistor 12L will be described. The number of source wires WSL is set to N (number of wires). In this case, the parasitic inductance L of the N source wires WSL between the first lower arm transistor 11L and the second lower arm transistor 12L is set to N (number of wires). w_ss_1N L w_ss_1N =4.548 / N (nH / wire). In addition, the total parasitic inductance L of the connection part between the first lower arm transistor 11L and the first connection wiring 41 and the connection part between the second lower arm transistor 12L and the second connection wiring 42 among the N source wires WSL is w_ss_2N L w_ss_2N = 37.545 / N (nH / wire). Therefore, the parasitic inductance L ssg L ssg = 37.545 / N + 104.802 (nH). And the source inductance L ss L ss =L w_ss_1 / / L ssg Therefore, L ss =4.548×(37.545+104.802N) / (N(42.093+104.802N))≒(170.755+476.639N) / (42.093N+104.802N 2 )

[0133] These gate inductances L gg , drain inductance L dd , and the source inductance L ss and the capacitance ratio (C gd / C ds ) = 0.1, and the ratio (ωp2 / ω z The number N of source wires WSL for which ω p2 / ω z ) and N≧0.62. In other words, it is sufficient that there is one or more source wires WSL.

[0134] Next, the gate inductance L between the first lower arm transistor 11L and the fourth lower arm transistor 14L is gg , drain inductance L dd , and the source inductance L ss The calculation of is explained below.

[0135] The gate inductance L between the first lower arm transistor 11L and the fourth lower arm transistor 14L gg is calculated as the sum of the parasitic inductances of the gate wire WGL connected to the first lower arm transistor 11L and the gate wire WGL connected to the fourth lower arm transistor 14L, and the parasitic inductance of the second gate wiring 62 between these gate wires WGL. Here, the length in the X direction between the gate wire WGL connected to the first lower arm transistor 11L and the gate wire WGL connected to the fourth lower arm transistor 14L of the second gate wiring 62 is 21 mm.

[0136] Parasitic inductance L of one gate wire WGL w_gg_1 As mentioned above, L w_gg_1 ≒ 5.921 (nH / piece). The parasitic inductance L of the second gate wiring 62 c_gg is obtained from the above formula. L c_gg ≒ 0.2 × 21 × (ln(2 × 21) / (2 × 0.07)) + 0.2235 × (2 + 0.07) / 21 + 0.5 ≒ 14.835 (nH).

[0137] Therefore, the gate inductance L gg L gg =5.921×2+14.835=26.677(nH). The drain inductance L between the first lower arm transistor 11L and the fourth lower arm transistor 14L dd is the parasitic inductance L of the portion of the output wiring 50 between the first lower arm transistor 11L and the fourth lower arm transistor 14L. c_dd Here, the width (dimension in the Y direction) of the portion of the output wiring 50 between the first lower arm transistor 11L and the fourth lower arm transistor 14L is 5 mm, and the length (dimension in the X direction) of the portion of the output wiring 50 between the first lower arm transistor 11L and the fourth lower arm transistor 14L is 16 mm.

[0138] Therefore, the parasitic inductance L c_dd L c_dd ≒0.2×16×(ln(2×16) / (5×0.07))+0.2235×(5+0.07) / 16+0.5≒7.722(nH). Therefore, the drain inductance L dd =7.772(nH).

[0139] Source inductance L ss is the sum of the parasitic inductance of the source wire WSL connected to the first lower arm transistor 11L and the source wire WSL connected to the fourth lower arm transistor 14L, and the parasitic inductance between the above two source wires WSL of the second power supply wiring 40 and the ground terminal TN.

[0140] Here, the length of the source wire WSL between the first lower arm transistor 11L and the fourth lower arm transistor 14L is 21 mm. The total length of the connection portion of the source wire WSL between the first lower arm transistor 11L and the first connection wiring 41 and the connection portion of the fourth lower arm transistor 14L and the second connection wiring 42 is 24 mm. The width (dimension in the X direction) of each of the first connection wiring 41, the second connection wiring 42, and the linking wiring 43 of the second power supply wiring 40 is 5 mm, and the length of the second power supply wiring 40 from both ends of the source wire WSL in the X direction to the terminal connection portion 44 is 120 mm.

[0141] The parasitic inductance L of the source wire WSL between the first lower arm transistor 11L and the fourth lower arm transistor 14L w_ss_1 L w_ss_1 ≒ 0.2 × 21 × (ln(2 × 21 / 0.2)-1) ≒ 18.258 (nH / piece).

[0142] The total parasitic inductance L of the connection part of the source wire WSL between the first lower arm transistor 11L and the first connection wiring 41 and the connection part of the source wire WSL between the fourth lower arm transistor 14L and the second connection wiring 42 is w_ss_2 L w_ss_2 ≒ 0.2 × 24 × (ln(2 × 24 / 0.2)-1) ≒ 21.507 (nH / piece).

[0143] The parasitic inductance L of the second power supply wiring 40 c_ss L c_ss ≒ 0.2 × 120 × (ln(2 × 120) / (5 × 0.07)) + 0.2235 × (5 + 0.07) / 120 + 0.5 ≒ 104.802 (nH).

[0144] Here, if the number of source wires WSL is N (number of wires), the parasitic inductance L of the N source wires WSL between the first lower arm transistor 11L and the second lower arm transistor 12L is w_ss_1N L w_ss_1N =18.258 / N (nH / wire). In addition, the total parasitic inductance L of the connection part between the first lower arm transistor 11L and the first connection wiring 41 and the connection part between the fourth lower arm transistor 14L and the second connection wiring 42 among the N source wires WSL is w_ss_2N L w_ss_2N = 21.507 / N (nH / wire). Therefore, the parasitic inductance L of the path electrically connected to the ground terminal TN ssg L ssg = 21.507 / N + 104.802 (nH). And the source inductance L ss L ss =L w_ss_1 / / L ssg Therefore, Lss =18.258×(21.507+104.802N) / (N(39.765+104.802N))≒(392.675+1913.475N) / (39.765N+104.802N 2 )

[0145] These gate inductances L gg , drain inductance L dd , and the source inductance L ss and the capacitance ratio (C gd / C ds ) = 0.1, and the ratio (ω p2 / ω z The number N of source wires WSL for which ω p2 / ω z ) and N≧4.16. In other words, the number of source wires WSL needs to be five or more.

[0146] Thus, the gate inductance L gg The ratio (ω p2 / ω z ) is 0.55 or more, the number of source wires WSL is one. In this case, however, there is a risk of parallel oscillation occurring due to the parasitic inductance between the first lower arm transistor 11L and the fourth lower arm transistor 14L. ss and the drain inductance L dd The ratio (ω p2 / ω z ) is 0.55 or more is 5. Therefore, if five source wires WSL are provided in the semiconductor module 10, the occurrence of parallel oscillation can be suppressed.

[0147] [Effects of the second embodiment] According to the semiconductor module 10 of the second embodiment, the following effects can be obtained. (2-1) The semiconductor module 10 includes first to fourth lower arm transistors 11L to 14L connected in parallel to one another. A parallel resonant circuit of the first to fourth lower arm transistors 11L to 14L has a first pole frequency ω p1 and the first pole frequency ω p1 Second pole frequency ω higher than p2 and the zero point frequency ω z and the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the two is set to be smaller than 180°.

[0148] According to this configuration, the semiconductor module 10 has a second pole frequency ω p2 and zero-point frequency ω z Since the absolute value of the phase delay between the first and fourth lower arm transistors 11L to 14L is smaller than 180°, parallel oscillation can be suppressed when the first to fourth lower arm transistors 11L to 14L are turned on and off.

[0149] (2-2) The parasitic inductance of the conductive path between the first source electrode SL1 of the first lower arm transistor 11L and the fourth source electrode SL4 of the fourth lower arm transistor 14L is defined as the source inductance L ss Then, the second pole frequency ω p2 is the source inductance L ss The source inductance L is a parameter that changes depending on the ss is the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the two is set to be smaller than 180°.

[0150] According to this configuration, the source inductance L ss By changing the second pole frequency ω p2 and zero-point frequency ω zThe absolute value of the phase delay between the first and fourth lower arm transistors 11L to 14L can be made smaller than 180°, thereby making it possible to suppress the occurrence of parallel oscillation when the first to fourth lower arm transistors 11L to 14L are turned on and off.

[0151] (2-3) Zero point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3. According to this configuration, the semiconductor module 10 has a ratio (ω p2 / ω z ) is configured to be greater than 0.3, so the ratio (ω p2 / ω z ) is less than 0.3, the occurrence of parallel oscillation can be suppressed when the first to fourth lower arm transistors 11L to 14L are turned on and off.

[0152] (2-4) Zero point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or greater. According to this configuration, the semiconductor module 10 has a ratio (ω p2 / ω z ) is 0.55 or more, it is possible to reduce the occurrence of parallel oscillation to substantially zero when the first to fourth lower arm transistors 11L to 14L are turned on and off.

[0153] (2-5) The semiconductor module 10 includes a plurality of source wires WSL connected to the first to fourth source electrodes SL1 to SL4 of the first to fourth lower arm transistors 11L to 14L. The plurality of source wires WSL have the same length and the same wire diameter. The plurality of source wires WSL are arranged at a ratio (ω p2 / ω z The first to fourth source electrodes SL1 to SL4 and the second power supply wiring 40 are connected in numbers that satisfy the relationship that the difference between the number of source electrodes SL1 and SL4 is 0.55 or more.

[0154] According to this configuration, the source inductance L ss can be easily changed by changing the number of source wires WSL. Therefore, by changing the number of source wires WSL, the ratio (ω p2 / ω z ) to be 0.55 or more. This makes it possible to adjust the ratio (ω p2 / ω z ) is 0.55 or more, the source inductance L ss Therefore, parallel oscillation of the semiconductor module 10 can be easily suppressed without making any major design changes.

[0155] (2-6) The lengths of the gate wires WGL connected to the first to fourth gate electrodes GL1 to GL4 of the first to fourth lower arm transistors 11L to 14L, respectively, are equal to each other. This configuration can prevent variations from occurring in the preset timings of the gate voltages applied to the first to fourth gate electrodes GL1 to GL4 of the first to fourth lower arm transistors 11L to 14L.

[0156] (Example of application of semiconductor modules) The semiconductor module 10 can be applied to an inverter device for vehicles such as electric vehicles, hybrid vehicles, and electrically assisted bicycles. This inverter device may be, for example, an inverter device for supplying current to the U-phase coil, V-phase coil, and W-phase coil of a three-phase brushless motor serving as a drive source. The inverter device includes a U-phase arm section that supplies current to the U-phase coil, a V-phase arm section that supplies current to the V-phase coil, and a W-phase arm section that supplies current to the W-phase coil. Each arm section constitutes, for example, a half-bridge inverter circuit. The semiconductor module 10 may be applied to each of the U-phase arm section, the V-phase arm section, and the W-phase arm section.

[0157] <Example of change> The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0158] In the semiconductor module 10 of the above embodiment, the ratio (ω p2 / ω z Although the number of source wires WSL was adjusted to make the ratio (ω ) 0.55 or more, the parameters related to the source wires WSL are not limited to the number. For example, at least one of the wire diameter and length of the source wires WSL may be changed. p2 / ω z The wire diameter, length, and number of the source wires WSL may be adjusted so that the difference (%) is 0.55 or more.

[0159] In the semiconductor module 10 of the above embodiment, the ratio (ω p2 / ω z ) to be 0.55 or more, the number of source wires WSL was adjusted, but the ratio (ω p2 / ω z The method for adjusting the ratio (ω) is not limited to the source wire WSL. For example, the ratio (ω) can be adjusted by changing the shape and size of the second power supply wiring 40. p2 / ω z ) may be set to 0.55 or more. p2 / ω z ) is the source inductance L ss Not only the adjustment of the gate inductance L gg and the drain inductance L dd At least one of these may be adjusted.

[0160] In the semiconductor module 10 of the above embodiment, when a plurality of source wires WSL are provided, the wire diameters of the plurality of source wires WSL may be different from one another. In the semiconductor module 10 of the above embodiment, when a plurality of source wires WSL are provided, the lengths of the plurality of source wires WSL may be different from one another.

[0161] In the semiconductor module 10 of the above embodiment, when a plurality of source wires WSU are provided connected to the first to fourth upper arm transistors 11U to 14U, the wire diameters of the plurality of source wires WSU may be different from one another.

[0162] In the semiconductor module 10 of the above embodiment, when a plurality of source wires WSU are provided, the lengths of the plurality of source wires WSU may be different from one another. In the semiconductor module 10 of the above embodiment, the length of the gate wire WGL connected to the first lower arm transistor 11L may be different from the length of the gate wire WGL connected to the second lower arm transistor 12L. The length of the gate wire WGL connected to the first lower arm transistor 11L may be different from the length of the gate wire WGL connected to the fourth lower arm transistor 14L. The lengths of the gate wires WGL connected to the first to fourth lower arm transistors 11L to 14L may be different from each other.

[0163] In the semiconductor module 10 of the above embodiment, the wire diameters of the gate wires WGL connected to the first to fourth lower arm transistors 11L to 14L may be different from one another.

[0164] In the semiconductor module 10 of the above embodiment, the wire diameters of the gate wires WGU connected to the first to fourth upper arm transistors 11U to 14U may be different from one another.

[0165] In the semiconductor module 10 of the above embodiment, the lengths of the gate wires WGU connected to the first to fourth upper arm transistors 11U to 14U may be different from one another.

[0166] In the semiconductor module 10 of the above embodiment, the ratio (ω p2 / ω z When calculating the capacity ratio (C gd / C ds) is set to 0.1, but is not limited to this. For example, the zero point frequency ω z In order to change the parasitic capacitance C between the gate and the drain of the first to fourth lower arm transistors 11L to 14L, gd In this case, the parasitic capacitance C gd is the second pole frequency ω p2 and zero-point frequency ω z The absolute value of the phase delay between the first and second inputs is set to be smaller than 180°.

[0167] In the semiconductor module 10 of the above embodiment, the ratio (ω p2 / ω z The number of source wires WSL is set so that the ratio (ω) is 0.55 or more, but this is not limited to this. p2 / ω z The number of source wires WSL may be set so that the ratio (ω ) is greater than 0.3. In this case, the lengths of the plurality of source wires WSL are equal to each other, and the wire diameters of the plurality of source wires WSL are equal to each other. In addition, as an example, p2 / ω z The wire diameter, length, and number of the source wires WSL may be set so that the difference (%) is greater than 0.3.

[0168] In the semiconductor module 10 of the above embodiment, the ratio (ω p2 / ω z ) is 0.55 or more, the gate inductances L gg , source inductance L ss , and the drain inductance L dd In one example, the ratio (ω p2 / ω z The number of source wires WSU of the first to fourth upper arm transistors 11U to 14U may be changed so that the ratio (ω) is 0.55 or more. In this case, the lengths of the source wires WSU are equal to each other, and the wire diameters of the source wires WSU are equal to each other. In addition, as an example, p2 / ω zThe wire diameter, length, and number of the source wires WSU may be set so that the difference (%) is 0.55 or more.

[0169] In the semiconductor module 10 of the above embodiment, the ratio (ω p2 / ω z ) is set to be greater than 0.3. gg , source inductance L ss , and the drain inductance L dd In one example, the ratio (ω p2 / ω z The number of source wires WSU of the first to fourth upper arm transistors 11U to 14U may be changed so that the ratio (ω) is greater than 0.3. In this case, the lengths of the source wires WSU are equal to one another, and the wire diameters of the source wires WSU are equal to one another. In addition, as an example, p2 / ω z The wire diameter, length, and number of the source wires WSU may be set so that the difference (%) is greater than 0.3.

[0170] In the semiconductor module 10 of the above embodiment, the ratio (ω p2 / ω z ) may be less than 1. That is, the ratio (ω p2 / ω z ) may be greater than 0.3 and less than 1 (0.3<(ω p2 / ω z )<1). Also, the ratio (ω p2 / ω z ) may be 0.55 or more and less than 1 (0.55≦(ω p2 / ω z )<1). In addition, in the semiconductor module 10, the ratio (ω p2 / ω z ) may be greater than 1.

[0171] In the semiconductor module 10 of the above embodiment, the source connection member connecting the first source electrode SU1 of the first upper arm transistor 11U and the second source electrode SU2 of the second upper arm transistor 12U is not limited to the source wire WSU. For example, the source connection member may be a ribbon, a clip, or a bus bar instead of the source wire WSU. Similarly, the source connection member connecting the third source electrode SU3 of the third upper arm transistor 13U and the fourth source electrode SU4 of the fourth upper arm transistor 14U may be a ribbon, a clip, or a bus bar instead of the source wire WSU. In this way, the source connection member may be any member that can electrically connect the first to fourth source electrodes SU1 to SU4.

[0172] In this case, in one example, the source connection member is connected to the zero point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3. z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more. Here, the size of each source connection member may be, for example, the length, width, and thickness of the source connection member. The sizes of the multiple source connection members may be the same or different from each other. In one example, when the multiple source connection members are the same size, the multiple source connection members are connected to the first source electrode SU1, the second source electrode SU2 (or any of the second source electrodes SU2 to SU4), and the output wiring 50 in such a manner that the zero-point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z) is greater than 0.3, the source connection members are connected to the first source electrode SU1, the second source electrode SU2 (or any of the second source electrodes SU2 to SU4), and the output wiring 50. In another example, when the plurality of source connection members are of the same size, the source connection members are connected to the first source electrode SU1, the second source electrode SU2 (or any of the second source electrodes SU2 to SU4), and the output wiring 50 in such a manner that the zero-point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more, the first source electrode SU1, the second source electrode SU2 (or any of the second source electrodes SU2 to SU4), and the output wiring 50.

[0173] In the semiconductor module 10 of the above embodiment, the source connection member connecting the first source electrode SL1 of the first lower arm transistor 11L and the second source electrode SL2 of the second lower arm transistor 12L is not limited to the source wire WSL. For example, the source connection member may be a ribbon, a clip, or a bus bar instead of the source wire WSL. Similarly, the source connection member connecting the third source electrode SL3 of the third lower arm transistor 13L and the fourth source electrode SL4 of the fourth lower arm transistor 14L may be a ribbon, a clip, or a bus bar instead of the source wire WSL. In this way, the source connection member may be any member that can electrically connect the first to fourth source electrodes SL1 to SL4.

[0174] In this case, in one example, the source connection member is connected to the zero point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3. z Second pole frequency ω p2 The ratio (ω p2 / ω z) is 0.55 or more. Here, the size of each source connection member may be, for example, the length, width, and thickness of the source connection member. The sizes of the multiple source connection members may be the same or different from each other. In one example, when the multiple source connection members are the same size, the multiple source connection members are connected to the first source electrode SL1, the second source electrode SL2 (or any of the second source electrodes SL2 to SL4), and the second power supply wiring 40 in such a manner that the zero-point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3. In another example, when a plurality of source connection members are of the same size, the source connection members may be connected to the first source electrode SL1, the second source electrode SL2 (or any of the second source electrodes SL2 to SL4), and the second power supply wiring 40 in such a manner that the zero-point frequency ω z Second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more.

[0175] In the semiconductor module 10 of the above embodiment, the number of lower arm transistors can be changed as desired. For example, the number of lower arm transistors may be six. Also, for example, the number of lower arm transistors may be eight.

[0176] In the semiconductor module 10 of the above embodiment, the number of upper arm transistors can be changed as desired. For example, the number of upper arm transistors may be six. Also, for example, the number of upper arm transistors may be eight.

[0177] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0178] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this disclosure being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0179] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0180] [Appendix 1] The device includes a first transistor (11L / 11U) and a second transistor (12L, 12L to 14L / 12U, 12U to 14U) connected in parallel with each other, The parallel resonant circuit of the first transistor (11L / 11U) and the second transistor (12L, 12L to 14L / 12U, 12U to 14U) is 1st pole frequency ω p1 and, The first pole frequency ω p1 Second pole frequency ω higher than p2 and, Zero point frequency ω z and, It has The second pole frequency ω p2 and the zero point frequency ω z The absolute value of the phase delay at A semiconductor module (10).

[0181] [Appendix 2] The parasitic inductance of the conductive path between the first source electrode (SL1 / SU1) of the first transistor (11L / 11U) and the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4) of the second transistor (12L, 12L to 14L / 12U, 12U to 14U) is L ss In this case, The second pole frequency ω p2 is the parasitic inductance L ss is a parameter that changes depending on The parasitic inductance L ss is the second pole frequency ω p2 and the zero point frequency ω z The absolute value of the phase delay at 2. The semiconductor module of claim 1.

[0182] [Appendix 3] The parasitic capacitance between the gate and drain of the first transistor (11L / 11U) or the second transistor (12L, 12L to 14L / 12U, 12U to 14U) is C gd In this case, The zero point frequency ω z is the parasitic capacitance C gd is a parameter that changes depending on The parasitic capacitance C gd is the second pole frequency ω p2 and the zero point frequency ω z The absolute value of the phase delay at 2. The semiconductor module of claim 1.

[0183] [Appendix 4] The zero point frequency ω zThe second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3 4. The semiconductor module according to claim 1.

[0184] [Appendix 5] The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than or equal to 0.55 4. The semiconductor module according to claim 1.

[0185] [Appendix 6] the first transistor (11L / 11U) includes a first gate electrode (GL1 / GU1), a first drain electrode (DL1 / DU1), and the first source electrode (SL1 / SU1); the second transistors (12L, 12L to 14L / 12U, 12U to 14U) include second gate electrodes (GL2, GL2 to GL4 / GU2, GU2 to GU4), second drain electrodes (DL2, DL2 to DL4 / DU2, DU2 to DU4), and the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), a drain wiring (50 / 30) to which the first drain electrode (DL1 / DU1) and the second drain electrodes (DL2, DL2 to DL4 / DU2, DU2 to DU4) are electrically connected; a source wiring (40 / 50) that is disposed apart from the drain wiring (50 / 30) and to which the first source electrode (SL1 / SU1) and the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4) are electrically connected; a gate wiring (62 / 61) disposed apart from both the drain wiring (50 / 30) and the source wiring (40 / 50) and electrically connected to the first gate electrode (GL1 / GU1) and the second gate electrode (GL2, GL2 to GL4 / GU1, GU2 to GU4); a source connection member (WSL / WSU) that connects the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50); a first gate connection member (WGL / WGU) that connects the first gate electrode (GL1 / GU1) and the gate wiring (62 / 61); a second gate connection member (WGL / WGU) that connects the second gate electrodes (GL2, GL2 to GL4 / GU2, GU2 to GU4) and the gate wiring (62 / 61); Contains 3. The semiconductor module according to claim 2.

[0186] [Appendix 7] The source connection member is connected to the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3, and the size and number of the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfy the relationship. 7. The semiconductor module according to claim 6.

[0187] [Appendix 8] The source connection member is a source wire (WSL / WSU), and the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3, and the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) are connected to the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50). 7. The semiconductor module according to claim 6.

[0188] [Appendix 9] The source connection member is connected to the zero point frequency ω z The second pole frequency ω p2The ratio (ω p2 / ω z ) is 0.55 or more, and the size and number of the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) are connected to the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50). 7. The semiconductor module according to claim 6.

[0189] [Appendix 10] The source connection member is a source wire (WSL / WSU), and the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more, and the wire diameter, length, and number of wires connected to the first source electrode (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfy the relationship. 7. The semiconductor module according to claim 6.

[0190] [Appendix 11] The source connection members are provided in a plurality of sizes identical to each other, The plurality of source connection members are connected to the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3 and is connected to the first source electrode (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50). 7. The semiconductor module according to claim 6.

[0191] [Appendix 12] The source connection members are provided in a plurality of sizes identical to each other, The plurality of source connection members are connected to the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z) is 0.55 or more, and the number of the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) is connected to the first source electrode (SL1 / SU1), 7. The semiconductor module according to claim 6.

[0192] [Appendix 13] The source connection member includes a plurality of source wires (WSL / WSU) having the same wire diameter and length, The plurality of source wires (WSL / WSU) are connected to the zero-point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3, and the number of lines connected to the first source electrode (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfies the relationship 7. The semiconductor module according to claim 6.

[0193] [Appendix 14] The source connection member includes a plurality of source wires (WSL / WSU) having the same wire diameter and length, The plurality of source wires (WSL / WSU) are connected to the zero-point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more, and the number of wires connected to the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfies the relationship. 7. The semiconductor module according to claim 6.

[0194] [Appendix 15] Each of the plurality of source wires (WSL) extends in a first direction (X) in a plan view, The plurality of source wires (WSL) are arranged side by side in a second direction (Y) perpendicular to the first direction (X) in a plan view. 15. The semiconductor module according to claim 13 or 14.

[0195] [Appendix 16] the first transistor (11L) and the second transistors (12L, 12L to 14L) are arranged apart from each other in a first direction (X); The source wiring (40) a first wiring portion (41) disposed on one side of the first transistor (11L) and the second transistors (12L, 12L to 14L) in the first direction (X); a second wiring portion (42) disposed on the other side of the first transistor (11L) and the second transistors (12L, 12L to 14L) in the first direction (X); Including, The source connection member (WSL) extends in the first direction (X) in a plan view and is connected to the first source electrode (SL1), the second source electrodes (SL2, SL2 to SL4), the first wiring portion (41), and the second wiring portion (42). 16. The semiconductor module according to any one of claims 6 to 15.

[0196] [Appendix 17] The length of the first gate connecting member (WGL / WGU) is equal to the length of the second gate connecting member (WGL / WGU). 17. The semiconductor module according to any one of claims 6 to 16.

[0197] [Appendix 18] The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is less than 1 16. The semiconductor module according to any one of claims 7 to 15.

[0198] [Appendix 19] The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 1 7. The semiconductor module according to claim 6.

[0199] [Appendix 20] The device includes a first transistor (11L / 11U) and a second transistor (12L, 12L to 14L / 12U, 12U to 14U) connected in parallel with each other, The parallel resonant circuit of the first transistor (11L / 11U) and the second transistor (12L, 12L to 14L / 12U, 12U to 14U) is 1st pole frequency ω p1 and, A second pole frequency ω higher than the first pole frequency p2 and, Zero point frequency ω z and, It has The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3 A semiconductor module (10).

[0200] [Appendix 21] The first transistor (11L / 12U) includes a first gate electrode (GL1 / GU1), a first source electrode (SL1 / SU1), and a first drain electrode (DL1 / DU1), the second transistors (12L, 12L to 14L / 12U, 12U to 14U) include second gate electrodes (GL2, GL2 to GL4 / GU2, GU2 to GU4), second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and second drain electrodes (DL2, DL2 to DL4 / DU2, DU2 to DU4), a drain wiring (50 / 30) to which the first drain electrode (DL1 / DU1) and the second drain electrodes (DL2, DL2 to DL4 / DU2, DU2 to DU4) are electrically connected; a source wiring (40 / 50) that is disposed apart from the drain wiring (50 / 30) and to which the first source electrode (SL1 / SU1) and the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4) are electrically connected; a gate wiring (62 / 61) disposed apart from both the drain wiring (50 / 30) and the source wiring (40 / 50) and electrically connected to the first gate electrode (GL1 / GU1) and the second gate electrode (GL2, GL2 to GL4 / GU2, GU2 to GU4); a source connection member (WSL / WSU) that connects the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50); a first gate connection member (WGL / WGU) that connects the first gate electrode (GL1 / GU1) and the gate wiring (62 / 61); a second gate connection member (WGL / WGU) that connects the second gate electrodes (GL2, GL2 to GL4 / GU2, GU2 to GU4) and the gate wiring (62 / 61); Contains 21. The semiconductor module of claim 20.

[0201] [Appendix 22] The source connection member is connected to the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3, and the size and number of the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfy the relationship. 22. The semiconductor module of claim 21.

[0202] [Appendix 23] The source connection member is a source wire (WSL / WSU), and the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ωz ) is greater than 0.3, and the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) are connected to the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50). 22. The semiconductor module of claim 21.

[0203] [Appendix 24] The source connection members are provided in a plurality of sizes identical to each other, The plurality of source connection members are connected to the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3 and is connected to the first source electrode (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50). 22. The semiconductor module of claim 21.

[0204] [Appendix 25] The source connection member includes a plurality of source wires (WSL / WSU) having the same wire diameter and length, The plurality of source wires (WSL / WSU) are connected to the zero-point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than 0.3, and the number of lines connected to the first source electrode (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfies the relationship 22. The semiconductor module of claim 21.

[0205] [Appendix 26] Each of the plurality of source wires (WSL) extends in a first direction (X) in a plan view, The plurality of source wires (WSL) are arranged side by side in a second direction (Y) perpendicular to the first direction (X) in a plan view. 26. The semiconductor module of claim 25.

[0206] [Appendix 27] the first transistor (11L) and the second transistors (12L, 12L to 14L) are arranged apart from each other in a first direction (X); The source wiring (40) a first wiring portion (41) disposed on one side of the first transistor (11L) and the second transistors (12L, 12L to 14L) in the first direction (X); a second wiring portion (42) disposed on the other side of the first transistor (11L) and the second transistors (12L, 12L to 14L) in the first direction (X); Including, The source connection member (WSL) extends in the first direction (X) in a plan view and is connected to the first source electrode (SL1), the second source electrodes (SL2, SL2 to SL4), the first wiring portion (41), and the second wiring portion (42). 27. A semiconductor module according to any one of claims 21 to 26.

[0207] [Appendix 28] The length of the first gate connecting member (WGL / WGU) is equal to the length of the second gate connecting member (WGL / WGU). 28. A semiconductor module according to any one of claims 21 to 27.

[0208] [Appendix 29] The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is less than 1 22. The semiconductor module of claim 21.

[0209] [Appendix 30] The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ωz ) is greater than 1 22. The semiconductor module of claim 21.

[0210] [Appendix 31] The device includes a first transistor (11L / 11U) and a second transistor (12L, 12L to 14L / 12U, 12U to 14U) connected in parallel with each other, The parallel resonant circuit of the first transistor (11L / 11U) and the second transistor (12L, 12L to 14L / 12U, 12U to 14U) is 1st pole frequency ω p1 and, A second pole frequency ω higher than the first pole frequency p2 and, Zero point frequency ω z and, It has The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is greater than or equal to 0.55 A semiconductor module (10).

[0211] [Appendix 32] The first transistor (11L / 11U) includes a first gate electrode (GL1 / GU1), a first source electrode (SL1 / SU1), and a first drain electrode (DL1 / DU1), the second transistors (12L, 12L to 14L / 12U, 12U to 14U) include second gate electrodes (GL2, GL2 to GL4 / GU2, GU2 to GU4), second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and second drain electrodes (DL2, DL2 to DL4 / DU2, DU2 to DU4), a drain wiring (50 / 30) to which the first drain electrode (DL1 / DU1) and the second drain electrodes (DL2, DL2 to DL4 / DU2, DU2 to DU4) are electrically connected; a source wiring (40 / 50) that is disposed apart from the drain wiring (50 / 30) and to which the first source electrode (SL1 / SU1) and the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4) are electrically connected; a gate wiring (62 / 61) disposed apart from both the drain wiring (50 / 30) and the source wiring (40 / 50) and electrically connected to the first gate electrode (GL1 / GU1) and the second gate electrode (GL2, GL2 to GL4 / GU2, GU2 to GU4); a source connection member (WSL / WSU) that connects the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50); a first gate connection member (WGL) that connects the first gate electrode (GL1 / GU1) and the gate wiring (62 / 61); a second gate connection member (WGL / WGU) that connects the second gate electrodes (GL2, GL2 to GL4 / GU2, GU2 to GU4) and the gate wiring (62 / 61); Contains 32. The semiconductor module of claim 31.

[0212] [Appendix 33] The source connection member is connected to the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more, and the size and number of the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) are connected to the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50). 33. The semiconductor module of claim 32.

[0213] [Appendix 34] The source connection member is a source wire (WSL / WSU), and the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z) is 0.55 or more, and the wire diameter, length, and number of wires connected to the first source electrode (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfy the relationship. 33. The semiconductor module of claim 32.

[0214] [Appendix 35] The source connection members are provided in a plurality of sizes identical to each other, The plurality of source connection members are connected to the zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more, and the number of the first source electrodes (SL1 / SU1), the second source electrodes (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) is connected to the first source electrode (SL1 / SU1), 33. The semiconductor module of claim 32.

[0215] [Appendix 36] The source connection member includes a plurality of source wires (WSL) having the same wire diameter and length, The plurality of source wires (WSL) are connected to the zero-point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is 0.55 or more, and the number of wires connected to the first source electrode (SL1 / SU1), the second source electrode (SL2, SL2 to SL4 / SU2, SU2 to SU4), and the source wiring (40 / 50) satisfies the relationship. 33. The semiconductor module of claim 32.

[0216] [Appendix 37] Each of the plurality of source wires (WSL) extends in a first direction (X) in a plan view, The plurality of source wires (WSL) are arranged side by side in a second direction (Y) perpendicular to the first direction (X) in a plan view. 37. The semiconductor module of claim 36.

[0217] [Appendix 38] the first transistor (11L) and the second transistors (12L, 12L to 14L) are arranged apart from each other in a first direction (X); The source wiring (40) a first wiring portion (41) disposed on one side of the first transistor (11L) and the second transistors (12L, 12L to 14L) in the first direction (X); a second wiring portion (42) disposed on the other side of the first transistor (11L) and the second transistors (12L, 12L to 14L) in the first direction (X); Including, The source connection member (WSL) extends in the first direction (X) in a plan view and is connected to the first source electrode (SL1), the second source electrodes (SL2, SL2 to SL4), the first wiring portion (41), and the second wiring portion (42). 38. The semiconductor module according to any one of claims 32 to 37.

[0218] [Appendix 39] The length of the first gate connecting member (WGL / WGU) is equal to the length of the second gate connecting member (WGL / WGU). 39. The semiconductor module according to any one of appendices 32 to 38.

[0219] [Appendix 40] The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z ) is less than 1 32. The semiconductor module of claim 31.

[0220] [Appendix 41] The zero point frequency ω z The second pole frequency ω p2 The ratio (ω p2 / ω z) is greater than 1 32. The semiconductor module of claim 31.

[0221] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0222] 10...Semiconductor module 11U: Transistor for first upper arm 11L...1st lower arm transistor 12U: Second upper arm transistor 12L: Second lower arm transistor 13U: Third upper arm transistor 13L...Third lower arm transistor 14U: Transistor for the fourth upper arm 14L...4th lower arm transistor 20...Substrate 21...First board surface 22...Second board surface 23~26...1st~4th board side 30...1st power supply wiring 31...Element mounting section 32...Terminal connection part 33...Opening 40…Second power supply wiring 41...First connection wiring 42...Second connection wiring 43...Connecting wiring 44...Terminal connection part 50...Output wiring 51...Element mounting section 52...Terminal connection part 53...Opening 61...First gate wiring 62...Second gate wiring 101...Current source DU1, DL1...First drain electrode DU2, DL2...Second drain electrode DU3, DL3...Third drain electrode DU4, DL4...Fourth drain electrode GU1, GL1...first gate electrode GU2, GL2...Second gate electrodes GU3, GL3...Third gate electrode GU4, GL4...Fourth gate electrode SU1, SL1...First source electrode SU2, SL2...Second source electrode SU3, SL3...Third source electrode SU4, SL4...Fourth source electrode SD: Conductive adhesive SBD: Schottky barrier diode TG1: First gate terminal TG2: Second gate terminal TN: Ground terminal TO: Output terminal TP…Power terminal WGU, WGL...Gate wire WSU,WSL…Source Wire WR...Wire RD...Drain conduction path RS…Source conductive path RG...gate conduction path R1~R4…1st~4th area

Claims

1. a first transistor and a second transistor connected in parallel with each other; The parallel resonant circuit of the first transistor and the second transistor is 1st pole frequency ω ｐ１ and, The first pole frequency ω ｐ１ The second pole frequency ω is higher than ｐ２ and, Zero point frequency ω ｚ and, It has The second pole frequency ω ｐ２ and the zero point frequency ω ｚ The absolute value of the phase delay between the Semiconductor module.

2. The parasitic inductance of the conductive path between the first source electrode of the first transistor and the second source electrode of the second transistor is L ｓｓ In this case, The second pole frequency ω ｐ２ is the parasitic inductance L ｓｓ is a parameter that changes depending on The parasitic inductance L ｓｓ is the second pole frequency ω ｐ２ and the zero point frequency ω ｚ The absolute value of the phase delay between the The semiconductor module according to claim 1 .

3. The parasitic capacitance between the gate and drain of the first transistor or the second transistor is C ｇｄ In this case, The zero point frequency ω ｚ is the parasitic capacitance C ｇｄ is a parameter that changes depending on The parasitic capacitance C ｇｄ is the second pole frequency ω ｐ２ and the zero point frequency ω ｚ The absolute value of the phase delay between the The semiconductor module according to claim 1 .

4. The zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is greater than 0.3 The semiconductor module according to claim 1 .

5. The zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is 0.55 or more The semiconductor module according to claim 1 .

6. the first transistor includes a first gate electrode, a first drain electrode, and the first source electrode; the second transistor includes a second gate electrode, a second drain electrode, and the second source electrode; a drain wiring to which the first drain electrode and the second drain electrode are electrically connected; a source wiring that is disposed apart from the drain wiring and to which the first source electrode and the second source electrode are electrically connected; a gate wiring disposed apart from both the drain wiring and the source wiring and electrically connected to the first gate electrode and the second gate electrode; a source connection member that connects the first source electrode, the second source electrode, and the source wiring; a first gate connection member that connects the first gate electrode and the gate wiring; a second gate connection member that connects the second gate electrode and the gate wiring; Contains The semiconductor module according to claim 2 .

7. The source connection member is connected to the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is greater than 0.3, and the size and number of the electrodes are connected to the first source electrode, the second source electrode, and the source wiring. The semiconductor module according to claim 6 .

8. The source connection member is a source wire, and the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is greater than 0.3, and the wire diameter, length, and number of wires are connected to the first source electrode, the second source electrode, and the source wiring. The semiconductor module according to claim 6 .

9. The source connection member is connected to the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is 0.55 or more, and The semiconductor module according to claim 6 .

10. The source connection member is a source wire, and the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is 0.55 or more, and the wire diameter, length, and number of wires are connected to the first source electrode, the second source electrode, and the source wiring. The semiconductor module according to claim 6 .

11. The source connection members are provided in a plurality of sizes identical to each other, The plurality of source connection members are connected to the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is greater than 0.3 and is connected to the first source electrode, the second source electrode, and the source wiring. The semiconductor module according to claim 6 .

12. The source connection members are provided in a plurality of sizes identical to each other, The plurality of source connection members are connected to the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is 0.55 or more, and The semiconductor module according to claim 6 .

13. the source connection member includes a plurality of source wires having the same wire diameter and length; The plurality of source wires are connected to the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is greater than 0.3, and the number of the first source electrode, the second source electrode, and the source wiring is greater than 0.

3. The semiconductor module according to claim 6 .

14. the source connection member includes a plurality of source wires having the same wire diameter and length; The plurality of source wires are connected to the zero point frequency ω ｚ The second pole frequency ω ｐ２ The ratio of (ω ｐ２ / ω ｚ ) is 0.55 or more, and The semiconductor module according to claim 6 .

15. Each of the plurality of source wires extends in a first direction in a plan view, The plurality of source wires are arranged side by side in a second direction perpendicular to the first direction in a plan view. The semiconductor module according to claim 13 .

16. the first transistor and the second transistor are spaced apart from each other in a first direction, The source wiring is a first wiring portion disposed on one side of the first transistor and the second transistor in the first direction; a second wiring portion disposed on the other side of the first transistor and the second transistor in the first direction; Including, The source connection member extends in the first direction in a plan view and is connected to the first source electrode, the second source electrode, the first wiring portion, and the second wiring portion. The semiconductor module according to claim 6 .

17. The length of the first gate connecting member is equal to the length of the second gate connecting member. The semiconductor module according to any one of claims 6 to 16.

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