Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor in which deterioration of high temperature load reliability is suppressed.SOLUTION: In multilayer ceramic capacitor 1, in the cross section of multilayer body 2 in the plane parallel or substantially parallel to width direction W and height direction T, effective layer portion 14 includes first region 351 defined by four corner portions 330 of effective layer portion 14 and second region 352 defined as a region of effective layer portion 14 excluding first region 351, an amount of segregation of manganese and magnesium in first region 351 is larger than an amount of segregation of manganese and magnesium in second region 352, and the internal electrode layer in first region 351 includes an insulating portion.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] For example, the multilayer ceramic capacitor described in Patent Document 1 includes a capacitor body made of a sintered ceramic body made of a dielectric material such as barium titanate. The capacitor body includes internal electrode layers made of a noble metal material such as silver or a silver-palladium alloy, or a base metal material such as nickel, with ceramic layers serving as dielectric layers interposed between them. The internal electrode layers are alternately routed to one end face and the other end face of the capacitor body. The alternately routed internal electrode layers are electrically connected to external electrodes at different potentials.

[0003] The internal electrode layers of the multilayer capacitor described in Patent Document 1 are made of a metal material, and the external electrodes are made of a glass component and multiple metal components, including the same metal or metals that can be alloyed with the internal electrode layers. The external electrodes are bonded to the wiring board via a conductive resin adhesive. The area occupancy rate of the metal components relative to the cross-sectional area of ​​the external electrodes is in the range of 60% to 95%. This makes it possible for the multilayer capacitor described in Patent Document 1 to be mounted on the wiring board inexpensively and with high reliability without using solder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-237137 Summary of the Invention [Problem to be solved by the invention]

[0005] In the above-described general multilayer ceramic capacitor, the thickness of the dielectric layers and the thickness of the internal electrode layers may be thinned near the corners of the multilayer ceramic capacitor. When the thickness of the dielectric layers or the internal electrode layers is thinned, the high-temperature load reliability tends to decrease starting from the thinned portion. Thus, conventional multilayer ceramic capacitors have the problem of being prone to a decrease in high-temperature load reliability.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor in which the deterioration of high temperature load reliability is suppressed. [Means for solving the problem]

[0007] The multilayer ceramic capacitor of the present invention includes a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction, the laminate including an effective layer portion formed by alternately laminating the dielectric layers and the internal electrode layers, and outer layer portions arranged to sandwich the effective layer portion from the first main surface side and the second main surface side; and a second external electrode disposed on the second end face, wherein in a cross section of the laminate in a plane parallel to the width direction and the height direction, the effective layer portion has a first region defined by four corners of the effective layer portion and a second region defined as a region of the effective layer portion excluding the first region, and the segregation amounts of manganese and magnesium in the first region are greater than the segregation amounts of manganese and magnesium in the second region, and the internal electrode layer in the first region includes an insulating portion. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the deterioration of high-temperature load reliability is suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line 101-101 in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line 102-102 of FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line 104-104 in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line 105-105 in FIG. [Figure 7] FIG. 7 is a diagram showing the results of elemental analysis of the multilayer ceramic capacitor of this embodiment. [Figure 8] FIG. 8 is a diagram showing the results of elemental analysis of the multilayer ceramic capacitor of this embodiment. [Figure 9] FIG. 9 is a table showing examples of the multilayer ceramic capacitor of this embodiment. [Figure 10] FIG. 10 is a diagram showing the side gap element and the side gap sheet. [Figure 11] FIG. 11 is a diagram showing a laminated chip in which a side gap sheet is laminated on a side gap element body. DETAILED DESCRIPTION OF THE INVENTION

[0010] (multilayer ceramic capacitors) A multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line 101-101 of FIG. 1. FIG. 3 is a cross-sectional view taken along line 102-102 of FIG. 2. FIG. 4 is a cross-sectional view taken along line 103-103 of FIG. 2. FIG. 5 is a cross-sectional view taken along line 104-104 of FIG. 2.

[0011] 1, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 2 and spaced apart from each other.

[0012] In Fig. 1, arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the laminate 2. This height direction T is also the thickness direction and lamination direction of the multilayer ceramic capacitor 1 and the laminate 2. In Fig. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 2, which is perpendicular to the height direction T. In Fig. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 2, which is perpendicular to the height direction T and the length direction L. A pair of external electrodes 40 is disposed at one end and the other end of the length direction L of the laminate 2, respectively.

[0013] The cross section shown in Figure 2 is called the LT cross section, the cross section shown in Figure 3 is called the WT cross section, and the cross sections shown in Figure 4 and Figure 5 are called the LW cross sections.

[0014] (Laminate) The two surfaces of the laminate 2 that face each other in the height direction T are called the first main surface 3 and the second main surface 4. The two surfaces that face each other in the length direction L, which is perpendicular to the height direction T of the laminate, are called the first end surface 7 and the second end surface 8. The two surfaces of the laminate 2 that face each other in the width direction W, which is perpendicular to the height direction T and the length direction L, are called the first side surface 5 and the second side surface 6.

[0015] As shown in FIG. 1, the shape of the laminate 2 is a substantially rectangular parallelepiped. The length of the laminate 2 in the longitudinal direction L does not have to be longer than the length of the laminate 2 in the width direction W. The corners and ridges of the laminate 2 are preferably rounded. A corner is a portion where three faces of the laminate intersect. A ridge is a portion where two faces of the laminate 2 intersect. The shape of part or all of the surfaces constituting the laminate 2 may be a shape formed with irregularities or the like.

[0016] The size of the laminate 2 is not limited. The preferred length of the laminate 2 in the longitudinal direction L is 0.2 mm or more and 6 mm or less. The preferred length of the laminate 2 in the height direction T is 0.05 mm or more and 5 mm or less. The preferred length of the laminate 2 in the width direction W is 0.1 mm or more and 5 mm or less.

[0017] (Division in the height direction) 2 and 3 , the laminate 2 is divided into an inner layer portion 10 and a main surface side outer layer portion 11 in the height direction T. The main surface side outer layer portion 11 includes a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13. The first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 are located on either side of the inner layer portion 10 in the height direction T. In other words, the laminate 2 is divided into the first main surface side outer layer portion 12, the inner layer portion 10, and the second main surface side outer layer portion 13.

[0018] (dielectric layer) The inner layer portion 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the height direction T. The inner layer portion 10 includes, in the height direction T, the internal electrode layer 30 located closest to the first main surface 3 to the internal electrode layer 30 located closest to the second main surface 4. In the inner layer portion 10, the multiple internal electrode layers 30 are arranged facing each other with the dielectric layer 20 interposed therebetween. The inner layer portion 10 is a portion that generates electrostatic capacitance and essentially functions as a capacitor. The dielectric layer 20 included in the inner layer portion 10 is called an inner dielectric layer 21. The dielectric layer 20 included in the first main surface side outer layer portion 12 and the dielectric layer 20 included in the second main surface side outer layer portion 13 are called outer dielectric layers 22.

[0019] The multiple dielectric layers 20 are made of a dielectric material. Examples of the dielectric material are dielectric ceramics containing components such as barium titanate, calcium titanate, strontium titanate, or calcium zirconate. The dielectric material may be made by adding a secondary component such as a manganese compound, an iron compound, a copper compound, a cobalt compound, or a nickel compound to these main components. A preferred dielectric material is one containing barium titanate as the main component.

[0020] The preferred thickness of the dielectric layer 20 is 0.2 μm or more and 10 μm or less. The preferred number of laminated dielectric layers 20 is 15 or more and 1200 or less. The number of dielectric layers 20 is the sum of the number of inner dielectric layers 21 and the number of outer dielectric layers 22.

[0021] (Internal electrode layer) The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the height direction T with the dielectric layer 20 sandwiched between them. The first internal electrode layers 31 are extended to the first end face 7. The second internal electrode layers 32 are extended to the second end face 8.

[0022] As shown in Fig. 4, the first internal electrode layer 31 is divided into a first opposing portion 33 and a first lead portion 35. The first opposing portion 33 is a portion that faces the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween. The first lead portion 35 is a portion that is led from the first opposing portion 33 to the first end face 7. The first lead portion 35 is exposed at the first end face 7.

[0023] As shown in Fig. 5, the second internal electrode layer 32 is divided into a second opposing portion 34 and a second lead portion 36. The second opposing portion 34 is a portion that faces the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween. The second lead portion 36 is a portion that is led from the second opposing portion 34 to the second end face 8. The second lead portion 36 is exposed at the second end face 8.

[0024] In the multilayer ceramic capacitor 1, capacitance is formed by the first opposing portion 33 and the second opposing portion 34 facing each other via the dielectric layer 20. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0025] The shapes of the first opposing portion 33 and the second opposing portion 34 are not limited. A preferred shape for the first opposing portion 33 and the second opposing portion 34 is a rectangular shape. Similarly, the shapes of the first drawer portion 35 and the second drawer portion 36 are not limited. A preferred shape for the first drawer portion 35 and the second drawer portion 36 is a rectangular shape. In the above-mentioned rectangular shape, the corners of the rectangular shape may be rounded. The corners of the rectangular shape may be formed at an angle.

[0026] The length in the width direction W of the first facing portion 33 and the length in the width direction W of the first lead portion 35 may be the same. Either the length in the width direction W of the first facing portion 33 or the length in the width direction W of the first lead portion 35 may be shorter. The length in the width direction W of the second facing portion 34 and the length in the width direction W of the second lead portion 36 may be the same. Either the length in the width direction W of the second facing portion 34 or the length in the width direction W of the second lead portion 36 may be shorter.

[0027] Examples of materials for the first internal electrode layers 31 and the second internal electrode layers 32 are conductive materials such as metals such as nickel, copper, silver, palladium, and gold, and alloys containing at least one of these metals. When an alloy is used, an example of the material for the first internal electrode layers 31 and the second internal electrode layers 32 is an alloy of silver and palladium.

[0028] A preferred example of the thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is 0.2 μm or more and 2.0 μm or less. A preferred total number of layers of the first internal electrode layers 31 and the second internal electrode layers 32 is 15 or more and 1000 or less.

[0029] (Outer layer on main surface side) As shown in FIGS. 2 and 3 , a portion consisting of a set of multiple dielectric layers 20 located between the first main surface 3 and the internal electrode layer 30 closest to the first main surface 3 is called the first main surface side outer layer portion 12. The first main surface side outer layer portion 12 is located on the first main surface 3 side of the laminate 2. A portion consisting of a set of multiple dielectric layers 20 located between the second main surface 4 and the internal electrode layer 30 closest to the second main surface 4 is called the second main surface side outer layer portion 13. The second main surface side outer layer portion 13 is located on the second main surface 4 side of the laminate 2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 10. The material of the internal dielectric layer 21 and the material of the external dielectric layer 22 may be the same.

[0030] (effective layer) The portion where the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 oppose each other is called the effective layer portion 14. The effective layer portion 14 is a portion formed by alternately stacking the dielectric layers 20 and the internal electrode layers 30. The effective layer portion 14 is a part of the internal layer portion 10. Figures 4 and 5 show the range of the effective layer portion 14 in the width direction W and length direction L. The effective layer portion 14 is a portion of the internal layer portion 10 excluding the side gaps and end gaps described below. The effective layer portion 14 is also called a capacitance forming portion or a capacitor effective portion.

[0031] (W direction division) The laminate 2 is divided into a first side surface side outer layer portion 15, an effective layer portion 14, and a second side surface side outer layer portion 16 in the width direction W. The first side surface side outer layer portion 15 is a portion including a dielectric layer 20 located between the effective layer portion 14 and the first side surface 5. The second side surface side outer layer portion 16 is a portion including a dielectric layer 20 located between the effective layer portion 14 and the second side surface 6. Figures 3, 4, and 5 show the ranges in the width direction W of the first side surface side outer layer portion 15, the effective layer portion 14, and the second side surface side outer layer portion 16. The first side surface side outer layer portion 15 and the second side surface side outer layer portion 16 are called W gaps or side gaps.

[0032] (L direction division) The laminate 2 is divided into a first end face side outer layer portion 17, an effective layer portion 14, and a second end face side outer layer portion 18 in the longitudinal direction L. The first end face side outer layer portion 17 is a portion including the dielectric layers 20 and the first lead portion 35 located between the effective layer portion 14 and the first end face 7. The first end face side outer layer portion 17 is an assembly of the portions of the multiple dielectric layers 20 on the first end face 7 side and the multiple first lead portions 35. The second end face side outer layer portion 18 is a portion including the dielectric layers 20 and the second lead portion 36 located between the effective layer portion 14 and the second end face 8. The second end face side outer layer portion 18 is an assembly of the portions of the multiple dielectric layers 20 on the second end face 8 side and the multiple second lead portions 36. 2, 4, and 5 show the ranges in the length direction L of the first end-side outer layer portion 17, the effective layer portion 14, and the second end-side outer layer portion 18. The first end-side outer layer portion 17 and the second end-side outer layer portion 18 are called L gaps or end gaps.

[0033] (external electrode) The external electrodes 40 include a first external electrode 41 and a second external electrode 42. The first external electrode 41 is an external electrode arranged on the first end face 7 side of the laminate 2. The second external electrode 42 is an external electrode arranged on the second end face 8 side of the laminate 2.

[0034] The first external electrode 41 and the second external electrode 42 have the same basic configuration. The first external electrode 41 and the second external electrode 42 have shapes that are approximately symmetrical with respect to the WT cross section at the center of the length direction L of the multilayer ceramic capacitor 1.

[0035] The first external electrode 41 is disposed on the first end face 7. The first external electrode 41 contacts the first lead portions 35 of each of the multiple first internal electrode layers 31 exposed at the first end face 7. The first external electrode 41 is electrically connected to the multiple first internal electrode layers 31. The first external electrode 41 may also be disposed on part of the first main surface 3 and part of the second main surface 4, as well as part of the first side surface 5 and part of the second side surface 6. In this embodiment, the first external electrode 41 is formed to extend from on the first end face 7 to part of the first main surface 3 and part of the second main surface 4, as well as part of the first side surface 5 and part of the second side surface 6.

[0036] The second external electrode 42 is disposed on the second end face 8. The second external electrode 42 contacts the second lead portions 36 of each of the second internal electrode layers 32 exposed at the second end face 8. The second external electrode 42 is electrically connected to the second internal electrode layers 32. The second external electrode 42 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the second external electrode 42 is formed to extend from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0037] In the laminate 2, a capacitance is formed by the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 opposing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 41 connected to the first internal electrode layer 31 and the second external electrode 42 connected to the second internal electrode layer 32.

[0038] (base electrode layer) 2, 4, and 5, the first external electrode 41 includes a first base electrode layer 51 and a first plating layer 71. The first plating layer 71 is disposed on the first base electrode layer 51. The second external electrode 42 includes a second base electrode layer 52 and a second plating layer 72. The second plating layer 72 is disposed on the second base electrode layer 52.

[0039] The first base electrode layer 51 is disposed on the first end face 7. The first base electrode layer 51 contacts the first lead portions 35 of each of the multiple first internal electrode layers 31 exposed at the first end face 7. The first base electrode layer 51 is formed to extend from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0040] The second base electrode layer 52 is disposed on the second end face 8. The second base electrode layer 52 contacts the second lead portions 36 of each of the plurality of second internal electrode layers 32 exposed at the second end face 8. The second base electrode layer 52 is formed to extend from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0041] The first base electrode layer 51 and the second base electrode layer 52 are baked layers. The baked layer preferably contains a metal component. In addition to the metal component, the baked layer preferably contains at least one of a glass component and a ceramic component. The metal component includes at least one selected from, for example, copper, nickel, silver, palladium, a silver-palladium alloy, and gold. The glass component includes at least one selected from, for example, boron, silicon, barium, magnesium, aluminum, and lithium. The ceramic component may be the same type of ceramic material as the dielectric layer 20. The ceramic component may be a different type of ceramic material from the dielectric layer 20. The ceramic component may include at least one selected from, for example, barium titanate, calcium titanate, a mixed crystal material in which part of the barium in barium titanate is replaced with calcium, strontium titanate, calcium zirconate, and the like.

[0042] An example of a baked layer is a layer formed by applying and baking a conductive paste containing glass and metal to a laminate. The baked layer is formed by simultaneously firing a pre-fired laminated chip, which is the material for the laminate including multiple internal electrode layers and multiple dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, the baked layer is formed by firing the laminated chip to obtain a laminate, and then applying and baking a conductive paste to the laminate. When the conductive paste is baked after obtaining the laminate, the baked layer is preferably formed by baking a conductive paste to which a ceramic material has been added instead of a glass component. When using a conductive paste to which a ceramic material has been added, the added ceramic material is preferably the same type of ceramic material as the dielectric layer. The baked layer may be multiple layers.

[0043] A preferred example of the thickness in the length direction L of the first base electrode layer 51 on the first end face 7 is approximately 10 μm or more and 200 μm or less at the center in the height direction T and width direction W of the first base electrode layer 51.

[0044] A preferred example of the thickness in the length direction L of the second base electrode layer 52 on the second end face 8 is approximately 10 μm or more and 200 μm or less at the center in the height direction T and width direction W of the second base electrode layer 52.

[0045] When the first base electrode layer 51 is provided on a portion of at least one of the first main surface 3 or the second main surface 4, an example of a preferred thickness in the height direction T of the first base electrode layer 51 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and width direction W of the first base electrode layer 51 provided on this portion.

[0046] When the first base electrode layer 51 is provided on a portion of at least one of the first side surface 5 or the second side surface 6, an example of a preferred thickness in the width direction W of the first base electrode layer 51 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and height direction T of the first base electrode layer 51 provided on this portion.

[0047] When the second base electrode layer 52 is provided on a portion of at least one of the first main surface 3 and the second main surface 4, an example of a preferred thickness in the height direction T of the second base electrode layer 52 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and width direction W of the second base electrode layer 52 provided on this portion.

[0048] When the second base electrode layer 52 is provided on a portion of at least one of the first side surface 5 or the second side surface 6, an example of a preferred thickness in the width direction W of the second base electrode layer 52 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and height direction T of the second base electrode layer 52 provided on this portion.

[0049] The first plating layer 71 is disposed so as to cover the first base electrode layer 51. The second plating layer 72 is disposed so as to cover the second base electrode layer 52.

[0050] The first plating layer 71 and the second plating layer 72 may contain at least one selected from, for example, copper, nickel, tin, silver, palladium, a silver-palladium alloy, and gold. The first plating layer 71 and the second plating layer 72 may each be formed of multiple layers. A preferred structure for the first plating layer 71 and the second plating layer 72 is a two-layer structure in which a tin plating layer is formed on a nickel plating layer.

[0051] The first plating layer 71 is disposed so as to cover the first base electrode layer 51. In this embodiment, the first plating layer 71 includes a first nickel plating layer 73 and a first tin plating layer 75. The first tin plating layer 75 is located on the first nickel plating layer 73.

[0052] The second plating layer 72 is disposed so as to cover the second base electrode layer 52. In this embodiment, the second plating layer 72 includes a second nickel plating layer 74 and a second tin plating layer 76. The second tin plating layer 76 is located on the second nickel plating layer 74.

[0053] The nickel plating layer prevents the first base electrode layer 51 and the second base electrode layer 52 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The tin plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. The tin plating layer facilitates mounting of the multilayer ceramic capacitor 1. The first nickel plating layer 73, the first tin plating layer 75, the second nickel plating layer 74, and the second tin plating layer 76 each preferably have a thickness of 2 μm or more and 10 μm or less.

[0054] The external electrode 40 may include a conductive resin layer containing conductive particles and a thermosetting resin. When the external electrode 40 includes a conductive resin layer, the conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plated layer. The baked layer corresponds to the first base electrode layer 51 and the second base electrode layer 52. The plated layer corresponds to the first plating layer 71 and the second plating layer 72. The conductive resin layer may completely cover the baked layer. The conductive resin layer may also cover a portion of the baked layer.

[0055] Conductive resin layers containing thermosetting resins are more flexible than conductive layers made of plating films or fired conductive pastes. Therefore, when a multilayer ceramic capacitor is subjected to physical shock or shock due to thermal cycling, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer prevents cracks from occurring in the multilayer ceramic capacitor.

[0056] Examples of metals constituting the conductive particles include silver, copper, nickel, tin, bismuth, or an alloy containing at least two of these metals. The conductive particles preferably contain silver. An example of the conductive particles is silver metal powder. Silver has the lowest resistivity among metals. Silver is suitable as an electrode material. Silver is a noble metal. Silver is resistant to oxidation. Silver has high weather resistance. For these reasons, silver metal powder is suitable as the conductive particles.

[0057] The conductive particles may be metal powder whose surface is silver-coated. When using conductive particles whose surface is silver-coated, the metal powder is preferably a powder of copper, nickel, tin, bismuth, or an alloy thereof. In order to maintain the properties of silver while making the base metal inexpensive, it is preferable to use a silver-coated metal powder.

[0058] The conductive particles may be copper or nickel that has been subjected to an antioxidant treatment. The conductive particles may be metal powder whose surface is coated with tin, nickel, or copper. When using metal powder whose surface is coated with tin, nickel, or copper, the metal powder is preferably silver, copper, nickel, tin, bismuth, or an alloy powder containing at least two of these metals.

[0059] The shape of the conductive particles is not limited. Examples of the shape of the conductive particles include spherical and flat shapes. It is preferable to use a mixture of spherical metal powder and flat metal powder.

[0060] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. When multiple conductive particles come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0061] Examples of the resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. Among these, one of the most suitable resins is epoxy resin. Epoxy resins have excellent heat resistance, moisture resistance, and adhesion. The resin of the conductive resin layer preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds.

[0062] The conductive resin layer may be formed of multiple layers. The preferred thickness of the thickest part of the conductive resin layer is 10 μm or more and 150 μm or less.

[0063] The above is the basic configuration of the multilayer ceramic capacitor 1. The length in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 40, is preferably 0.2 mm or more and 6 mm or less. The length in the height direction T of the multilayer ceramic capacitor 1 is preferably 0.05 mm or more and 5 mm or less. The length in the width direction W of the multilayer ceramic capacitor 1 is preferably 0.1 mm or more and 5 mm or less.

[0064] (Manganese and magnesium segregation) In the multilayer ceramic capacitor 1 of this embodiment, manganese and magnesium are concentrated in large amounts at the corners of the effective layer portion.

[0065] (First region 351 and second region 352) FIG. 6 is a cross-sectional view taken along line 105-105 in FIG. 2. FIG. 6 shows a WT cross section of the multilayer ceramic capacitor 1. The WT cross section shown in FIG. 6 is a WT cross section at the center of the length direction L of the multilayer ceramic capacitor 1. As shown in FIG. 6, the effective layer portion 14 has a first region 351 and a second region 352 in the WT cross section. The first region 351 is a region defined by four corners 330 of the effective layer portion 14. The second region 352 is a region defined as the effective layer portion 14 excluding the first region 351. The segregation amounts of manganese and magnesium in the first region 351 are greater than the segregation amounts of manganese and magnesium in the second region 352. The internal electrode layer 30 in the first region 351 includes an insulating portion.

[0066] (Corner of the effective layer) Continuing with reference to Fig. 6, the corner portion 330 of the effective layer portion 14 will be described. In Fig. 6, line 301 indicates one end of the effective layer portion 14 in the height direction T, and line 305 indicates the other end of the effective layer portion 14 in the height direction T. Lines 302, 303, and 304 are lines that divide the area from line 301 to line 305 into four equal parts.

[0067] 6, line 311 indicates one end of the effective layer portion 14 in the width direction W, and line 315 indicates the other end of the effective layer portion 14 in the width direction W. Lines 312, 313, and 314 divide the area from line 311 to line 315 into four equal parts.

[0068] (Corner of laminate) Of the four corners of the laminate 2 described above, the corner where the first main surface 3 and the first side surface 5 intersect will be referred to as the first corner 201 of the laminate 2. The corner where the first main surface 3 and the second side surface 6 intersect will be referred to as the second corner 202 of the laminate 2. The corner where the second main surface 4 and the second side surface 6 intersect will be referred to as the third corner 203 of the laminate 2. The corner where the second main surface 4 and the first side surface 5 intersect will be referred to as the fourth corner 204 of the laminate 2.

[0069] (Apex of the effective layer) When the shape of the effective layer portion 14 in the WT cross section is considered to be a rectangle, the four vertices of the rectangle are indicated by points 321 to 324. Vertex 321 is the intersection of line 301 and line 311. Vertex 322 is the intersection of line 301 and line 315. Vertex 323 is the intersection of line 305 and line 315. Vertex 324 is the intersection of line 305 and line 311.

[0070] The vertex 321 is close to the first corner 201 of the laminate 2. The vertex 322 is close to the second corner 202 of the laminate 2. The vertex 323 is close to the third corner 203 of the laminate 2. The vertex 324 is close to the fourth corner 204 of the laminate 2.

[0071] The corner portion 330 of the effective layer portion 14 is a triangular portion in the WT cross section that includes one vertex of the effective layer portion 14. The corner portion 330 of the effective layer portion 14 includes one vertex of the effective layer portion 14 as one of the three vertices of the triangle that defines the corner portion 330 of the effective layer portion 14.

[0072] The corner 330 of the effective layer portion 14 including the vertex 321 is defined as the first corner 331 of the effective layer portion 14. The corner 330 of the effective layer portion 14 including the vertex 322 is defined as the second corner 332 of the effective layer portion 14. The corner 330 of the effective layer portion 14 including the vertex 323 is defined as the third corner 333 of the effective layer portion 14. The corner 330 of the effective layer portion 14 including the vertex 324 is defined as the fourth corner 334 of the effective layer portion 14.

[0073] The corner 330 of the effective layer 14 will be described in more detail using the first corner 331 of the effective layer 14 as an example. The first corner 331 of the effective layer 14 is a triangular portion having vertices 321, point 341 shown in FIG. 6, and point 342 shown in FIG. 6 as vertices.

[0074] Point 341 is the intersection of line 301 and line 312. Point 341 is located along one of the outer sides of the effective layer portion 14, a distance of ¼ of the length of that side from vertex 321. In this case, this side is a side parallel to the width direction W.

[0075] Point 342 is the intersection of line 302 and line 311. The position of point 342 is a position that is ¼ of the length of one side of the outer periphery of the effective layer portion 14 from vertex 321. In this case, one side is a side that is parallel to the height direction T.

[0076] The triangular portion formed by connecting the above-mentioned vertex 321, point 341, and point 342 is a first corner 331 of the effective layer portion 14. A second corner 332 of the effective layer portion 14, a third corner 333 of the effective layer portion 14, and a fourth corner 334 of the effective layer portion 14 are also defined in the same manner as the first corner 331 of the effective layer portion 14.

[0077] As described above, the corner portion 330 of the effective layer portion 14 is a triangular portion enclosed in the WT cross section by connecting the vertex of the effective layer portion 14, a point that is 1 / 4 of the length of one side of the effective layer portion 14 from the vertex of the effective layer portion 14 in the direction of that side, and a point that is 1 / 4 of the length of the other side of the effective layer portion 14 from the vertex of the effective layer portion 14 in the direction of that side.

[0078] (First area) The first region 351 is a region that includes the four corners 330 of the effective layer 14, namely, the first corner 331 of the effective layer 14, the second corner 332 of the effective layer 14, the third corner 333 of the effective layer 14, and the fourth corner 334 of the effective layer 14.

[0079] (Second Area) The second region 352 is a region of the effective layer portion 14 excluding the first region 351 in the WT cross section.

[0080] The second region 352 is the region of the effective layer portion 14 excluding the corner portion close to the first corner portion 201 of the laminate 2, the corner portion close to the second corner portion 202 of the laminate 2, the corner portion close to the third corner portion 203 of the laminate 2, and the corner portion close to the fourth corner portion 204 of the laminate 2.

[0081] (Method for measuring segregation amount) A method for measuring the segregation amounts of manganese and magnesium will be described. The segregation amounts of manganese and magnesium are determined by performing elemental analysis on a cross section obtained by cutting the multilayer ceramic capacitor 1. The cross section is a WT cross section at the center position in the longitudinal direction L of the multilayer ceramic capacitor 1. The segregation amounts can be measured by performing elemental analysis using wavelength dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (TEM-EDX). At this time, the element concentrations are measured in five segregation regions in each of the first corner 331 to the fourth corner 334, and the average value is taken as the segregation amount.

[0082] (Segregation measurement results) The results of elemental analysis of the WT cross section of the multilayer ceramic capacitor 1 of this embodiment will be described with reference to Fig. 7 and Fig. 8. Both Fig. 7 and Fig. 8 are diagrams showing the results of elemental analysis of the WT cross section of the multilayer ceramic capacitor 1 of this embodiment. Both Fig. 7 and Fig. 8 show images obtained by transmission electron microscope-energy dispersive X-ray analysis. The multilayer ceramic capacitor 1 whose elemental analysis results are shown in Fig. 7 and the multilayer ceramic capacitor 1 whose elemental analysis results are shown in Fig. 8 are the same sample.

[0083] 7 and 8 both show the first corner 331 of the effective layer 14 as an example of the first region 351. However, FIGS. 7 and 8 show only a portion of the first corner 331 of the effective layer 14, rather than the entire first corner 331. In addition, both FIGS. 7 and 8 show the portion adjacent to the first corner 331 of the effective layer 14 as part of the second region 352.

[0084] In Fig. 7, light-colored dots 360 indicate manganese segregation, and in Fig. 8, light-colored dots 360 indicate magnesium segregation. Boxed area 361 in Fig. 7 indicates the range where manganese segregation is predominant, and boxed area 361 in Fig. 8 indicates the range where magnesium segregation is predominant. It can be seen that manganese and magnesium are segregated in large amounts in first area 351, not in second area 352.

[0085] As described above, in the multilayer ceramic capacitor 1 of this preferred embodiment, the segregation amounts of manganese and magnesium in the first region 351 are greater than the segregation amounts of manganese and magnesium in the second region 352.

[0086] 7 and 8, manganese or magnesium is present in large amounts on the lines of the internal electrode layers 30 in the WT cross section. Manganese or magnesium segregates in voids, which are missing portions of the internal electrode layers 30. The presence of voids in the internal electrode layers 30 and the segregation of manganese or magnesium in the voids reduces the resistivity of the internal electrode layers 30.

[0087] 7 and 8, manganese and magnesium are segregated in large amounts in the internal electrode layer 30 in the first region 351. Therefore, the resistivity of the first region 351 is higher than the resistivity of the second region 352. The internal electrode layer 30 in the first region 351 includes an insulating portion.

[0088] In the multilayer ceramic capacitor 1 of this embodiment, as described above, the segregation amounts of manganese and magnesium in the first region 351 are greater than the segregation amounts of manganese and magnesium in the second region 352. In particular, the segregation of manganese and magnesium is concentrated in the internal electrode layer 30 in the first region 351. As a result, the internal electrode layer 30 in the first region 351 includes an insulating portion.

[0089] As described above, in the multilayer ceramic capacitor 1 of this embodiment, manganese and magnesium are concentrated and segregated in the internal electrode layers 30 at the corners 330 of the effective layer portion 14, thereby providing insulating portions in the internal electrode layers 30 at the corners 330 of the effective layer portion 14. In the multilayer ceramic capacitor 1 of this embodiment, the high-temperature reliability can be improved by insulating the corners 330 of the effective layer portion 14, which are likely to be a cause of a decrease in high-temperature load reliability.

[0090] The manganese segregation amount in the first region 351 is preferably 5 mol % or more and 10 mol % or less, and the magnesium segregation amount is preferably 5 mol % or more and 10 mol % or less. By setting the manganese segregation amount and the magnesium segregation amount within the above ranges, an insulating portion can be more efficiently provided in the internal electrode layer of the corner portion 330 of the effective layer portion 14. As a result, the high-temperature reliability of the multilayer ceramic capacitor 1 can be further improved.

[0091] If the amount of manganese or magnesium segregation in the first region 351 is less than 5 mol %, the corners 330 of the effective layer 14 will not be sufficiently insulated. If the amount of manganese or magnesium segregation in the first region 351 is more than 10 mol %, the insulating area will extend to areas other than the corners 330 of the effective layer 14. As a result, the capacitance of the multilayer ceramic capacitor 1 will decrease.

[0092] (Example) Examples of the multilayer ceramic capacitor 1 of this embodiment will be described with reference to Fig. 9. Fig. 9 is a table showing examples of the multilayer ceramic capacitor of this embodiment. The samples, evaluation items, evaluation conditions, etc. of the examples are as follows. According to the manufacturing method described below, samples in which the manufacturing conditions were adjusted so that the segregation amount was different were manufactured in lots as samples of Examples 1 to 6. The samples in each lot were manufactured under the same manufacturing conditions. For each Example, n=3 samples for segregation amount measurement, n=5 samples for capacitance evaluation, and n=77 samples for high-temperature load reliability evaluation were taken out and prepared from the same lot. In the segregation amount measurement and capacitance evaluation, evaluations were made using the average values ​​of the measurement results and evaluation results.

[0093] (sample) Dimensions of the multilayer ceramic capacitor: length L 3.15 mm, width W 1.65 mm, height T 1.65 mm Main material of dielectric layer: Barium titanate Capacity: 0.01μF Internal electrode layer material: Nickel

[0094] (Evaluation of high temperature load reliability) Applied voltage: 756V (×1.2WV), 125℃, 2000hr Number of samples: 77 Judgment criteria: 〇 (good) means 0 defective items, △ (fairly good) means 1 to 2 defective items

[0095] (Evaluation of capacitance (ΔC / C)) Capacitance C measuring device: LCR meter ΔC / C = (capacitance when magnesium and manganese are added (segregated) to the corners of the effective layer) - capacitance when magnesium and manganese are not added (not segregated) to the corners of the effective layer) / (capacitance when magnesium and manganese are not added (not segregated)) x 100 (%) Judgment criteria: 〇 (good) indicates ΔC / C is -10(%) or more, △ (fairly good) indicates ΔC / C is less than -10(%) and -30(%) or more

[0096] (Overall judgment) Judgment criteria: 〇 (good), △ (fairly good)

[0097] As shown in FIG. 9 , the evaluation of high-temperature reliability in all examples was judged to be either ◯ (good) or Δ (slightly good). In Example 5, in which the amount of manganese segregation in the region where segregation is observed in first region 351 is less than 5 mol % and the amount of magnesium segregation in the region where segregation is observed in first region 351 is less than 5 mol %, the evaluation of high-temperature reliability was judged to be Δ (slightly good). In Example 6, in which the amount of manganese segregation in the region where segregation is observed in first region 351 is more than 10 mol % and the amount of magnesium segregation in the region where segregation is observed in first region 351 is more than 10 mol %, ΔC / C was −20%. Therefore, the evaluation of the capacitance (ΔC / C) in Example 6 was judged to be Δ (slightly good).

[0098] Based on the results of the evaluation of high-temperature load reliability and the evaluation of capacitance (ΔC / C), the overall judgment of Examples 1 to 4 is ◯ (good), and the overall judgment of Examples 5 and 6 is △ (fairly good).

[0099] (Manufacturing method of multilayer ceramic capacitors) A method for manufacturing the multilayer ceramic capacitor 1 will be described with reference to Figs. 10 and 11. Fig. 10 is a diagram showing a side gap element 80, a first side gap sheet 91, and a second side gap sheet 92. Fig. 11 is a diagram showing a multilayer chip 90 in which the first side gap sheet 91 and the second side gap sheet 92 are laminated on the side gap element 80. In Figs. 10 and 11, the portions relating to the internal electrode layers are particularly simplified. Note that the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method below.

[0100] In the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment, manganese and magnesium are segregated at the corner portions 330 of the effective layer portion 14, and the laminate 2 is formed using the first side gap sheet 91 and the second side gap sheet 92 in order to turn the first region 351 into an insulating layer.

[0101] (Correspondence between laminate and laminated chip) In the following description, the laminate 2 before firing is referred to as a laminated chip 90. In the laminated chip 90, a portion corresponding to the first lateral surface outer layer portion 15 after firing is referred to as a first side gap sheet 91, and a portion corresponding to the second lateral surface outer layer portion 16 after firing is referred to as a second side gap sheet 92. In addition, in the laminated chip 90, a portion other than the first side gap sheet 91 and the second side gap sheet 92 is referred to as a side gap element 80.

[0102] In addition, in the side gap element 80, the portion corresponding to the first main surface side outer layer portion 12 after firing is referred to as the first element outer layer 81, and the portion corresponding to the second main surface side outer layer portion 13 after firing is referred to as the second element outer layer 82. In the side gap element 80, the portion other than the first element outer layer 81 and the second element outer layer 82 is referred to as the element inner layer 83. A portion of the element inner layer 83 becomes the effective layer portion 14 after firing.

[0103] (Side gap body) First, dielectric sheets for the first element body outer layer 81, the second element body outer layer 82, and the element body inner layer 83 are prepared. In addition, a conductive paste for the element body inner layer 83 is prepared. The dielectric sheets become the dielectric layers 20 in the laminate 2. The conductive paste becomes the internal electrode layers 30 in the laminate 2. Both the dielectric sheets and the conductive paste contain a binder and a solvent. The binder and solvent may be known. The conductive paste contains a metal powder, an organic binder, and an organic solvent.

[0104] On the dielectric sheet for the element inner layer 83, the conductive paste for the internal electrode layer 30 is printed using a printing plate patterned to the shape of the internal electrode layer 30. Examples of the printing method are screen printing and gravure printing. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0105] A predetermined number of dielectric sheets for the first element outer layer 81, on which the pattern of the internal electrode layer 30 is not printed, are stacked to form a portion that becomes the first main surface side outer layer portion 12. On top of that, dielectric sheets for the element inner layer 83, on which the pattern of the first internal electrode layer 31 is printed, and dielectric sheets for the element inner layer 83, on which the pattern of the second internal electrode layer 32 is printed, are stacked alternately in this order. In this way, an element inner layer 83 is formed in which dielectric sheets 84 for the element inner layer 83 and conductive paste 85 printed on the dielectric sheets 84 are stacked alternately.

[0106] Further laminated on top of this is the portion that will become the second main surface side outer layer portion 13. This portion is formed by laminating a predetermined number of dielectric sheets for the second element body outer layer 82, on which the pattern of the internal electrode layer 30 is not printed. In this way, the side gap element body 80 is obtained.

[0107] (Side gap seat) A predetermined number of dielectric sheets for the first side gap sheet 91, on which no conductive paste is printed, are stacked to obtain the first side gap sheet 91. The second side gap sheet 92 is obtained in the same manner.

[0108] 10, a first side gap sheet 91 is laminated on the first LT surface 87 of the side gap element 80. Similarly, as shown by arrow 96, a second side gap sheet 92 is laminated on the second LT surface 88 of the side gap element 80. In this way, a laminated chip 90 is obtained.

[0109] Figure 11 shows laminated chip 90. As shown in Figure 11, the portions corresponding to first corner 331, second corner 332, third corner 333, and fourth corner 334 are located in positions that are partially surrounded by the outer layer dielectric sheet and the side gap sheet dielectric sheet.

[0110] (Addition of magnesium and manganese to dielectric sheets) Segregation of manganese and magnesium at the corners 330 of the effective layer 14 and insulating the corners 330 can be achieved by causing magnesium and manganese to segregate from the dielectric sheets for the first element outer layer 81, the second element outer layer 82, the first side gap sheet 91, and the second side gap sheet 92 to the corners 330 of the effective layer 14. Therefore, in addition to the dielectric sheet for the element inner layer 83, the dielectric sheets for the first element outer layer 81, the second element outer layer 82, the first side gap sheet 91, and the second side gap sheet 92 each contain magnesium and manganese at 3 mol % to 5 mol %. This allows the concentrations of magnesium and manganese to be higher in the corners 330 of the effective layer 14 than in other parts.

[0111] As described above, the corners 330 of the effective layer 14 are close to the dielectric sheets for the outer layers and the dielectric sheets for the side gap sheets. Therefore, the corners 330 of the effective layer 14 are susceptible to migration of magnesium and manganese contained in the dielectric sheets for the outer layers and the dielectric sheets for the side gap sheets. Therefore, the concentrations of magnesium and manganese in the corners 330 of the effective layer 14 can be easily increased.

[0112] The laminated chip is then fired to obtain the laminate 2. Before firing, the laminated chip may be pressed or polished by barrel polishing or the like to round off corners or ridges, as necessary. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably, for example, 900°C or higher and 1400°C or lower.

[0113] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 2. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer is formed by applying a conductive paste containing a glass component and a metal to the laminate 2 by a method such as dipping, and then performing a baking process. The temperature for the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0114] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, the ceramic material added is preferably the same type as that of the dielectric layer 20. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 2 with the fired layer.

[0115] Thereafter, a plating layer is formed on the surface of the base electrode layer 50, which is made of a baked layer. In this embodiment, a first plating layer 71 is formed on the surface of the first base electrode layer 51. A second plating layer 72 is formed on the surface of the second base electrode layer 52. In this embodiment, a nickel plating layer and a tin plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which makes the process more complicated. Therefore, it is usually preferable to use electrolytic plating. The nickel plating layer and the tin plating layer are formed sequentially, for example, by barrel plating.

[0116] When a conductive resin layer is provided, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, followed by heat treatment at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably a nitrogen atmosphere. To prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0117] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0118] As described above, in the multilayer ceramic capacitor 1 of this embodiment, by concentrating the segregation of manganese and magnesium in the internal electrode layers 30 at the corners 330 of the effective layer portion 14, the corners 330, which are weak points in high-temperature load reliability, can be made into insulating layers, thereby improving high-temperature reliability. As a result, in the multilayer ceramic capacitor 1 of this embodiment, the thicknesses of the dielectric layers and the internal electrode layers are likely to be thin near the corners of the multilayer ceramic capacitor, and it is possible to suppress a decrease in high-temperature load reliability starting from these thinned portions.

[0119] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. A combination of two or more of the individual desirable configurations described in the above-described embodiments also constitutes the present invention. [Explanation of symbols]

[0120] 1. Multilayer ceramic capacitors 2. Laminate 3 First main surface 4 Second main surface 5. First Aspect 6. The Second Aspect 7 First end face 8 Second end face 10 Inner layer 11 Outer layer on main surface side 14 Effective layer 20 dielectric layer 21 Inner dielectric layer 22 outer dielectric layer 30 Internal electrode layer 40 External electrode 50 Base electrode layer 80 Side gap body 81 First outer layer of the element 82 Second outer layer of the body 83 Inner layer of element 84 Dielectric Sheet 85 Conductive Paste 90 stacked chips 91 First Side Gap Sheet 92 Second Side Gap Sheet 330 Corner 351 First Area 352 Second Area L lengthwise T Height direction W width direction

Claims

1. a plurality of dielectric layers stacked one upon the other and a plurality of internal electrode layers stacked one upon the other; a first main surface and a second main surface facing each other in a height direction; a first side surface and a second side surface facing each other in a width direction perpendicular to the height direction; a first end surface and a second end surface facing each other in a length direction perpendicular to the height direction and the width direction; an effective layer portion formed by alternately stacking the dielectric layers and the internal electrode layers; a laminate including outer layer portions arranged to sandwich the effective layer portion from the first principal surface side and the second principal surface side; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface; In a multilayer ceramic capacitor having In a cross section of the laminate in a plane parallel to the width direction and the height direction, the effective layer portion has a first region defined by four corners of the effective layer portion and a second region defined as a region of the effective layer portion excluding the first region, A multilayer ceramic capacitor, wherein the segregation amounts of manganese and magnesium in the first region are greater than the segregation amounts of manganese and magnesium in the second region, and the internal electrode layers in the first region include insulating portions.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the segregation amount of manganese in the insulating portion of the first region is 5 mol % or more and 10 mol % or less, and the segregation amount of magnesium is 5 mol % or more and 10 mol % or less.

Images