Signal transmission device, electronic apparatus, vehicle, and insulated gate driver IC

Abstract

To stably transmit a plurality of signals.SOLUTION: The signal transmission device 400 includes a transmission circuit 411, a reception circuit 421, and a plurality of insulating elements 431 (1) to (n) that respectively transmit a plurality of signals I11 (1) to (n) from the transmission circuit 411 to the reception circuit 412 while insulating between the transmission circuit 411 and the reception circuit 421 (for example, n = 3). The transmission circuit 411 includes an oscillation circuit 510 that generates a plurality of clock signals CK (1) to (n) having different phases, and a plurality of drive circuits 520 (1) to (n) that drive the plurality of insulating elements 431 (1) to (n) in synchronization with the plurality of clock signals CK (1) to (n), respectively.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present disclosure relates to a signal transmission device, an electronic device, a vehicle, and an isolated gate driver integrated circuit (IC). [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] An example of the prior art related to the above is Patent Document 1 by the applicant of the present application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944

[0005] [overview] Conventional signal transmission devices have room for improvement in terms of multi-channelization.

[0006] For example, a signal transmission device according to the present disclosure includes a transmitting circuit, a receiving circuit, and a plurality of isolation elements configured to transmit a plurality of signals from the transmitting circuit to the receiving circuit while isolating the transmitting circuit from the receiving circuit, respectively, and the transmitting circuit includes an oscillator circuit configured to generate a plurality of clock signals having different phases, and a plurality of drive circuits configured to drive the plurality of isolation elements in synchronization with each of the plurality of clock signals. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2]FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a signal transmission device. [Figure 11] FIG. 11 is a diagram illustrating an example of a pulse generation operation. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of a receiving circuit. [Figure 13] FIG. 13 is a diagram showing an example of multi-channel driving. [Figure 14] FIG. 14 is a diagram showing how signals are attenuated during multi-channel driving. [Figure 15] FIG. 15 is a diagram illustrating a comparative example of a transmission circuit. [Figure 16] FIG. 16 is a diagram showing an example of drive timing in the comparative example. [Figure 17] FIG. 17 is a diagram illustrating a first embodiment of a transmission circuit. [Figure 18] FIG. 18 is a diagram showing an example of drive timing in the first embodiment. [Figure 19] FIG. 19 is a diagram illustrating a second embodiment of the transmission circuit. [Figure 20]FIG. 20 is a diagram showing an example of drive timing in the second embodiment. [Figure 21] FIG. 21 is a diagram illustrating a third embodiment of the transmission circuit. [Figure 22] FIG. 22 is a diagram showing an example of drive timing in the third embodiment. [Figure 23] FIG. 23 is a diagram illustrating a fourth embodiment of the transmission circuit. [Figure 24] FIG. 24 is a diagram showing how the drive timings overlap. [Figure 25] FIG. 25 is a diagram showing the temperature dependence of the oscillation frequency. [Figure 26] FIG. 26 is a diagram showing the exterior of the vehicle.

[0008] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0020] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0024] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0074] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0085] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the breakdown voltage of the insulating layer 51 is enhanced.

[0088] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulating layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81 respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this embodiment, the dummy pattern 85 is routed at a line density per unit area equal to that of the high-potential coil 23. The line density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0133] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] <Signal transmission device> 10 is a diagram showing an example of the configuration of a signal transmission device 400. The signal transmission device 400 of this example configuration includes a first chip 410, a second chip 420, and a third chip 430. The first chip 410, the second chip 420, and the third chip 430 may be sealed in a single package. The signal transmission device 400 may be provided to the market as an integrated semiconductor integrated circuit device (a so-called insulated gate driver IC).

[0154] The first chip 410 has integrated therein, for example, a transmitting circuit 411. The transmitting circuit 411 generates pulse signals I11 and I12 in accordance with the logic level of an externally input control signal DIN. For example, the transmitting circuit 411 generates the pulse signal I11 when the control signal DIN is at a high level. The transmitting circuit 411 also generates the pulse signal I12 when the control signal DIN is at a low level. The pulse signals I11 and I12 are each pulse-driven in synchronization with a reference clock signal CK. The reference clock signal CK may be input from outside the signal transmission device 400 or may be generated inside the signal transmission device 400.

[0155] For example, a receiving circuit 421 is integrated on the second chip 420. The receiving circuit 421 outputs an output pulse signal GO in response to the induced currents I21 and I22 input from the third chip 430 (details will be described later).

[0156] For example, a plurality of transformers 431 and 432 are integrated in the third chip 430. The transformers 431 and 432 correspond to insulating elements for transmitting the pulse signals I11 and I12 of the first chip 410 as pulse signals (induced currents I21 and I22) of the second chip 420 while electrically insulating the transmitting circuit 411 from the receiving circuit 421.

[0157] Referring to the figure, the transformer 431 includes a primary coil 431p to which a pulse signal I11 is applied and a secondary coil 431s that is electromagnetically coupled to the primary coil 431p to induce an induction current I21. The transformer 432 includes a primary coil 432p to which a pulse signal I12 is applied and a secondary coil 432s that is electromagnetically coupled to the primary coil 432p to induce an induction current I22. Second terminals of the secondary coils 431s and 432s are both connected to a terminal to which a reference voltage SI is applied.

[0158] It should be noted that a capacitor may be used as the insulating element instead of the transformer.

[0159] <Transmitting circuit> Continuing with reference to FIG. 10, the configuration and operation of the transmission circuit 411 will be described. The transmission circuit 411 includes transistors 411a to 411d, an edge detection circuit 411e, an AND gate 411f, buffers 411g and 411i, and an inverter 411h. The transistors 411a and 411c may be P-channel type. The transistors 411b and 411d may be N-channel type.

[0160] The source and back gate of the transistor 411a are connected to a power supply terminal. The source and back gate of the transistor 411b are connected to a ground terminal. The drains of the transistors 411a and 411b are connected to a terminal to which a pulse signal I11 is applied. The gate of the transistor 411a is connected to a terminal to which a gate signal G1 is applied. The gate of the transistor 411b is connected to a terminal to which a gate signal G2 is applied. The transistors 411a and 411b connected in this manner function as a first half-bridge output stage for outputting the pulse signal I11 in response to the gate signals G1 and G2.

[0161] The source and back gate of the transistor 411c are connected to the power supply terminal. The source and back gate of the transistor 411d are connected to the ground terminal. The drains of the transistors 411c and 411d are connected to the application terminal of the pulse signal I12. The gate of the transistor 411c is connected to the application terminal of the gate signal G3. The gate of the transistor 411d is connected to the application terminal of the gate signal G4. The transistors 411c and 411d connected in this manner function as a second half-bridge output stage for outputting the pulse signal I12 in response to the gate signals G3 and G4. The gate signal G4 may be fixed to a low level.

[0162] The edge detection circuit 411e detects a pulse edge (rising edge or falling edge) of the reference clock signal CK and outputs an edge detection signal S1. The edge detection signal S1 may be, for example, a pulse signal that falls from a high level to a low level for a predetermined period in synchronization with the rising edge of the reference clock signal CK.

[0163] The AND gate 411f outputs a logical product signal S2 of the control signal DIN and the edge detection signal S1. Therefore, the logical product signal S2 is at a low level when at least one of the control signal DIN and the edge detection signal S1 is at a low level. The logical product signal S2 is at a high level when both the control signal DIN and the edge detection signal S1 are at a high level.

[0164] The buffer 411g generates the gate signal G1 by buffering and amplifying the logical product signal S2 while maintaining its logical level. Therefore, the gate signal G1 goes high when the logical product signal S2 is high. At this time, the transistor 411a is turned off. Also, the gate signal G1 goes low when the logical product signal S2 is low. At this time, the transistor 411a is turned on.

[0165] The inverter 411h generates the gate signal G2 by inverting the logic level of the control signal DIN. Therefore, the gate signal G2 is at a low level when the control signal DIN is at a high level. At this time, the transistor 411b is in an off state. Furthermore, the gate signal G2 is at a high level when the control signal DIN is at a low level. At this time, the transistor 411b is in an on state.

[0166] The buffer 411i generates the gate signal G3 by buffering and amplifying the edge detection signal S1 while maintaining its logic level. Therefore, the gate signal G3 goes high when the edge detection signal S1 is high. At this time, the transistor 411c is turned off. Also, the gate signal G3 goes low when the edge detection signal S1 is low. At this time, the transistor 411c is turned on.

[0167] 11 is a diagram showing an example of a pulse generation operation in the transmission circuit 411. In this diagram, from top to bottom, the control signal DIN, the reference clock signal CK, the edge detection signal S1, and the pulse signals I11 and I12 are depicted.

[0168] As shown in the figure, during the high level period of the control signal DIN, both pulse signals I11 and I12 are pulse-driven in synchronization with the reference clock signal CK, whereas during the low level period of the control signal DIN, only pulse signal I12 is pulse-driven in synchronization with the reference clock signal CK.

[0169] <Receiving circuit> 12 is a diagram showing an example of the configuration of the receiving circuit 421. The receiving circuit 421 of this example configuration includes, for example, transistors n1 to n5, transistors N1 to N6, a transistor P1, capacitors C1 to C5, resistors R1 to R7, and diodes D1 to D5. The transistors n1 to n5 may be of an npn type. The transistors N1 to N6 may be of an N-channel type. The transistor P1 may be of a P-channel type. The diode D1 may be a Zener diode.

[0170] The base and collector of transistor n1 are connected to the application terminal of induced current I21 (=first terminal of secondary coil 431s). The emitter of transistor n1 and the base and collector of transistor n2 are all connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is connected to the application terminal of induced current I22 (=first terminal of secondary coil 432s). The emitter of transistor n2 and the first terminal of resistor R1 are both connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the application terminal of induced current I21.

[0171] The second terminal of resistor R1, the drain of transistor N1, and the cathode of diode D1 are all connected to an application terminal for output pulse signal GO. The source and back gate of transistor N1 and the anode of diode D1 are all connected to an application terminal for reference voltage SI. Diode D1 corresponds to an electrostatic protection element.

[0172] The base and collector of the transistor n3 are connected to the application terminal of the inductive current I22. The emitter of the transistor n3 is connected to the first terminal of the resistor R3. The second terminal of the resistor R3 is connected to the gate of the transistor N1.

[0173] The collector of transistor n4 and the first terminal of capacitor C3 are both connected to the application terminal of induced current I21. The base of transistor n4 is connected to the second terminal of capacitor C3 and the first terminal of resistor R2. The emitter of transistor n4 and the second terminal of resistor R2 are both connected to the first terminal of resistor R4. The second terminal of resistor R4 is connected to the gate of transistor N2. The source and back gate of transistor N2 are both connected to the application terminal of reference voltage SI. The drain of transistor N2 is connected to the gate of transistor N1.

[0174] The first terminals of the resistor R5 and the capacitor C5 are both connected to the node to which the reference voltage SI is applied, and the second terminals of the resistor R5 and the capacitor C5 are both connected to the gate of the transistor N12.

[0175] The collector of transistor n5 and the first terminal of capacitor C4 are both connected to the application terminal of induced current I22. The base of transistor n5 is connected to the second terminal of capacitor C4 and the first terminal of resistor R6. The emitter of transistor n5 and the second terminal of resistor R6 are both connected to the first terminal of resistor R7.

[0176] The gates of transistors N3 and N4 are both connected to the drain of transistor N3. The drain of transistor N3 is connected to the second terminal of resistor R7. The drain of transistor N4 is connected to the gate of transistor N2. The sources and back gates of transistors N3 and N4 are both connected to the terminal to which reference voltage SI is applied. Transistors N3 and N4 form a current mirror that replicates the drain current of transistor N3 as the drain current of transistor N4.

[0177] The cathodes of diodes D2 and D5 are connected to the drain of transistor N5. The anode of diode D2 and the cathode of diode D3 are all connected to the application terminal of induced current I21. The anodes of diodes D3 and D4 and the source, gate, and back gate of transistor N5 are all connected to the application terminal of reference voltage SI. The cathode of diode D4 and the anode of diode D5 are all connected to the application terminal of induced current I22. Diodes D2 to D5 and transistor N5 correspond to electrostatic protection elements.

[0178] The drain of transistor N6 is connected to the application terminal of output pulse signal GO. The source, gate, and back gate of transistor N6 are all connected to the application terminal of reference voltage SI. The drain of transistor N7 is connected to the application terminal of substrate voltage PSUB. The source, gate, and back gate of transistor N7 are all connected to the application terminal of reference voltage SI. Transistors N6 and N7 correspond to electrostatic protection elements.

[0179] The signal transmission device 400 is mounted on the electronic device A together with the switch circuit 440. The signal transmission device 400 and the switch circuit 440 may be sealed in a common package.

[0180] The switch circuit 440 includes transistors 441 and 442. Both the transistors 441 and 442 may be N-channel transistors.

[0181] The sources and back gates of the transistors 441 and 442 are both connected to a terminal to which a reference voltage SI is applied, and the gates of the transistors 441 and 442 are both connected to a terminal to which an output pulse signal GO is applied.

[0182] In the first connection mode, the drain of the transistor 441 can be connected to the application terminal of the power supply voltage VCC2 via the load ZL1, and the drain of the transistor 442 can be connected to the application terminal of the ground voltage GND2. In this case, the switch circuit 440 functions as a lower switch.

[0183] In a second connection mode, the drain of the transistor 441 can be connected to the application terminal of the ground voltage GND2 via the load ZL2, and the drain of the transistor 442 can be connected to the application terminal of the power supply voltage VCC2. In this case, the switch circuit 440 functions as an upper switch.

[0184] Next, the basic operation of the signal transmission device 400 will be described. During the high-level period of the control signal DIN, pulse driving of the pulse signals I11 and I12 is initiated. Therefore, induced currents I21 and I22 are generated in the second chip 420. This causes the output pulse signal GO to rise to a high level. As a result, the transistors 441 and 442 are turned on, and a drive current can be supplied to the load ZL1 (or load ZL2).

[0185] On the other hand, during the low-level period of the control signal DIN, the pulse signal I11 stops being pulsed, while the pulse signal I12 continues being pulsed. Therefore, the induced current I21 stops flowing, while the induced current I22 continues to flow. This causes the output pulse signal GO to fall to a low level. As a result, the transistors 441 and 442 are both turned off, and no drive current is supplied to the load ZL1 (or load ZL2).

[0186] <Multi-channel drive> 13 is a diagram showing an example of multi-channel driving in a signal transmission device 400. The signal transmission device 400 in this diagram includes a transmission circuit 411, a reception circuit 421, and transformers 431 and 432 for two channels. In this diagram, the transmission circuit 411, the reception circuit 421, and the transformers 431 and 432 that make up channel CH(1) are each designated by a suffix (1). On the other hand, the transmission circuit 411, the reception circuit 421, and the transformers 431 and 432 that make up channel CH(2) are each designated by a suffix (2).

[0187] As mentioned above, in insulated communication using a transformer (coil), signal transmission from the primary side to the secondary side is achieved by passing a current pulse (= the aforementioned pulse signal I11) through the transformer (coil). The strength of the communication at this time is determined by the amplitude of the current pulse. In other words, the larger the amplitude of the current pulse, the more stable the signal transmission from the primary side to the secondary side.

[0188] However, the above current pulse causes a momentary drop in the power supply voltage VCC1. In particular, when the communication timings of channels CH(1) and CH(2) are close to each other, the amplitude of the current pulse decreases due to the drop in the power supply voltage VCC1, which can impair the stability of signal transmission.

[0189] Figure 14 shows how signals are attenuated during multi-channel driving. The upper part shows the power supply voltage VCC1. The lower part shows the pulse signal I11(*) (where *=1, 2, ..., n).

[0190] As shown in this diagram, when multiple channels are driven simultaneously, the drop in power supply voltage VCC1 is greater than when a single channel is driven. In particular, the greater the number of channels driven simultaneously, the greater the drop in power supply voltage VCC1 can be. Furthermore, if the timing of a drop in power supply voltage VCC1 coincides with the timing of isolated communication, the amplitude of pulse signal I11(*) may decrease.

[0191] <Transmitter circuit (comparison example)> 15 is a diagram showing a comparative example of a transmission circuit 411 (= an example of a circuit configuration to be compared with the embodiments described later). The transmission circuit 411 of this comparative example includes an oscillation circuit 510 and three-channel drive circuits 520(1) to (3). The number of channels may be two, or may be four or more.

[0192] The oscillation circuit 510 includes an oscillator 501. The oscillator 501 generates a reference clock signal CK.

[0193] The drive circuits 520(1) to (3) each drive a corresponding transformer (not shown) in synchronization with a reference clock signal CK common to all channels. The drive circuits 520(1) to (3) can be understood as functional blocks including the circuit elements 411a to 411i depicted in FIG. 10.

[0194] 16 is a diagram showing an example of drive timing in this comparative example. From the top, the diagram depicts a reference clock signal CK, the drive timing of each of drive circuits 520(1) to (3), and a power supply voltage VCC1.

[0195] The drive timing of each of the drive circuits 520(1) to (3) is determined in synchronization with a common reference clock signal CK (rising edge in this figure). Therefore, the drive timing of each of the drive circuits 520(1) to (3) overlaps between channels. As a result, the drop in the power supply voltage VCC1 becomes larger. The larger the drop in the power supply voltage VCC1, the more likely it is that the amplitude of each of the pulse signals I11(1) to (3) will decrease, which may impair the stability of signal transmission.

[0196] In view of the above considerations, an embodiment that allows stable signal transmission even during multi-channel driving will be proposed below.

[0197] <Transmitter Circuit (First Embodiment)> 17 is a diagram showing a first embodiment of a transmission circuit 411. The transmission circuit 411 of this embodiment is based on the comparative example (FIG. 15) described above, with a modification made to the configuration of the oscillation circuit 510. Referring to this diagram, the oscillation circuit 510 includes delay circuits 502(1) to (3) in addition to the oscillator 501 described above.

[0198] The delay circuits 502(1) to (3) are connected in series to the output terminal of the oscillator 501, that is, the terminal to which the reference clock signal CK is applied.

[0199] A reference clock signal CK is input from an oscillator 501 to a delay circuit 502(1) provided in the first stage at the most upstream position. The delay circuit 502(1) delays the reference clock signal CK to generate a clock signal CK(1). The clock signal CK(1) is output to a drive circuit 520(1). The drive circuit 520(1) drives a transformer (not shown) of channel CH(1) in synchronization with the clock signal CK(1).

[0200] The delay circuit 502(2) provided in the second stage receives the clock signal CK(1) from the delay circuit 502(1). The delay circuit 502(2) delays the clock signal CK(1) to generate a clock signal CK(2). The clock signal CK(2) is output to the drive circuit 520(2). The drive circuit 520(2) drives a transformer (not shown) of the channel CH(2) in synchronization with the clock signal CK(2).

[0201] The delay circuit 502(3) provided in the third stage, which is the most downstream, receives the clock signal CK(2) from the delay circuit 502(2). The delay circuit 502(3) delays the clock signal CK(2) to generate a clock signal CK(3). The clock signal CK(3) is output to a drive circuit 520(3). The drive circuit 520(3) drives a transformer (not shown) of the channel CH(3) in synchronization with the clock signal CK(3).

[0202] In this way, the oscillator circuit 510 generates clock signals CK(1) to (3) with different phases by using the delay circuits 502(1) to (3).

[0203] The drive circuits 520(1)-(3) drive their corresponding transformers (not shown) in synchronization with the clock signals CK(1)-(3), respectively. As mentioned above, the drive circuits 520(1)-(3) can be understood as functional blocks including the circuit elements 411a-411i depicted in FIG. 10, respectively.

[0204] Fig. 18 is a diagram showing an example of drive timing in the first embodiment. In this diagram, similar to Fig. 16, from top to bottom, the reference clock signal CK, the drive timing of each of the drive circuits 520(1) to (3), and the power supply voltage VCC1 are depicted.

[0205] The drive timing of each of the drive circuits 520(1)-(3) is determined in synchronization with clock signals CK(1)-(3) of different phases. Therefore, the drive timing of each of the drive circuits 520(1)-(3) is shifted between channels. As a result, the drop in the power supply voltage VCC1 is reduced. The smaller the drop in the power supply voltage VCC1, the less likely the amplitude of each of the pulse signals I11(1)-(3) to decrease, thereby improving the stability of signal transmission.

[0206] <Transmitter Circuit (Second Embodiment)> 19 is a diagram showing a second embodiment of the transmission circuit 411. The transmission circuit 411 of this embodiment includes an oscillation circuit 510 and four-channel drive circuits 520(1) to (4). The number of channels may be two, three, or five or more.

[0207] The oscillation circuit 510 includes inverters 503(1) to (5). The input terminal of the inverter 503(1) and the output terminal of the inverter 503(5) are both connected to the application terminal of the clock signal CK(0). The output terminal of the inverter 503(1) and the input terminal of the inverter 503(2) are both connected to the application terminal of the clock signal CK(1). The output terminal of the inverter 503(2) and the input terminal of the inverter 503(3) are both connected to the application terminal of the clock signal CK(2). The output terminal of the inverter 503(3) and the input terminal of the inverter 503(4) are both connected to the application terminal of the clock signal CK(3). The output terminal of the inverter 503(4) and the input terminal of the inverter 503(5) are both connected to the application terminal of the clock signal CK(4).

[0208] The inverter 503(1) inverts the logic level of the clock signal CK(0) to generate the clock signal CK(1). Therefore, when the clock signal CK(0) rises from low to high, the clock signal CK(1) falls from high to low. Conversely, when the clock signal CK(0) falls from high to low, the clock signal CK(1) rises from low to high. The rising / falling timing of the clock signal CK(1) lags behind the falling / rising timing of the clock signal CK(0). Therefore, the inverter 503(1) also functions as a delay circuit that delays the clock signal CK(0) to generate the clock signal CK(1).

[0209] Similarly to the above, inverter 503(2) inverts and delays the logic level of clock signal CK(1) to generate clock signal CK(2). Inverter 503(3) inverts and delays the logic level of clock signal CK(2) to generate clock signal CK(3). Inverter 503(4) inverts and delays the logic level of clock signal CK(3) to generate clock signal CK(4). Inverter 503(5) inverts and delays the logic level of clock signal CK(4) to generate clock signal CK(0).

[0210] In this way, the oscillation circuit 510 can be understood as a ring oscillator including inverters 503(1)-(5) connected in a ring. The oscillation circuit 510 outputs clock signals CK(1)-(4) with different phases from the output terminals of the inverters 503(1)-(4), i.e., from the intermediate nodes of the ring oscillator.

[0211] The drive circuits 520(1)-(4) drive their corresponding transformers (not shown) in synchronization with the clock signals CK(1)-(4), respectively. As mentioned above, the drive circuits 520(1)-(4) can be understood as functional blocks including the circuit elements 411a-411i depicted in FIG. 10, respectively.

[0212] 20 is a diagram showing an example of drive timing in the second embodiment, in which clock signals CK(1) to CK(4) are depicted in order from the top.

[0213] The drive timing of each of the drive circuits 520(1) to (4) is determined in synchronization with one edge, for example, the rising edge, of each of the clock signals CK(1) to (4) having different phases. Therefore, the drive timing of each of the drive circuits 520(1) to (4) is shifted between channels. Note that the drive timing of each of the drive circuits 520(1) to (4) may also be determined in synchronization with the falling edge of each of the clock signals CK(1) to (4).

[0214] For example, consider a case where the oscillator circuit 510 is configured with five stages of inverters 503(1)-(5). In this case, the drive timing of each of the drive circuits 520(1)-(4) is shifted by at least T / 5, where T is the period of each of the clock signals CK(0)-(4). As a result, the drop in the power supply voltage VCC1 becomes smaller. The smaller the drop in the power supply voltage VCC1, the less likely the amplitude of each of the pulse signals I11(1)-(4) to decrease, thereby improving the stability of signal transmission.

[0215] <Transmitter Circuit (Third Embodiment)> 21 is a diagram showing a third embodiment of the transmission circuit 411. The transmission circuit 411 of this embodiment is based on the second embodiment (FIG. 19) described above, but changes are made to the drive timing of each of the drive circuits 520(1) to (4), the power supply path to the drive circuits 520(1) to (4), and the configuration of the oscillation circuit 510.

[0216] The first change is that the drive timing of each of the drive circuits 520(1) to (4) is determined in synchronization with both edges, i.e., both rising and falling edges, of the clock signals CK(1) to (4) that have different phases.

[0217] This configuration makes it possible to double the drive timing of each of the drive circuits 520(1)-(4) while maintaining the oscillation frequency f(=1 / T) of each of the clock signals CK(0)-(4). This configuration is particularly effective in applications where it is desired to increase the signal transmission speed, such as insulated gate driver ICs.

[0218] However, if the above changes are made to the second embodiment (FIG. 19) without any special measures, the phase shift between the channels will be reduced to T / 10. Therefore, if the oscillation frequency f of each of the clock signals CK(1) to CK(4) is high, there is a risk that the drive timings of the drive circuits 520(1) to CK(4) will overlap.

[0219] Therefore, as a second change, the drive circuits 520(1) to (4) are supplied with power from different power supply lines depending on the groups to which they belong. For example, the drive circuits 520(1) and (2) belonging to group GRP1 are both supplied with power from the application terminal of power supply voltage VCC1 via power supply line PL1. On the other hand, the drive circuits 520(3) and (4) belonging to group GRP2 are both supplied with power from the application terminal of power supply voltage VCC1 via power supply line PL2.

[0220] With this configuration, even if the drive timing of the drive circuits 520(1) and (2) belonging to group GRP1 and the drive timing of the drive circuits 520(3) and (4) belonging to group GRP2 are close to each other, the influence between the two groups is unlikely to be felt. Therefore, a drop in the power supply voltage VCC1 can be suppressed.

[0221] In particular, to minimize the influence between channels, it is desirable to provide separate and independent power supply lines PL(1)-(4) for the drive circuits 520(1)-(4). However, if it is difficult to adopt such a configuration due to chip area restrictions, a certain degree of effect can be achieved simply by providing at least two separate power supply lines L1 and L2, as proposed in this embodiment.

[0222] It is also desirable that the power supply lines PL1 and PL2 are connected to separate power supply terminals, but if it is difficult to adopt such a configuration, the power supply lines PL1 and PL2 may ultimately be connected to a common power supply terminal.

[0223] The configuration in which the power supply lines are separated among multiple channels can be applied not only to the case in which the drive circuits 520(1) to (4) are synchronized with both edges of the clock signals CK(1) to (4), but also to the case in which they are synchronized with one edge.

[0224] Furthermore, with the provision of the two-split power supply lines PL1 and PL2, the third change is that the clock signals CK(i) and (i+1) output from adjacent inverters 503(i) and (i+1) (where i=1, 2, or 3) among inverters 503(1) to (4), respectively, are output to drive circuits belonging to different groups GRP1 or GRP2 among drive circuits 520(1) to (4).

[0225] Referring to this figure, the drive circuits 520(1) to (4) are not assigned in order as the output destinations of the clock signals CK(1) to (4), but the order of the output destinations of the clock signals CK(2) and (3) is swapped. Specifically, the clock signal CK(2) is output to the drive circuit 520(3), and the clock signal CK(3) is output to the drive circuit 520(2).

[0226] Focusing on inverters 503(1) and (2), clock signal CK(1) is output to drive circuit 520(1) belonging to group GRP1, while clock signal CK(2) is output to drive circuit 520(3) belonging to group GRP2.

[0227] Focusing on inverters 503(2) and (3), clock signal CK(2) is output to drive circuit 520(3) belonging to group GRP2, while clock signal CK(3) is output to drive circuit 520(2) belonging to group GRP1.

[0228] Focusing on inverters 503(3) and (4), clock signal CK(3) is output to drive circuit 520(2) belonging to group GRP1, while clock signal CK(4) is output to drive circuit 520(4) belonging to group GRP2.

[0229] With this configuration, a phase difference can be created in the drive timing between the drive circuits 520(1) and (2) belonging to group GRP1, and between the drive circuits 520(3) and (4) belonging to group GRP2.

[0230] Fig. 22 is a diagram showing an example of drive timing in the third embodiment. In this diagram, as in Fig. 20, clock signals CK(1) to (4) are depicted in order from the top.

[0231] As shown in this figure, the drive timing of each of the drive circuits 520(1) to (4) is determined in synchronization with both the rising edge and the falling edge of each of the clock signals CK(1) to (4).

[0232] As described above, the order of the output destinations of the clock signals CK(2) and (3) is reversed, so that a phase difference of at least T / 5 can be ensured between the drive timings of the drive circuits 520(1) and (2) belonging to group GRP1 and the drive timings of the drive circuits 520(3) and (4) belonging to group GRP2.

[0233] <Transmitter Circuit (Fourth Embodiment)> 23 is a diagram showing a fourth embodiment of the transmission circuit 411. The transmission circuit 411 of this embodiment is based on the second embodiment (FIG. 19) and further includes frequency divider circuits 504(1)-(4), multiplexers 505(1)-(4), and a trimming circuit 506.

[0234] The frequency divider circuits 504(1) to (4) respectively divide the frequency of the clock signals CK(1) to (4) to generate frequency-divided clock signals CK(1)' to (4)'.

[0235] The multiplexers 505(1)-(4) each select one of the clock signals CK(1)-(4) and the divided clock signals CK(1)'-(4)' as selected clock signals CK(1)"-(4)" in response to the mode switching signal SEL, and output the selected clock signals CK(1)"-(4)" to the drive circuits 520(1)-(4). For example, when the mode switching signal SEL is at a high level (= a logic level in high-speed mode), the clock signals CK(1)-(4) are selected and output as selected clock signals CK(1)"-(4)". On the other hand, when the mode switching signal SEL is at a low level (= a logic level in low-speed mode), the divided clock signals CK(1)'-(4)' are selected and output as selected clock signals CK(1)"-(4)".

[0236] The mode switching signal SEL may be input from outside the signal transmission device 400, or may be read from a memory or register built into the signal transmission device 400.

[0237] The driving circuits 520(1) to (4) drive the corresponding transformers (not shown) in synchronization with the selected clock signals CK(1)" to (4)" output from the multiplexers 505(1) to (4), respectively.

[0238] With this configuration, the drive frequency of each of the drive circuits 520(1) to (4) can be arbitrarily switched by switching the logic level of the mode switching signal SEL. Therefore, when high-speed drive is not required, the phase difference between the channels can be widened by lowering the drive frequency of each of the drive circuits 520(1) to (4). This configuration is particularly effective in applications such as isolated gate driver ICs, where the required signal transmission speed varies greatly depending on the specifications.

[0239] The trimming circuit 506 adjusts the oscillation frequency f of each of the clock signals CK(0) to (4). For example, the trimming circuit 506 may adjust the drive current of each of the inverters 503(1) to (5). In this case, the greater the drive current of each of the inverters 503(1) to (5), the higher the oscillation frequency f of each of the clock signals CK(0) to (4). Conversely, the greater the drive current of each of the inverters 503(1) to (5), the lower the oscillation frequency f of each of the clock signals CK(0) to (4). The trimming circuit 506 may also be used to fine-tune the oscillation frequency f.

[0240] Furthermore, the trimming circuit 506 may adjust the drive current of each of the inverters 503(1)-(5) so as to lower the oscillation frequency f of each of the clock signals CK(0)-(4) in the low-speed mode (SEL=L) and to raise the oscillation frequency f of each of the clock signals CK(0)-(4) in the high-speed mode (SEL=H). In this case, the previously mentioned frequency divider circuits 504(1)-(4) and multiplexers 505(1)-(4) may be omitted.

[0241] <Considerations regarding high-speed driving> 24 is a diagram showing overlapping drive timings of multiple channels. From top to bottom, the diagram shows a reference clock signal CK, pulse signals I11(1) and I11(2), and an added pulse signal I11(1)+I11(2). The added pulse signal I11(1)+I11(2) can be understood as a combined current flowing through the terminal to which the power supply voltage VCC1 is applied. The reference clock signal CK can also be interpreted as the clock signals CK(1)-(n) described above.

[0242] If the oscillation frequency f of the reference clock signal CK is increased to increase the signal transmission speed, overlapping of the on-times of the pulse signals I11(1) and I11(2) may occur even if the drive timing between multiple channels is shifted. Therefore, when multiple channels are driven simultaneously, the peak value of the sum pulse signal I11(1)+I11(2), i.e., the combined current flowing to the terminal to which the power supply voltage VCC1 is applied, may increase compared to when a single channel is driven.

[0243] Generally, the higher the temperature (junction temperature Tj or ambient temperature Ta) of the signal transmission device 400, the lower the current capacity of the transistor 411a included in the transmission circuit 411. The lower the current capacity of the transistor 411a, the duller the waveforms of the pulse signals I11(1) and I11(2). Therefore, at high temperatures, the overlap of the on-times described above tends to become larger.

[0244] In view of the above considerations, the oscillation circuit 510 may be configured such that the reference clock signal CK or the oscillation frequency f of each of the clock signals CK(1) to (n) has a negative temperature characteristic.

[0245] FIG. 25 is a diagram showing the temperature dependence of the oscillation frequency f. As shown in this figure, the oscillation frequency f may be linearly changed according to the temperature TEMP such that the oscillation frequency becomes f1 at temperature T1 and the oscillation frequency becomes f2 (<f1) at temperature T2 (>T1). That is, the oscillation frequency f may be decreased as the temperature TEMP is higher. For example, the temperature coefficient of the oscillation frequency f may be -100 ppm / °C or less.

[0246] In the case of the above-described second embodiment (FIG. 19), third embodiment (FIG. 21), or fourth embodiment (FIG. 23), the drive current of each of the inverters 503(1) to (5) may be decreased as the temperature TEMP is higher.

[0247] With such a configuration, even at high temperatures, it becomes difficult for the on-times of the pulse signals I11(1) and I11(2) to overlap.

[0248] Note that at high temperatures, generally the on-threshold voltage of a transistor decreases. Therefore, compared with low temperatures, a smaller pulse current is required to drive the reception circuit 421. Therefore, even if the oscillation frequency f is decreased at high temperatures, the application can be established without problems.

[0249] <Combination of Embodiments> The embodiments proposed above may be arbitrarily combined within a non-contradictory range. For example, in the above-described third embodiment (FIG. 21), although the second embodiment (FIG. 19) is the basis, the configuration in which the power supply lines are separated between a plurality of channels may be applied based on the comparative example (FIG. 15), the first embodiment (FIG. 17), and the fourth embodiment (FIG. 23).

[0250] Also, for example, the aforementioned fourth embodiment (FIG. 23) is based on the second embodiment (FIG. 19), but a frequency divider circuit 504 and a multiplexer 505 may be introduced based on the first embodiment (FIG. 17) or the third embodiment (FIG. 21).

[0251] <Application to vehicles> 26 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate on power supplied from a battery.

[0252] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0253] The signal transmission devices 200 and 400 described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0254] <Additional Notes> The signal transmission device according to the present disclosure is capable of stably transmitting a plurality of signals.

[0255] [Appendix 1] A transmitting circuit (411); A receiving circuit (421); a plurality of isolation elements (431(1) to (n)) configured to transmit a plurality of signals (I11(1) to (n), where n is an integer of 2 or more) from the transmission circuit (411) to the reception circuit (421) while insulating the transmission circuit (411) from the reception circuit (421); Equipped with The transmission circuit (411) an oscillator circuit (510) configured to generate a plurality of clock signals (CK(1) to (n)) having different phases; a plurality of drive circuits (520(1) to (n)) configured to drive the plurality of isolation elements (431(1) to (n)) in synchronization with the plurality of clock signals (CK(1) to (n)), respectively; A signal transmission device (400).

[0256] [Appendix 2] The oscillator circuit (510) an oscillator (501) configured to generate a reference clock signal (CK); A plurality of delay circuits (502(1) to (n)) connected in series; Including, The signal transmission device (400) according to appendix 1, wherein the reference clock signal (CK) is input to a delay circuit (502(1)) that is located most upstream among the plurality of delay circuits (502(1) to (n)), and the plurality of clock signals (CK(1) to CK(n)) are output from each of the plurality of delay circuits (502(1) to (n)).

[0257] [Appendix 3] The oscillation circuit (510) is a ring oscillator including a plurality of inverters (503(1) to 503(n+1)) connected in a ring, The signal transmission device (400) according to Supplementary Note 1, wherein the plurality of clock signals (CK(1) to (n)) are output from the plurality of inverters (503(1) to (n)), respectively.

[0258] [Appendix 4] The signal transmission device (400) according to any one of appendices 1 to 3, wherein the plurality of drive circuits (520(1) to (n)) respectively drive the plurality of isolation elements (431(1) to (n)) in synchronization with both a rising edge and a falling edge of each of the plurality of clock signals (CK(1) to (n)).

[0259] [Appendix 5] The signal transmission device (400) described in any one of Appendices 1 to 4, wherein the plurality of drive circuits (520(1) to (n)) receive power supply from different power supply lines (PL1, PL2) for each of the plurality of groups (GRP1, GRP2) to which they belong.

[0260] [Appendix 6] The plurality of drive circuits (520(1) to (n)) are supplied with power from different power supply lines (PL1, PL2) for the plurality of groups (GRP1, GRP2) to which they belong, A signal transmission device (400) according to appendix 3, wherein clock signals (CK(i), CK(i+1)) output from adjacent inverters (503(i), 503(i+1), where i=1, 2, ..., n-1)) among the plurality of inverters (503(1) to (n)) are output to drive circuits belonging to different groups (GRP1, GRP2) among the plurality of drive circuits (520(1) to (n)).

[0261] [Appendix 7] a frequency divider circuit (504(1) to (n)) configured to divide the frequency of each of the plurality of clock signals (CK(1) to (n)) to generate a plurality of frequency-divided clock signals (CK(1)' to (n)'); a multiplexer (505(1) to (n)) configured to output one of the plurality of clock signals (CK(1) to (n)) and the plurality of frequency-divided clock signals (CK(1)' to (n)') to the plurality of drive circuits (520(1) to (n)) as a plurality of selected clock signals (CK(1)" to (n)"); Furthermore, The signal transmission device (400) according to any one of appendices 1 to 6, wherein the plurality of drive circuits (520(1) to (n)) drive the plurality of isolation elements (431(1) to (n)) in synchronization with the plurality of selection clock signals (CK(1)″ to (n)″).

[0262] [Appendix 8] The signal transmission device (400) according to any one of appendices 1 to 7, wherein the oscillation circuit (510) includes a trimming circuit (506) configured to adjust the oscillation frequency of each of the plurality of clock signals (CK(1) to (n)).

[0263] [Appendix 9] The signal transmission device (400) according to any one of appendices 1 to 8, wherein the oscillation circuit (510) is configured so that the oscillation frequencies of the plurality of clock signals (CK(1) to (n)) each have a negative temperature characteristic.

[0264] [Appendix 10] 10. The signal transmission device (400) according to any one of appendices 1 to 9, wherein each of the insulating elements (431(1) to (n)) is a transformer or a capacitor.

[0265] [Appendix 11] A transmitting circuit (411); A receiving circuit (421); a plurality of isolation elements (431(1) to (n)) configured to transmit a plurality of signals (I11(1) to (n)) from the transmission circuit (411) to the reception circuit (421) while insulating the transmission circuit (411) from the reception circuit (421); Equipped with The transmission circuit (411) an oscillator circuit (510) configured to generate a clock signal (CK); a plurality of drive circuits (520(1) to (n)) configured to receive power supply from different power supply lines (PL1, PL2) for each of a plurality of groups (GRP1, GRP2) to which they belong, and to drive the plurality of isolation elements (431(1) to (n)) in synchronization with the clock signal (CK); A signal transmission device (400).

[0266] [Appendix 12] An electronic device (A) comprising a signal transmission device (400) according to any one of appendices 1 to 11.

[0267] [Appendix 13] A vehicle (B) equipped with an electronic device (A) according to Appendix 12.

[0268] [Appendix 14] An insulated gate driver IC, which is configured by integrating a signal transmission device (400) according to any one of appendices 1 to 11.

[0269] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0270] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 400 Signal Transmission Device 410 First Chip 411, 411(1), 411(2) Transmitting circuit 411a, 411c Transistor (P-channel type) 411b, 411d Transistor (N-channel type) 411e Edge detection circuit 411f AND Gate 411g, 411i buffer 411h inverter 420 Second Chip 421, 421(1), 421(2) receiving circuit 430 3rd Chip 431, 431(1), 431(2) Transformer (Isolation element) 432, 432(1), 432(2) Transformer (Isolation element) 431p, 432p Primary coil 431s, 432s Secondary coil 440 Switch Circuit 441, 442 Transistor (N-channel type) 501 Oscillator 502(1)~502(3) Delay circuit 503(1)~503(5) Inverter 504(1)~504(4) Frequency divider circuit 505(1)~505(4) Multiplexer 506 Trimming Circuit 510 Oscillator Circuit 520(1)~520(4) Drive circuit a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads n1~n5 transistors (npn type) A Electronic equipment B vehicle C1~C5 capacitors D1~D5 diodes GRP1 and GRP2 groups L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil N1~N6 transistors (N-channel type) P1 Transistor (P-channel type) PL1, PL2 power lines R1~R7 resistance T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias ZL1, ZL2 load

Claims

1. A transmitting circuit; A receiving circuit; a plurality of isolation elements configured to transmit a plurality of signals from the transmitter circuit to the receiver circuit while providing isolation between the transmitter circuit and the receiver circuit; Equipped with The transmission circuit an oscillator circuit configured to generate a plurality of clock signals having different phases; a plurality of drive circuits configured to drive the plurality of isolation elements in synchronization with the plurality of clock signals, respectively; A signal transmission device comprising:

2. The oscillator circuit comprises: an oscillator configured to generate a reference clock signal; a plurality of delay circuits connected in series; Including, 2. The signal transmission device according to claim 1, wherein the reference clock signal is input to a delay circuit provided most upstream among the plurality of delay circuits, and the plurality of clock signals are output from the plurality of delay circuits, respectively.

3. the oscillation circuit is a ring oscillator including a plurality of inverters connected in a ring, 2. The signal transmission device according to claim 1, wherein the plurality of clock signals are output from the plurality of inverters, respectively.

4. 2. The signal transmission device according to claim 1, wherein the plurality of drive circuits respectively drive the plurality of isolation elements in synchronization with both rising edges and falling edges of the plurality of clock signals.

5. 2. The signal transmission device according to claim 1, wherein the plurality of drive circuits are supplied with power from different power supply lines for each of the plurality of groups to which they belong.

6. the plurality of drive circuits are supplied with power from different power supply lines for each of the plurality of groups to which they belong; 4. The signal transmission device according to claim 3, wherein clock signals output from adjacent inverters among the plurality of inverters are output to drive circuits among the plurality of drive circuits which belong to different groups.

7. a frequency divider circuit configured to divide the frequency of each of the plurality of clock signals to generate a plurality of frequency-divided clock signals; a multiplexer configured to output one of the plurality of clock signals and the plurality of frequency-divided clock signals as a plurality of selected clock signals to the plurality of drive circuits, respectively; Furthermore, 2. The signal transmission device according to claim 1, wherein the plurality of drive circuits drive the plurality of isolation elements in synchronization with the plurality of selected clock signals.

8. 2. The signal transmission device according to claim 1, wherein the oscillator circuit includes a trimming circuit configured to adjust the oscillation frequency of each of the plurality of clock signals.

9. 2. The signal transmission device according to claim 1, wherein the oscillation circuit is configured so that the oscillation frequency of each of the plurality of clock signals has a negative temperature characteristic.

10. The signal transmission device according to claim 1 , wherein each of the plurality of isolation elements is a transformer or a capacitor.

11. A transmitting circuit; A receiving circuit; a plurality of isolation elements configured to transmit a plurality of signals from the transmitter circuit to the receiver circuit while providing isolation between the transmitter circuit and the receiver circuit; Equipped with The transmission circuit an oscillator circuit configured to generate a clock signal; a plurality of drive circuits configured to receive power supply from different power supply lines for each of a plurality of groups to which the drive circuits belong, and to drive the plurality of isolation elements in synchronization with the clock signal; A signal transmission device comprising:

12. An electronic device comprising the signal transmission device according to any one of claims 1 to 11.

13. A vehicle comprising the electronic device according to claim 12.

14. An insulated gate driver IC, which is formed by integrating the signal transmission device according to any one of claims 1 to 11.

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