Pulse power supply device and bias control method for plasma etching apparatus

Abstract

To realize good commutation while simplifying the circuitry and control.SOLUTION: This circuit is provided with switches V1, V3 and V4 for respectively selecting a voltage source 11 for outputting a voltage S1, a voltage source 13 for outputting a voltage S3 and a voltage source 14 for outputting a voltage S4 to an outputting terminal 10, and a current source 12 connected between the outputting terminal 10 and a ground terminal 9 through the switches S3. A control part 20 turns on the switch V1 after the voltage is lowered to the vicinity of the voltage S1 by the second half-wave resonance to maintain the voltage Vop1 at a low level, and turns on the switch S3 to make the current of the first half-wave resonance flow in a resonance loop including a capacitor load, an inductor Ln, etc., to raise the voltage Vop1. When the voltage Vop1 becomes the voltage V5 and rises to the voltage V6 by making the DC current of the current source 12 flow, the switch S4 is turned on, and the current of second half-wave resonance is made to flow by a resonance loop including a capacitor load, an inductor Ln, etc., to lower the voltage Vop1 to the voltage V1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a pulse power supply device used in a plasma etching device for semiconductor manufacturing and the like, and a method for controlling the bias of the pulse power supply device. [Background technology]

[0002] In semiconductor manufacturing processes, plasma etching systems are widely used to etch semiconductor substrates using plasma. Reactive ion etching systems typically generate plasma from an etching gas in a chamber using high-frequency inductive coupling or electron cyclotron resonance, and apply a bias voltage, such as a high-frequency voltage, to a substrate placed in the chamber. This generates a self-bias potential between the substrate and the plasma, causing ion and radical species in the plasma to accelerate toward the substrate and collide with its surface, resulting in etching.

[0003] To perform precise etching in a plasma etching apparatus, it is important to properly control the ion energy distribution (IED) on the substrate surface. Generally, it is desirable for the IED on the substrate surface to be a single IED with as narrow a peak width as possible. To achieve such an IED, the substrate surface voltage must be kept nearly constant. However, because the ion current derived from the plasma constantly charges the dielectric substrate surface, the substrate surface voltage does not remain constant even when a constant voltage is applied to the substrate. In contrast, the conventional pulse power supply described in Patent Document 1 compensates for the ion current by supplying a direct current during the processing period, thereby maintaining a nearly constant substrate surface voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2022-530078 Summary of the Invention [Problem to be solved by the invention]

[0005] The conventional pulse power supply described in Patent Document 1 includes a current source for supplying a constant DC current, as well as a voltage source for charging auxiliary voltage during commutation operation to promote charging and discharging of substrate capacitors and floating capacitors. This pulse power supply also includes resonant commutation means for applying in advance a voltage that is approximately half the charging auxiliary voltage to an LC series circuit of a capacitor, including a substrate capacitor, etc., and a floating inductor, such as a wiring, thereby reducing losses during commutation operation and improving the bias waveform.

[0006] However, the conventional pulse power supply described above has, in addition to a voltage source for forming a current source and a voltage source for auxiliary charging, additional voltage sources for pulse-on commutation and pulse-off commutation, and also requires switches to connect these voltage sources to the output. This results in a large circuit size and correspondingly higher costs. Furthermore, the on / off operation of multiple switches must be controlled individually, and the control is complicated because accurate management of the half-wave resonance period is required.

[0007] Generally, the waveform of a pulse bias voltage in a plasma etching apparatus is a negative pulse waveform in which the voltage changes in the negative direction (downward in a typical waveform diagram), and the actual etching process occurs at the peak of this negative pulse waveform. Therefore, in this specification, a voltage change (negative change) toward the peak of the pulse waveform where the etching process occurs is referred to as a voltage rise (or increase), and conversely, a voltage change from the peak of the pulse waveform where the etching process occurs toward the positive direction is referred to as a voltage drop (or drop, decrease). Furthermore, the relationship between high and low voltages is defined according to this voltage rise or drop. In other words, when a voltage rises from a certain voltage A to another voltage B, it is expressed as voltage A being lower than voltage B (and conversely, voltage B being higher than voltage A).

[0008] The present invention has been made to solve the above-mentioned problems, and its main object is to provide a pulse power supply device for a plasma etching apparatus, which can apply a pulse bias with a good waveform to a substrate or the like while simplifying the circuit configuration and control, and a bias control method therefor. [Means for solving the problem]

[0009] One aspect of a bias control method according to the present invention is a bias control method for forming a pulsed voltage waveform at an output terminal of a pulse power supply device in order to supply a bias to a plasma reactor (Pr) including a processing object in a plasma etching apparatus, the method comprising: selectively supplying to the output terminal a DC current having a predetermined current value, a third DC voltage having a third voltage value (V3) referenced to a ground potential, a fourth DC voltage having a fourth voltage value (V4), and a first voltage value (V1) lower than the third voltage value (V3) and the fourth voltage value (V4), a) a first step of coupling the first DC voltage to the output terminal to reduce the output voltage at the output terminal to a first voltage value (V1) when the voltage drops due to half-wave resonance in a fourth step described below and becomes lower than the third voltage value (V3) and the fourth voltage value (V4), and maintaining the first voltage value in a capacitor load of a plasma reactor to maintain the output voltage at a low level; b) a second step of coupling the third DC voltage to the output terminal in place of the first DC voltage, and causing a current to flow by half-wave resonance in a resonant loop including at least the capacitor load and an inductor including a wiring between the pulse power supply device and the plasma reactor, thereby increasing the output voltage; c) a third step of coupling the DC current to the output terminal when the output voltage reaches a potential of a predetermined fifth voltage value (V5) higher than the third voltage value (V3) due to the voltage increase in the second step, and further linearly increasing the output voltage over time using the DC current; d) a fourth step of coupling the fourth DC voltage to the output terminal instead of the DC current after the output voltage has risen to a potential that is a predetermined sixth voltage value (V6) in the third step, and lowering the output voltage by flowing a current due to half-wave resonance in a resonance loop that includes at least the capacitor load and the inductor; It has.

[0010] In the above-described aspect of the bias control method according to the present invention, as an example, when ΔV and Vc are respectively predetermined positive voltage values, the third voltage value (V3) can be 0, the fourth voltage value (V4) can be -Vc / 2, the first voltage value (V1) can be +ΔV / 2, the fifth voltage value (V5) can be -ΔV / 2, and the sixth voltage value (V6) can be -(ΔV / 2)-Vc.

[0011] Furthermore, in the above-described aspect of the bias control method according to the present invention, as another example, when ΔV and Vc are each a predetermined positive voltage value, the third voltage value (V3) can be +ΔV / 2, the fourth voltage value (V4) can be (ΔV-Vc) / 2, the first voltage value (V1) can be +ΔV, the fifth voltage value (V5) can be 0, and the sixth voltage value (V6) can be -Vc.

[0012] In the above-described aspect of the bias control method according to the present invention, as another example, when ΔV and Vc are respectively predetermined positive voltage values, the third voltage value (V3) can be −ΔV / 2, the fourth voltage value (V4) can be −(ΔV+Vc) / 2, the first voltage value (V1) can be 0, the fifth voltage value (V5) can be −ΔV, and the sixth voltage value (V6) can be −ΔV-Vc.

[0013] Furthermore, one aspect of the pulse power supply device for a plasma processing apparatus according to the present invention is a device for realizing the bias control method of the above aspect, and is a pulse power supply device that generates a pulsed voltage waveform between an output terminal (10) connected to a plasma reactor (Pr) including a processing object via wiring and a ground terminal (9) in order to supply a bias to the plasma reactor (Pr) in a plasma etching apparatus, a) a first voltage source (11) that generates a first DC voltage having a first voltage value (V1) referenced to a ground potential; b) a third voltage source (13) that generates a third DC voltage having a third voltage value (V3) referenced to ground potential; c) a fourth voltage source (14) that generates a fourth DC voltage having a fourth voltage value (V4) referenced to ground potential; d) a first switch (S1) coupling the first voltage source to the output; e) a third switch (S3) coupling the third voltage source to the output; f) a fourth switch (S4) that couples the fourth voltage source to the output; g) a current source (12) having a current inflow end and a current outflow end, the inflow end being coupled to the output end via the third switch, and the outflow end being coupled to the ground end, and supplying a DC current of a predetermined current value; h) a third diode (Da) for reverse blocking, which is arranged between the third switch and the third voltage source or between the third voltage source and the ground terminal, and which blocks current flow from the ground terminal side to the third switch side; i) a fourth diode (Db) for reverse blocking, connected in series with the fourth switch and the fourth voltage source, for blocking current flow from the output terminal to the ground terminal; j) turning on the first switch to couple the first voltage source to the output terminal, and holding a voltage of a first voltage value from the first voltage source in a capacitor load of the plasma reactor, thereby maintaining the output voltage at the output terminal at a low level; turning on the third switch to couple the third voltage source to the output terminal; causing a current to flow by first half-wave resonance in a resonance loop including at least the capacitor load and an inductor including the wiring, thereby increasing the output voltage; and the voltage increase causes the output voltage to reach a potential of a predetermined fifth voltage value higher than the third voltage value; and further changing the third diode from a conductive state to a reverse blocking state, thereby increasing the current. a control unit (20) that controls on / off operations of the first switch, the third switch, and the fourth switch so that, when the output voltage rises to a potential of a predetermined sixth voltage value as a result of a DC current from a current source flowing through a load, the control unit turns on the fourth switch to couple the fourth voltage source to the output terminal, the control unit includes at least the capacitor load and the inductor, and controls a current due to second half-wave resonance in a resonant loop including the fourth diode to decrease the output voltage, and when the output voltage becomes lower than the third voltage value and the fourth voltage value, the control unit turns on the first switch to couple the first voltage source to the output terminal, and controls the output voltage to decrease to a first voltage value; Equipped with.

[0014] In the pulse power supply device for a plasma processing apparatus according to the above aspect, either the first voltage value or the third voltage value can be set to 0, and the other voltage values ​​can be set to predetermined voltages accordingly.

[0015] The pulse power supply device for a plasma processing apparatus according to the above aspect may be configured to include a high-speed constant current power supply connected in parallel with the current source.

[0016] It should be clear to those skilled in the art that the "ground potential" in the phrase "based on the ground potential" does not necessarily mean strictly 0 V. For example, in this type of device, a current-limiting resistor (limiting resistor) is often inserted in series on the line connected to the ground terminal or output terminal (the ground terminal, which is usually the low-voltage side). In this case, since there is a voltage drop across the current-limiting resistor, even if the potential at the ground terminal is 0 V, the potential at the end of the current-limiting resistor opposite the ground terminal will naturally not be 0 V. However, in the present invention, this potential can be used as the reference within the device.

[0017] The conventional pulse power supply described in Patent Document 1 includes a dedicated switch for connecting the current source to the output terminal, and in the step corresponding to the third step in the bias control method according to the present invention, the switch is turned on to connect the current source to the output terminal. In contrast, the present inventors have devised a configuration that utilizes the fact that the third diode (Da) for reverse blocking, which passes the first half-wave resonant current, can be switched between a conducting state and a blocking state. The current path of the current source connected in parallel to the third diode or the series circuit of the third diode and the third voltage source is switched between two paths: a short circuit caused by the reverse current of the third diode and the load (output terminal) without using a selection switch. This allows the conventional pulse power supply to function as both a dedicated switch for connecting the current source to the output terminal and a switch for connecting the third voltage source to the output terminal. This configuration reduces the number of switches and achieves good commutation with reduced voltage and current oscillations when transitioning from the second step to the third step. [Effects of the Invention]

[0018] In this way, according to the present invention, compared to conventional pulsed power supply devices, it is possible to simplify the circuit configuration by reducing devices such as switches, and furthermore, it is possible to apply a pulsed bias with a good waveform to a processing object while omitting the complicated control of matching the half-wave resonance period with the switching timing of the switches, thereby achieving good etching processing of processing objects such as substrates. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a conceptual diagram showing an example of the overall configuration of a plasma etching apparatus including a pulse power supply device according to the present invention; [Figure 2] FIG. 2 is a schematic circuit diagram of a pulse power supply unit according to the first embodiment. [Figure 3] 3A and 3B are diagrams showing examples of voltage waveforms of a substrate surface voltage Vsub, an output voltage Vop1, and a stage voltage Vop2. [Figure 4] 4 is a time chart showing an example of waveforms at various points during a commutation period Ta in the pulse power supply unit of the first embodiment. [Figure 5] 4 is a time chart showing an example of waveforms at various points during a commutation period Tb in the pulse power supply unit of the first embodiment. [Figure 6] 3 is a schematic diagram showing a current path during a commutation period Ta (times t0 to t1) in the pulse power supply unit of the first embodiment. FIG. [Figure 7] FIG. 4 is a schematic diagram showing a current path during a commutation period Tb (times t2 to t3) in the pulse power supply unit of the first embodiment. [Figure 8] FIG. 4 is a schematic diagram showing a current path during a commutation period Tb (times t3 to t4) in the pulse power supply unit of the first embodiment. [Figure 9] FIG. 4 is a schematic diagram showing a current path during a commutation period Tb (times t4 to t5) in the pulse power supply unit of the first embodiment. [Figure 10] 6 is a time chart showing another example of waveforms at each part of the commutation period Tb in the pulse power supply unit of the first embodiment. [Figure 11] FIG. 10 is a schematic circuit diagram of a pulse power supply unit according to a modified example. [Figure 12] FIG. 10 is a schematic circuit diagram of a pulse power supply unit according to another modified example. [Figure 13] FIG. 10 is a schematic circuit diagram of a pulse power supply unit according to another modified example. [Figure 14] FIG. 10 is a schematic circuit diagram of a pulse power supply unit according to another modified example. [Figure 15] FIG. 10 is a schematic circuit diagram of a pulse power supply unit according to another modified example. DETAILED DESCRIPTION OF THE INVENTION

[0020] [Plasma etching equipment configuration] FIG. 1 is a conceptual diagram showing a typical example of the overall configuration of a plasma etching apparatus using a pulse power supply device according to the present invention. As shown in FIG. 1, the plasma etching apparatus includes a process control unit 1, an ion source plasma power supply unit 2, a bias pulse power supply unit 3, and a processing chamber 4.

[0021] Although not shown, the processing chamber 4 is equipped with an ion source that receives power supplied from the ion source plasma power supply unit 2 and generates plasma 5 from the introduced etching gas by various methods, such as inductively coupled plasma (ICP), electron cyclone resonance (ECR) plasma, or helicon wave plasma (HWP).

[0022] On the other hand, the bias pulse power supply unit (hereinafter simply referred to as the "pulse power supply unit") 3 applies a pulsed bias to the substrate 6 to be processed in order to attract ions in the plasma 5 by imparting kinetic energy to them. To obtain a desired (usually narrow, single) IED on the surface 6a of the dielectric substrate 6, the pulse power supply unit 3 supplies current to the substrate 6 via the stage 7 so that the voltage value on the surface 6a of the substrate 6 remains substantially constant during a predetermined processing period. In this plasma etching apparatus, the ion source plasma power supply unit 2 and the pulse power supply unit 3 are provided separately, and the process control unit 1 independently controls the power supplies 2 and 3, thereby increasing the flexibility of the etching process. In the following description, the entire processing chamber 4 containing the plasma 5 will be referred to as the plasma reactor Pr, as is customary.

[0023] [Equivalent circuit of plasma reactor Pr] The area enclosed by the dashed line on the right side of Fig. 2 is a diagram showing a circuit centered on a simplified electrical equivalent circuit of the plasma reactor Pr, which is the load of the pulsed power supply unit 3. In this diagram, the equivalent circuit of the substrate-side ion sheath and the equivalent circuit of the wall-side ion sheath in the plasma reactor Pr are combined, and some of them are omitted.

[0024] 2, Rp is the DC resistance of the ion sheath (hereinafter referred to as "sheath resistance"), Cp is the inductive capacitor of the substrate 6 (hereinafter referred to as "substrate capacitor"), Dp is an equivalent diode due to the rectifying action of the ion sheath (hereinafter referred to as "sheath diode"), Cs is the capacitor of the ion sheath (hereinafter referred to as "sheath capacitor"), Zp is the plasma bulk resistance (hereinafter referred to as "plasma resistance"), and Cn is the total floating-to-ground capacitor (hereinafter referred to as "floating capacitor"). Furthermore, Ln is an inductor (hereinafter referred to as "wiring inductor") mainly resulting from the wiring connecting the pulse power supply unit 3 and the plasma reactor Pr, and Cb is a blocking capacitor provided on the wiring.

[0025] In Figure 2, the ion sheath rectification, which is caused by the difference in mobility between ions and electrons in the plasma, is represented by a parallel circuit consisting of a sheath diode Dp and a sheath resistance Rp. The sheath resistance Rp corresponds to the ion current, and the forward resistance of the sheath diode Dp corresponds to the electron current, each as a DC resistance. These elements, plus a sheath capacitor Cs, are connected in parallel. A plasma resistance Zp is connected to one end of this parallel circuit, and a substrate capacitor Cp is connected to the other end. A floating capacitor Cn is also connected to both ends of this series circuit. The junction between the plasma resistance Zp and the floating capacitor Cn is connected to the ground terminal 9 of the pulse power supply unit 3 and is also grounded. The junction between the substrate capacitor Cp and the floating capacitor Cn is connected to the output terminal 10 of the pulse power supply unit 3 via a series circuit consisting of a blocking capacitor Cb and a wiring inductor Ln.

[0026] The surface 6a of the substrate 6 is the connection point between the other end of the parallel circuit of the sheath diode Dp, sheath resistor Rp, and sheath capacitor Cs and the substrate capacitor Cp, and the voltage generated between this connection point and ground is the substrate surface voltage Vsub. The floating capacitor Cn, substrate capacitor Cp, and sheath capacitor Cs form a capacitor load, and in a typical example, their capacitance ratio is Cn ≒ 5 Cp, Cp ≒ 20 Cs. Typically, the capacitance of the sheath capacitor Cs is significantly smaller than the capacitance of the other components, so it can be effectively ignored in circuit operation. Therefore, in Figure 2, the connection line for the sheath capacitor Cs is shown with a dashed line.

[0027] In FIG. 2, the pulse power supply unit 3 does not include a blocking capacitor Cb, but the pulse power supply unit 3 may be considered to include the blocking capacitor Cb.

[0028] In the following description, the symbols indicating each component and the symbols specifying the voltage or current at a specific location are also used to represent the numerical values ​​of the parameters of the component itself. For example, a symbol indicating a specific capacitor, such as Cp described below, is also used to represent the capacitance value of the capacitor, and a symbol indicating a voltage at a specific location, such as Vop1, is also used to represent the voltage value of that voltage.

[0029] [Waveforms of substrate surface voltage Vsub and output voltage Vop1] Figures 3(a) to 3(c) are diagrams showing examples of the waveforms of the substrate surface voltage Vsub, the output voltage Vop1, and the stage voltage Vop2 shown in Figure 2. The numbers in brackets [ ] shown on the right side of Figure 3(b) correspond to the symbols indicating the voltage sources that generate the voltages shown in the waveform diagram (Figure 3) in the schematic circuit diagram of the pulse power supply unit 3 shown in Figure 2.

[0030] As described above, the substrate surface voltage Vsub is the voltage generated between the surface 6a of the substrate 6 and ground. The output voltage Vop1 is the voltage generated by the output from the pulse power supply unit 3 between the connection point between the wiring inductor Ln and the blocking capacitor Cb connected to the output terminal 10 and ground. The stage voltage Vop2 is the voltage generated between the stage 7 and ground.

[0031] The period T is one cycle of the pulse waveform, and during the etching process, this pulsed bias is repeatedly applied to the substrate 6. The repetition frequency of the pulse waveform is determined appropriately, but as an example, the repetition frequency is several hundred kHz. For example, when the frequency is 400 kHz, the period T is 2.5 μs. Within this period T, Tp excluding the commutation period Ta described below is the etching process period during which the actual etching process is performed on the substrate 6. Generally, when a narrow single IED is required on the substrate 6 as described above, the substrate surface voltage Vsub needs to be maintained at a certain voltage value during the etching process, as shown in FIG. 3(a).

[0032] Between two adjacent etching processing periods Tp, a discharge period Td is provided to discharge the charge accumulated in the substrate capacitor Cp and the floating capacitor Cn during the etching process. Ta is the commutation period from the end of the discharge period Td to the transition to the etching processing period Tp, while Tb is the commutation period from the end of the etching processing period Tp to the transition to the discharge period Td. For example, when T = 2.5 μs and the maximum duty ratio of the etching processing period Tp is 80%, Tp = 2 μs and Td = 0.5 μs. To increase the etching efficiency by widening the effective etching processing period Tp for a narrow single IED while keeping the length of the period T constant (i.e., with a constant repetition frequency), it is desirable to shorten the commutation periods Ta and Tb as much as possible.

[0033] As described above, in order to maintain the substrate surface voltage Vsub at a constant voltage during the etching processing period Tp excluding the commutation period Ta, the pulse power supply unit 3 of this embodiment sets the current Icp flowing through the substrate capacitor Cp to a constant negative pulse current during that period Tp. The waveform of the output voltage Vop1 during this period Tp is a combination of the incremental change in the capacitor load voltage due to the output current Io (=Ic), Vc≈Ic·t / (Cp+Cn), and the auxiliary charging voltage change ΔV≈Vsub (both potential differences) for rapidly increasing the substrate surface voltage Vsub during the commutation period Ta when the pulse is on. The former forms a ramp-like waveform with a substantially constant slope during the period Tp.

[0034] The substrate surface voltage Vsub is expressed as the voltage drop across the sheath resistance Rp and plasma resistance Zp due to the current Icp flowing through the substrate capacitor Cp (assuming the forward resistance of the sheath diode Dp is zero and the reverse resistance is infinite). During the etching process period Tp, excluding the commutation period Ta, Vsub = -Icp · (Rp + Zp) when the current Icp is constant. Also, after the sheath diode Dp becomes conductive during the discharge period Td, Vsub = Icp · Zp. The resistance of the plasma resistance Zp is small, at most a few ohms, and the current Icp can rapidly discharge the accumulated charge in the substrate capacitor Cp. The current Io output from the pulse power supply 3 during the etching process period Tp is divided into Icn and Icp as shown in Figure 2, so Icp ≈ -Io · Cp / (Cp + Cn).

[0035] In the pulse power supply unit of the first embodiment and other embodiments described below, the voltage value of the output voltage Vop1 at time t5 is the voltage V1 due to the charge accumulated in the capacitor load Cre, which is a combination of the substrate capacitor Cp and the floating capacitor Cn. In the pulse power supply unit of the first embodiment, the voltage value of the voltage V1 is +ΔV / 2, which is equal to the output voltage of the first voltage source 11. While specific operation will be described later, during the commutation period Ta, a half-wave resonant current is passed through the capacitor load Cre to rapidly charge the capacitor load. This causes the output voltage Vop1 to rapidly rise from +ΔV / 2 to −ΔV / 2. On the other hand, during the commutation period Tb, a half-wave resonant current is passed out of the capacitor load Cre to rapidly discharge the capacitor load. This causes the output voltage Vop1 to rapidly drop from −ΔV / 2-Vc to near +ΔV / 2 and then to be fixed at +ΔV / 2. As a result, the output voltage Vop1 has a waveform as shown in FIG. 3(b).

[0036] The stage voltage Vop2 is the waveform of the output voltage Vop1, which is given a DC floating zero potential by the blocking capacitor Cb, shifted negatively (or positively) by the DC voltage, which is the average voltage of the substrate surface voltage Vsub. Therefore, even if the output voltage Vop1 as a whole is shifted vertically while the potential difference (absolute value) between ΔV and Vc shown in FIG. 3(b) remains the same, the stage voltage Vop2 will have the same waveform as shown in FIG. 3(c). The blocking capacitor Cb is provided to prevent DC current generated by an external voltage from flowing into the pulsed power supply unit 3. Its capacitance is set, for example, to Cb ≈ 50·Cn. However, it will be clear to those skilled in the art that the blocking capacitor Cb is not an essential component of the present invention and can be omitted as appropriate.

[0037] [Details of the configuration and operation of the pulse power supply] Next, the configuration and operation of the pulse power supply unit 3 of the first embodiment shown in FIG. 2 will be described in detail. In the pulse power supply unit 3 of the first embodiment, a series circuit of a third voltage source 13 outputting a voltage value V3, a third reverse-blocking diode Da, and a third switching unit S3, and a series circuit of a first voltage source 11 outputting a voltage value V1, a damping resistor Rd, and a first switching unit S1 are connected between a first node N1 connected to a ground terminal 9 and a second node N2 connected to an output terminal 10. However, as will be described later, in this first embodiment, since the voltage value V3=0 V, the third voltage source 13 does not actually exist and can be considered to be short-circuited. For this reason, the third voltage source 13 is shown by a dashed line in FIG. 2. The damping resistor Rd is not essential.

[0038] A series circuit of a fourth voltage source 14 outputting a voltage value V4, a fourth diode Db, and a fourth switching unit S4 is connected between the output terminal 10 and a third node N3 connected via the second node N2, the inductor Li, and the second current sensor Ct2. If the inductor Li is not required, the third node N3 and the second node N2 can be considered to coincide with each other. In this case, the series circuit of the fourth voltage source 14, the fourth diode Db, and the fourth switching unit S4 can be considered to be connected between the output terminal 10 and the ground terminal 9. A current source 12 capable of supplying a constant current Ic is connected between the first node N1 and the fourth node N4, which is the connection point between the third diode Da and the third switching unit S3. That is, the current source 12 and the series circuit of the third diode Da and the third voltage source 13 are connected in parallel.

[0039] Current source 12, which outputs a constant current Ic, is composed of a series circuit consisting of inductor Lo (with an inductance of approximately 2 mH) and voltage source 15. This series circuit also includes current sensor Ct1, but it is clear that current sensor Ct1 is not directly related to the current supply itself. Current source 12 also includes a series circuit consisting of fifth switching unit S5 and diode Dc, connected in parallel to the series circuit of inductor Lo and first current sensor Ct1. Switching units S1, S3, S4, and S5 are all composed of semiconductor switching elements such as power MOSFETs, and anti-parallel diodes D1, D3, D4, and D5 are parasitic diodes of the semiconductor switching elements, respectively.

[0040] The control unit 20 receives command signals from the process control unit 1, including values ​​such as the voltage value of the substrate surface voltage Vsub, the processing cycle T (pulse frequency: PW-f), and the processing period Tp. The control unit 20 also monitors the output voltage Vop1 and sends control signals G1, G3, G4, and G5 to the switching units S1, S3, S4, and S5, controlling their on / off operations according to a predetermined algorithm. The control unit 20 also detects the current flowing through the inductor Lo using a current sensor Ct1 and variably controls the current Ic from the current source 12 by varying the voltage Vo from the voltage source 15. The control unit 20 also samples the values ​​of the substrate surface voltage Vsub, the output current Io, and the output voltage Vop1 over time during the period Tp, and variably controls the voltage V4 from the fourth voltage source 14 and, if necessary, the voltage V3 from the third voltage source 13 (note that in the example of FIG. 2, the third voltage source 13 is short-circuited) to optimal values.

[0041] The control unit 20 can be configured to include a high-speed logic circuit, such as an FPGA (Field Programmable Gate Array), a microcomputer including a CPU, ROM, a timer, etc., and an AD converter, and can generate control signals, etc. for performing the processing described below by executing processing according to a pre-set program.

[0042] Next, the operation of the pulse power supply unit 3 of this embodiment will be described in detail with reference to Fig. 4 to Fig. 9. Fig. 4 and Fig. 5 are time charts showing waveforms of the main parts of the commutation periods Ta and Tb in Fig. 3. Fig. 6 to Fig. 9 are schematic diagrams showing current paths.

[0043] 2, in the pulse power supply unit 3 of the first embodiment, the voltages V1, V3, and V4 of the voltage sources 11, 13, and 14 are V1=+ΔV / 2, V3=0, and V4=−Vc / 2. In this pulse power supply unit 3, the control unit 20 detects actual measured values ​​of the output current Io and output voltage Vop1 of the current source 12, which change over time, at predetermined time intervals, and variably controls the output current Io, the voltage V4 of the second voltage source 14, and the voltage value V1 of the first voltage source 11 to their optimum values ​​based on these values ​​and the set value (target value) of the substrate surface voltage Vsub. Note that it is also possible to use the second current sensor Ct2 to detect zero of the output current Io (more specifically, the current flowing through the path from the second node N2 to the third node N3) during the commutation period Tb in the discharge period Td, and adjust the control signals G1 and G4 based on this timing.

[0044] The main features of this pulse power supply unit 3 are that it employs a new resonant commutation method that does not require management of commutation time, it generates an auxiliary charging voltage ΔV that corresponds to zero point floating, it suppresses unnecessary damping of resonance by the current source 12, it regenerates energy to the voltage source, and it reduces the total number of voltage sources and switching units compared to conventional pulse power supply devices.

[0045] First, the operation during the commutation period Ta (t0 to t1) when the pulse is on will be described with reference to FIGS. 4 and 6. As shown in FIG. 4, just before time t0, the control signal G1, which was previously in a high (logic "1") state, changes to a low (logic "0") state. At time t0, a predetermined dead time Te has elapsed since that time, and the control signal G3 changes to a high state. The control signal G5, which is in a high state at that time, changes to a low state after a period of time Tf overlaps with the control signal G1. When the control signal G1 goes low, the first switching unit S1 turns off, but the output voltage Vop1, which is the stage voltage Vop2, which is the voltage across the floating capacitor Cn (in this case, equal to the voltage across the substrate capacitor Cp), shifted by the voltage of the blocking capacitor Cb, is maintained at a value (V1) that is higher by +ΔV / 2 than the voltage of the first voltage source 11, relative to the ground point.

[0046] Furthermore, since the fifth switching unit S5 is in the on state until the control signal G5 changes to the low state, in the current source 12, the current flowing through the inductor Lo (the constant current Ic supplied by the current source 12 during the discharge period Td) is returned to the inductor Lo through the fifth switching unit S5, and the current is maintained.

[0047] At time t0, when the control signal G3 changes to a high state and the third switching unit S3 turns on, the reverse diode Da is forward biased, and the voltage Vpn between the first node N1 and the fourth node N4 becomes approximately 0. As a result, a resonant current (=-[0.5ΔV / √(Ln / Cre)]·sinθ) consisting of the output voltage Vop1, which is the voltage value (V1=+ΔV / 2) maintained as described above, the combined value Cre≈Cn of the capacitances of the capacitors Cn, Cp, Cs, and Cb, and the wiring inductor Ln flows as the output current Io through the path shown by the solid arrow in Fig. 6.

[0048] At the same time, diode Dc is reverse-biased, releasing the short circuit across inductor Lo in current source 12. As described above, the resonant current flows, and constant current Ic supplied by current source 12 flows back through diode Da, which is conductive. When control signal G5 transitions to a low state, fifth switching unit S5 switches off by current switching while maintaining zero voltage. Because the voltage value of output voltage Vop1 is 0.5ΔV·cosθ, as shown in FIG. 4(a), output voltage Vop1 rises from +ΔV / 2 (V1) at time t0 to -ΔV / 2 (V5) at time t1. Therefore, the magnitude of the voltage change (increase) during commutation period Ta is ΔV, which corresponds to twice the difference (=ΔV / 2) between the voltage value +ΔV / 2 of first voltage source 11 and the voltage value 0 of third voltage source 13.

[0049] Because the stage voltage Vop2 is floating at zero point due to the blocking capacitor Cb, the waveform of the stage voltage Vop2 is determined only by the voltage difference between the two voltages, regardless of polarity, as shown in Figure 3(c). Therefore, there is no problem in obtaining the auxiliary charging voltage ΔV during commutation operation through resonance from a voltage of ΔV / 2. The commutation period Ta is calculated using the following half-wave resonance period formula, which is determined by the LC time constant. Ta=π√(Ln·Cre)

[0050] That is, the difference between the stage voltage Vop2, which is the voltage across floating capacitor Cn and changes rapidly due to resonance, and the voltage across substrate capacitor Cp, which changes slowly due to the action of sheath resistance Rp, is the substrate surface voltage Vsub. The current Icp flowing through the path indicated by the dashed arrow in Figure 6 is roughly the voltage value of the substrate surface voltage Vsub at this time divided by the resistance value of the series circuit consisting of sheath resistance Rp and plasma resistance Zp, and is diverted from the output current Io and flows back through floating capacitor Cn.

[0051] After time t1, the output current Io due to the resonant current attempts to reverse direction, but the resonant current stops because the diode Da is reverse-biased. Meanwhile, the constant current Ic supplied from the current source 12, which had been flowing backward through the diode Da, flows through the resonant path as Io = Ic. As a result, the current source 12, which has a very high output impedance, is connected in series with the resonant path. Immediately after this resonant commutation, no voltage or current oscillations occur due to the wiring inductor Ln and the combined capacitance Cre. However, when the output current Io switches from the resonant current to the constant current Ic, a momentary current interruption occurs due to the reverse recovery time of the diode Da, which may result in a surge voltage across the PN. To suppress this surge voltage, a surge protection element such as a voltage clamp circuit or a voltage clamp element, such as a TVS (Transient Voltage Suppressor), may be inserted between the first node N1 and the fourth node N4.

[0052] The circuit operation during the commutation period Ta when the pulse is on as described above can be realized without the need for a power supply and switching elements for generating the auxiliary charging voltage ΔV, which are provided in conventional pulse power supplies, or strict management of the commutation time to match the half-wave resonance period.

[0053] After the end of the commutation period Ta, the constant current Ic supplied from the current source 12 flows as the output current Io through the third switching unit S3 and is divided into the current Icp flowing through the substrate capacitor Cp and the current In flowing through the floating capacitor Cn. As a result, the output voltage Vop1 increases in the negative direction from V5 = -ΔV / 2 at a substantially constant rate, generating a ramp-shaped voltage waveform as shown in Figure 3(b).

[0054] Next, the operation during the commutation period Tb when the pulse is off will be described. As shown in FIG. 5, just before time t2, the control signal G3 is high and the other control signals G1, G4, and G5 are low. From this state, the control signal G5 changes to a high state, and after a period Tf during which the control signal G5 and the high state overlap, the control signal G3 changes to a low state. Then, at time t2 after a predetermined dead time Te has elapsed, the control signal G4 changes to a high state. Then, at time t4, the control signal G4 changes to a low state, and almost simultaneously, the control signal G1 changes to a high state. Thereafter, the state in which the control signals G3 and G4 are low and the control signals G1 and G5 are high is maintained until just before the aforementioned time t0.

[0055] Immediately before the end of the steady-state processing period Tp, the third switching unit S1 is in the ON state, and as described above, the constant current Ic supplied from the current source 12 flows as the output current Io to the capacitive load formed by the substrate capacitor Cp and the floating capacitor Cn. The output voltage Vop1 (=V6) at time t2 is determined by Vop1=-(ΔV / 2+Vc)=-[ΔV / 2+Ic·(Tp-Ta) / (Cp+Cn)].

[0056] Just before time t2, when the control signal G5 changes to a high state and the fifth switching unit S5 turns on, the output current Io (=Ic) flowing through the capacitive load, including the substrate capacitor Cp, stops. Instead, the constant current Ic that had been flowing through inductor Lo is circulated via the path indicated by the dashed-dotted arrow in Figure 7. Also, when the control signal G4 changes to a high state at time t2 and the fourth switching unit S4 turns on, a resonant current due to the composite capacitor Cre (≒Cn) and composite inductor (Ln + Li) flows out of the floating capacitor Cn via the path indicated by the solid-line arrow in Figure 7. Here, the output voltage Vop1 = -(ΔV / 2 + Vc) at time t2 changes to approximately the output voltage Vop1 = ΔV / 2 at time t4 due to the resonant amplitude value, so the initial resonant voltage in this case is (ΔV + Vc) / 2. The voltage value V4=-Vc / 2 of the fourth voltage source 14 is a correction value based on the first node N1 to obtain this initial resonant voltage value from the output voltage Vop1 at time t2. The resonant current value is Io=Idb=[{(Vc+ΔV) / 2} / √{(Ln+Li) / Cre}]·sinθ. The inductor Li corrects the increase in resonant current caused by the increase in the difference Vc / 2 between the initial resonant voltages at time t0 and time t2 by increasing the characteristic impedance.

[0057] Furthermore, the difference between the stage voltage Vop2, which is the voltage value of the floating capacitor Cn and changes rapidly due to resonance, and the voltage value of the substrate capacitor Cp, which changes slowly due to the action of the sheath resistance Rp, is the substrate surface voltage Vsub. Therefore, the current Icp flowing through the current path shown by the dashed line in Figure 7 is roughly the value obtained by dividing the substrate surface voltage Vsub in this case by the resistance value (Rp + Zp).

[0058] At time t3, the stage voltage Vop2, which decreases rapidly, and the voltage Vcp of the substrate capacitor Cp, which changes slowly due to the sheath resistance Rp, become equal, and the substrate surface voltage Vsub becomes 0. After time t3, when Vcp > Vop2, the diode Dp becomes conductive due to the ion sheath rectification, and a current Icp flows, as shown by the dashed arrow in Figure 8. This current Icp is the substrate surface voltage Vsub divided by the resistance Zp, and increases significantly. At this point, the substrate surface voltage Vsub exceeds 0 and becomes a positive voltage, contributing to the discharge of the accumulated charge in the substrate capacitor Cp during the discharge period Td. Furthermore, the current Ic flowing through the inductor Lo is maintained as described above.

[0059] At time t4, the fourth switching unit S2 turns off and, at approximately the same time, the first switching unit S1 turns on. At this time, the control unit 20 uses the second current sensor Ct2 to detect that the current in the path from the second node N2 to the third node N3 has become zero, and can synchronize the on operation of the first switching unit S1 with the timing of this zero current. This means that the half-wave resonance period (t2 to t4) (=π√[(Li + Ln) · Cre]) in the commutation period Tb is matched with the resonant current flow period of Io = Idb (see FIG. 5(c)). At this time, the voltage value of the output voltage Vop1 is ideally ΔV / 2, which is the same potential as the voltage value V1 of the first voltage source 11, so the current Ird of the first switching unit S1 does not flow.

[0060] If the voltage value of output voltage Vop1 has not yet dropped to +ΔV / 2 at time t4, current Ird flows from first voltage source 11, as shown in FIG. 9. On the other hand, if the voltage value of output voltage Vop1 exceeds ΔV / 2 in the positive direction at time t4, current Ird flows in the reverse direction, and output voltage Vop1 is clamped to the voltage value ΔV / 2 of first voltage source 11. As a result, the voltage value of output voltage Vop1 quickly converges to the voltage value ΔV / 2 (= V1) of first voltage source 11 and is reliably maintained at ΔV / 2. Damping resistor Rd has the function of suppressing unnecessary oscillations of current Ird, and its resistance value is preferably set to Rd ≈ 2 √(Ln / Cre). However, as mentioned above, damping resistor Rd is not an essential element for operation.

[0061] As shown in the time chart of Fig. 10, if the switching operation at time t4 occurs earlier than the time when the second current sensor Ct2 detects that the current Idb is zero due to factors such as a time error in the timing control by the control unit 20, the diode D2 will be conductive. Then, a current Id2 having a value substantially equal to the current Idb that had been flowing up until then will flow through the path indicated by the solid arrow in Fig. 9, and the energy stored in the composite inductor of inductors Li and Ln will be regenerated to the first voltage source 11. As a result, no overvoltage will be generated in the fourth switching unit S4, which is turned off earlier than the first switching unit S1 is turned on, and the pulse power supply unit 3 of this embodiment can operate safely and stably.

[0062] The operation during the commutation period Tb when the pulse is off as described above can be achieved without the need for a dedicated switching unit for coupling the current source 12 to the output terminal 10, or for commutation time management in accordance with the half-wave resonance period, which were necessary in conventional pulse power supplies. Furthermore, the constant current Ic flowing through the inductor Lo indicated by the dashed-dotted arrow in Figure 9 is maintained in the same manner as described above.

[0063] As described above, the pulse power supply unit 3 of this embodiment can achieve stable and good operation during both the pulse-on and pulse-off commutation periods without strict management of the commutation time to match the half-wave resonance period. Furthermore, it is possible to appropriately recover energy during commutation operation and reduce loss.

[0064] [Variations] Next, several modifications related to the pulse power supply unit 3 of the first embodiment will be described. 11 is a schematic diagram of a pulse power supply unit 3 according to a modified example. The configuration of this modified example is basically the same as that of the first embodiment, but the voltages V1, V3, and V4 of the first voltage source 11, third voltage source 13, and fourth voltage source 14 are different: V1=0, V3=-ΔV, and V4=-(ΔV+Vc) / 2. Therefore, the first voltage source 11 does not exist as an entity but is in a short-circuited state, while the third voltage source 13 does not exist as an entity but is not in a short-circuited state. There is no change in the operation timing of the control signals G1, G2, G4, and G5 output from the control unit 20, and the operation is essentially the same as that of the first embodiment.

[0065] That is, the output voltage Vop1 at this time has a shape obtained by shifting the waveform shown in Figure 3(b) by ΔV / 2 in the negative voltage direction (i.e., downward along the vertical axis). Furthermore, reflecting this waveform shift, the voltage waveforms shown in Figures 4 and 5 are also appropriately shifted in the vertical direction. Meanwhile, as described above, the stage voltage Vop2 is obtained by simply shifting the waveform of the output voltage Vop1, to which a DC floating zero potential is applied by the blocking capacitor Cb, in the negative direction (or positive direction) by the DC voltage that is the average voltage of the substrate surface voltage Vsub. Therefore, the waveform of the stage voltage Vop2 is as shown in Figure 3(c).

[0066] 12 is a schematic diagram of another modified pulse power supply unit 3. The configuration of this modified example is basically the same as that of the first embodiment, but the voltages V1, V3, and V4 of the first voltage source 11, third voltage source 13, and fourth voltage source 14 are different: V1=+ΔV, V3=+ΔV / 2, and V4=−(ΔV−Vc) / 2. Therefore, in this configuration, the first voltage source 11 and the third voltage source 13 are not short-circuited but exist as actual entities. There is no change in the operation timing of the control signals G1, G2, G4, and G5 output from the control unit 20, and the substantial operation is the same as that of the first embodiment.

[0067] That is, the output voltage Vop1 at this time has a shape obtained by shifting the waveform shown in Figure 3(b) by ΔV / 2 in the direction of the positive polarity of the voltage (i.e., upward along the vertical axis). Furthermore, reflecting this waveform shift, the voltage waveforms shown in Figures 4 and 5 are also appropriately shifted in the direction of the vertical axis. Meanwhile, as described above, the stage voltage Vop2 is obtained by simply shifting the waveform of the output voltage Vop1, to which a DC floating zero potential is applied by the blocking capacitor Cb, in the negative (or positive) direction by the DC voltage that is the average voltage of the substrate surface voltage Vsub, so the waveform of the stage voltage Vop2 is as shown in Figure 3(c).

[0068] In the operation of the commutation period Tb in the pulse power supply unit 3 of the first embodiment, as described above, even if the switching operation at time t4 occurs earlier than the time when the current in the path from the second node N2 to the third node N3 is detected to be zero, the diode D2 is made conductive, allowing the resonant current to continue to flow. Furthermore, even if the voltage of the output voltage Vop1 does not reach +ΔV / 2, the clamping action of the first voltage source 11 can compensate for the voltage value to +ΔV / 2. However, if the voltage value of the output voltage Vop1 exceeds the range in which the above-mentioned compensation operation can be performed, the voltage V4 of the fourth voltage source 14 must be adjusted.

[0069] The time chart shown in FIG. 10 illustrates a state in which the switching operation at time t4 is significantly earlier than the detection of zero current. When the switching unit S4 turns off and the resonant current, which is the output current Io (=Idb), is interrupted, diode D2 conducts, and current Id2 flows through the path indicated by the solid arrow in FIG. 9, extending the resonant current period. This corresponds to shifting time t4 shown in FIG. 10 to time t4a in FIG. 10, which corresponds to time t4 in FIG. 5. Furthermore, current Ird flows from the first voltage source 11 through the path shown in FIG. 9, ensuring the voltage ΔV / 2 of the output voltage Vop1. This means that, with the exception of the second current sensor Ct2, the pulsed power supply unit 3 of the first embodiment can omit both the function of detecting zero current in the path from the second node N2 to the third node N3 and the function of synchronizing the timing of this zero detection with the switching operation at time t4 during the commutation period Tb. Therefore, such functions may be omitted.

[0070] However, as the difference between time t4 and time t4a in the time chart shown in Figure 10 increases, the current Ird increases, and the power consumption of the damping resistor Rd also increases. Therefore, attention must be paid to the power tolerance of the damping resistor Rd. In addition, in response to this increase in power consumption of the damping resistor Rd, the current Ird can be reduced by shifting the timing at which the control signal G1 changes to a high state at time t4, turning on the switching unit S1, to around time t4a, when the current Id2 becomes zero.

[0071] On the other hand, in the pulsed power supply unit 3 of the above embodiment and each modification, if the capacitor load is short-circuited for a short time during the processing period Tp due to a plasma arc discharge or the like, the synchronous control between the detection of zero current in the control unit 20 and the switching operation at time t4 as described above may become out of sync, which may increase the time required for control to be established or may result in a situation where control is not established for a long time. However, due to the peculiarities of the plasma etching process, if the arc discharge is weak, the pulsed power supply unit may continue to operate without being stopped, and therefore it may be possible to deliberately not perform the synchronous control as described above and instead use asynchronous control.

[0072] For this reason, immediately after the start of operation of the pulsed power supply unit 3, synchronous control of the zero current detection and the switching operation at time t4 may be performed, and the duty ratio corresponding to time t4 determined by this synchronous control may be reduced only slightly (for example, by about 0.01) to set a fixed value with a margin of advance at time t4, and subsequent control (effectively asynchronous control) may be performed. In other words, the above-mentioned synchronous control is not essential for the pulsed power supply unit according to the present invention.

[0073] In the pulse power supply unit 3 of the first embodiment, the inductor Li arranged between the second node N2 and the third node N3 has the function of compensating, by increasing the characteristic impedance, for an increase in the resonant current due to the difference between the initial resonant voltage values ​​at time t0 and time t2 (the start points of the commutation periods Ta and Tb). Therefore, if circuit devices such as switching elements can handle the current increase in the resonant path at time t2, it is possible to adopt a configuration in which the inductor Li is omitted. This is also desirable in terms of shortening the commutation period Tb.

[0074] 13 is a schematic diagram of a pulse power supply unit according to a modified example in which inductor Li is omitted. As shown in the figure, switching unit S3, which was connected between second node N2 and fourth node N4 in the first embodiment, is moved to between third node N3, which is essentially the same as second node N2, and fourth node N4. In this case, diode D2 is unnecessary, and anti-parallel diode D3 of switching unit S3 can function in place of diode D2. Furthermore, the inductance value of the composite inductor (Li+Ln) shown in the above-mentioned formulas and the like is the inductance value of wiring inductor Ln alone.

[0075] Figure 14 is a schematic circuit diagram of a pulse power supply unit that further simplifies the configuration shown in Figure 13. This pulse power supply unit 3 does not include fourth voltage source 14, which outputs voltage V4, a compensation voltage based on first node N1 to obtain the initial resonant voltage value. This is essentially the same as setting the voltage of fourth voltage source 14 to 0 (short circuit), and can be considered as V4=0.

[0076] When V4=0, the initial resonant voltage during the commutation period Tb when the pulse is off is Vop1(t2)=-{(ΔV / 2)+Vc}, and after the end of the half-wave resonant period, Vop1(t4)={(ΔV / 2)+Vc}. As a result, the output voltage Vop1 becomes higher than the voltage +ΔV / 2 of the first voltage source 11 by Vc, significantly deviating from +ΔV / 2. As a result, it cannot be compensated to +ΔV / 2 by the voltage clipping function, as described above. Therefore, in this case, time t4, at which the switching unit S2 turns off, is set earlier than the zero-current detection point in the path from the second node N2 to the third node N3, which corresponds to the half-wave resonant period, compared to time t4 shown in FIG. 10, for example, to further shorten the period during which the resonant current Idb flows, so that the output voltage Vop1 at time t4 is approximately ΔV / 2. Furthermore, it is advisable to shift the timing at which the control signal G1 changes to high at time t4 to turn on the switching unit S1 to near time t4a, when the current Id2 becomes 0, thereby reducing the current Ird. This makes it possible to achieve good commutation operation in the pulse power supply unit 3 shown in FIG.

[0077] 15 is a schematic circuit diagram of a pulse power supply unit 3 according to yet another modification. The basic configuration of this embodiment is the same as that of the first embodiment, but a high-speed constant current power supply Ap is provided in parallel with the current source 12.

[0078] This high-speed constant-current power supply Ap adds +Ic to the current Ic from the current source 12 in response to a command from the control unit 20 specifying a set current value +Ic. This added current +Ic can be applied in response to a command from the process control unit 1 to correct the substrate surface voltage Vsub when the substrate surface voltage Vsub changes due to changes in the sheath conditions caused by changes in the gas pressure in the plasma reactor Pr or fluctuations in the output of the ion source plasma power supply unit 2. Therefore, the current +Ic is a current value that corresponds only to the change in the substrate surface voltage Vsub. Since this current is smaller than the current Ic from the current source 12, the output of the high-speed constant-current power supply Ap can have a small power capacity. Therefore, a switching element with a small capacity and good high-frequency characteristics, such as a gallium nitride (GAN) element, can be used. High-speed control is possible by increasing the PWM switching frequency and adopting a multi-phase configuration using a phase-shift multilevel cascade converter or the like.

[0079] It should be noted that the values ​​obtained by the formulas used in the above explanation are ideal values ​​that do not include circuit resistance, etc., and it goes without saying that it is desirable to appropriately correct all set values, including set values ​​V1, V3, V4, etc., in accordance with the actual operating conditions.

[0080] Furthermore, the above-described embodiment and modified examples are merely examples of the present invention, and it is clear that any modifications, changes, or additions made within the spirit of the present invention will also be encompassed within the scope of the claims of this application. [Explanation of symbols]

[0081] 1...Process control section 2...Plasma power supply for ion source 3...Bias pulse power supply 4...Processing chamber 5...Plasma 6...Substrate 7...Stage 9...Grounding end 10...Output terminal 12…Current source 11, 13, 14, 15...Voltage source 20...Control unit S1, S2, S4, S5...Switching section D1, D2, D3, D4, D5, Da, Db, Dc...Diodes N1, N2, N3, N4...nodes Ct1, Ct2...Current sensors Cb: Blocking capacitor Cn: floating capacitor Cp: ​​Substrate capacitor Cs: sheath capacitor Dp...Sheath diode Lo, Li... inductor Ln: Wiring inductor Rd...damping resistance Rp: Sheath resistance Zp: Plasma resistance

Claims

1. A bias control method for forming a pulsed voltage waveform at an output terminal of a pulsed power supply in order to supply a bias to a plasma reactor (Pr) including a processing object in a plasma etching apparatus, comprising: selectively supplying to the output terminal a DC current having a predetermined current value, a third DC voltage having a third voltage value, a fourth DC voltage having a fourth voltage value, and a first voltage value lower than the third voltage value (V3) and the fourth voltage value, all of which are referenced to a ground potential; a) a first step of coupling the first DC voltage to the output terminal to reduce the output voltage at the output terminal to a first voltage value when the voltage drops due to half-wave resonance in a fourth step described below and becomes lower than the third voltage value and the fourth voltage value, and maintaining the first voltage value in a capacitor load of a plasma reactor to maintain the output voltage at a low level; b) a second step of coupling the third DC voltage to the output terminal in place of the first DC voltage, and causing a current to flow by half-wave resonance in a resonant loop including at least the capacitor load and an inductor including a wiring between the pulse power supply device and the plasma reactor, thereby increasing the output voltage; c) a third step of coupling the DC current to the output terminal when the output voltage reaches a potential of a predetermined fifth voltage value higher than the third voltage value due to the voltage increase in the second step, and further linearly increasing the output voltage over time using the DC current; d) a fourth step of coupling the fourth DC voltage to the output terminal in place of the DC current after the output voltage has risen to a potential that is a predetermined sixth voltage value in the third step, and causing a current to flow by half-wave resonance in a resonance loop that includes at least the capacitor load and the inductor, thereby decreasing the output voltage; A bias control method comprising:

2. 2. The bias control method according to claim 1, wherein, when ΔV and Vc are predetermined positive voltage values, the third voltage value is 0, the fourth voltage value is −Vc / 2, the first voltage value is +ΔV / 2, the fifth voltage value is −ΔV / 2, and the sixth voltage value is −(ΔV / 2)−Vc.

3. 2. The bias control method according to claim 1, wherein, when ΔV and Vc are predetermined positive voltage values, the third voltage value is +ΔV / 2, the fourth voltage value is (ΔV-Vc) / 2, the first voltage value is +ΔV, the fifth voltage value is 0, and the sixth voltage value is -Vc.

4. 2. The bias control method according to claim 1, wherein, when ΔV and Vc are respectively predetermined positive voltage values, the third voltage value is −ΔV / 2, the fourth voltage value is −(ΔV+Vc) / 2, the first voltage value is 0, the fifth voltage value is −ΔV, and the sixth voltage value is −ΔV−Vc.

5. 1. A pulse power supply device for generating a pulsed voltage waveform between an output terminal connected to a plasma reactor via wiring and a ground terminal in order to supply a bias to the plasma reactor including a processing object in a plasma etching device, a) a first voltage source generating a first DC voltage having a first voltage value referenced to ground; b) a third voltage source generating a third DC voltage having a third voltage value referenced to ground; c) a fourth voltage source generating a fourth DC voltage having a fourth voltage value referenced to ground; d) a first switch coupling the first voltage source to the output; e) a third switch coupling the third voltage source to the output; f) a fourth switch coupling the fourth voltage source to the output; g) a current source having a current inflow end and a current outflow end, the inflow end being coupled to the output end via the third switch and the outflow end being coupled to the ground end, and supplying a DC current of a predetermined current value; h) a third diode for reverse blocking, which is arranged between the third switch and the third voltage source or between the third voltage source and the ground terminal, and which blocks current flow from the ground terminal side to the third switch side; i) a fourth reverse-blocking diode connected in series to the fourth switch and the fourth voltage source, and blocking current flow from the output terminal to the ground terminal; j) turning on the first switch to couple the first voltage source to the output terminal, and holding a voltage of a first voltage value from the first voltage source in a capacitor load of the plasma reactor, thereby maintaining the output voltage at the output terminal at a low level; turning on the third switch to couple the third voltage source to the output terminal; causing a current to flow by first half-wave resonance in a resonance loop including at least the capacitor load and an inductor including the wiring, thereby increasing the output voltage; and due to this voltage increase, the output voltage reaches a potential of a predetermined fifth voltage value higher than the third voltage value; and further, the third diode changes from a conductive state to a reverse blocking state, thereby increasing the output voltage. a control unit that controls on / off operations of the first switch, the third switch, and the fourth switch so that, when the output voltage rises to a potential of a predetermined sixth voltage value as a result of a DC current from the current source flowing through a load, the control unit turns on the fourth switch to couple the fourth voltage source to the output end, and decreases the output voltage by causing a current to flow by second half-wave resonance in a resonant loop that includes at least the capacitor load and the inductor and that includes the fourth diode, and when the output voltage becomes lower than the third voltage value and the fourth voltage value, the control unit turns on the first switch to couple the first voltage source to the output end, and decreases the output voltage to a first voltage value; A pulse power supply device for a plasma processing apparatus comprising:

6. 6. The pulse power supply device for a plasma processing apparatus according to claim 5, wherein either one of the first voltage value or the third voltage value is set to 0 to short-circuit the first voltage source or the third voltage source, and the other voltage values ​​are set to predetermined voltages corresponding thereto.

7. 7. The pulse power supply device for a plasma processing apparatus according to claim 5, further comprising a high-speed constant current power supply connected in parallel with said current source.

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