Semiconductor device

Abstract

To improve quality.SOLUTION: The semiconductor device includes a wiring substrate, a first stacked body including N (an integer of 2 or more) first plate-shaped portions each having a first width in a width direction intersecting a vertical direction, the N first plate-shaped portions being stacked in the vertical direction above the wiring substrate, and a second stacked body having a second width larger than the first width in the width direction. A second stacked body including a second plate-shaped portion provided above the first stacked body and M (an integer of 1 or more) third plate-shaped portions provided above the second plate-shaped portion and having a first width in a width direction, the second plate-shaped portion and the M third plate-shaped portions being stacked in an up-down direction, the first plate-shaped portion including a first memory chip, the second plate-shaped portion including a second memory chip and a first resin layer connected to a first side of the second memory chip in the width direction, the third plate-shaped portion includes a third memory chip, a second side of the first stacked body and the second stacked body opposite to the first side in the width direction has a stepped shape, and an end portion of the second stacked body on the second side is located on the second side relative to an end portion of the first stacked body on the second side.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] Some semiconductor devices have a plurality of stacked chips disposed on a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication US2018 / 0240782 [Patent Document 2] US Patent Application Publication US2022 / 0336417 [Patent Document 3] US Patent Application Publication US2023 / 0378128 Summary of the Invention [Problem to be solved by the invention]

[0004] Depending on the method of stacking multiple chips, the quality of the semiconductor device may be reduced.

[0005] An object of the present disclosure is to provide a semiconductor device capable of improving quality. [Means for solving the problem]

[0006] a first stacked body above the wiring substrate, the first stacked body including N first plate-like portions having a first width in a first width direction intersecting with the vertical direction, the N first plate-like portions being stacked in the vertical direction; a second plate-like portion having a second width greater than the first width in the first width direction and being provided above the first stacked body; and M third plate-like portions being provided above the second plate-like portion and having the first width in the first width direction, the second stacked body being stacked in the vertical direction, the second stacked body including M third plate-like portions being stacked in the vertical direction, the first plate-like portion including a first memory chip having first electrode pads on an upper surface thereof and electrically connected to the wiring substrate through first bonding wires; The second plate-shaped portion includes a second memory chip having second electrode pads on its upper surface that are electrically connected to the wiring board through second bonding wires, and a first resin layer connected to a first side in the first width direction of the second memory chip, and the third plate-shaped portion includes a third memory chip having third electrode pads on its upper surface that are electrically connected to the wiring board through the second bonding wires, and a second side of the first laminate, which is opposite to the first side in the first width direction, is stepped with the first electrode pads located on step surfaces, and the second side of the second laminate is stepped with the second electrode pads or the third electrode pads located on step surfaces, and when the main surface is viewed in a plane, the end of the second side of the second laminate is located on the second side further than the end of the second side of the first laminate.

[0007] A semiconductor device according to the present disclosure includes a wiring substrate having a main surface intersecting with a vertical direction, L sixth plate-shaped portions and L seventh plate-shaped portions each having a first width in a first width direction intersecting with the vertical direction, and an eighth plate-shaped portion having a second width in the first width direction that is larger than the first width, wherein the L sixth plate-shaped portions are stacked in the vertical direction above the wiring substrate, and the L seventh plate-shaped portions are stacked in the vertical direction on a first side in the first width direction of the L sixth plate-shaped portions, and the eighth plate-shaped portion is the uppermost sixth plate-shaped portion. and a fourth stacked body arranged across the upper surface of the plate-shaped portion and the upper surface of the seventh plate-shaped portion of the topmost tier, wherein the sixth plate-shaped portion and the seventh plate-shaped portion include a seventh memory chip and an eighth memory chip, respectively, and the eighth plate-shaped portion includes a ninth memory chip, a fourth resin layer connected to the first side of the ninth memory chip, and a tenth memory chip arranged on the first side of the fourth resin layer, and the first side and a second side opposite to the first side of the fourth stacked body are stepped.

[0008] A semiconductor device according to the present disclosure includes a wiring substrate having a main surface intersecting with a vertical direction, a first stacked body including N first plate-like portions having a first width in a first width direction intersecting with the vertical direction, the first stacked body being formed above the wiring substrate by stacking the N first plate-like portions in the vertical direction, a third stacked body including N fourth plate-like portions having the first width in the first width direction, the third stacked body being formed on a first side of the first stacked body in the first width direction by stacking the N fourth plate-like portions in the vertical direction, and a second stacked body having a second width in a second width direction intersecting with the vertical direction and the first width direction that is greater than the first width, the third stacked body being formed on an upper surface and a front surface of the first stacked body. a second laminate including a second plate-shaped portion provided across an upper surface of the third laminate, M third plate-shaped portions provided above the second plate-shaped portion and having the first width in the second width direction, and M fifth plate-shaped portions having the first width in the second width direction, the second plate-shaped portion and the M third plate-shaped portions being stacked in the vertical direction, and the M fifth plate-shaped portions being stacked in the vertical direction on a third side in the second width direction of the M third plate-shaped portions, and the first plate-shaped portion has a first electrode pad provided on its upper surface, the first electrode pad being electrically connected to the wiring board through a first bonding wire. the fourth plate-shaped portion includes a fourth memory chip having fourth electrode pads on an upper surface thereof, the fourth electrode pads being electrically connected to the wiring board through third bonding wires; the second plate-shaped portion includes a second memory chip having second electrode pads on an upper surface thereof, the second electrode pads being electrically connected to the wiring board through second bonding wires; a first resin layer connected to the third side in the second width direction of the second memory chip; and a fifth electrode pad on an upper surface thereof, the fifth electrode pads being electrically connected to the wiring board through fourth bonding wires; the third plate-shaped portion includes a third memory chip having third electrode pads on an upper surface thereof, the third electrode pads being electrically connected to the wiring board through the second bonding wires; the fifth plate-shaped portion includes a sixth memory chip having sixth electrode pads on an upper surface thereof, the sixth electrode pads being electrically connected to the wiring board through the fourth bonding wires; a second side of the first laminate opposite to the first side in the first width direction is stepped with the first electrode pads located on step surfaces; and the second side of the third laminate in the first width direction isThe fourth side of the second laminate, which is opposite to the third side in the second width direction, is also stair-shaped with the second electrode pad or the third electrode pad located on a step surface, and the fourth side of the second laminate in the second width direction is also stair-shaped with the fifth electrode pad or the sixth electrode pad located on a step surface. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing a cross section parallel to a YZ plane of the semiconductor device according to the first embodiment. [Figure 2] 1 is a plan view of a semiconductor chip according to a first embodiment, viewed from above. [Figure 3] FIG. 10 is a plan view of the plate-shaped portion 411 as seen from above. [Figure 4] FIG. 10 is a plan view of the plate-shaped portion 412 as seen from above. [Figure 5] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 13]2A to 2C are schematic views showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 14] FIG. 10 is a schematic diagram showing a cross section of a semiconductor device according to a comparative example when viewed from the side; [Figure 15] FIG. 10 is a plan view of a semiconductor chip according to a comparative example, viewed from above. [Figure 16] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 17] 10A to 10C are schematic diagrams showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the second embodiment. [Figure 18] 10A to 10C are schematic diagrams showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the second embodiment. [Figure 19] FIG. 10 is a schematic view showing a cross section of a first modified example of the semiconductor device according to the second embodiment. [Figure 20] FIG. 10 is a schematic view showing a cross section of a second modified example of the semiconductor device according to the second embodiment. [Figure 21] FIG. 10 is a schematic view showing a cross section of a third modified example of the semiconductor device according to the second embodiment. [Figure 22] FIG. 10 is a schematic view showing a cross section of a fourth modified example of the semiconductor device according to the second embodiment. [Figure 23] FIG. 10 is a schematic view showing a cross section of a fifth modified example of the semiconductor device according to the second embodiment. [Figure 24] FIG. 10 is a schematic view showing a cross section of a sixth modified example of the semiconductor device according to the second embodiment. [Figure 25] FIG. 13 is a schematic view showing a cross section of a seventh modified example of the semiconductor device according to the second embodiment. [Figure 26] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 27] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 28] 10A to 10C are schematic diagrams showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the fourth embodiment. [Figure 29] 10A to 10C are schematic diagrams showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the fourth embodiment. [Figure 30] 10A to 10C are schematic diagrams showing cross sections parallel to the YZ plane, illustrating the manufacturing process of the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0011] [First embodiment] The configuration of the semiconductor device according to the first embodiment will be described below. Each drawing may show an X-axis, a Y-axis, and a Z-axis. The X-axis, Y-axis, and Z-axis form a right-handed, three-dimensional Cartesian coordinate system. Hereinafter, the direction of the X-axis arrow may be referred to as the X-axis + direction, and the direction opposite to the arrow may be referred to as the X-axis - direction. The same applies to the other axes. The Z-axis + direction and the Z-axis - direction may be referred to as "upper" and "lower," respectively. Furthermore, planes perpendicular to the X-axis, Y-axis, or Z-axis may be referred to as the YZ plane, ZX plane, or XY plane. Furthermore, the Z-axis direction may be referred to as the "vertical direction." The terms "upper," "lower," and "vertical direction" merely indicate relative positions within the drawing, and do not define orientations relative to the vertical direction.

[0012] In addition, unless otherwise specifically explained, the dimensions of the components shown in each drawing may be shown differently from the actual dimensions in order to make the explanation easier to understand.

[0013] In this specification, the term "connection" includes not only physical connection but also electrical connection, and unless otherwise specified, includes not only direct connection but also indirect connection.

[0014] In this specification, "formed above" does not only mean forming in contact with the upper part, but also includes forming above via another object unless otherwise specified. The same applies to "formed below" and the like.

[0015] Fig. 1 is a schematic diagram showing a cross section parallel to the YZ plane of the semiconductor device according to the first embodiment. Fig. 2 is a plan view of the semiconductor chip according to the first embodiment as seen from above. For ease of understanding, sealing resin 65 is not shown in Fig. 2.

[0016] 1 and 2, the semiconductor device 11 includes a wiring substrate 25, a sealing resin 65 (an example of a "sixth resin layer"), and two one-tower structures 501. The one-tower structure 501 includes bonding wires 81a (an example of a "first bonding wire") and 81b (an example of a "second bonding wire"), and laminates 401 (an example of a "first laminate") and 402 (an example of a "second laminate").

[0017] One of the two one tower structures 501 is obtained by rotating the other one tower structure 501 by 180 degrees around the Z axis as the rotation axis. In the following, one tower structure 501 on the negative Y-axis side will be described as a representative example, but the same applies to the one tower structure 501 on the positive Y-axis side.

[0018] The wiring board 25 has a surface 25a (an example of a "principal surface") that intersects with the vertical direction (Z-axis direction). In this embodiment, the surface 25a is substantially parallel to the XY plane.

[0019] A plurality of substrate electrodes 26a and a plurality of substrate electrodes 26b are provided on surface 25a.

[0020] A plurality of board electrodes 26a are arranged in a line along the X-axis direction to form bonding fingers. The bonding fingers of board electrodes 26a are located on the negative side of tower structure 501 in the Y-axis direction.

[0021] Similarly, bonding fingers are formed by arranging multiple board electrodes 26b in a line along the X-axis direction. The bonding fingers of board electrode 26b are located on the negative Y-axis side of the bonding fingers of board electrode 26a.

[0022] A plurality of solder balls 64 are provided on the lower surface of the wiring board 25. An electrode pattern (not shown) is also formed on the wiring board 25. Some or all of the board electrodes 26a and 26b are electrically connected to the plurality of solder balls 64 via the electrode pattern formed on the wiring board 25.

[0023] 3 is a plan view of plate-shaped portion 411 viewed from above. As shown in FIGS. 1 to 3, laminate 401 includes N (N is an integer of 2 or more) plate-shaped portions 411 (an example of a "first plate-shaped portion") and N die attach films 421. In this embodiment, laminate 401 includes four plate-shaped portions 411 and four die attach films 421.

[0024] The plate-shaped portion 411 has a width W1 (an example of a "first width") in a Y-axis direction (an example of a "first width direction") that intersects with the up-down direction. The width W1 of each plate-shaped portion 411 may vary within a manufacturing tolerance.

[0025] In this embodiment, the thickness of the bottommost plate-shaped portion 411 of the four plate-shaped portions 411 is greater than the thicknesses of the other three plate-shaped portions 411. Note that the thickness of each plate-shaped portion 411 in the vertical direction may be the same.

[0026] The plate-shaped portion 411 includes a memory chip 411a (an example of a "first memory chip"), a CMOS (Complementary Metal-Oxide-Semiconductor) chip 411b (an example of a "second semiconductor chip"), a molded resin 411c (an example of a "resin layer"), and a plurality of electrode pads 411d (an example of a "first electrode pad").

[0027] The memory chip 411a is, for example, a NAND flash memory chip. The memory chip 411a is located closer to the end of the plate-shaped portion 411 on the negative Y-axis side than to the end of the plate-shaped portion 411 on the positive Y-axis side.

[0028] A plurality of electrode pads 411d are provided on the upper surface of the memory chip 411a, the number of which is the same as the number of substrate electrodes 26a that form bonding fingers.

[0029] The electrode pads 411d are located closer to the negative end of the Y axis than to the positive end of the Y axis of the memory chip 411a, and are aligned in a row along the X axis. The electrode pads 411d are electrically connected to the substrate electrodes 26a via bonding wires 81a, respectively.

[0030] The CMOS chip 411b controls the memory chip 411a. The memory chip 411a is attached to a part of the upper surface of the CMOS chip 411b (hereinafter, sometimes referred to as the attachment surface). The CMOS chip 411b and the memory chip 411a are electrically and mechanically connected by direct bonding. Details of direct bonding will be described later.

[0031] A molding resin 411c is connected to the positive Y-axis direction side (an example of the "first side") of the memory chip 411a.

[0032] In this embodiment, a molding resin 411c is connected to the upper surface of the CMOS chip 411b excluding the bonding surface, and to the side surfaces of the memory chip 411a parallel to the ZX plane and the YZ plane. The width of the molding resin 411c in the Y-axis direction and the width of the CMOS chip 411b are W1. The width W1 of the CMOS chip 411b in the Y-axis direction is larger than the width of the memory chip 411a.

[0033] A die attach film 421 is provided on the lower surface of the CMOS chip 411b. The method for manufacturing the plate-shaped portion 411 will be described in detail later.

[0034] The four plate-shaped portions 411 are stacked in the vertical direction above the wiring substrate 25. In detail, the lowest plate-shaped portion 411 is connected to the surface 25a of the wiring substrate 25 by, for example, a die attach film 421 having a width W1 in the Y-axis direction. The second plate-shaped portion 411 from the bottom is connected to the upper surface of the lowest plate-shaped portion 411 by the die attach film 421. In this way, the four plate-shaped portions 411 are stacked to form the laminate 401.

[0035] The negative Y-axis side (an example of a "second side") of the laminate 401, which is opposite to the positive Y-axis side, is stepped. The steps have a step surface (terrace surface) SP1 parallel to the XY plane. An electrode pad 411d is located on the step surface SP1.

[0036] 4 is a plan view of plate-shaped portion 412 viewed from above. As shown in FIGS. 1 to 4, laminate 402 includes plate-shaped portion 412 (an example of a "second plate-shaped portion"), M (M is an integer of 1 or more) plate-shaped portions 413 (an example of a "third plate-shaped portion"), die attach film 422, and M die attach films 423.

[0037] In this embodiment, the laminate 402 includes a plate-shaped portion 412 , three plate-shaped portions 413 , a die attach film 422 , and three die attach films 423 .

[0038] Plate-shaped portion 412 is provided above stacked body 401, and has a width W2 (an example of a "second width") in the Y-axis direction that is larger than width W1. Plate-shaped portion 412 includes a memory chip 412a (an example of a "second memory chip"), a CMOS chip 412b (an example of a "second semiconductor chip"), a mold resin 412c (an example of a "first resin layer"), and a plurality of electrode pads 412d (an example of a "second electrode pad").

[0039] The memory chip 412a is, for example, a NAND flash memory chip similar to the memory chip 411a. The memory chip 412a is located closer to the end of the plate-shaped portion 412 on the negative side of the Y axis than to the end of the plate-shaped portion 412 on the positive side of the Y axis. The width of the memory chip 412a in the Y axis direction is approximately the same as the width of the memory chip 411a in the Y axis direction.

[0040] A plurality of electrode pads 412d are provided on the upper surface of the memory chip 412a, the number of which is the same as the number of substrate electrodes 26b that form bonding fingers.

[0041] The electrode pads 412d are located closer to the negative end of the Y axis of the memory chip 412a than to the positive end of the Y axis, and are aligned in a row along the X axis. The electrode pads 412d are electrically connected to the substrate electrodes 26b via bonding wires 81b, respectively.

[0042] The CMOS chip 412b is, for example, the same chip as the CMOS chip 411b. The CMOS chip 412b controls the memory chip 412a. The width of the CMOS chip 412b in the Y-axis direction is approximately the same as the width of the CMOS chip 411b in the Y-axis direction. The memory chip 412a is attached to a part of the upper surface of the CMOS chip 412b (hereinafter, sometimes referred to as the attachment surface).

[0043] A molding resin 412c is connected to the positive Y-axis direction side (an example of the "first side") of the memory chip 412a.

[0044] In this embodiment, a molding resin 412c is connected to the upper surface of the CMOS chip 412b excluding the bonding surface, and to the side surfaces of the memory chip 412a parallel to the ZX plane and the YZ plane.

[0045] The width of the molding resin 412c in the Y-axis direction is greater than the width of the CMOS chip 412b in the Y-axis direction. Specifically, the molding resin 412c extends further in the Y-axis direction than the end of the CMOS chip 412b on the Y-axis positive side.

[0046] For this reason, the width W2 of the plate-shaped portion 412 is larger than the width W1 of the plate-shaped portion 411. In other words, the plate-shaped portion 412 is extended in the positive Y-axis direction by the mold resin 412c compared to the plate-shaped portion 411. Hereinafter, the mold resin 412c on the positive Y-axis side of the end of the CMOS chip 412b on the positive Y-axis side may be referred to as the extension portion.

[0047] A die attach film 422 having a width, for example, width W2, larger than width W1 in the Y-axis direction of die attach film 421 is provided on the lower surface of CMOS chip 412b and the lower surface of the extension of mold resin 412c. A manufacturing method for plate-shaped portion 412 will be described in detail later.

[0048] 1 to 3, the three plate-shaped portions 413 are provided above the plate-shaped portion 412. The plate-shaped portions 413 have a width W1 in the Y-axis direction. The width W1 of each plate-shaped portion 413 may vary within the range of manufacturing tolerance.

[0049] The plate-shaped portion 413 includes a memory chip 413a (an example of a "third memory chip"), a CMOS chip 413b (an example of a "second semiconductor chip"), a molded resin 413c (an example of a "resin layer"), and a plurality of electrode pads 413d (an example of a "third electrode pad").

[0050] The memory chip 413a, CMOS chip 413b, mold resin 413c, electrode pads 413d, and die attach film 423 are the same as the memory chip 411a, CMOS chip 411b, mold resin 411c, electrode pads 411d, and die attach film 421 in the plate-shaped portion 411, respectively.

[0051] The memory chip 413a is located closer to the end of the plate-shaped portion 413 on the negative Y-axis side than to the end of the plate-shaped portion 413 on the positive Y-axis side. Electrode pads 413d, the number of which is equal to the number of substrate electrodes 26b forming bonding fingers, are provided on the upper surface of the memory chip 413a.

[0052] The electrode pads 413d are located closer to the negative end of the Y axis of the memory chip 413a than to the positive end of the Y axis, and are aligned in a row along the X axis. The electrode pads 413d are electrically connected to the substrate electrodes 26b via bonding wires 81b, respectively.

[0053] The plate-shaped portion 412 and the three plate-shaped portions 413 are stacked in the vertical direction above the laminate 401. In detail, the lowermost plate-shaped portion 412 is connected to the upper surface of the uppermost plate-shaped portion 411 in the laminate 401 by a die attach film 422. The thickness of the die attach film 422 in the vertical direction is greater than that of the die attach films 421 and 423 in order to bury the bonding wire 81a.

[0054] The second plate-shaped portion 413 from the bottom is connected to the upper surface of the bottom plate-shaped portion 412 by a die attach film 423. In this way, the plate-shaped portion 412 and the three plate-shaped portions 411 are stacked to form the laminate 402.

[0055] The negative Y-axis direction side of the laminate 402 is stepped. The steps have a step surface (terrace surface) SP2 parallel to the XY plane. An electrode pad 412d or 413d is located on the step surface SP2.

[0056] When surface 25a of wiring board 25 is viewed in plan, end 402a on the negative Y-axis side of laminate 402 is located closer to the negative Y-axis side than end 401a on the negative Y-axis side of laminate 401.

[0057] The sealing resin 65 seals at least one tower structure 501. Specifically, the sealing resin 65 buries the two tower structures 501 and the surface 25a of the wiring board 25 above the wiring board 25. The two tower structures 501 and the surface 25a of the wiring board 25 are insulated and sealed by the sealing resin 65.

[0058] Sealing resin 65 has a composition different from that of mold resin 411c, 412c, or 413c. Sealing resin 65 also has a composition different from that of die attach film 421, 422, or 423.

[0059] Specifically, the material of sealing resin 65 is different from the material of mold resin 411c, 412c, or 413c, and the material of die attach film 421, 422, or 423. Note that some or all of these materials may be the same.

[0060] More specifically, molding resin 411c, 412c, or 413c is, for example, a resin used in a glass clothless fluororesin substrate. Molding resin 411c, 412c, or 413c may contain glass cloth. This increases the hardness of molding resin 411c, 412c, or 413c.

[0061] [Method of manufacturing semiconductor device 11] Hereinafter, a method for manufacturing the semiconductor device 11 will be described as an example of a method for manufacturing a semiconductor device according to this embodiment.

[0062] 5, a CMOS chip 410b is placed above a silicon wafer 311. A CMOS circuit is formed on the surface above a semiconductor layer 61 of the CMOS chip 410b. An insulating layer 62 including pads 51 (an example of a "first pad") and a wiring layer 62a is formed above the CMOS circuit on the semiconductor layer 61. The pads 51 are formed so as to be exposed and approximately flush with the bonding surface 37 above the insulating layer 62.

[0063] Additionally, an insulating layer 72 including a memory array 72a, vias 72b and 72c, a wiring layer 72d, and a pad 52 (an example of a "second pad") is formed below the semiconductor layer 71 in the memory chip 410a. The semiconductor layer 71 includes, for example, silicon. The pad 52 is formed so as to be exposed substantially flush with the lower surface of the insulating layer 72. The via 72c has a shape that extends in the vertical direction. The lower end of the via 72c is electrically connected to the pad 52.

[0064] Pads 51 and 52 are annealed while in contact with each other, and by bonding pads 51 and 52 together, memory chip 410a and CMOS chip 410b are bonded together at bonding surface 37. Specifically, pads 51 and 52 are bonded together by direct bonding, in which copper contained in pad 51 directly bonds with copper contained in pad 52. This bonds pads 51 and 52 electrically and mechanically. At this time, the upper surface of insulating layer 62 and the lower surface of insulating layer 72 are bonded together by hydrogen bonding.

[0065] 6, a molding resin 410c is formed above the silicon wafer 311. As a result, the memory chip 410a and the CMOS chip 410b are sealed with the molding resin 410c.

[0066] 7, the upper surface of the molding resin 410c is subjected to chemical mechanical polishing, thereby exposing the upper surface of the semiconductor layer 71, i.e., the surface 22c of the memory chip 410a, from the molding resin 410c. Then, the silicon wafer 311 is subjected to degas annealing.

[0067] Next, as shown in FIG. 8, after a film is formed on the surface 22c of the memory chip 410a by a PEP (Photo Engraving Process) method, a resist is applied, exposed, developed, and peeled off, a hole 22b is formed in the memory chip 410a by reactive ion etching, penetrating to the insulating layer 72.

[0068] Next, as shown in FIG. 9, after performing film formation, resist application, exposure, development, and peeling on the surface 22c of the memory chip 410a by the PEP method, an insulating layer 74 containing, for example, polyimide is formed above the memory chip 410a.

[0069] 10, a resist insulating layer 75 is formed by performing film formation, resist coating, exposure, development, and peeling on the upper surface of the insulating layer 74 using the PEP method. Then, nickel and gold are vapor-deposited to form an electrode pad 410d.

[0070] The electrode pad 410d is electrically connected to the upper end of the via 72c, thereby electrically connecting the electrode pad 410d to the CMOS circuit formed in the semiconductor layer 61 through the via 72c, the pads 52 and 51, and the wiring layer 62a.

[0071] The CMOS circuit is electrically connected to the memory array 72a through the wiring layer 62a, the pads 51 and 52, and the wiring layer 72d or vias 72b.

[0072] Next, as shown in FIG. 11, the insulating layer 75 is removed by, for example, an etching process.

[0073] 12, the silicon wafer 311 is diced along the dicing lines 112X, and the lower surface of the separated silicon wafer 311 is chemically mechanically polished, thereby separating a portion of the silicon wafer 311 into plate-shaped portions 412 (see FIGS. 1 and 4). The silicon wafer 311 is, for example, removed by the chemical mechanical polishing. Note that a portion of the silicon wafer 311 may remain after the chemical mechanical polishing.

[0074] The separated memory chip 410a, CMOS chip 410b, molding resin 410c, and electrode pads 410d become memory chip 412a, CMOS chip 412b, molding resin 412c, and electrode pads 412d, respectively.

[0075] 13, silicon wafer 311 is diced along dicing lines 111X, and the lower surface of each separated silicon wafer 311 is chemically mechanically polished, thereby separating a portion of silicon wafer 311 into plate-shaped portions 411 and 413 (see FIGS. 1 to 3). The separated memory chip 410a, CMOS chip 410b, molding resin 410c, and electrode pad 410d become memory chip 411a, CMOS chip 411b, molding resin 411c, and electrode pad 411d, respectively. Plate-shaped portion 413 has the same configuration as plate-shaped portion 411, so a description thereof will be omitted.

[0076] 1, the four plate-shaped portions 411 are each disposed on the surface 25a of the wiring board 25 or on the upper surface of the lower plate-shaped portion 411 via a die attachment film 421, thereby forming a laminate 401. Then, the plate-shaped portion 412 is disposed on the upper surface of the laminate 401 via a die attachment film 422, and the three plate-shaped portions 413 are disposed on the upper surface of the plate-shaped portion 412 or on the upper surface of the lower plate-shaped portion 413 via a die attachment film 423, thereby forming a laminate 402.

[0077] (effect) Fig. 14 is a schematic diagram showing a cross section of a semiconductor device according to a comparative example when viewed from the side. Fig. 15 is a plan view of a semiconductor chip according to a comparative example when viewed from above. For ease of understanding, sealing resin 65 is not shown in Fig. 15.

[0078] As shown in FIGS. 14 and 15, the semiconductor device 91 according to the comparative example includes two one-tower structures 901 instead of the two one-tower structures 501 in the semiconductor device 11 (see FIG. 1).

[0079] In one tower structure 901, a stacked body 401 is provided above another stacked body 401. In one tower structure 901, when surface 25a of wiring board 25 is viewed in a plan view, end portions 402a of two stacked bodies 401 on the negative Y-axis direction side are aligned.

[0080] Therefore, the multiple board electrodes 26a forming the bonding fingers and the multiple board electrodes 26b forming the bonding fingers are arranged close to each other, which increases the density of the board electrodes 26a and 26b. Furthermore, if the board electrodes 26a and 26b were arranged farther apart, the length of the bonding wire 81b would be long.

[0081] In contrast, in the semiconductor device 11, the width W2 of the plate-shaped portion 412 in the laminate 402 is larger than the width W1 of the plate-shaped portion 411 in the laminate 401, so that when the surface 25a of the wiring board 25 is viewed in a plane, the end 402a of the laminate 402 can be stably positioned on the negative side of the Y-axis relative to the end 401a of the laminate 401.

[0082] This allows the board electrodes 26a and 26b to be spaced apart without increasing the length of the bonding wire 81b, thereby reducing the density of the board electrodes 26a and 26b. Furthermore, the distance between the bonding wires 81a and 81b can be increased, reducing mounting defects of the bonding wires 81a and 81b, and providing a semiconductor device that can improve quality.

[0083] [Second embodiment] A semiconductor device according to a second embodiment will be described. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and only differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0084] 16 is a schematic cross-sectional view of the semiconductor device according to the second embodiment, which should be viewed in the same manner as FIG.

[0085] As shown in Figure 16, the semiconductor device 12 differs from the semiconductor device 11 of the first embodiment in that the two plate-shaped portions 412 included in each of the two one-tower structures 501 are combined into one to form a two-tower connected structure 502, as compared to the semiconductor device 11 shown in Figure 1.

[0086] Compared to the semiconductor device 11 shown in FIG. 1, the semiconductor device 12 includes a two-tower connected structure 502 instead of the two one-tower structures 501 .

[0087] The two-tower connecting structure 502 includes bonding wires 81a (an example of a "first bonding wire"), 81b (an example of a "second bonding wire"), 81c (an example of a "third bonding wire"), and 81d (an example of a "fourth bonding wire"), and laminates 401 (an example of a "first laminate"), 402 (an example of a "second laminate"), and 403 (an example of a "third laminate").

[0088] The laminate 403 includes N plate-shaped portions 414 (an example of a "fourth plate-shaped portion") and N die attach films 424. In this embodiment, the laminate 403 has the same configuration as the laminate 401 rotated 180° around the Z axis.

[0089] Specifically, the laminate 403 includes four plate-shaped portions 414 and four die attach films 424. The plate-shaped portions 414 have a width W1 in the Y-axis direction. Note that the width W1 of each plate-shaped portion 414 may vary within the range of manufacturing error.

[0090] The plate-shaped portion 414 includes a memory chip 414a (an example of a "fourth memory chip"), a CMOS chip 414b (an example of a "second semiconductor chip"), a molded resin 414c (an example of a "resin layer"), and a plurality of electrode pads 414d (an example of a "fourth electrode pad").

[0091] The memory chip 414a, CMOS chip 414b, mold resin 414c, electrode pads 414d, and die attach film 424 are the same as the memory chip 411a, CMOS chip 411b, mold resin 411c, electrode pads 411d, and die attach film 421 in the plate-shaped portion 411, respectively.

[0092] The memory chip 414a is located closer to the end of the plate-shaped portion 414 on the positive side of the Y axis than to the end of the plate-shaped portion 414 on the negative side of the Y axis. Electrode pads 414d, the number of which is equal to the number of board electrodes 26a that form bonding fingers, are provided on the upper surface of the memory chip 414a.

[0093] The electrode pads 414d are located closer to the positive end of the Y axis than to the negative end of the Y axis of the memory chip 414a, and are aligned in a row along the X axis. The electrode pads 414d are electrically connected to the substrate electrodes 26a via bonding wires 81c, respectively.

[0094] The four plate-shaped portions 414 are stacked in the vertical direction on the positive Y-axis direction side of the laminate 401. In detail, the lowest plate-shaped portion 414 is connected to the surface 25a of the wiring board 25 by, for example, a die attach film 424 having a width W1 in the Y-axis direction. The second plate-shaped portion 414 from the bottom is connected to the upper surface of the lowest plate-shaped portion 414 by the die attach film 424. In this way, the four plate-shaped portions 414 are stacked to form the laminate 403.

[0095] The positive Y-axis direction side of the laminate 403 is stepped. The steps have a step surface (terrace surface) SP3 parallel to the XY plane. An electrode pad 414d is located on the step surface SP3.

[0096] Compared to the laminate 402 shown in FIG. 1, the laminate 402 in the semiconductor device 12 further includes three plate-shaped portions 415 (an example of a “fifth plate-shaped portion”) and three die attach films 425.

[0097] Compared to the plate-shaped portion 412 shown in Figure 1, the plate-shaped portion 412 in the semiconductor device 12 further includes a memory chip 412f (an example of a "fifth memory chip"), a CMOS chip 412g, and a plurality of electrode pads 412i (an example of a "fifth electrode pad").

[0098] The plate-like portion 412 is provided across the upper surface of the stack 401 and the upper surface of the stack 403 .

[0099] Die attach film 422 (an example of a "second resin layer") is provided between plate-shaped portion 412 of laminate 402 and laminates 401 and 403. Specifically, the upper surface of die attach film 422 contacts the lower surface of plate-shaped portion 412. The lower surface of die attach film 422 contacts the upper surface of laminate 401 and the upper surface of laminate 403.

[0100] Memory chip 412f in plate-shaped portion 412 has the same configuration as memory chip 412a rotated 180 degrees around the Z axis.

[0101] The memory chip 412f is provided on the positive side of the Y axis of the mold resin 412c. In this embodiment, the memory chip 412f is located closer to the end of the plate-shaped portion 412 on the positive side of the Y axis than to the end of the plate-shaped portion 412 on the negative side of the Y axis, and is connected to the positive side of the Y axis of the mold resin 412c.

[0102] On the upper surface of the memory chip 412f, electrode pads 412i are provided in the same number as the number of substrate electrodes 26b forming bonding fingers.

[0103] The electrode pads 412i are located closer to the positive end of the Y axis than to the negative end of the Y axis of the memory chip 412f, and are aligned in a row along the X axis. The electrode pads 412i are electrically connected to the substrate electrodes 26b via bonding wires 81d, respectively.

[0104] A CMOS chip 412g is attached to the lower surface of the memory chip 412f. The CMOS chip 412g has the same configuration as the CMOS chip 412b rotated 180 degrees around the Z axis.

[0105] In this embodiment, the three plate-shaped portions 415 have the same configuration as the three plate-shaped portions 413 rotated 180° around the Z axis.

[0106] Specifically, the three plate-shaped portions 415 are provided on the positive Y-axis direction side of the three plate-shaped portions 413. The plate-shaped portions 415 have a width W1 in the Y-axis direction. Note that the width W1 of each plate-shaped portion 415 may vary within the range of manufacturing error.

[0107] The plate-shaped portion 415 includes a memory chip 415a (an example of a "sixth memory chip"), a CMOS chip 415b (an example of a "second semiconductor chip"), a molding resin 415c (an example of a "resin layer"), and a plurality of electrode pads 415d (an example of a "sixth electrode pad").

[0108] The memory chip 415a, CMOS chip 415b, mold resin 415c, electrode pads 415d, and die attach film 425 are the same as the memory chip 411a, CMOS chip 411b, mold resin 411c, electrode pads 411d, and die attach film 421 in the plate-shaped portion 411, respectively.

[0109] The memory chip 415a is located closer to the end of the plate-shaped portion 415 on the positive Y-axis side than to the end of the plate-shaped portion 415 on the negative Y-axis side. Electrode pads 415d, the number of which is equal to the number of substrate electrodes 26b forming bonding fingers, are provided on the upper surface of the memory chip 415a.

[0110] The electrode pads 415d are located closer to the positive end of the Y axis than to the negative end of the Y axis of the memory chip 415a, and are aligned in a row along the X axis. The electrode pads 415d are electrically connected to the substrate electrodes 26b via bonding wires 81d, respectively.

[0111] The three plate-shaped portions 415 are stacked in the vertical direction above the plate-shaped portion 412 and on the +Y-axis direction side of the three plate-shaped portions 413. In detail, the lowest plate-shaped portion 415 is connected to the upper surface of the plate-shaped portion 412 by a die attach film 425. The second plate-shaped portion 415 from the bottom is connected to the upper surface of the lowest plate-shaped portion 415 by a die attach film 425. In this way, the three plate-shaped portions 415 are stacked to form the laminate 402.

[0112] The positive Y-axis direction side of the laminate 402 is stepped. The steps have a step surface (terrace surface) SP4 parallel to the XY plane. An electrode pad 412i or 415d is located on the step surface SP4.

[0113] When surface 25a of wiring board 25 is viewed in plan, end 402b of laminate 402 on the positive Y-axis side is located closer to the positive Y-axis side than end 403a of laminate 403 on the positive Y-axis side.

[0114] [Method of manufacturing the semiconductor device 12] In the manufacturing method of the semiconductor device 12, first, as shown in FIG. 17, when the CMOS chip 410b on the negative side of the Y axis and the CMOS chip 410b on the positive side of the Y axis are placed on the silicon wafer 311, they are placed so that the orientation of one is the same as the orientation of the other rotated 180° around the Z axis.

[0115] Specifically, in the CMOS chip 410b on the negative side of the Y axis, the electrode pad 410d is located on the negative side of the Y axis, while in the CMOS chip 410b on the positive side of the Y axis, the electrode pad 410d is located on the positive side of the Y axis.

[0116] Next, the same processes as those shown in FIGS. 6 to 11 are performed.

[0117] Next, as shown in FIG. 18, the silicon wafer 311 is diced along the dicing lines 122X, and the lower surface of the separated silicon wafer 311 is chemically mechanically polished, thereby separating a portion of the silicon wafer 311 into plate-shaped portions 412 (see FIG. 16).

[0118] The separated memory chip 410a on the negative Y-axis side and the memory chip 410a on the positive Y-axis side become memory chips 412a and 412f, respectively.

[0119] The separated CMOS chip 410b on the negative side of the Y axis and the CMOS chip 410b on the positive side of the Y axis become CMOS chips 412b and 412g, respectively.

[0120] The separated electrode pad 410d on the negative Y-axis side and the electrode pad 410d on the positive Y-axis side become electrode pads 412d and 412i, respectively.

[0121] (effect) In this way, the configuration in which plate-like portion 412 of laminate 402 is provided across the upper surface of laminate 401 and the upper surface of laminate 403 can increase the rigidity of wiring board 25 against warpage, thereby suppressing warpage of wiring board 25. Therefore, it is possible to provide a semiconductor device capable of improving quality.

[0122] (First Modification of Semiconductor Device 12) Fig. 19 is a schematic diagram showing a cross section of a first modified example of the semiconductor device according to the second embodiment. As shown in Fig. 19, semiconductor device 12A, which is the first modified example of semiconductor device 12, differs from semiconductor device 12 shown in Fig. 16 in that it further includes a controller chip 63A (an example of a "first semiconductor chip") connected to surface 25a of wiring substrate 25 between stacked body 401 and stacked body 403.

[0123] The controller chip 63A is, for example, flip-chip connected to the wiring board 25 and electrically connected to the wiring board 25. The controller chip 63A controls, for example, the CMOS chips 411b, 412b, 412g, 413b, 414b, and 415b.

[0124] The stepped configuration on the negative Y-axis direction side of stacked body 401 and the positive Y-axis direction side of stacked body 403 forms a space that expands downward between stacked body 401 and stacked body 402. By arranging controller chip 63A in such a space, the space in semiconductor device 12A can be effectively utilized, and the size of semiconductor device 12A can be made compact.

[0125] (Second Modification of Semiconductor Device 12) Fig. 20 is a schematic diagram showing a cross section of a second modified example of the semiconductor device according to the second embodiment. As shown in Fig. 20, semiconductor device 12B, which is the second modified example of semiconductor device 12, differs from semiconductor device 12A shown in Fig. 19 in that plate-shaped portion 412 further includes molding resin 412h (an example of a "third resin layer") connected to the negative Y-axis side of memory chip 412f, and semiconductor layer 451B (an example of a "first semiconductor layer") connected to the positive Y-axis side of molding resin 412c and the negative Y-axis side of molding resin 412h.

[0126] The semiconductor layer 451B includes, for example, silicon. The semiconductor layer 451B is, for example, a spacer. The rigidity of the semiconductor layer 451B is higher than the rigidity of the molding resins 412c and 412h. Note that the semiconductor layer 451B may be formed of a material other than a semiconductor as long as it has high rigidity and does not electrically interfere with other chips.

[0127] In this manner, by providing the semiconductor layer 451B between the memory chip 412a and the CMOS chip 412b and the memory chip 412f and the CMOS chip 412g, it is possible to increase the bending rigidity of the plate-shaped portion 412. This makes it possible to effectively suppress warping of the wiring board 25.

[0128] (Third Modification of Semiconductor Device 12) Fig. 21 is a schematic diagram showing a cross section of a third modified example of the semiconductor device according to the second embodiment. As shown in Fig. 21, a semiconductor device 12C, which is the third modified example of the semiconductor device 12, differs from the semiconductor device 12A shown in Fig. 19 in that it further includes a semiconductor layer 451C (an example of a "first semiconductor layer") provided above a molding resin 412c.

[0129] Semiconductor layer 451C is similar to semiconductor layer 451B. In this modification, the lower surface of semiconductor layer 451C contacts the upper surface of mold resin 412c. This makes it possible to suppress bending deformation of mold resin 412c. In other words, since the bending rigidity of plate-shaped portion 412 can be increased, warping of wiring substrate 25 can be effectively suppressed.

[0130] Note that a configuration may be adopted in which the semiconductor layer 451B shown in FIG. 20 is provided below the semiconductor layer 451C.

[0131] (Fourth Modification of the Semiconductor Device 12) Fig. 22 is a schematic diagram showing a cross section of a fourth modified example of the semiconductor device according to the second embodiment. As shown in Fig. 22, a semiconductor device 12D, which is the fourth modified example of the semiconductor device 12, differs from the semiconductor device 12A shown in Fig. 19 in that it further includes a semiconductor layer 451D (an example of a "first semiconductor layer") provided below the molding resin 412c.

[0132] Semiconductor layer 451D is similar to semiconductor layer 451B. In this modification, the upper surface of semiconductor layer 451D contacts die attach film 422. The lower surface of semiconductor layer 451D is connected to the upper surface of controller chip 63A via, for example, a die attach film (not shown).

[0133] This makes it possible to suppress bending deformation of mold resin 412c. That is, since the bending rigidity of plate-shaped portion 412 can be increased, warping of wiring board 25 can be effectively suppressed.

[0134] Note that at least one of the semiconductor layer 451B (see FIG. 20) and the semiconductor layer 451C (see FIG. 21) may be provided above the semiconductor layer 451D.

[0135] (Fifth Modification of Semiconductor Device 12) Fig. 23 is a schematic diagram showing a cross section of a fifth modified example of the semiconductor device according to Embodiment 2. As shown in Fig. 23, semiconductor device 12E, which is the fifth modified example of semiconductor device 12, differs from semiconductor device 12A shown in Fig. 19 in that the upper surface of controller chip 63E is in contact with die attach film 422.

[0136] 19, semiconductor device 12E includes a controller chip 63E instead of controller chip 63A. The vertical height of controller chip 63E is greater than the vertical height of controller chip 63A. The upper surface of controller chip 63E is aligned with the upper surface of stacked body 401 and the upper surface of stacked body 403.

[0137] This configuration can suppress bending deformation of mold resin 412c. That is, since the bending rigidity of plate-shaped portion 412 can be increased, warping of wiring board 25 can be effectively suppressed.

[0138] (Sixth Modification of the Semiconductor Device 12) Fig. 24 is a schematic diagram showing a cross section of a sixth modified example of the semiconductor device according to the second embodiment. As shown in Fig. 24, a semiconductor device 12F, which is the sixth modified example of the semiconductor device 12, differs from the semiconductor device 12A shown in Fig. 19 in that a plurality of stacked bodies 402 are stacked.

[0139] Compared to the two-tower connection structure 502 in the semiconductor device 12A shown in Figure 19, the two-tower connection structure 502 in the semiconductor device 12F includes stacks 402A, 402B and 402C instead of stack 402, and further includes bonding wires 81c and 81d.

[0140] The laminates 402A, 402B, and 402C are examples of the laminate 402. In this modification, two plate-shaped portions 411 and two plate-shaped portions 414 are laminated in each of the laminates 401 and 403. Note that the laminate 401 may have a configuration in which three or more plate-shaped portions 411 are laminated. In this case, the laminate 403 has the same number of plate-shaped portions 414 laminated as the number of plate-shaped portions 411 in the laminate 401.

[0141] The laminates 402A, 402B, and 402C are stacked in this order from bottom to top. In the laminates 402A, 402B, and 402C, the plate-shaped portions 413 and 415 are stacked on the negative Y-axis side and the positive Y-axis side, respectively, on the upper surface of the plate-shaped portion 412.

[0142] In the laminates 402A, 402B, and 402C, two or more plate-like portions 413 may be stacked on the negative Y-axis direction side on the upper surface of the plate-like portion 412. In this case, the same number of plate-like portions 415 as the number of plate-like portions 413 are stacked on the positive Y-axis direction side.

[0143] Furthermore, the number of plate-shaped portions 413 stacked in laminate 402A, the number of plate-shaped portions 413 stacked in laminate 402B, and the number of plate-shaped portions 413 stacked in laminate 402C may be the same in part or may be different from each other.

[0144] The width of stacked body 402A in the Y-axis direction increases in this order, followed by the width of stacked body 402B in the Y-axis direction and the width of stacked body 402C in the Y-axis direction.

[0145] When surface 25a of wiring board 25 is viewed in a plane, end 402Ca on the Y-axis negative side of laminate 402C, end 402Ba on the Y-axis negative side of laminate 402B, and end 402Aa on the Y-axis negative side of laminate 402A are located closer to the Y-axis negative side than end 402Ba, end 402Aa, and end 401a on the Y-axis negative side of laminate 401, respectively.

[0146] When surface 25a of wiring board 25 is viewed in a plane, end 402Cb on the +Y-axis side of laminate 402C, end 402Bb on the +Y-axis side of laminate 402B, and end 402Ab on the +Y-axis side of laminate 402A are located further toward the +Y-axis side than end 402Bb, end 402Ab, and end 403a on the +Y-axis side of laminate 403, respectively.

[0147] With this configuration, the electrode spacing in the Y-axis direction of the board electrodes 26a to 26d can be increased without increasing the length of the bonding wires 81a to 81d, thereby reducing the density of the board electrodes 26a to 26d.

[0148] (Seventh Modification of Semiconductor Device 12) Fig. 25 is a schematic diagram showing a cross section of a seventh modified example of the semiconductor device according to the second embodiment. As shown in Fig. 25, semiconductor device 12G, which is the seventh modified example of semiconductor device 12, differs from semiconductor device 12 shown in Fig. 16 in that width direction D1 (an example of a "first width direction") in which stacked bodies 401 and 403 are aligned and width direction D2 (an example of a "second width direction") in which plate-like portions 413 and 415 of stacked body 402 are aligned are substantially perpendicular to each other.

[0149] In this modification, the width directions D1 and D2 are approximately parallel to the Y-axis direction and the X-axis direction, respectively.

[0150] On the upper surface of the plate-shaped portion 412, three plate-shaped portions 413 are stacked vertically on the negative side of the X axis (an example of the "fourth side"), and three 415 are stacked vertically on the positive side of the X axis (an example of the "third side").

[0151] A plurality of substrate electrodes 26b forming bonding fingers are provided on the positive X-axis side and the negative X-axis side of the laminate 402.

[0152] The negative X-axis direction side of the laminate 402 is stepped. The steps have a step surface SP2 parallel to the XY plane. An electrode pad 412d or 413d is located on the step surface SP2.

[0153] The positive X-axis direction side of the laminate 402 is stepped. The steps have a step surface SP4 parallel to the XY plane. An electrode pad 412i or 415d is located on the step surface SP4.

[0154] In this modified example, the width direction D1 and the width direction D2 are substantially perpendicular to each other, but the present invention is not limited to this. The angle formed by the width direction D1 and the width direction D2 may be any angle greater than 0° and less than 180°.

[0155] [Third embodiment] A semiconductor device according to a third embodiment will now be described. Fig. 26 is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Fig. 26 can be viewed in the same way as Fig. 1.

[0156] As shown in Figure 26, the semiconductor device 13 differs from the semiconductor device 11 of the first embodiment in that, compared to the semiconductor device 11 shown in Figure 1, the stacked bodies 401 and 402 are arranged below and above, respectively, and two one-tower structures 501 are stacked in the vertical direction to form one tower structure 501A.

[0157] Compared to the semiconductor device 11 shown in FIG. 1, the semiconductor device 13 includes one tower structure 501A instead of the two one tower structures 501.

[0158] One tower structure 501A includes a controller chip 63A, stacked bodies 401L and 401U, and stacked bodies 402L and 402U.

[0159] The laminates 401L and 401U are examples of the laminate 401. In this modification, two plate-shaped portions 411 are stacked in each of the laminates 401L and 401U. Note that the laminates 401L and 401U may each have three or more plate-shaped portions 411 stacked.

[0160] The laminates 402L and 402U are examples of the laminate 402. In this modification, the laminates 402L and 402U have plate-shaped portions 412 and 413 stacked thereon, respectively. Note that the laminates 402L and 402U may each have a configuration in which a plate-shaped portion 412 and a plurality of plate-shaped portions 413 are stacked thereon, respectively.

[0161] The controller chip 63A, stacked bodies 401L, 401U, 402L, and 402U are stacked in this order from bottom to top.

[0162] The positive Y-axis direction sides of the stacked body 401L and the stacked body 402L are stepped, and the negative Y-axis direction sides of the stacked body 401U and the stacked body 402U are stepped.

[0163] When surface 25a of wiring board 25 is viewed in plan, end 402La of laminate 402L on the positive Y-axis side is located further to the positive Y-axis side than end 401La of laminate 401L on the positive Y-axis side.

[0164] When the surface 25a of the wiring board 25 is viewed in plan, the negative Y-axis end 402Ua of the laminate 402U is located closer to the negative Y-axis side than the negative Y-axis end 401Ua of the laminate 401U.

[0165] [Fourth embodiment] A semiconductor device according to a fourth embodiment will now be described. Fig. 27 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Fig. 27 can be viewed in the same way as Fig. 1.

[0166] As shown in Figure 27, the semiconductor device 14 differs from the semiconductor device 11 of the first embodiment in that two stacked bodies 401 facing opposite directions are combined to form a stacked body 404, as compared to the semiconductor device 11 shown in Figure 1.

[0167] Compared to the semiconductor device 11 shown in FIG. 1, the semiconductor device 14 includes a two-tower connected structure 503 instead of the two one-tower structures 501 .

[0168] The two-tower connection structure 503 includes bonding wires 81a, 81b, 81c, and 81d, and stacks 404L and 404U. Hereinafter, each of the stacks 404L and 404U may be referred to as stack 404 (an example of a "fourth stack").

[0169] The laminate 404L includes L (L is an integer greater than or equal to 1) plate-shaped portions 416 (an example of a "sixth plate-shaped portion"), L plate-shaped portions 417 (an example of a "seventh plate-shaped portion"), plate-shaped portion 418 (an example of an "eighth plate-shaped portion"), L die attach films 426, L die attach films 427, and die attach film 428.

[0170] The laminate 404U includes K (K is an integer greater than or equal to 1) plate-shaped portions 416 (an example of a "ninth plate-shaped portion"), K plate-shaped portions 417 (an example of a "tenth plate-shaped portion"), K plate-shaped portions 418 (an example of an "eleventh plate-shaped portion"), K die attach films 426, K die attach films 427, and die attach film 428.

[0171] In this embodiment, each of the laminates 404L and 404U includes three plate-shaped portions 416, three plate-shaped portions 417, a plate-shaped portion 418, three die attach films 426, three die attach films 427, and a die attach film 428.

[0172] The stacked body 404U is stacked above the stacked body 404L. Below, the lower stacked body 404L will be described as a representative example, but the same applies to the upper stacked body 404U.

[0173] Plate-shaped portion 416 has width W1 in the Y-axis direction. Plate-shaped portion 416 includes a memory chip 416a (an example of a "seventh memory chip" and an "eleventh memory chip"), a CMOS chip 416b (an example of a "second semiconductor chip"), a molding resin 416c (an example of a "resin layer"), and a plurality of electrode pads 416d.

[0174] The memory chip 416a, CMOS chip 416b, mold resin 416c, electrode pads 416d, and die attach film 426 are similar to the memory chip 411a, CMOS chip 411b, mold resin 411c, electrode pads 411d, and die attach film 421 in the plate-shaped portion 411, respectively.

[0175] The memory chip 416a is located closer to the end of the plate-shaped portion 416 on the negative Y-axis side than to the end of the plate-shaped portion 416 on the positive Y-axis side. Electrode pads 416d, the number of which is equal to the number of substrate electrodes 26a forming bonding fingers, are provided on the upper surface of the memory chip 416a.

[0176] The electrode pads 416d are located closer to the negative end of the Y axis of the memory chip 416a than to the positive end of the Y axis, and are aligned in a row along the X axis. The electrode pads 416d are electrically connected to the substrate electrodes 26a via bonding wires 81a, respectively.

[0177] The three plate-shaped portions 416 are stacked in the vertical direction above the wiring substrate 25. In detail, the lowest plate-shaped portion 416 is connected to the surface 25a of the wiring substrate 25 by, for example, a die attach film 426 having a width W1 in the Y-axis direction. The second plate-shaped portion 416 from the bottom is connected to the upper surface of the lowest plate-shaped portion 416 by the die attach film 426. In this way, the three plate-shaped portions 416 are stacked.

[0178] The three plate-shaped portions 417 have the same configuration as the three plate-shaped portions 416 rotated 180° around the Z axis.

[0179] The plate-shaped portion 417 includes a memory chip 417a (an example of an "eighth memory chip" and a "twelfth memory chip"), a CMOS chip 417b (an example of a "second semiconductor chip"), a molding resin 417c (an example of a "resin layer"), and a plurality of electrode pads 417d.

[0180] The memory chip 417a, CMOS chip 417b, mold resin 417c, electrode pads 417d, and die attach film 427 are the same as the memory chip 411a, CMOS chip 411b, mold resin 411c, electrode pads 411d, and die attach film 421 in the plate-shaped portion 411, respectively.

[0181] Memory chip 417a is located closer to the end of plate-shaped portion 417 on the positive Y-axis side than to the end of plate-shaped portion 417 on the negative Y-axis side. Electrode pads 417d, the number of which is equal to the number of substrate electrodes 26a forming bonding fingers, are provided on the upper surface of memory chip 417a.

[0182] The electrode pads 417d are located closer to the positive end of the Y axis than to the negative end of the Y axis of the memory chip 417a, and are aligned in a row along the X axis. The electrode pads 417d are electrically connected to the substrate electrodes 26a via bonding wires 81c, respectively.

[0183] The three plate-shaped portions 417 are stacked in the vertical direction on the positive Y-axis direction side of the three plate-shaped portions 416. In detail, the lowest plate-shaped portion 417 is connected to the surface 25a of the wiring board 25 by, for example, a die attach film 427 having a width W1 in the Y-axis direction. The second plate-shaped portion 417 from the bottom is connected to the upper surface of the lowest plate-shaped portion 417 by the die attach film 427. In this way, the three plate-shaped portions 417 are stacked.

[0184] The plate-shaped portion 418 includes memory chips 418a (an example of a "ninth memory chip" and a "thirteenth memory chip") and 418f (an example of a "tenth memory chip" and a "fourteenth memory chip"), a CMOS chip 418b (an example of a "second semiconductor chip"), a molded resin 418c (an example of a "fourth resin layer" and a "fifth resin layer"), and a plurality of electrode pads 418d and 418i.

[0185] Plate-shaped portion 418 has a width W2 and is provided across the upper surface of uppermost plate-shaped portion 416 and the upper surface of uppermost plate-shaped portion 417.

[0186] The die attach film 428 is provided between the plate-shaped portion 418 and the uppermost plate-shaped portion 416 and the uppermost plate-shaped portion 417. Specifically, the upper surface of the die attach film 428 contacts the lower surface of the plate-shaped portion 418. The lower surface of the die attach film 428 contacts the upper surface of the uppermost plate-shaped portion 416 and the upper surface of the uppermost plate-shaped portion 417.

[0187] Memory chip 418a is a memory chip similar to memory chip 412a (see FIG. 1). Memory chip 418a is located closer to the end of plate-shaped portion 418 on the negative Y-axis side than to the end of plate-shaped portion 418 on the positive Y-axis side.

[0188] On the upper surface of the memory chip 418a, electrode pads 418d are provided in the same number as the number of substrate electrodes 26a forming bonding fingers.

[0189] The electrode pads 418d are located closer to the negative end of the Y axis of the memory chip 418a than to the positive end of the Y axis, and are aligned in a row along the X axis. The electrode pads 418d are electrically connected to the substrate electrodes 26a via bonding wires 81a, respectively.

[0190] Mold resin 418c is connected to the +Y-axis side of memory chip 418a. Memory chip 418f is located closer to the +Y-axis side end of plate-shaped portion 418 than to the -Y-axis side end of plate-shaped portion 418, and is connected to the +Y-axis side of mold resin 418c.

[0191] Memory chip 418f has the same configuration as memory chip 418a rotated 180 degrees around the Z axis.

[0192] On the upper surface of the memory chip 418f, electrode pads 418i are provided in the same number as the number of substrate electrodes 26a forming bonding fingers.

[0193] The electrode pads 418i are located closer to the positive end of the Y axis than to the negative end of the Y axis of the memory chip 418f, and are aligned in a row along the X axis. The electrode pads 418i are electrically connected to the substrate electrodes 26a via bonding wires 81c, respectively.

[0194] CMOS chip 418b is a chip in which CMOS chips 412b and 412g (see FIG. 16) are integrated. CMOS chip 418b controls memory chips 418a and 418f. The width of CMOS chip 418b in the Y-axis direction is approximately twice the width of CMOS chip 412b or 412g in the Y-axis direction. Memory chips 418a and 418f are bonded to the bonding surface on the negative Y-axis direction side and the bonding surface on the positive Y-axis direction side of the upper surface of CMOS chip 418b, respectively.

[0195] A molding resin 418c is connected to the upper surface of the CMOS chip 418b excluding the bonding surface, and to the side surfaces of the memory chips 418a and 418f parallel to the ZX plane and the YZ plane.

[0196] A die attach film 428 having a width W2 is provided on the lower surface of the CMOS chip 418b.

[0197] The lowermost plate-shaped portion 416 and the lowermost plate-shaped portion 417 of the laminate 404U are connected to the upper surface of the plate-shaped portion 418 of the laminate 404L by die attach films 426 and 427, respectively.

[0198] The positive Y-axis direction sides of the stacked bodies 404L and 404U are stepped. The negative Y-axis direction sides of the stacked bodies 404L and 404U are stepped.

[0199] When the surface 25a of the wiring board 25 is viewed in a plane, the end 404a on the Y-axis negative side of the lowest plate-shaped portion 416 in the laminate 404U is located closer to the Y-axis negative side than the end 404c on the Y-axis negative side of the plate-shaped portion 418 in the laminate 404L.

[0200] When the surface 25a of the wiring board 25 is viewed in a plane, the end 404b on the positive Y-axis side of the lowest plate-shaped portion 417 in the laminate 404U is located closer to the positive Y-axis side than the end 404d on the positive Y-axis side of the plate-shaped portion 418 in the laminate 404L.

[0201] Although the configuration in which the number of stacked plate-shaped portions 416 in laminate 401L is the same as the number of stacked plate-shaped portions 416 in 401U has been described, the present invention is not limited to this. The number of stacked plate-shaped portions 416 in laminate 401L may be different from the number of stacked plate-shaped portions 416 in 401U.

[0202] Furthermore, plate-shaped portion 418 may have a configuration in which semiconductor layer 451B (see FIG. 20) is provided between memory chip 418a and memory chip 418f.

[0203] [Method of manufacturing semiconductor device 14] In the method for manufacturing the semiconductor device 14, first, as shown in FIG. 28, a plurality of dies of CMOS chips 410b are formed on the upper surface of a silicon wafer 311, aligned along the Y-axis direction.

[0204] For two adjacent CMOS chips 410b in the Y-axis direction, the die of the CMOS chip 410b on the negative Y-axis side (hereinafter sometimes referred to as the CMOS die CDL) is formed to be identical to the die of the CMOS chip 410b on the positive Y-axis side (hereinafter sometimes referred to as the CMOS die CDR) rotated 180 degrees around the Z-axis as the axis of rotation.

[0205] Next, two memory chips 410a are attached to the CMOS dies CDL and CDR, respectively, as shown in Fig. 29. At this time, the orientation of one of the two memory chips 410a is the same as the orientation of the other memory chip rotated 180° around the Z axis.

[0206] Specifically, the memory chip 410a is attached to the CMOS die CDL on the negative side of the Y axis so that the via 72c connected to the electrode pad 410d is located on the negative side of the Y axis. On the other hand, the memory chip 410a is attached to the CMOS die CDR on the positive side of the Y axis so that the via 72c connected to the electrode pad 410d is located on the positive side of the Y axis.

[0207] Next, the same processes as those shown in FIGS. 6 to 11 are performed.

[0208] Next, as shown in FIG. 30, the silicon wafer 311 is diced along the dicing line 132X, and the lower surface of the separated silicon wafer 311 is chemically mechanically polished, thereby separating a portion of the silicon wafer 311 into plate-shaped portions 418 (see FIG. 27).

[0209] The separated memory chip 410a on the negative side of the Y axis and the memory chip 410a on the positive side of the Y axis become memory chips 418a and 418f, respectively.

[0210] The CMOS dies CDL and CDR are separated as a single unit into a CMOS chip 418b.

[0211] The separated electrode pad 410d on the negative Y-axis side and the electrode pad 410d on the positive Y-axis side become electrode pads 418d and 418i, respectively.

[0212] (a) In the embodiment, the plate-shaped portion 411 includes a memory chip 411a, which is a NAND flash memory chip, and a CMOS chip 411b that controls the memory chip 411a. However, the present invention is not limited to this. The plate-shaped portion 411 may include a volatile memory chip such as a DRAM (Dynamic Random Access Memory) instead of the memory chip 411a. Furthermore, the plate-shaped portion 411 may include both a nonvolatile memory chip and a volatile memory chip. The CMOS chip 411b may also be a chip including a CPU (Central Processing Unit) that has calculation and control functions. The same applies to the plate-shaped portions 412 to 418.

[0213] (b) a wiring substrate having a main surface intersecting the vertical direction; a first stack including N first plate-shaped portions each having a first width in a first width direction intersecting the vertical direction, the N first plate-shaped portions being stacked in the vertical direction above the wiring substrate; a second stacked body including a second plate-shaped portion having a second width greater than the first width in the first width direction and provided above the first stacked body, and M third plate-shaped portions provided above the second plate-shaped portion and having the first width in the first width direction, wherein the second plate-shaped portion and the M third plate-shaped portions are stacked in the vertical direction, the first plate-shaped portion includes a first memory chip; the second plate-shaped portion includes a second memory chip and a first resin layer connected to a first side of the second memory chip in the first width direction; the third plate-shaped portion includes a third memory chip, a second side of the first laminate opposite to the first side in the first width direction is stepped, the second side of the second stack is stepped; When the main surface is viewed in plan, an end portion on the second side of the second stacked body is located closer to the second side than an end portion on the second side of the first stacked body. Semiconductor device.

[0214] (c) The semiconductor device further includes a sixth resin layer having a composition different from that of the first resin layer and sealing the first stack and the second stack.

[0215] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Design modifications to these specific examples made by a person skilled in the art as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements of the above-described specific examples, as well as their arrangement, conditions, shape, etc., are not limited to those exemplified and can be modified as appropriate. The elements of the above-described specific examples can be combined in various ways as appropriate, as long as no technical contradictions arise. [Explanation of symbols]

[0216] 11, 12, 12A, 12B, 12C, 12D, 12E, 12F, 12G, 13, 14...Semiconductor device 25...Wiring board 25a...side 26a, 26b, 26c, 26d...Substrate electrode 63A, 63E...Controller chip 65...Sealing resin 81a, 81b, 81c, 81d... Bonding wires 401, 401L, 401U...Laminate 401a, 401La, 401Ua...end 402, 402A, 402B, 402C, 402L, 402U...Laminate 402a, 402b, 402Aa, 402Ab, 402Ba, 402Bb, 402Ca, 402Cb, 402La, 402Ua...end 403...Laminate 403a...end 404, 404U, 404L...Laminate 411, 412, 414, 415, 416, 417, 418...Plate-shaped parts 411a, 412a, 412f, 413a, 414a, 415a, 416a, 417a, 418a, 418f... memory chips 411b, 412b, 412g, 413b, 414b, 415b, 416b, 417b, 418b…CMOS chips 411c, 412c, 412h, 413c, 414c, 415c, 416c, 417c, 418c...Molding resin 411d, 412d, 412i, 413d, 414d, 415d, 416d, 417d, 418d, 418i...Electrode pads 421, 422, 423, 424, 425, 426, 427, 428...Die attach film 451B, 451C, 451D...Semiconductor layer 501, 501A...1 tower structure 502, 503...2-tower linked structure

Claims

1. a wiring substrate having a main surface intersecting the vertical direction; a first stack including N (N is an integer of 2 or more) first plate-shaped portions each having a first width in a first width direction intersecting with the vertical direction, the N first plate-shaped portions being stacked in the vertical direction above the wiring substrate; a second stack including a second plate-shaped portion having a second width greater than the first width in the first width direction and provided above the first stack; and M (M is an integer of 1 or more) third plate-shaped portions provided above the second plate-shaped portion and having the first width in the first width direction, wherein the second plate-shaped portion and M third plate-shaped portions are stacked in the vertical direction; the first plate-shaped portion includes a first memory chip having first electrode pads on an upper surface thereof, the first electrode pads being electrically connected to the wiring board through first bonding wires; the second plate-like portion includes a second memory chip having second electrode pads on an upper surface thereof, the second electrode pads being electrically connected to the wiring board through second bonding wires, and a first resin layer connected to a first side of the second memory chip in the first width direction; the third plate-shaped portion includes a third memory chip having third electrode pads on an upper surface thereof, the third electrode pads being electrically connected to the wiring board through the second bonding wires; a second side of the first stacked body opposite to the first side in the first width direction has a stepped shape with the first electrode pads located on step surfaces; the second side of the second stacked body has a stepped shape in which the second electrode pad or the third electrode pad is located on a step surface, When the main surface is viewed in plan, an end portion on the second side of the second stacked body is located closer to the second side than an end portion on the second side of the first stacked body. Semiconductor device.

2. the second memory chip is located closer to the end of the second plate-shaped portion on the second side than to the end of the second plate-shaped portion on the first side; The semiconductor device according to claim 1 .

3. The semiconductor device includes: a third stacked body including N fourth plate-shaped portions each having the first width in the first width direction, the N fourth plate-shaped portions being stacked in the vertical direction on the first side of the first stacked body; the fourth plate-shaped portion includes a fourth memory chip having fourth electrode pads on an upper surface thereof, the fourth electrode pads being electrically connected to the wiring board through third bonding wires; the first side of the third stacked body has a stepped shape with the fourth electrode pad located on a step surface; The second plate-shaped portion of the second stack is provided across an upper surface of the first stack and an upper surface of the third stack. The semiconductor device according to claim 1 .

4. the second plate-shaped portion further includes a fifth memory chip provided on an upper surface thereof, the fifth electrode pad being electrically connected to the wiring board through a fourth bonding wire, and the fifth memory chip being provided on the first side of the first resin layer; the second stack further includes M fifth plate-shaped portions provided on the first sides of the M third plate-shaped portions and having the first width in the first width direction, The M fifth plate-shaped portions are stacked in the vertical direction, the fifth plate-shaped portion includes a sixth memory chip having sixth electrode pads on an upper surface thereof, the sixth electrode pads being electrically connected to the wiring board through the fourth bonding wires; the first side of the second stacked body has a stepped shape in which the fifth electrode pad or the sixth electrode pad is located on a step surface, When the main surface is viewed in plan, an end portion on the first side of the second stacked body is located closer to the first side than an end portion on the first side of the third stacked body. The semiconductor device according to claim 3 .

5. The semiconductor device includes: a second resin layer in contact with a lower surface of the second plate-shaped portion of the second laminate and in contact with an upper surface of the first laminate and an upper surface of the third laminate; The semiconductor device according to claim 3 .

6. The semiconductor device includes: a first semiconductor chip connected to the main surface of the wiring substrate between the first stack and the third stack; The semiconductor device according to claim 3 .

7. The semiconductor device includes: a second resin layer in contact with a lower surface of the second plate-shaped portion of the second laminate and in contact with an upper surface of the first laminate and an upper surface of the third laminate, an upper surface of the first semiconductor chip contacts the second resin layer; The semiconductor device according to claim 6.

8. the second plate-shaped portion further includes a third resin layer connected to the second side of the fifth memory chip, and a first semiconductor layer connected to the first side of the first resin layer and the second side of the third resin layer. The semiconductor device according to claim 4 .

9. the fifth memory chip in the second plate-shaped portion is connected to the first side of the first resin layer; The semiconductor device includes: Further comprising a first semiconductor layer provided above the first resin layer. The semiconductor device according to claim 4 .

10. the fifth memory chip in the second plate-shaped portion is connected to the first side of the first resin layer; The semiconductor device includes: Further comprising a first semiconductor layer provided below the first resin layer. The semiconductor device according to claim 4 .

11. The semiconductor device includes: a controller chip provided below the first stack and connected to the main surface of the wiring substrate; The semiconductor device according to claim 1 .

12. a wiring substrate having a main surface intersecting the vertical direction; a fourth stack including L (L is an integer of 1 or more) sixth plate-shaped portions and L seventh plate-shaped portions each having a first width in a first width direction intersecting with the vertical direction, and an eighth plate-shaped portion having a second width in the first width direction that is larger than the first width, wherein the L sixth plate-shaped portions are stacked in the vertical direction above the wiring substrate, and the L seventh plate-shaped portions are stacked in the vertical direction on a first side in the first width direction of the L sixth plate-shaped portions, and the eighth plate-shaped portion is provided across an upper surface of the uppermost sixth plate-shaped portion and an upper surface of the uppermost seventh plate-shaped portion, the sixth plate-shaped portion and the seventh plate-shaped portion include a seventh memory chip and an eighth memory chip, respectively; the eighth plate-shaped portion includes a ninth memory chip, a fourth resin layer connected to the first side of the ninth memory chip, and a tenth memory chip provided on the first side of the fourth resin layer, The first side of the fourth stack and a second side opposite to the first side are stepped. Semiconductor device.

13. the eighth plate-shaped portion has an upper surface in contact with a lower surface of the ninth memory chip and a lower surface of the tenth memory chip, and further includes a second semiconductor chip that controls the ninth memory chip and the tenth memory chip. The semiconductor device according to claim 12.

14. a fifth stack including K (K is an integer of 1 or more) ninth plate-shaped portions and K tenth plate-shaped portions each having the first width in the first width direction, and an eleventh plate-shaped portion having the second width in the first width direction, wherein the K ninth plate-shaped portions are stacked in the vertical direction above the L sixth plate-shaped portions, and the K tenth plate-shaped portions are stacked in the vertical direction on the first sides of the K ninth plate-shaped portions, and the eleventh plate-shaped portions are provided across an upper surface of the uppermost ninth plate-shaped portion and an upper surface of the uppermost tenth plate-shaped portion, the ninth plate-shaped portion and the tenth plate-shaped portion include an eleventh memory chip and a twelfth memory chip, respectively; the eleventh plate-shaped portion includes a thirteenth memory chip, a fifth resin layer connected to the first side of the thirteenth memory chip, and a fourteenth memory chip provided on the first side of the fifth resin layer, the first side and the second side of the fifth stack are stepped; The semiconductor device according to claim 12.

15. When the main surface is viewed in a plane, the second-side end of the ninth plate-shaped portion at the lowest level is located closer to the second side than the second-side end of the eighth plate-shaped portion, and the first-side end of the tenth plate-shaped portion at the lowest level is located closer to the first side than the first-side end of the eighth plate-shaped portion. The semiconductor device according to claim 14.

16. a wiring substrate having a main surface intersecting the vertical direction; a first stack including N (N is an integer of 2 or more) first plate-shaped portions each having a first width in a first width direction intersecting with the vertical direction, the N first plate-shaped portions being stacked in the vertical direction above the wiring substrate; a third stacked body including N fourth plate-shaped portions each having the first width in the first width direction, the N fourth plate-shaped portions being stacked in the vertical direction on a first side in the first width direction of the first stacked body; a second stack including: a second plate-shaped portion having a second width greater than the first width in a second width direction intersecting the vertical direction and the first width direction, the second plate-shaped portion being provided across an upper surface of the first stack and an upper surface of the third stack; M (M is an integer of 1 or more) third plate-shaped portions being provided above the second plate-shaped portion and having the first width in the second width direction; and M fifth plate-shaped portions having the first width in the second width direction, the second plate-shaped portion and the M third plate-shaped portions being stacked in the vertical direction, and the M fifth plate-shaped portions being stacked in the vertical direction on a third side in the second width direction of the M third plate-shaped portions, the first plate-shaped portion includes a first memory chip having first electrode pads on an upper surface thereof, the first electrode pads being electrically connected to the wiring board through first bonding wires; the fourth plate-shaped portion includes a fourth memory chip having fourth electrode pads on an upper surface thereof, the fourth electrode pads being electrically connected to the wiring board through third bonding wires; the second plate-like portion includes: a second memory chip having second electrode pads on an upper surface thereof, the second electrode pads being electrically connected to the wiring board through second bonding wires; a first resin layer connected to the third side in the second width direction of the second memory chip; and a fifth memory chip having fifth electrode pads on an upper surface thereof, the fifth electrode pads being electrically connected to the wiring board through fourth bonding wires, the fifth memory chip being provided on the third side of the first resin layer, the third plate-shaped portion includes a third memory chip having third electrode pads on an upper surface thereof, the third electrode pads being electrically connected to the wiring board through the second bonding wires; the fifth plate-shaped portion includes a sixth memory chip having sixth electrode pads on an upper surface thereof, the sixth electrode pads being electrically connected to the wiring board through the fourth bonding wires; a second side of the first stacked body opposite to the first side in the first width direction has a stepped shape with the first electrode pads located on step surfaces; the second side of the third stacked body in the first width direction has a stepped shape with the fourth electrode pads located on step surfaces, a fourth side of the second stacked body, which is opposite to the third side in the second width direction, has a stepped shape in which the second electrode pad or the third electrode pad is located on a step surface; the third side in the second width direction of the second stacked body has a stepped shape in which the fifth electrode pad or the sixth electrode pad is located on a step surface; Semiconductor device.

17. the plate-like portion including any one of the first memory chip to the fourteenth memory chip has an upper surface in contact with a lower surface of the memory chip, and further includes a second semiconductor chip that controls the memory chip; The width of the second semiconductor chip in the width direction is larger than the width of the memory chip in the width direction.

17. The semiconductor device according to claim 1, 3, 4, 12, 14 or 16.

18. a first pad is formed on an upper surface of the second semiconductor chip; a second pad is formed on a lower surface of the memory chip; the memory chip and the second semiconductor chip are bonded together by bonding the first pads and the second pads together; The semiconductor device according to claim 17.

19. the memory chip includes vias extending in the up-down direction and electrically connecting the second pads to the electrode pads provided on the upper surface of the memory chip; 19. The semiconductor device according to claim 18.

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