Semiconductor device and power conversion device

Abstract

To provide a semiconductor device capable of suppressing peeling of a metal wire by suppressing adhesion of solder to a part where the metal wire is bonded in a circuit pattern when the solder for bonding the circuit pattern and a semiconductor element is scattered.SOLUTION: The semiconductor device 202 includes a metal substrate 11 including a metal base 1, an insulating layer 2 provided on an upper surface of the metal base 1, and a circuit pattern 6 provided on an upper surface of the insulating layer 2, a semiconductor element 3 mounted on the circuit pattern 6 by solder bonding, a resin case 7 provided so as to surround the metal substrate 11 in a top view and incorporating a terminal 8 connected to the semiconductor element 3, and a sealing resin 9 filling the resin case 7 and sealing the semiconductor element 3. The circuit pattern 6 includes a wall 12 protruding upward so as to surround the semiconductor element 3 in a top view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which semiconductor chips (corresponding to semiconductor elements) are soldered to a circuit pattern on a base circuit board (corresponding to a metal board), and bonding wires (corresponding to metal wires) are connected between the semiconductor chips or between the semiconductor chips and the circuit pattern. In this semiconductor device, the base circuit board and a case (corresponding to a resin case) are bonded together, and the semiconductor chips, bonding wires, and circuit pattern are sealed with a sealing member (corresponding to a sealing resin). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-132080 Summary of the Invention [Problem to be solved by the invention]

[0004] When soldering a circuit pattern on a base circuit board to a semiconductor chip, a paste solder material made by mixing flux and solid solder is commonly used. The flux evaporates as the temperature rises, removing the oxide film on the circuit pattern and improving wettability between the solder and the circuit pattern. However, when the solder is in a semi-molten state, the viscosity of the solder increases, and the flux is not expelled from the solder placed directly below the semiconductor chip, but remains in the solder as bubbles.

[0005] When the solder is completely melted, the viscosity of the solder decreases and the air bubbles are expelled from the solder to the outside. At this time, the air bubbles pop, causing some of the solder to scatter and adhere to the circuit pattern. When a bonding wire is bonded to a location where solder has adhered, the bonding area between the bonding wire and the circuit pattern becomes smaller, reducing the bonding strength between the two and causing the bonding wire to peel off, which is an issue.

[0006] Therefore, the present disclosure aims to provide a semiconductor device that, when solder joining a circuit pattern and a semiconductor element splatters, prevents the solder from adhering to the location where the metal wire in the circuit pattern is joined, thereby preventing the metal wire from peeling off. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure comprises a metal substrate including a metal base, an insulating layer provided on an upper surface of the metal base, and a circuit pattern provided on an upper surface of the insulating layer, a semiconductor element mounted on the circuit pattern by solder bonding, a resin case that is arranged to surround the metal substrate in a top view and has built-in terminals that are connected to the semiconductor element, and a sealing resin that is filled into the resin case and seals the semiconductor element, and the circuit pattern includes a wall that protrudes upward so as to surround the semiconductor element in a top view. [Effects of the Invention]

[0008] According to the present disclosure, since a wall is provided that protrudes upward so as to surround the semiconductor element in a top view, if solder that joins the circuit pattern and the semiconductor element splashes, the solder is prevented from spilling over the wall and from adhering to the portion of the circuit pattern where the metal wire is joined. This prevents a decrease in the bonding strength between the metal wire and the circuit pattern, and therefore prevents the metal wire from peeling off. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a top view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 10 is a top view of a semiconductor device according to a second embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along line CC in FIG. [Figure 6] FIG. 10 is a top view of a semiconductor device according to a third embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along the line DD in FIG. 6. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 10 is a top view of a semiconductor device according to a fifth embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along the line EE in FIG. 9. [Figure 11] FIG. 13 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a sixth embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiment 1 The first embodiment will be described below with reference to the drawings. Fig. 1 is a top view of a semiconductor device 202 according to the first embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Fig. 3 is a cross-sectional view taken along line BB in Fig. 1. However, sealing resin 9 is not shown in Fig. 1.

[0011] As shown in FIGS. 1 to 3, the semiconductor device 202 includes a metal substrate 11, a plurality of semiconductor elements 3, a resin case 7, and a sealing resin 9.

[0012] The metal substrate 11 includes a metal base 1, an insulating layer 2, and multiple circuit patterns 6. The metal base 1 is a substrate made of a metal such as aluminum or copper, and has a thickness of 1 mm or more and 3 mm or less. The insulating layer 2 is provided on the upper surface of the metal substrate 11. The insulating layer 2 is formed by mixing silica or the like with epoxy resin, and is responsible for providing insulation between the circuit patterns 6 and the metal base 1 and for the heat dissipation properties of the metal substrate 11 itself. The multiple circuit patterns 6 are made of copper or the like and are provided on the upper surface of the insulating layer 2. The multiple circuit patterns 6 include one circuit pattern 6A, three circuit patterns 6B, one circuit pattern 6C, three circuit patterns 6D, and one circuit pattern 6E, on which semiconductor elements 3 are mounted, as well as multiple circuit patterns 6F on which semiconductor elements 3 are not mounted. When there is no need to distinguish between these, they are referred to as "circuit patterns 6."

[0013] The semiconductor elements 3 are mounted on the circuit patterns 6 via solder 4. More specifically, multiple semiconductor elements 3 are mounted on each of the circuit patterns 6A, 6B, and 6E, and one semiconductor element 3 is mounted on each of the circuit patterns 6C and 6D. The solder 4 is a paste solder made by mixing flux and solid solder.

[0014] The semiconductor element 3 includes, for example, an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor element 3 may also include an electrically connected free wheel diode (FWD). The semiconductor element 3 is formed of a semiconductor such as silicon, or a wide band gap semiconductor. The wide band gap semiconductor is silicon carbide, a gallium nitride semiconductor, or diamond.

[0015] The semiconductor elements 3 are connected to each other, the semiconductor elements 3 and the circuit patterns 6 are connected to each other, and the circuit patterns 6 are connected to each other by metal wires 5. The circuit patterns 6 include walls 12 that protrude upward so as to surround the semiconductor elements 3 in a top view. The walls 12 are provided on each of the circuit patterns 6A, 6B, 6C, 6D, and 6E.

[0016] As shown in FIG. 1 , seven semiconductor elements 3 are arranged in circuit pattern 6A. Walls 12 provided in circuit pattern 6A surround an area including the seven semiconductor elements 3 and surrounding areas where metal wires 5 are not joined in top view. Two semiconductor elements 3 are arranged in each circuit pattern 6B. Walls 12 provided in each circuit pattern 6B surround an area including the two semiconductor elements 3 and surrounding areas where metal wires 5 are not joined in top view. One semiconductor element 3 is arranged in circuit pattern 6C. Walls 12 provided in circuit pattern 6C surround an area including one semiconductor element 3 and surrounding areas where metal wires 5 are not joined in top view.

[0017] One semiconductor element 3 is mounted on each circuit pattern 6D. Walls 12 provided on each circuit pattern 6D surround an area including one semiconductor element 3 and surrounding areas to which metal wires 5 are not joined, when viewed from above. Three semiconductor elements 3 are arranged on circuit pattern 6E. Walls 12 provided on circuit pattern 6E surround an area including three semiconductor elements 3 and surrounding areas to which metal wires 5 are not joined, when viewed from above.

[0018] Heat from the semiconductor element 3 is dissipated by the insulating layer 2 and the metal base 1 via the circuit pattern 6. Furthermore, the provision of the wall 12 increases the heat capacity of the circuit pattern 6, improving the heat dissipation performance of the circuit pattern 6.

[0019] 1 to 3, the connection points of the metal wires 5 in the circuit pattern 6 and the mounting points of the semiconductor elements 3 (in other words, the positions where the solder 4 is disposed) are at the same height. The height position of the walls 12 is higher than the height position of the solder 4 and lower than the height position of the apexes of the metal wires 5. The height position of the walls 12 refers to the height position of the upper ends of the walls 12.

[0020] Furthermore, the walls 12 are provided so as to surround one or more semiconductor elements 3 in a top view. Because the height position of the walls 12 is higher than the height position of the solder 4, the walls 12 function to prevent the solder 4 that is scattered when the solder 4 melts from adhering to the connection points of the metal wires 5 in the circuit pattern 6. It has been confirmed through experiments that the height position at which the solder 4 scatters is within 0.5 mm above the height position at which the solder 4 is arranged. Therefore, it is desirable that the height position of the walls 12 be 0.5 mm or more and 1.0 mm or less.

[0021] The circuit pattern 6 is formed from a high heat dissipation material such as copper or aluminum, and has a thickness of 0.03 mm to 1 mm. The surface of the circuit pattern 6 may be made of solid copper or may be plated with nickel or gold. The circuit pattern 6 is manufactured by etching twice. The circuit pattern 6 is formed by the first etching, and the walls 12 are formed by the second etching.

[0022] The metal wire 5 is made of a metal such as copper, aluminum, or gold, and frictional heat is generated between the metal wire 5 and the circuit pattern 6 by ultrasonic vibration or the like, causing the metal wire 5 to melt and bond to the circuit pattern 6.

[0023] The resin case 7 is formed in a rectangular frame shape when viewed from above, and is provided so as to surround the metal substrate 11. The resin case 7 is adhered to the peripheral edge of the metal substrate 11 (more specifically, on the insulating layer 2) with an adhesive 10. The adhesive 10 is an epoxy-based or silicone-based adhesive. The resin case 7 has a plurality of terminals 8 built in. The resin case 7 is made of a thermoplastic resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT). The plurality of terminals 8 are insert-molded into the resin case 7.

[0024] As shown in FIG. 3, one ends of the plurality of terminals 8 are exposed from the resin case 7 at the inner periphery of the resin case 7. A flat surface 8a is formed at one end of the plurality of terminals 8 to be connected to the metal wire 5. The height position of the flat surface 8a of the plurality of terminals 8 is higher than the height position of the circuit pattern 6. The lower surface of the metal base 1 is exposed from the lower surface of the resin case 7. The other ends of the plurality of terminals 8 protrude from the upper surface of the outer periphery of the resin case 7 and are connected to an external device (not shown).

[0025] 2, the sealing resin 9 is filled in the resin case 7 and seals the portion of the metal substrate 11 above the insulating layer 2, the semiconductor element 3, and one end of the terminal 8. The sealing resin 9 is, for example, a gel material such as a silicone resin or a thermosetting resin such as an epoxy resin.

[0026] Next, the operation and effect of the first embodiment will be described with reference to FIGS. 1 to 3. As described above, the solder 4 is a paste solder made by mixing flux and solid solder, and is controlled to a predetermined thickness using a printing mask. The semiconductor element 3 and the circuit pattern 6 are solder-joined by melting the solder 4 using a reflow device or the like and then cooling it. Meanwhile, when the solder 4 is heated, the flux volatilizes, forming bubbles (in other words, voids) within the solder 4 arranged directly below the semiconductor element 3. Because the flux has a lower melting point than the solder 4, bubbles of the solder 4 and the flux are mixed together when the solder 4 is in a semi-molten state.

[0027] Furthermore, when the solder 4 is heated to its melting temperature, multiple bubbles coalesce and the amount of volatilized flux increases, increasing the number of bubbles. This increases the air pressure of the bubbles within the solder 4, causing the bubbles to be expelled from the solder 4 to the outside. At this time, solder 4 particles with a particle size of tens of microns to hundreds of microns may scatter along with the bubbles and adhere to the circuit pattern 6. When a metal wire 5 is bonded to the portion of the circuit pattern 6 where the solder 4 is attached, ultrasonic waves may not be transmitted well between the metal wire 5 and the circuit pattern 6, resulting in a smaller bonding area between the metal wire 5 and the circuit pattern 6. As a result, there is a concern that the bonding strength between the metal wire 5 and the circuit pattern 6 may decrease, causing the metal wire 5 to peel off.

[0028] Furthermore, to reduce the void ratio, which is the ratio of the bonded area to the area occupied by voids after the solder 4 has melted, a vacuum reflow device that promotes the expulsion of air bubbles is used. However, in this case, forcibly expelling the air bubbles in the solder 4 causes a lot of solder 4 to splash, and the solder 4 splashes farther, increasing the probability that the solder 4 will adhere to the circuit pattern 6. As a result, there is concern that the peeling of the metal wire 5 will increase, raising the defect rate.

[0029] In contrast, in the first embodiment, the semiconductor device 202 includes a metal substrate 11 including a metal base 1, an insulating layer 2 provided on the upper surface of the metal base 1, and a circuit pattern 6 provided on the upper surface of the insulating layer 2, a semiconductor element 3 mounted on the circuit pattern 6 by soldering, a resin case 7 that is provided to surround the metal substrate 11 in a top view and that has built-in terminals 8 to be connected to the semiconductor element 3, and a sealing resin 9 that is filled in the resin case 7 and seals the semiconductor element 3. The circuit pattern 6 includes a wall 12 that protrudes upward so as to surround the semiconductor element 3 in a top view.

[0030] Therefore, because the wall 12 is provided so as to protrude upward to surround the semiconductor element 3 in a top view, even if the solder 4 joining the circuit pattern 6 and the semiconductor element 3 splashes, the solder 4 is prevented from spilling over the wall 12 and from adhering to the portion of the circuit pattern 6 where the metal wire 5 is joined. This prevents a decrease in the joining strength between the metal wire 5 and the circuit pattern 6, and therefore prevents the metal wire 5 from peeling off.

[0031] Furthermore, compared to when the wall 12 is not provided on the circuit pattern 6, the heat capacity of the circuit pattern 6 increases, thereby improving the heat dissipation performance of the circuit pattern 6. This eliminates the need to provide a new heat dissipation member, allowing the semiconductor device 202 to be made smaller, thereby reducing the manufacturing cost of the semiconductor device 202.

[0032] Furthermore, since the contact area between the sealing resin 9 and the circuit pattern 6 increases, the adhesion between the sealing resin 9 and the circuit pattern 6 improves, and peeling of the sealing resin 9 between the sealing resin 9 and the circuit pattern 6 can be suppressed.

[0033] Embodiment 2 Next, a second embodiment will be described. Fig. 4 is a top view of a semiconductor device 202 according to the second embodiment. Fig. 5 is a cross-sectional view taken along line CC in Fig. 4. However, Fig. 4 does not show the sealing resin 9. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0034] 4 and 5, in the second embodiment, the semiconductor element 3 (corresponding to the first semiconductor element) through which a large current flows is connected to the terminal 8 (corresponding to the first terminal) by direct lead bonding using the plate-like wiring 13. On the other hand, the semiconductor element 3 (corresponding to the second semiconductor element) through which a small current smaller than the large current flows is connected to the terminal 8 (corresponding to the second terminal) by the metal wire 5. Here, the first semiconductor element is the semiconductor element 3 mounted on the circuit patterns 6A and 6B, and the second semiconductor element is the semiconductor element 3 mounted on the circuit patterns 6C, 6D, and 6E.

[0035] In Figure 4, the semiconductor elements 3 mounted on the circuit patterns 6D and 6E are also connected by plate-like wiring 13, but the semiconductor elements 3 mounted on the circuit patterns 6D and 6E may also be connected by metal wires 5 instead of plate-like wiring 13.

[0036] The plate-like wiring 13 is made of a highly heat-dissipating material such as copper or aluminum. By using the plate-like wiring 13 to connect the semiconductor element 3 that generates a lot of heat, the heat can be dissipated from the plate-like wiring 13. This eliminates the need to provide a new heat dissipation member and allows the semiconductor device 202 to be made smaller, thereby reducing the manufacturing cost of the semiconductor device 202.

[0037] Furthermore, after the semiconductor element 3 is joined to the circuit pattern 6 with the solder 4, the plate-like wiring 13 and the semiconductor element 3, the plate-like wiring 13 and the circuit pattern 6, and the plate-like wiring 13 and the flat surface 8a of the terminal 8 are joined with the solder 4. Furthermore, a wall 14 (corresponding to a second wall) that protrudes upward is provided on the portion of the resin case 7 on the circuit pattern 6 side at the connection point between the terminal 8 and the plate-like wiring 13. The height position of the wall 14 is higher than the height position of the solder 4 arranged directly below the plate-like wiring 13. This prevents the solder 4 from spilling over the wall 14 even if the solder 4 joining the terminal 8 and the plate-like wiring 13 splashes.

[0038] After soldering the plate-like wiring 13, the metal wire 5 is joined. At this time, as with the soldering of the semiconductor element 3 and the circuit pattern 6, the soldering of the plate-like wiring 13 may also cause splattering of the solder 4. The height position of the flat surface 8a of the terminal 8 is higher than the height position of the circuit pattern 6, but the height position of the solder 4 disposed directly below the plate-like wiring 13 joined to the terminal 8 is lower than the height position of the wall 14. Therefore, even if the solder 4 joining the terminal 8 and the plate-like wiring 13 splatters, the solder 4 is prevented from going over the wall 14 and adhering to the portion of the circuit pattern 6 where the metal wire 5 is joined.

[0039] Furthermore, the height position of the wall 12 is higher than the height position of the solder 4 arranged between the first semiconductor element and the plate-like wiring 13. Even if the solder 4 joining the first semiconductor element and the plate-like wiring 13 splashes, the solder 4 is prevented from spilling over the wall 12, and is prevented from adhering to the portion of the circuit pattern 6 where the metal wire 5 is joined. Furthermore, the surface of the semiconductor element 3 to which the metal wire 5 is connected is plated with aluminum, so that even if the solder 4 adheres to the semiconductor element 3, it can be easily removed.

[0040] As described above, in the second embodiment, the semiconductor element 3 includes a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows. The terminal 8 includes a first terminal connected to the first semiconductor element and a second terminal connected to the second semiconductor element. The first semiconductor element is connected to the first terminal by direct lead bonding using the plate-like wiring 13, and the second semiconductor element is connected to the second terminal by the metal wire 5.

[0041] Therefore, even if the solder 4 joining the first semiconductor element and the plate-like wiring 13 splashes, the solder 4 is prevented from going over the wall 12, and the solder 4 is prevented from adhering to the portion of the circuit pattern 6 where the metal wire 5 is joined. This prevents a decrease in the joining strength between the metal wire 5 and the circuit pattern 6, and therefore prevents the metal wire 5 from peeling off.

[0042] Furthermore, a wall 14 is provided on the resin case 7 at the circuit pattern 6 side of the connection portion between the first terminal and the plate-like wiring 13. Therefore, even if the solder 4 joining the terminal 8 and the plate-like wiring 13 splashes, the solder 4 is prevented from spilling over the wall 14, and the solder 4 is prevented from adhering to the portion of the circuit pattern 6 where the metal wire 5 is joined. This prevents a decrease in the joining strength between the metal wire 5 and the circuit pattern 6, and therefore prevents the metal wire 5 from peeling off.

[0043] Furthermore, by using the plate-like wiring 13 when connecting the first semiconductor element, heat can be dissipated from the plate-like wiring 13. This eliminates the need to provide a new heat dissipation member, and allows the semiconductor device 202 to be made smaller, thereby reducing the manufacturing cost of the semiconductor device 202.

[0044] Embodiment 3 Next, a third embodiment will be described. Fig. 6 is a top view of a semiconductor device 202 according to the third embodiment. Fig. 7 is a cross-sectional view taken along line DD in Fig. 6. However, Fig. 6 does not show the resin case 7, terminals 8, and sealing resin 9, and Fig. 7 does not show some of the metal wires 5. Note that in the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0045] As shown in FIGS. 6 and 7 , in the third embodiment, the thickness of the wall 12 surrounding the first semiconductor element is thicker than the thickness of the wall 12 surrounding the second semiconductor element. Specifically, the thickness of the wall 12 surrounding the semiconductor elements 3 mounted on the circuit patterns 6A and 6B is thicker than the thickness of the wall 12 surrounding the semiconductor elements 3 mounted on the circuit patterns 6C, 6D, and 6E. This is because the semiconductor elements 3 mounted on the circuit patterns 6A and 6B generate heat at a higher temperature than the semiconductor elements 3 mounted on the circuit patterns 6C, 6D, and 6E. Therefore, by increasing the thickness of the wall 12 surrounding the semiconductor elements 3 mounted on the circuit patterns 6A and 6B, the heat dissipation performance of the circuit patterns 6A and 6B is improved. Note that the wall 12 of the third embodiment can also be adopted in the second embodiment.

[0046] As described above, in the third embodiment, semiconductor element 3 includes a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows, and wall 12 surrounding first semiconductor element is thicker than wall 12 surrounding second semiconductor element, so that in addition to the effect of the first embodiment, it is possible to further improve the heat dissipation of circuit patterns 6A, 6B on which semiconductor element 3, which generates high heat temperature, is mounted. Since there is no need to provide a new heat dissipation member and semiconductor device 202 can be made smaller, the manufacturing cost of semiconductor device 202 can be reduced.

[0047] Furthermore, since the semiconductor element 3 that generates a large amount of heat has a large difference between high and low temperatures, there is a concern that the sealing resin 9 may peel off due to thermal stress. In contrast, in the third embodiment, the thickness of the wall 12 that surrounds the semiconductor element 3 mounted on the circuit patterns 6A and 6B is increased, thereby increasing the contact area between the sealing resin 9 and the circuit pattern 6 compared to the first embodiment, and thus further improving the adhesion between the sealing resin 9 and the circuit pattern 6. This further reduces peeling of the sealing resin 9 between the sealing resin 9 and the circuit pattern 6.

[0048] Embodiment 4 Next, a fourth embodiment will be described. Fig. 8 is a cross-sectional view of a semiconductor device 202 according to the fourth embodiment. However, Fig. 8 does not show some of the metal wires 5, the resin case 7, the terminals 8, and the sealing resin 9. In the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0049] 8, in the fourth embodiment, the height position of the wall 12 surrounding the first semiconductor element is higher than the height position of the wall 12 surrounding the second semiconductor element. Specifically, the height position of the wall 12 surrounding the semiconductor elements 3 mounted on the circuit patterns 6A and 6B is higher than the height position of the wall 12 surrounding the semiconductor elements 3 mounted on the circuit patterns 6C, 6D, and 6E. This improves the heat dissipation performance of the circuit patterns 6A and 6B. Note that the wall 12 of the fourth embodiment can also be adopted in the second embodiment.

[0050] As described above, in the fourth embodiment, the semiconductor element 3 includes a first semiconductor element through which a large current flows and a second semiconductor element through which a current smaller than the large current flows, and the height position of the wall 12 surrounding the first semiconductor element is higher than the height position of the wall 12 surrounding the second semiconductor element, so that in addition to the effect of the first embodiment, it is possible to further improve the heat dissipation of the circuit patterns 6A, 6B on which the semiconductor element 3, which generates high heat temperature, is mounted. Since there is no need to provide a new heat dissipation member and the semiconductor device 202 can be made smaller, the manufacturing cost of the semiconductor device 202 can be reduced.

[0051] By increasing the height position of the wall 12 surrounding the semiconductor element 3 mounted on the circuit patterns 6A and 6B, the contact area between the sealing resin 9 and the circuit pattern 6 increases compared to the first embodiment, further improving the adhesion between the sealing resin 9 and the circuit pattern 6. This further reduces peeling of the sealing resin 9 between the sealing resin 9 and the circuit pattern 6.

[0052] Embodiment 5 Next, a fifth embodiment will be described. Fig. 9 is a top view of a semiconductor device 202 according to the fifth embodiment. Fig. 10 is a cross-sectional view taken along line EE in Fig. 9. However, some of the metal wires 5, the resin case 7, the terminals 8, and the sealing resin 9 are not shown in Figs. 9 and 10. Note that in the fifth embodiment, the same components as those described in the first to fourth embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0053] In the first to fourth embodiments, the circuit patterns 6A, 6B, 6C, 6D, and 6E are provided with walls 12, but in the fifth embodiment, as shown in Figures 9 and 10, downwardly recessed portions 15 are provided instead of the walls 12. The recessed portions 15 are provided at locations on the circuit patterns 6A, 6B, 6C, 6D, and 6E where the semiconductor element 3 is to be mounted and around those locations. Specifically, the recessed portions 15 are formed to be slightly larger in size than the outline of the semiconductor element 3 when viewed from above.

[0054] The semiconductor elements 3 are mounted in recesses 15 of the circuit pattern 6 via solder 4. Metal wires 5 connect the semiconductor elements 3 to each other, the circuit patterns 6 to each other, and the semiconductor elements 3 and the circuit patterns 6. The connection points of the metal wires 5 on the circuit pattern 6 are located higher than the mounting points of the semiconductor elements 3. Furthermore, all of the connection points of the metal wires 5 on the circuit pattern 6 are at the same height position, and all of the mounting points of the semiconductor elements 3 are also at the same height position.

[0055] The metal wire 5 is looped so as not to come into contact with the circuit pattern 6. Considering the scattering of the solder 4, it is desirable that the recessed portion 15 of the circuit pattern 6 has a recessed depth of 0.5 mm or more and 1.0 mm or less.

[0056] As described above, the contour of the recessed portion 15 in a top view is larger than the contour of the semiconductor element 3 in a top view. This is because, when the solder 4 melts, it spreads, causing the semiconductor element 3 to move in the direction of the solder 4, which may result in rotation of the semiconductor element 3. On the other hand, the semiconductor element 3 can only move within the recessed portion 15. If the gap between the semiconductor element 3 and the recessed portion 15 is 0.2 mm or more and 0.5 mm or less, rotation of the semiconductor element 3 is reduced, preventing poor connection of the metal wire 5. This allows the rotation of the semiconductor element 3 to be controlled by the gap between the semiconductor element 3 and the recessed portion 15, thereby suppressing rotation of the semiconductor element 3. As shown in FIG. 5, a wall 14 may be provided around the flat surface 8a of the terminal 8 in the resin case 7.

[0057] As described above, in the fifth embodiment, the semiconductor device 202 comprises a metal substrate 11 including a metal base 1, an insulating layer 2 provided on the upper surface of the metal base 1, and a circuit pattern 6 provided on the upper surface of the insulating layer 2, a semiconductor element 3 mounted on the circuit pattern 6 by soldering, a resin case 7 that is provided to surround the metal substrate 11 in a top view and that has built-in terminals 8 that are connected to the semiconductor element 3, and a sealing resin 9 that is filled in the resin case 7 and seals the semiconductor element 3. A recess 15 that is recessed downward is provided at the location on the circuit pattern 6 where the semiconductor element 3 is mounted and around the location.

[0058] Therefore, when the solder 4 joining the circuit pattern 6 and the semiconductor element 3 splatters, the solder 4 is prevented from spilling over the wall 12 and from adhering to the portion of the circuit pattern 6 where the metal wire 5 is joined. This prevents a decrease in the joining strength between the metal wire 5 and the circuit pattern 6, and therefore prevents the metal wire 5 from peeling off.

[0059] Furthermore, compared to when the circuit pattern 6 is flat, the heat capacity increases by thickening the portions of the circuit pattern 6 other than the portion where the semiconductor element 3 is mounted, thereby improving the heat dissipation of the circuit pattern 6. This eliminates the need to provide a new heat dissipation member and allows the semiconductor device 202 to be made smaller, thereby reducing the manufacturing cost of the semiconductor device 202.

[0060] Furthermore, since the surface of the circuit pattern 6 is uneven, the contact area between the sealing resin 9 and the circuit pattern 6 increases, improving the adhesion between the sealing resin 9 and the circuit pattern 6. As a result, peeling of the sealing resin 9 between the sealing resin 9 and the circuit pattern 6 can be suppressed.

[0061] Embodiment 6 In this embodiment, the semiconductor device 202 according to the above-described embodiments 1 to 5 is applied to a power conversion device. Although the application of the semiconductor device 202 according to the embodiments 1 to 5 is not limited to a specific power conversion device, a case where the semiconductor device 202 according to the embodiments 1 to 5 is applied to a three-phase inverter will be described below as embodiment 6.

[0062] FIG. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device 200 according to the sixth embodiment is applied.

[0063] The power conversion system shown in Fig. 11 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0064] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 11 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0065] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0066] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown) and freewheeling diodes (not shown). By switching the switching elements, DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit that can be configured with six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheeling diodes of the main conversion circuit 201 is configured with the semiconductor device 202 according to any one of the above-mentioned first to fifth embodiments. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0067] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element, but the drive circuit may be built into the semiconductor device 202, or may be provided separately from the semiconductor device 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0068] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to a drive circuit provided in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0069] In the power conversion device 200 according to this embodiment, the semiconductor device 202 according to any one of the first to fifth embodiments is applied as the switching element and free wheel diode of the main conversion circuit 201, and therefore miniaturization can be achieved.

[0070] In the present embodiment, an example has been described in which the semiconductor device 202 according to the first to fifth embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device 202 according to the first to fifth embodiments is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device 202 according to the first to fifth embodiments may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device 202 according to the first to fifth embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0071] Furthermore, the power conversion device to which the semiconductor device 202 according to any one of the first to fifth embodiments is applied is not limited to the case where the load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0072] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0073] Various aspects of the present disclosure are summarized below as appendices.

[0074] (Appendix 1) a metal substrate including a metal base, an insulating layer provided on an upper surface of the metal base, and a circuit pattern provided on an upper surface of the insulating layer; a semiconductor element mounted on the circuit pattern by soldering; a resin case that is provided to surround the metal substrate in a top view and that has built-in terminals that are connected to the semiconductor element; a sealing resin filled in the resin case and sealing the semiconductor element, The semiconductor device, wherein the circuit pattern includes a wall that protrudes upward so as to surround the semiconductor element in a top view.

[0075] (Appendix 2) The semiconductor elements include a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows, the terminals include a first terminal connected to the first semiconductor element and a second terminal connected to the second semiconductor element; the first semiconductor element is connected to the first terminal by direct lead bonding using a plate-like wiring; 2. The semiconductor device according to claim 1, wherein the second semiconductor element is connected to the second terminal by a metal wire.

[0076] (Appendix 3) 3. The semiconductor device according to claim 2, wherein a second wall is provided at a portion of the resin case on the circuit pattern side at a connection point between the first terminal and the plate-like wiring.

[0077] (Appendix 4) The semiconductor elements include a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows, 4. The semiconductor device according to claim 1, wherein the thickness of the wall surrounding the first semiconductor element is greater than the thickness of the wall surrounding the second semiconductor element.

[0078] (Appendix 5) The semiconductor elements include a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows, 4. The semiconductor device according to claim 1, wherein the wall surrounding the first semiconductor element is higher in height than the wall surrounding the second semiconductor element.

[0079] (Appendix 6) a metal substrate including a metal base, an insulating layer provided on an upper surface of the metal base, and a circuit pattern provided on an upper surface of the insulating layer; a semiconductor element mounted on the circuit pattern by soldering; a resin case that is provided to surround the metal substrate in a top view and that has built-in terminals that are connected to the semiconductor element; a sealing resin filled in the resin case and sealing the semiconductor element, A recessed portion recessed downward is provided at a location on the circuit pattern where the semiconductor element is mounted and around the location.

[0080] (Appendix 7) a main conversion circuit including the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit; A power conversion device comprising: [Explanation of symbols]

[0081] 1 metal base, 2 insulating layer, 3 semiconductor element, 6, 6A, 6B, 6C, 6D, 6E, 6F circuit patterns, 7 resin case, 8 terminal, 11 metal substrate, 12 wall, 13 plate-shaped wiring, 14 wall, 15 recessed portion, 200 power conversion device, 201 main conversion circuit, 202 semiconductor device, 203 control circuit.

Claims

1. a metal substrate including a metal base, an insulating layer provided on an upper surface of the metal base, and a circuit pattern provided on an upper surface of the insulating layer; a semiconductor element mounted on the circuit pattern by soldering; a resin case that is provided to surround the metal substrate in a top view and that has built-in terminals that are connected to the semiconductor element; a sealing resin filled in the resin case and sealing the semiconductor element, The semiconductor device, wherein the circuit pattern includes a wall that protrudes upward so as to surround the semiconductor element in a top view.

2. The semiconductor elements include a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows, the terminals include a first terminal connected to the first semiconductor element and a second terminal connected to the second semiconductor element; the first semiconductor element is connected to the first terminal by direct lead bonding using a plate-like wiring; The semiconductor device according to claim 1 , wherein the second semiconductor element is connected to the second terminal by a metal wire.

3. 3. The semiconductor device according to claim 2, wherein a second wall is provided at a portion of said resin case on said circuit pattern side at a connection point between said first terminal and said plate-like wiring.

4. The semiconductor elements include a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows, The semiconductor device according to claim 1 , wherein the thickness of the wall surrounding the first semiconductor element is greater than the thickness of the wall surrounding the second semiconductor element.

5. The semiconductor elements include a first semiconductor element through which a large current flows and a second semiconductor element through which a small current smaller than the large current flows, The semiconductor device according to claim 1 , wherein the height position of the wall surrounding the first semiconductor element is higher than the height position of the wall surrounding the second semiconductor element.

6. a metal substrate including a metal base, an insulating layer provided on an upper surface of the metal base, and a circuit pattern provided on an upper surface of the insulating layer; a semiconductor element mounted on the circuit pattern by soldering; a resin case that is provided to surround the metal substrate in a top view and that has built-in terminals that are connected to the semiconductor element; a sealing resin filled in the resin case and sealing the semiconductor element, A recessed portion recessed downward is provided at a location on the circuit pattern where the semiconductor element is mounted and around the location.

7. a main conversion circuit including the semiconductor device according to any one of claims 1 to 6, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit; A power conversion device comprising:

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