Driving device for switching element

Abstract

To suppress a surge voltage even when a switching speed is high.SOLUTION: The switching device driving apparatus 10 generates a drive signal S1 based on a control signal S2 that changes between a low level and a high level, and outputs the drive signal S2 to a gate G of the switching device Q2, thereby switching the switching device Q2 on and off. When the switching device Q2 is turned on, the driving device 10 stores the ON delay time from the start of the rise of the control signal S1 to the start of the decrease of the drain-source voltage Vds of the switching device Q2, and sets the period in which the drive signal S2 is at the low level within the period in which the control signal S2 is at the high level based on the ON delay time at the previous turn-on of the drive signal S1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a driving device for a switching element. [Background technology]

[0002] The driving device described in Patent Document 1 drives a switching element. The switching element has a control terminal, a first terminal, and a second terminal. When a voltage is applied to the control terminal, a current flows between the first terminal and the second terminal.

[0003] The drive device includes an active drive unit and a drive control unit. The active drive unit includes two series-connected bodies, each of which has a switch and a resistance element connected in series. The resistance elements of the two series-connected bodies have different resistance values. By switching the switches of the two series-connected bodies between on and off, the resistance element connected to the control terminal of the switching element is switched. This allows the voltage applied to the control terminal of the switching element to be changed.

[0004] When switching the switching element from on to off, the drive control unit controls the switch to switch the resistive element connected to the control terminal when the voltage between the first terminal and the second terminal reaches a predetermined value. This suppresses surge voltage. In this way, active control has been proposed to control the gate voltage during switching transitions. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2022-67980 Summary of the Invention [Problem to be solved by the invention]

[0006] There is a time delay between when a drive signal is applied to the control terminal of a switching element and when the switching element actually turns on. The same applies when turning it off. This time delay varies depending on the load voltage, load current, temperature, and variations in the element itself. Therefore, in active control, feedback control is desirable, which detects the start of switching element operation and controls the gate voltage. However, when the switching speed of switching elements such as SiC and GaN, which have recently become practical, is fast, the feedback may not be able to keep up and surge voltage may not be suppressed. [Means for solving the problem]

[0007] A switching element driver that solves the above problem generates a drive signal based on a control signal that changes between low and high levels for a switching element having a first terminal, a second terminal, and a control terminal, and outputs the drive signal to the control terminal to switch the switching element on and off. The driver performs at least one of the following: a turn-on process that, when turning on the switching element, stores an on-delay time from when the control signal starts rising to when the voltage between the first terminal and the second terminal starts to drop, and sets a period during which the drive signal is at a low level within a period during which the control signal is at a high level based on the on-delay time of the drive signal when the switching element was last turned on; and a turn-off process that, when turning off the switching element, stores an off-delay time from when the control signal starts falling to when the voltage between the first terminal and the second terminal starts to rise, and sets a period during which the drive signal is at a high level within a period during which the control signal is at a low level based on the off-delay time of the drive signal when the switching element was last turned off.

[0008] The switching element turns on when the drive signal goes high, and turns off when the drive signal goes low. There is a delay between when the control signal starts to rise and when the voltage between the first and second terminals of the switching element starts to drop. This time is the on delay time. There is a delay between when the control signal starts to fall and when the voltage between the first and second terminals of the switching element starts to rise. This time is the off delay time.

[0009] During the turn-on process, the period during which the drive signal is at a low level is set within the period during which the control signal is at a high level based on the on-delay time of the previous turn-on. By setting the period during which the drive signal is at a low level using the on-delay time of the previous turn-on, it is not necessary to set the drive signal to a low level after detecting the turn-on of the switching element. This makes it possible to suppress surge voltages at turn-on even when the switching speed is fast.

[0010] In the turn-off process, the period during which the drive signal is at a high level is set within the period during which the control signal is at a low level based on the off delay time from the previous turn-off. By setting the period during which the drive signal is at a high level using the off delay time from the previous turn-off, it is not necessary to set the drive signal to a high level after detecting the turn-off of the switching element. This makes it possible to suppress surge voltages at turn-off even when the switching speed is fast.

[0011] The driving device for the switching element may include a turn-on processing circuit that performs the turn-on processing, and a timing control unit, wherein the turn-on processing circuit includes a turn-on detection unit that detects the start of a drop in voltage between the first terminal and the second terminal, an on-delay time memory that stores the on-delay time, a turn-on delay unit configured to be able to read the on-delay time from the on-delay time memory, a turn-on one-shot unit that sets a period during which the drive signal is at a low level within a period during which the control signal is at a high level, and the on-delay time memory includes a first on-delay time memory and a second on-delay time memory, and the timing control unit may store the on-delay time in one of the first on-delay time memory and the second on-delay time memory at the time of turning on, and cause the turn-on delay unit to read the on-delay time from the other memory, and may switch between the first on-delay time memory and the second on-delay time memory in which the on-delay time is stored each time the switching element is turned on.

[0012] In the driving device for the switching element, the turn-on delay unit may correct the on delay time read from the on delay time memory according to a response delay time until the turn-on detection unit detects the start of a voltage drop between the first terminal and the second terminal.

[0013] The driving device for the switching element may include a turn-off processing circuit that performs the turn-off processing, and a timing control unit, wherein the turn-off processing circuit includes a turn-off detection unit that detects a start of a rise in voltage between the first terminal and the second terminal, an off delay time memory that stores the off delay time, a turn-off delay unit configured to be able to read the off delay time from the off delay time memory, and a turn-off one-shot unit that sets a period during which the drive signal is at a high level within a period during which the control signal is at a low level, wherein the off delay time memory includes a first off delay time memory and a second off delay time memory, and the timing control unit may store the off delay time in one of the first off delay time memory and the second off delay time memory at the time of turning off, and cause the turn-off delay unit to read the off delay time from the other memory, and may switch between the first off delay time memory and the second off delay time memory in which the off delay time is stored each time the switching element is turned off.

[0014] In the driving device for the switching element, the turn-off delay unit may correct the off delay time read from the off delay time memory according to a response delay time until the turn-off detection unit detects the start of a rise in voltage between the first terminal and the second terminal. [Effects of the Invention]

[0015] According to the present invention, surge voltages can be suppressed even when the switching speed is high. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing the configuration of a driving device for a switching element. [Figure 2] FIG. 2 is a time chart showing the relationship between time and voltage. DETAILED DESCRIPTION OF THE INVENTION

[0017] An embodiment of a driving device for a switching element will be described. As shown in FIG. 1, the power conversion device PC includes a high-side switching element Q1 and a low-side switching element Q2. A load (not shown) or the like is connected to the connection point between the switching element Q1 and the switching element Q2. The power conversion device PC converts input power and outputs the converted power to the load. The switching elements Q1 and Q2 are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The switching elements Q1 and Q2 may be made of, for example, a silicon carbide compound semiconductor (SiC) or a gallium nitride compound semiconductor (GaN). The switching element Q2 includes a gate G, a drain D, and a source S. The gate G is an example of a control terminal. The drain D is an example of a first terminal. The source S is an example of a second terminal. The switching elements Q1 and Q2 may be switching elements other than MOSFETs, such as insulated gate bipolar transistors.

[0018] The power conversion device PC includes a switching element driver 10. The switching element driver 10 switches on and off switching elements Q1 and Q2. As an example, the switching element driver 10 provided for switching element Q2 will be described, but a similar switching element driver 10 is also provided for switching element Q1.

[0019] The switching element driving device 10 includes a driver 11. The driver 11 includes, for example, a driver control circuit 12 and two transistors 13 and 14 connected in series. One of the terminals of the transistor 13, other than the terminal connected to the transistor 14, is connected to a control power supply. A control signal S1 is input to the driver control circuit 12. The control signal S1 is, for example, a signal determined by comparing a voltage command with a carrier signal. The control signal S1 is, for example, output from an IC. The control signal S1 is a pulse signal that changes between low and high levels. The rise of the control signal S1 occurs when the control signal S1 changes from low to high. The fall of the control signal S1 occurs when the control signal S1 changes from high to low.

[0020] The driver 11 generates a drive signal S2 based on the control signal S1 and outputs the drive signal S2 to the gate G of the switching element Q2. The drive signal S2 is a signal that switches the switching element Q2 between on and off. The drive signal S2 is a pulse signal that changes between low and high levels. When the drive signal S2 changes from low to high, it is called a rising edge of the drive signal S2. When the drive signal S2 changes from high to low, it is called a falling edge of the drive signal S2.

[0021] The driver control circuit 12 controls the transistors 13 and 14 in response to a control signal S1 and the output of a turn-on one-shot unit 25 or a turn-off one-shot unit 35, which will be described later. When the transistor 13 is turned on and the transistor 14 is turned off, a high-level drive signal S2 is output from the driver 11. This causes the voltage from the control power supply to turn on the switching element Q2. When the transistor 13 is turned off and the transistor 14 is turned on, a low-level drive signal S2 is output from the driver 11. This causes the voltage at the gate G to flow to the source S through a second connection line L2, which will be described later, thereby turning off the switching element Q2. When the drive signal S2 is high, the switching element Q2 turns on, and when the drive signal S2 is low, the switching element Q2 turns off.

[0022] The switching element driver 10 includes a first connection line L1 that connects the connection point of two transistors 13, 14 to the gate G, and a second connection line L2 that connects the transistor 14 to the source S. A drive signal S2 is applied to the gate G via the first connection line L1. The second connection line L2 connects the source S to a terminal of the transistor 14 that is different from the terminal connected to the transistor 13.

[0023] The switching element driver 10 includes a gate resistor R1, a resistive element R2, and a capacitor C. The gate resistor R1 is provided on the first connection line L1. The resistive element R2 and the capacitor C connect the first connection line L1 and the second connection line L2 on the gate G side of the gate resistor R1.

[0024] <Turn-on processing circuit> The switching element driver 10 includes a turn-on processing circuit 20. The turn-on processing circuit 20 performs turn-on processing. The turn-on processing is a process that performs active control when the switching element Q2 is turned on. The active control is a control that suppresses surge voltage by switching the drive signal S2 between high and low levels. The active control performed at turn-on is a control that sets the period during which the drive signal S2 is at low level within the period during which the control signal S1 is at high level.

[0025] The turn-on processing circuit 20 includes a turn-on detection unit 21 that detects the turn-on of the switching element Q2. The turn-on detection unit 21 detects the turn-on by comparing the drain-source voltage Vds with an ON threshold. When the drive signal S2 goes high, the gate-source voltage Vgs increases. When the gate-source voltage Vgs reaches a predetermined value or higher, the switching element Q2 turns on. When the switching element Q2 turns on, the drain-source voltage Vds decreases. Therefore, the turn-on can be detected by determining whether the drain-source voltage Vds has become less than the ON threshold.

[0026] The on-threshold is a predetermined value. The on-threshold is set so that the start of a drop in the drain-source voltage Vds can be detected. The start of the drop in the drain-source voltage Vds refers to the time when the drain-source voltage Vds starts to drop but before the drain-source voltage Vds has completely dropped. By setting the on-threshold in this manner, the turn-on detection unit 21 detects the start of a drop in the drain-source voltage Vds. The drain-source voltage Vds is an example of the voltage between the first terminal and the second terminal.

[0027] The turn-on detection unit 21 includes, for example, a comparator. The drain-source voltage Vds and an ON threshold are input to the comparator. When the drain-source voltage Vds is equal to or greater than the ON threshold, the comparator outputs a low-level signal. When the drain-source voltage Vds is less than the ON threshold, the comparator outputs a high-level signal. Note that a rise occurs when the output of the turn-on detection unit 21 changes from low level to high level.

[0028] The turn-on processing circuit 20 includes on-delay time memories 22 and 23. The on-delay time memories 22 and 23 include a first on-delay time memory 22 and a second on-delay time memory 23. The control signal S1 and the output of the turn-on detection unit 21 are input to the on-delay time memories 22 and 23. The on-delay time memories 22 and 23 store the time from the rising edge of the control signal S1 to the rising edge of the output of the turn-on detection unit 21 as the on-delay time of the switching element Q2. The on-delay time is the time from the start of the rising edge of the control signal S1 to the start of the decrease in the drain-source voltage Vds. In the switching element Q2, a transition period exists from the time when the drive signal S2 rises in response to the rising edge of the control signal S1 until the time when the drain-source voltage Vds begins to decrease, i.e., until the drain-source voltage Vds becomes less than the on-threshold value. This transition period is the on-delay time.

[0029] The on-delay time memories 22 and 23 are, for example, integrating circuits using capacitors. When a constant current flows through the capacitor during the time from the rising edge of the control signal S1 to the rising edge of the output of the turn-on detection unit 21, a charge corresponding to the on-delay time is stored in the capacitor. Therefore, the on-delay time memories 22 and 23 can store the on-delay time as a capacitor voltage.

[0030] The turn-on processing circuit 20 includes a turn-on delay unit 24. The turn-on delay unit 24 receives the control signal S1 and reads the on delay time from the on delay time memories 22 and 23. For example, the turn-on delay unit 24 reads the on delay time by generating a current corresponding to the voltage of the capacitor in the on delay time memories 22 and 23. The turn-on delay unit 24 may correct the on delay time read from the on delay time memories 22 and 23 according to a response delay time until the turn-on detection unit 21 detects the start of a drop in the drain-source voltage Vds. For example, the turn-on delay unit 24 may perform the correction by subtracting the response delay time from the on delay time read from the on delay time memories 22 and 23. The response delay time may be determined in advance through experiments or simulations. The turn-on delay unit 24 outputs the timing at which the on delay time elapses after the control signal S1 rises.

[0031] The turn-on processing circuit 20 includes a turn-on one-shot unit 25. The turn-on one-shot unit 25 outputs a negative pulse to the driver control circuit 12 at the timing output from the turn-on delay unit 24. The negative pulse is applied to the control signal S1 to control the transistors 13 and 14 so that the drive signal S2 output from the driver 11 goes low. While the negative pulse is being input from the turn-on one-shot unit 25, the driver control circuit 12 controls the transistors 13 and 14 so that the driver 11 outputs a low-level drive signal S2 even when the control signal S1 is high. In this way, the turn-on one-shot unit 25 sets the period during which the drive signal S2 goes low to within the period during which the control signal S1 is high. The width of the negative pulse may be constant or variable. To make the width of the negative pulse variable, the width of the negative pulse may be changed depending on the load state, for example.

[0032] The switching element driver 10 includes a timing control unit 40. The timing control unit 40 controls the switching element driver 10. When turning on, the timing control unit 40 stores an on delay time in one of the first on delay time memory 22 and the second on delay time memory 23, and causes the turn-on delay unit 24 to read the on delay time from the other memory.

[0033] One control cycle is defined as the time from when the control signal S1 rises to high level, to when it goes to low level, and to when it rises to high level again. The timing control unit 40 alternately switches between the on delay time memories 22, 23 that store the on delay time and the on delay time memories 22, 23 that cause the turn-on delay unit 24 to read the on delay time. That is, the timing control unit 40 switches between the first on delay time memory 22 and the second on delay time memory 23 to store the on delay time each time the device is turned on. As a result, the on delay time from the first on delay time memory 22 or the second on delay time memory 23 that is read into the turn-on delay unit 24 is also switched each time the device is turned on.

[0034] During a control cycle in which an ON delay time is stored in the first ON delay time memory 22, the timing control unit 40 causes the turn-on delay unit 24 to read the ON delay time from the second ON delay time memory 23. During a control cycle in which an ON delay time is stored in the second ON delay time memory 23, the timing control unit 40 causes the turn-on delay unit 24 to read the ON delay time from the first ON delay time memory 22. Thus, at turn-on, the ON delay time stored in the ON delay time memories 22 and 23 at the previous turn-on is read into the turn-on delay unit 24. Therefore, the timing at which the turn-on one-shot unit 25 outputs a negative pulse is set based on the ON delay time at the previous turn-on of the switching element Q2. The turn-on detection unit 21, the first ON delay time memory 22, and the second ON delay time memory 23 are reset, for example, after a predetermined time has elapsed or by a predetermined signal from the control signal S1 or the drive signal S2.

[0035] As described above, the turn-on process is a process in which, when the switching element Q2 is turned on, the on delay time is stored and the period during which the drive signal S2 is at a low level is set within the period during which the control signal S1 is at a high level based on the on delay time when the switching element Q2 was last turned on.

[0036] <Turn-off processing circuit> The switching element driver 10 includes a turn-off processing circuit 30. The turn-off processing circuit 30 performs turn-off processing. The turn-off processing is processing that performs active control when the switching element Q2 is turned off. The active control performed when the switching element Q2 is turned off is control that sets the period during which the drive signal S2 is at a high level within the period during which the control signal S1 is at a low level.

[0037] The turn-off processing circuit 30 includes a turn-off detection unit 31 that detects the turn-off of the switching element Q2. The turn-off detection unit 31 detects the turn-off by comparing the drain-source voltage Vds with an off threshold. When the drive signal S2 goes low, the gate-source voltage Vgs decreases. When the gate-source voltage Vgs falls below a predetermined value, the switching element Q2 turns off. When the switching element Q2 turns off, the drain-source voltage Vds increases. Therefore, the turn-off can be detected by determining whether the drain-source voltage Vds is equal to or greater than the off threshold.

[0038] The off-threshold is a predetermined value. The off-threshold is set so that the start of the rise in the drain-source voltage Vds can be detected. The start of the rise in the drain-source voltage Vds refers to the time when the drain-source voltage Vds starts to rise but before it reaches its maximum. By setting the off-threshold in this way, the turn-off detection unit 31 detects the start of the rise in the drain-source voltage Vds.

[0039] The turn-off detection unit 31 includes, for example, a comparator. The drain-source voltage Vds and an off threshold are input to the comparator. When the drain-source voltage Vds is equal to or greater than the off threshold, the comparator outputs a high-level signal. When the drain-source voltage Vds is less than the off threshold, the comparator outputs a low-level signal. Note that a rise occurs when the output of the turn-off detection unit 31 changes from low to high.

[0040] The turn-off processing circuit 30 includes off delay time memories 32 and 33. The off delay time memories 32 and 33 include a first off delay time memory 32 and a second off delay time memory 33. The control signal S1 and the output of the turn-off detection unit 31 are input to the off delay time memories 32 and 33. The off delay time memories 32 and 33 store the time from the falling edge of the control signal S1 to the rising edge of the output of the turn-off detection unit 31 as the off delay time of the switching element Q2. The off delay time is the time from the start of the falling edge of the control signal S1 to the start of the rise of the drain-source voltage Vds. In the switching element Q2, there is a transition period from the time when the drive signal S2 falls in response to the falling edge of the control signal S1 until the drain-source voltage Vds starts to rise, i.e., until the drain-source voltage Vds reaches or exceeds the off threshold. This transition period is the off delay time.

[0041] The off-delay time memories 32 and 33 are, for example, integrating circuits using capacitors. When a constant current flows through the capacitor during the period from the falling edge of the control signal S1 to the rising edge of the output of the turn-off detection unit 31, a charge corresponding to the off-delay time is stored in the capacitor. Therefore, the off-delay time memories 32 and 33 can store the off-delay time as a capacitor voltage.

[0042] The turn-off processing circuit 30 includes a turn-off delay unit 34. The turn-off delay unit 34 receives the control signal S1 and reads the off delay time from the off delay time memories 32 and 33. For example, the turn-off delay unit 34 reads the off delay time by generating a current corresponding to the voltage of the capacitor in the off delay time memories 32 and 33. The turn-off delay unit 34 may correct the off delay time read from the off delay time memories 32 and 33 according to a response delay time until the turn-off detection unit 31 detects the start of the rise in the drain-source voltage Vds. For example, the turn-off delay unit 34 may perform the correction by subtracting the response delay time from the off delay time read from the off delay time memories 32 and 33. The response delay time may be determined in advance through experiments or simulations. The turn-off delay unit 34 outputs the timing at which the off delay period elapses after the control signal S1 falls.

[0043] The turn-off processing circuit 30 includes a turn-off one-shot unit 35. The turn-off one-shot unit 35 outputs a positive pulse to the driver control circuit 12 at the timing output from the turn-off delay unit 34. The positive pulse is applied to the control signal S1 to control the transistors 13 and 14 so that the drive signal S2 output from the driver 11 goes high. While the positive pulse is being input from the turn-off one-shot unit 35, the driver control circuit 12 controls the transistors 13 and 14 so that the driver 11 outputs a high-level drive signal S2 even when the control signal S1 is low. In this way, the turn-off one-shot unit 35 sets the period during which the drive signal S2 goes high to within the period during which the control signal S1 is low. The width of the positive pulse may be constant or variable. To make the width of the positive pulse variable, the width of the positive pulse may be changed depending on the load state, for example.

[0044] At the time of turn-off, the timing control section 40 stores the OFF delay time in one of the first OFF delay time memory 32 and the second OFF delay time memory 33, and causes the turn-off delay section 34 to read the OFF delay time from the other memory.

[0045] The timing control section 40 alternately switches between the OFF delay time memories 32, 33 that store the OFF delay time and the OFF delay time memories 32, 33 that cause the turn-off delay section 34 to read the OFF delay time. That is, the timing control section 40 switches whether the OFF delay time is stored in the first OFF delay time memory 32 or the second OFF delay time memory 33 at each turn-off. As a result, at each turn-off, the OFF delay time is also switched from the first OFF delay time memory 32 or the second OFF delay time memory 33 to be read into the turn-off delay section 34.

[0046] During a control cycle in which an OFF delay time is stored in the first OFF delay time memory 32, the timing control unit 40 causes the turn-off delay unit 34 to read the OFF delay time from the second OFF delay time memory 33. During a control cycle in which an OFF delay time is stored in the second OFF delay time memory 33, the timing control unit 40 causes the turn-off delay unit 34 to read the OFF delay time from the first OFF delay time memory 32. Thus, at turn-off, the OFF delay time stored in the OFF delay time memories 32 and 33 at the time of the previous turn-off is read into the turn-off delay unit 34. Therefore, the timing at which the turn-off one-shot unit 35 outputs a positive pulse is set based on the OFF delay time at the previous turn-off of the switching element Q2. The turn-off detection unit 31, the first OFF delay time memory 32, and the second OFF delay time memory 33 are reset, for example, after a predetermined time has elapsed or by a predetermined signal from the control signal S1 or the drive signal S2.

[0047] As described above, the turn-off process is a process in which, when the switching element Q2 is turned off, the off delay time is stored and the period during which the drive signal S2 is at a high level is set within the period during which the control signal S1 is at a low level based on the off delay time when the switching element Q2 was previously turned off.

[0048] [Operation of this embodiment] The operation of this embodiment will be described below. As an example, a case will be described in which active control is not performed in the first control cycle, but is performed in the second and subsequent control cycles.

[0049] As shown in FIG. 2, when the first control cycle begins at time T11, the control signal S1 rises to high level. Accordingly, when the drive signal S2 rises to high level, the gate-source voltage Vgs increases. When the drain-source voltage Vds reaches the on threshold at time T12, the output of the turn-on detection unit 21 rises to high level at time T13. The first on-delay time memory 22 stores the on-delay time T1 from time T11 to time T13 as the capacitor voltage V1 of the integrating circuit. The time from time T12 to time T13 is the response delay time T7 of the turn-on detection unit 21. The response delay time T7 is the time required for the turn-on detection unit 21 to detect the start of a drop in the drain-source voltage Vds.

[0050] When the control signal S1 falls to low level at time T14, the drive signal S2 goes low. Accordingly, the gate-source voltage Vgs decreases. When the drain-source voltage Vds reaches the off threshold at time T15, the output of the turn-off detection unit 31 goes high at time T16. The first off delay time memory 32 stores the off delay time T3 from time T14 to time T16 as the capacitor voltage V3 of the integrating circuit. The time from time T15 to time T16 is the response delay time T8 of the turn-off detection unit 31. The response delay time T8 is the time required for the turn-off detection unit 31 to detect the start of the rise in the drain-source voltage Vds.

[0051] At time T17, the second control cycle begins, and the control signal S1 rises to a high level. This causes the drive signal S2 to rise to a high level, increasing the gate-source voltage Vgs. The turn-on delay unit 24 reads the on-delay time T1 stored in the first on-delay time memory 22 during the first control cycle. The on-delay time T1 is the on-delay time during the previous turn-on. The turn-on one-shot unit 25 outputs a negative pulse to the driver 11 at time T18, after the on-delay time T1' has elapsed since time T17. This allows the period during which the drive signal S2 is at a low level to be set within the period during which the control signal S1 is at a high level. The drive signal S2 is at a low level from time T18 to time T20. The on-delay time T1' may be the same as the on-delay time T1, or may be the on-delay time T1 minus the response delay time T7.

[0052] Time T18 coincides with the time when the drain-source voltage Vds reaches the ON threshold. This is because the load state fluctuates little between adjacent control cycles, so the time the control signal S1 is maintained at a high level is the same or nearly the same. Therefore, based on the ON delay time T1 from the previous turn-on, it is possible to estimate the time when the drain-source voltage Vds reaches the ON threshold during this turn-on. At this time, the drive signal S2 can be set to a low level.

[0053] At time T19, the output of the turn-on detection unit 21 goes high. The second on-delay time memory 23 stores the on-delay time T2 from time T17 to time T19 as the capacitor voltage V2 of the integrating circuit.

[0054] When the control signal S1 falls to low level at time T21, the drive signal S2 goes low. Accordingly, the gate-source voltage Vgs decreases. The turn-off delay unit 34 reads the off delay time T3 stored in the first off delay time memory 32 during the first control cycle. The off delay time T3 is the off delay time at the previous turn-off. The turn-off one-shot unit 35 outputs a positive pulse to the driver 11 at time T23, which is the off delay time T3' after time T21. This allows the period during which the drive signal S2 is high to be set within the period during which the control signal S1 is low. The drive signal S2 is high from time T23 to time T25. The off delay time T3' may be the same as the off delay time T3, or may be the off delay time T3 minus the response delay time T8.

[0055] There is a small difference between time T23 and time T22 when the drain-source voltage Vds reaches the off threshold. In this way, time T23 when the drive signal S2 reaches high level and time T22 may not coincide, but the time from when the drain-source voltage Vds reaches the off threshold until when the drive signal S2 reaches high level can be shortened compared to when the turn-off detection unit 31 detects turn-off and then turns the drive signal S2 to high level.

[0056] At time T24, the output of the turn-off detection unit 31 goes high. The second off delay time memory 33 stores the off delay time T4 from time T21 to time T24 as the capacitor voltage V4 of the integrating circuit.

[0057] In the third control cycle, the same control as in the second control cycle is performed. At the third turn-on, a period during which the drive signal S2 is at a low level is set within the period during which the control signal S1 is at a high level. The drive signal S2 becomes low after an on delay time T2' has elapsed from time T26 when the control signal S1 rises. The on delay time T2' may be the same as the on delay time T2, or may be the on delay time T2 minus the response delay time T7. The on delay time T2 is the on delay time during the second control cycle, i.e., the previous turn-on.

[0058] At time T27, the output of the turn-on detection unit 21 goes high. The first on-delay time memory 22 stores the on-delay time T5 from time T26 to time T27 as the capacitor voltage V5 of the integrating circuit. This on-delay time T5 is used the next time the switch is turned on.

[0059] At the third turn-off, a period during which the drive signal S2 is at a high level is set within the period during which the control signal S1 is at a low level. The drive signal S2 becomes high after an off delay time T4' has elapsed from time T28 when the control signal S1 falls. The off delay time T4' may be the same as the off delay time T4, or may be the off delay time T4 minus the response delay time T8. The off delay time T4 is the second control cycle, i.e., the off delay time at the previous turn-off.

[0060] At time T29, the output of turn-off detection circuit 31 goes high. First off delay time memory 32 stores off delay time T6 from time T28 to time T29 as capacitor voltage V6 of the integrating circuit. This off delay time T6 is used at the next turn-off.

[0061] [Effects of this embodiment] (1) The switching element driver 10 performs a turn-on process. During the turn-on process, the period during which the drive signal S2 is at a low level is set based on the on-delay time within the period during which the control signal S1 is at a high level. By setting the period during which the drive signal S2 is at a low level using the on-delay time of the previous turn-on, it is not necessary to set the drive signal S2 to a low level immediately after detecting the turn-on of the switching element Q2. Because there is little change in the load state between adjacent control cycles, the time during which the control signal S1 is maintained at a high level is the same or nearly the same. Therefore, the on-delay time of the previous turn-on and the on-delay time of the current turn-on can be considered the same. The on-delay time of the previous turn-on can be used to set the period during which the drive signal S2 is at a low level. Therefore, surge voltage can be suppressed regardless of the switching speed of the switching element Q2. The surge voltage includes ringing and overshoot of the drain-source voltage Vds.

[0062] For example, as shown by symbol A1 in Figure 2, in the first control cycle, active control is not performed, so a surge voltage occurs in the drain-source voltage Vds at turn-on. In contrast, in the second control cycle, active control is performed, so the increase in the gate-source voltage Vgs is temporarily suppressed, and the occurrence of a surge voltage in the drain-source voltage Vds is suppressed, as shown by symbol A2.

[0063] The on-delay time is the time from when the control signal S1 starts to rise until the drain-source voltage Vds starts to drop. After the drain-source voltage Vds drops, a surge voltage may occur. For this reason, if the on-delay time is set to the time until the drain-source voltage Vds has dropped to its lowest point, the surge voltage may not be suppressed. In contrast, by setting the on-delay time to the time until the drain-source voltage Vds starts to drop, the surge voltage can be suppressed.

[0064] (2) The switching element driver 10 performs a turn-off process. In the turn-off process, the period during which the drive signal S2 is at a high level is set based on the off delay time within the period during which the control signal S1 is at a low level. By setting the period during which the drive signal S2 is at a high level using the off delay time of the previous turn-off, it is not necessary to set the drive signal S2 at a high level immediately after detecting the turn-off of the switching element Q2. Because there is little change in the load state between adjacent control cycles, the time during which the control signal S1 is maintained at a high level is the same or almost the same. Therefore, the off delay time of the previous turn-off can be considered to be the same as the off delay time of the current turn-off. The off delay time of the previous turn-off can be used to set the period during which the drive signal S2 is at a high level. This allows surge voltage to be suppressed regardless of the switching speed of the switching element Q2.

[0065] For example, as shown by symbol A3 in Figure 2, in the first control cycle, active control is not performed, so a surge voltage occurs in the drain-source voltage Vds at turn-off. In contrast, in the second control cycle, active control is performed, so the decrease in the gate-source voltage Vgs is temporarily suppressed, and the occurrence of a surge voltage in the drain-source voltage Vds is suppressed, as shown by symbol A4.

[0066] The off delay time is the time from when the control signal S1 starts to fall to when the drain-source voltage Vds starts to rise. After the drain-source voltage Vds rises, a surge voltage may occur. For this reason, if the off delay time is set to the time until the drain-source voltage Vds has risen to its maximum, the surge voltage may not be suppressed. In contrast, by setting the off delay time to the time until the drain-source voltage Vds starts to rise, the surge voltage can be suppressed.

[0067] (3) At the time of turn-on, the timing control unit 40 stores the ON delay time in one of the first ON delay time memory 22 and the second ON delay time memory 23, and causes the turn-on delay unit 24 to read the ON delay time from the other memory. Furthermore, at each turn-on, the timing control unit 40 switches between the first ON delay time memory 22 and the second ON delay time memory 23 in which to store the ON delay time. This allows the current ON delay time to be stored in either the ON delay time memory 22 or 23 at the time of turn-on, and the period during which the drive signal S2 is at a low level to be set based on the ON delay time at the previous turn-on.

[0068] (4) The turn-on delay unit 24 corrects the on-delay time read from the on-delay time memories 22, 23 in accordance with the response delay time of the turn-on detection unit 21. There is a delay between when the drain-source voltage Vds starts to decrease and when the turn-on detection unit 21 detects that the drain-source voltage Vds has started to decrease. By correcting the on-delay time in accordance with the response delay time caused by this delay, the drive signal S2 can be set to low level at an appropriate timing.

[0069] (5) At the time of turn-off, the timing control unit 40 stores the OFF delay time in one of the first OFF delay time memory 32 and the second OFF delay time memory 33, and causes the turn-off delay unit 34 to read the OFF delay time from the other. Furthermore, at each turn-off, the timing control unit 40 switches whether to store the OFF delay time in the first OFF delay time memory 32 or the second OFF delay time memory 33. This allows the current OFF delay time at the time of turn-off to be stored in either the OFF delay time memory 32 or 33, and the period during which the drive signal S2 is at a high level to be set based on the OFF delay time at the previous turn-off.

[0070] (6) The turn-off delay unit 34 corrects the off delay time read from the off delay time memories 32 and 33 in accordance with the response delay time of the turn-off detection unit 31. There is a delay from when the drain-source voltage Vds starts to rise until the turn-off detection unit 31 detects that start of the rise in the drain-source voltage Vds. By correcting the off delay time in accordance with the response delay time caused by this delay, the drive signal S2 can be set to high level at an appropriate timing.

[0071] (7) When the switching element Q2 is turned on, a period during which the drive signal S2 is at a low level is set within a period during which the control signal S1 is at a high level. Also, when the switching element Q2 is turned off, a period during which the drive signal S2 is at a high level is set within a period during which the control signal S1 is at a low level. Therefore, compared to a configuration in which the gate resistance value is variable, it is not necessary to provide multiple gate resistors, and a switch for switching the resistance value is also not required.

[0072] [Example of change] The embodiment can be modified as follows: The embodiment and the following modifications can be combined with each other to the extent that they are not technically inconsistent.

[0073] The switching element driver 10 only needs to perform at least one of the turn-on process and the turn-off process. If the switching element driver 10 only performs the turn-on process, the switching element driver 10 does not need to include the turn-off process circuit 30. If the switching element driver 10 only performs the turn-off process, the switching element driver 10 does not need to include the turn-on process circuit 20.

[0074] The ON delay time memories 22 and 23 may have any configuration as long as they can store the ON delay time. For example, they may be configured with a digital circuit using a counter. Similarly, the OFF delay time memories 32 and 33 may have any configuration as long as they can store the OFF delay time.

[0075] [Definition] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more. [Explanation of symbols]

[0076] D...drain which is an example of a first terminal, G...gate which is an example of a control terminal, Q1, Q2...switching element, S...source which is an example of a second terminal, 10...driving device for switching element, 20...turn-on processing circuit, 21...turn-on detection unit, 22...first on delay time memory, 23...second on delay time memory, 24...turn-on delay unit, 25...turn-on one-shot unit, 30...turn-off processing circuit, 31...turn-off detection unit, 32...first off delay time memory, 33...second off delay time memory, 34...turn-off delay unit, 35...turn-off one-shot unit, 40...timing control unit.

Claims

1. A driving device for a switching element, the driving device generating a driving signal based on a control signal that changes between a low level and a high level for a switching element having a first terminal, a second terminal, and a control terminal, and outputting the driving signal to the control terminal to switch the switching element on and off, a turn-on process for storing an on-delay time from when the control signal starts rising to when the voltage between the first terminal and the second terminal starts decreasing when the switching element is turned on, and setting a period during which the drive signal is at a low level within a period during which the control signal is at a high level based on the on-delay time when the drive signal was last turned on; and a turn-off process for storing, when the switching element is turned off, an off delay time from when the control signal starts to fall until when the voltage between the first terminal and the second terminal starts to rise, and setting a period during which the drive signal is at a high level within a period during which the control signal is at a low level based on the off delay time of the drive signal at the previous time of turning off.

2. a turn-on processing circuit that performs the turn-on processing; a timing control unit, The turn-on processing circuit includes: a turn-on detection unit that detects the start of a voltage drop between the first terminal and the second terminal; an on-delay time memory that stores the on-delay time; a turn-on delay unit configured to be able to read the on-delay time from the on-delay time memory; a turn-on one-shot unit that sets a period during which the drive signal is at a low level within a period during which the control signal is at a high level; the on delay time memory includes a first on delay time memory and a second on delay time memory; The timing control unit At the time of turning on, the on delay time is stored in one of the first on delay time memory and the second on delay time memory, and the turn-on delay unit reads the on delay time from the other memory; 2. The driving device for a switching element according to claim 1, wherein the on-delay time is stored in either the first on-delay time memory or the second on-delay time memory, and the on-delay time is switched every time the switching element is turned on.

3. 3. The driving device for a switching element according to claim 2, wherein the turn-on delay unit corrects the on delay time read from the on delay time memory according to a response delay time until the turn-on detection unit detects a start of a voltage drop between the first terminal and the second terminal.

4. a turn-off processing circuit that performs the turn-off processing; a timing control unit, The turn-off processing circuit includes: a turn-off detection unit that detects the start of a rise in voltage between the first terminal and the second terminal; an OFF delay time memory that stores the OFF delay time; a turn-off delay unit configured to be able to read the off-delay time from the off-delay time memory; a turn-off one-shot unit that sets a period during which the drive signal is at a high level within a period during which the control signal is at a low level, the off delay time memory includes a first off delay time memory and a second off delay time memory; The timing control unit At the time of turning off, the off delay time is stored in one of the first off delay time memory and the second off delay time memory, and the turn-off delay unit reads the off delay time from the other memory; 2. The driving device for a switching element according to claim 1, wherein the driving device switches between the first off delay time memory and the second off delay time memory for storing the off delay time each time the switching element is turned off.

5. 5. The driving device for a switching element according to claim 4, wherein the turn-off delay unit corrects the off delay time read from the off delay time memory according to a response delay time until the turn-off detection unit detects a start of a rise in voltage between the first terminal and the second terminal.

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