Semiconductor wafer measuring stage and semiconductor wafer defect height measuring device

Abstract

To provide a stage for measuring a semiconductor wafer capable of accurately measuring the height of a defect and using the semiconductor wafer after measurement as a product.SOLUTION: A semiconductor wafer measurement stage that holds a semiconductor wafer to be measured, the semiconductor wafer measurement stage including a plurality of clamps that are configured to be movable along a surface direction of the semiconductor wafer and clamp the semiconductor wafer by coming into contact with outer edges or an outer peripheral surface of two main surfaces of the semiconductor wafer, wherein the plurality of clamps are configured such that a contact portion with the semiconductor wafer has an arc shape when viewed from a position facing the main surfaces.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a stage for measuring a semiconductor wafer and an apparatus for measuring the height of defects on a semiconductor wafer. [Background technology]

[0002] Conventionally, a configuration for measuring defects on the back surface of an epitaxial wafer is known (see, for example, Patent Document 1). The defects to be measured in the configuration of Patent Document 1 are defects (hereinafter sometimes referred to as "pin mark defects") caused by the shape of the lift pins of the vapor phase growth apparatus and the state of contact between the lift pins and the wafer during epitaxial growth. Pin mark defects are point-like defects consisting of an aggregate of minute scratches such as wear marks, or deposits that are difficult to remove, such as Si coating components on the lift pins of the vapor phase growth apparatus. Multiple pin mark defects occur in clusters at the contact points between the lift pins and the epitaxial wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-146482 Summary of the Invention [Problem to be solved by the invention]

[0004] As described in Patent Document 1, pin mark defects may cause defocusing in the photolithography process included in the device formation process. In order to suppress the occurrence of such defocusing, it is preferable to measure the height of the pin mark defects and eliminate defects that are tall enough to cause defocusing. However, the configuration of Patent Document 1 does not measure the height of pin mark defects.

[0005] One possible method for measuring the height of pin mark defects is to place the epitaxial wafer so that its front surface is in surface contact with a measurement stage and observe it from above using, for example, a laser microscope that can evaluate minute steps. However, with this method, dust from the measurement stage may adhere to the front surface, or the front surface may be scratched by contact with the measurement stage, making the epitaxial wafer unusable as a product after measurement.

[0006] In order to prevent the above-described adhesion of dust and the occurrence of scratches, it is conceivable to clamp only the peripheral portion of the epitaxial wafer when viewed from a position facing the main surface of the epitaxial wafer and measure it from above with a measuring instrument. However, if only the peripheral portion of the epitaxial wafer is clamped, depending on the method, the epitaxial wafer may vibrate during measurement of a minute step due to the operation of other equipment or the movement of the operator, and the height of the pin mark defect may not be measured accurately.

[0007] An object of the present invention is to provide a semiconductor wafer measurement stage and a semiconductor wafer defect height measurement device that can accurately measure the height of defects that occur on the back surface of a semiconductor wafer and enable the semiconductor wafer to be used as a product after measurement. [Means for solving the problem]

[0008] The semiconductor wafer measurement stage of the present invention is a semiconductor wafer measurement stage that holds a semiconductor wafer to be measured, and is configured to be movable along the surface direction of the semiconductor wafer.It is equipped with a plurality of clamps that clamp the semiconductor wafer by contacting the outer edges or outer peripheral surfaces of the two main surfaces of the semiconductor wafer, and the plurality of clamps are configured so that the contact portions with the semiconductor wafer are arc-shaped when viewed from a position facing the main surfaces.

[0009] The semiconductor wafer measurement stage of the present invention preferably includes a support body that supports an outer edge of one of the main surfaces of the semiconductor wafer from below.

[0010] In the semiconductor wafer measurement stage of the present invention, it is preferable that the plurality of clamps have clamp grooves into which the wafer fits, and that the clamp grooves are configured so that the semiconductor wafer supported by the support body rises when the semiconductor wafer fits into the clamp grooves.

[0011] In the semiconductor wafer measurement stage of the present invention, it is preferable that the multiple clamps are configured so that, when viewed from a position facing the main surface, a first contact ratio calculated by dividing the total length of contact portions of all the clamps with the semiconductor wafer by the diameter of the semiconductor wafer is 1.21 or more.

[0012] In the semiconductor wafer measurement stage of the present invention, it is preferable that the clamp includes at least one clamp portion that contacts the semiconductor wafer, and that the clamp portion is configured so that a second contact ratio, calculated by dividing the length of the contact portion with the semiconductor wafer by the diameter of the semiconductor wafer, is 0.70 or less when viewed from a position facing the main surface.

[0013] In the semiconductor wafer measurement stage of the present invention, it is preferable that the plurality of clamps are composed of a first set of clamps consisting of two or more of the clamps, and a second set of clamps consisting of the same number of clamps as the clamps in the first set, and that the first set of clamps and the second set of clamps clamp the semiconductor wafer by moving from positions on either side of a first imaginary line including the center of the semiconductor wafer along a second imaginary line perpendicular to the first imaginary line, when viewed from a position facing the main surface, in directions approaching each other.

[0014] The semiconductor wafer defect height measuring device of the present invention includes the semiconductor wafer measurement stage described above, and a measuring unit that measures the height of defects on the main surface of the semiconductor wafer clamped by the multiple clamps. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic diagram showing the configuration of a semiconductor wafer defect height measuring device according to an embodiment; [Figure 2] FIG. 2 is a plan view of a measurement stage according to the embodiment. [Figure 3] 3A and 3B are diagrams showing the main parts of a measurement stage according to an embodiment, in which (A) is a longitudinal cross-sectional view taken along line IIIA-IIIA in FIG. 2, and (B) is a longitudinal cross-sectional view taken along line IIIB-IIIB in FIG. [Figure 4] 10A and 10B are longitudinal cross-sectional views for explaining a clamping operation in the measurement stage according to the embodiment. [Figure 5] FIG. 1 is a schematic diagram showing the configuration of an apparatus in Experimental Example 1 of an embodiment. [Figure 6] 10 is a graph showing the average increase in LPD before and after defect height measurement in Experimental Example 2 of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] [Embodiment] An embodiment of the present invention will be described below. <Configuration of semiconductor wafer defect height measurement device> First, the configuration of the semiconductor wafer defect height measurement device according to this embodiment will be described. FIG. 1 is a schematic diagram showing the configuration of the semiconductor wafer defect height measurement device. FIG. 2 is a plan view of a measurement stage. FIG. 3 is a diagram showing the main parts of the measurement stage, where (A) is a vertical cross-sectional view taken along line IIIA-IIIA in FIG. 2, and (B) is a vertical cross-sectional view taken along line IIIB-IIIB in FIG. 2. FIG. 4 is a vertical cross-sectional view for explaining the clamping operation on the measurement stage. In the following description, each component may be described based on the direction shown in FIG. 1.

[0017] The defect height measurement device 1 for a semiconductor wafer W shown in FIG. 1 measures the height of defects on the back surface W1, which is the other main surface of the semiconductor wafer W. In this embodiment, the semiconductor wafer W to be measured is an epitaxial wafer having an epitaxial layer formed on the back surface W1. The defect to be measured is, for example, a pin mark defect caused by the shape of the lift pins of a vapor phase growth apparatus or the contact state between the lift pins and the semiconductor wafer W during epitaxial growth, as described above. In addition to pin mark defects, the height of particles or scratches attached to the back surface W1 for other reasons can also be measured. In this case, the semiconductor wafer W to be measured does not need to have an epitaxial layer formed thereon. The diameter of the semiconductor wafer W is not particularly limited. Each component of the defect height measurement device 1 may be formed to a size corresponding to the diameter of the semiconductor wafer W. The defect height measuring device 1 includes a stage 2, an aligner 3, a measurement stage 4, an observation unit 5, a transfer robot 6, and a control device .

[0018] The mounting table 2, the aligner 3, the measurement stage 4, the observation unit 5, and the transfer robot 6 are arranged inside a housing 10. A load port 11 is detachably attached to the front of the housing 10. A plurality of semiconductor wafers W are stored in the load port 11 with their back surfaces W1 facing downward. An opening is provided in the front of the housing 10 so that the semiconductor wafers W can be transported between the inside of the housing 10 and the inside of the load port 11.

[0019] The table 2 has four placement portions 21 arranged to form an imaginary circle. A semiconductor wafer W is placed on the upper surface of each mounting portion 21 with its front surface W2 facing upward. The upper surface of each mounting portion 21 is inclined so that the height position decreases as it approaches the center WC of the semiconductor wafer W (hereinafter sometimes referred to as the "wafer center WC": see FIG. 2). Therefore, the semiconductor wafer W is placed on the mounting table 2 with only the outer edge of its back surface W1 in contact with the mounting portion 21. By placing the semiconductor wafer W on the mounting table 2 as described above, the back surface W1 of the semiconductor wafer W is prevented from being contaminated with dust or being scratched.

[0020] The aligner 3 includes four mounting portions 31 and four grips 32 arranged in an imaginary circle. A semiconductor wafer W is placed on the upper surface of each mounting portion 31 with its back surface W1 facing upward. The upper surface of each mounting portion 31 is inclined in the same manner as the mounting portion 21 of the mounting table 2. Therefore, the semiconductor wafer W is placed on the mounting portion 31 with only the outer edge of its front surface W2, which is one of its main surfaces, in contact with the mounting portion 31. The four grips 32 are disposed between adjacent mounting portions 31. Based on the control of the control device 7, each grip 32 holds only the outer edge of the semiconductor wafer W and adjusts the position of the semiconductor wafer W on the mounting portion 31 so that the notch WN of the semiconductor wafer W is located at a predetermined position. By placing the semiconductor wafer W on the mounting portion 31 and holding the semiconductor wafer W by the grip 32 as described above, it is possible to prevent dust from adhering to the back surface W1 or the front surface W2 of the semiconductor wafer W and prevent scratches from occurring.

[0021] The measurement stage 4 holds the semiconductor wafer W so that the back surface W1 faces upward. The measurement stage 4 includes a wafer holder 41, and a lift pin driver and a clamp driver (not shown) that are driven under the control of the control device 7. The wafer holder 41 includes two supports 42, four stage lift pins 43, and four clamps 44. The detailed configurations of the support 42, the stage lift pins 43, and the clamp 44 will be described later. The lift pin driving unit raises and lowers the stage lift pins 43 under the control of the control device 7. The clamp driving unit moves the clamp 44 in the horizontal direction under the control of the control device 7.

[0022] The observation unit 5 includes an optical microscope 51, a white light interference microscope 52, and a moving unit (not shown). The optical microscope 51 captures an image of the measurement range of the semiconductor wafer W and outputs the image to the control device 7. The measurement range is the contact area with the lift pins of the vapor phase growth apparatus, and if the vapor phase growth apparatus has three lift pins, there will be three measurement ranges. The white light interference microscope 52 captures an image of each measurement target range at a higher magnification than the optical microscope 51, and outputs to the control device 7 an image used to measure the height of a defect. Instead of the white light interference microscope 52, a laser microscope or the like may be used to measure the height of the defect. The moving unit reciprocates the optical microscope 51 and the white light interferometer 52 independently in the up and down directions under the control of the control device 7. The moving unit reciprocates the measurement stage 4 in the left and right directions and the front and back directions under the control of the control device 7. With this configuration, the measurement stage 4 moves from the standby position shown in FIG. 1 to below the optical microscope 51 or the white light interferometer 52, and the optical microscope 51 or the white light interferometer 52 moves up and down, allowing a desired position on the semiconductor wafer W to be observed.

[0023] The transfer robot 6 includes an arm 61 and a plurality of chucks 62 that are driven under the control of a control device 7 . The arm 61 is configured to be rotatable. A plurality of chucks 62 are provided at the tip and base of the arm 61, respectively. The plurality of chucks 62 enable the semiconductor wafer W to be inverted while holding only the outer edge of the semiconductor wafer W. This prevents dust from adhering to the back surface W1 and the front surface W2 of the semiconductor wafer W and preventing scratches from occurring.

[0024] The control device 7 controls the aligner 3 , the measurement stage 4 , the observation unit 5 and the transfer robot 6 .

[0025] The materials used for the mounting portions 21, 31, grip 32, support 42, stage lift pin 43, clamp 44, and chuck 62, which come into direct contact with the semiconductor wafer W, are engineering plastics such as PEEK (poly ether ether ketone), thereby suppressing dust generation and metal contamination.

[0026] Next, the detailed configuration of the wafer holder 41 that constitutes the measurement stage 4 will be described. The wafer holder 41 holds the semiconductor wafer W with the back surface W1 facing upward and parallel to a horizontal plane. As shown in FIG. 2 , the wafer holder 41 includes two supports 42, four stage lift pins 43, and four clamps 44. In the following description, the "outer circumferential direction of the semiconductor wafer W held on the measurement stage 4" may be simply referred to as the "outer circumferential direction." When the measurement stage 4 is viewed from above, two imaginary lines that include the wafer center WC of the held semiconductor wafer W, are perpendicular to each other, and are parallel to the back surface W1 (horizontal plane) of the semiconductor wafer W, are defined as a first imaginary line L1 and a second imaginary line L2. Four imaginary regions defined by the first imaginary line L1 and the second imaginary line L2 are defined counterclockwise along the outer circumferential direction as a first imaginary region R1, a second imaginary region R2, a third imaginary region R3, and a fourth imaginary region R4. The first imaginary region R1 and the second imaginary region R2 are adjacent to each other across the second imaginary line L2.

[0027] When viewed from above, each support 42 is fixed so that it sandwiches the wafer center WC of the semiconductor wafer W supported by each support 42 and so that its center in the circumferential direction overlaps with the first virtual straight line L1.

[0028] 3(A), the upper surface of each support 42 constitutes a support mounting surface 421. The support mounting surface 421 is inclined so that the height position decreases as it approaches the wafer center WC of the supported semiconductor wafer W. Therefore, the semiconductor wafer W is supported by the support 42 with only the outer edge of the front surface W2 in contact with the support mounting surface 421. Supporting the semiconductor wafer W by each support 42 as described above prevents dust from adhering to the front surface W2 of the semiconductor wafer W and prevents scratches from occurring.

[0029] Each stage lift pin 43 is raised and lowered by being driven by a lift pin drive unit to receive a semiconductor wafer W before measurement from the transfer robot 6 and to deliver a semiconductor wafer W after measurement to the transfer robot 6. One stage lift pin 43 is arranged in each of the first to fourth imaginary regions R1 to R4. Each stage lift pin 43 is arranged so that the angle between an imaginary line connecting each stage lift pin 43 and the wafer center WC and the first imaginary line L1 is approximately 45°.

[0030] As shown in Figure 3(B), the upper surface of each stage lift pin 43 includes a pin mounting surface 431 located on the wafer center WC side of the semiconductor wafer W supported by each support 42, and a guide surface 432 located on the outer edge side of the semiconductor wafer W than the pin mounting surface 431. The pin mounting surface 431 is inclined so that its height position decreases as it approaches the wafer center WC. Therefore, the semiconductor wafer W is supported by the stage lift pins 43 with only the outer edge of the front surface W2 in contact with the pin mounting surface 431. Supporting the semiconductor wafer W by the stage lift pins 43 as described above prevents dust from adhering to the front surface W2 of the semiconductor wafer W and prevents scratches from occurring. The guide surface 432 is inclined so that its height position decreases as it approaches the wafer center WC. The guide surface 432 is inclined so that its angle with respect to the horizontal plane is larger than the angle between the pin mounting surface 431 and the horizontal plane. The lower end of the guide surface 432 is connected to the outer edge of the pin mounting surface 431.

[0031] One clamp 44 is arranged in each of the first to fourth imaginary regions R1 to R4. The clamps 44 in the first and second imaginary regions R1 and R2 constitute a first set of clamps 44A, and the clamps 44 in the third and fourth imaginary regions R3 and R4 constitute a second set of clamps 44B. The first set of clamps 44A and the second set of clamps 44B are located symmetrically with respect to the first imaginary straight line L1.

[0032] Each clamp 44 is configured to be reciprocally movable along the second imaginary straight line L2 by being driven by a clamp drive unit. Each clamp 44 moves in a direction approaching the first imaginary straight line L1 and comes into contact with the outer edges of the back surface W1 and front surface W2 of the semiconductor wafer W, thereby clamping the semiconductor wafer W supported by the support body 42. Each clamp 44 moves simultaneously at the same speed and the same distance. However, the movement direction of the first set of clamps 44A is opposite to the movement direction of the second set of clamps 44B. In the following description, the state in which each clamp 44 comes into contact with the semiconductor wafer W to clamp the semiconductor wafer W may be referred to as a "clamped state." The state in which each clamp 44 is separated from the semiconductor wafer W and does not clamp the semiconductor wafer W may be referred to as a "clamp standby state." The position and arrangement of each component of the clamp 44 may be described based on the semiconductor wafer W in the clamped state.

[0033] Each clamp 44 has a plate-shaped base 45. Each base 45 has an outer circumferential surface 451 located radially outward of the semiconductor wafer W. When viewed from above, the outer circumferential surface 451 is formed in an arc shape with a radius of curvature larger than the radius of the semiconductor wafer W.

[0034] Each base 45 has a recess 46 recessed from the outer peripheral surface 451 toward the wafer center WC. Each recess 46 is formed in a shape that does not hinder the raising and lowering of each stage lift pin 43 within the recess 46 in the clamp standby state and the clamped state.

[0035] At the end of each base portion 45 on the outer circumferential surface 451 side, a first clamp portion 47 and a second clamp portion 48 are provided which protrude upward. The first clamp portion 47 is located closer to the second imaginary line L2 than the recessed portion 46. The second clamp portion 48 is located closer to the first imaginary line L1 than the recessed portion 46. The length of the first clamp portion 47 in the outer circumferential direction is longer than the length of the second clamp portion 48 in the outer circumferential direction.

[0036] As shown in FIG. 4, the first and second inner peripheral portions 471, 481 of the first and second clamping portions 47, 48 on the wafer center WC side are formed in an arc shape with a radius of curvature larger than the radius of the semiconductor wafer W when viewed from above. A first clamp groove 472 extending along the outer periphery is provided in first inner periphery 471. A second clamp groove 482 extending along the outer periphery is provided in second inner periphery 481 at the same height as first clamp groove 472.

[0037] A semiconductor wafer W is fitted into the first and second clamp grooves 472, 482. The first and second clamp grooves 472, 482 include first and second lower inclined portions 473, 483 that are inclined so that their height position increases with increasing distance from the wafer center WC, and first and second upper inclined portions 474, 484 that are inclined so that their height position increases from the upper ends of the first and second lower inclined portions 473, 483 toward the wafer center WC. The connection portions between the first and second lower inclined portions 473, 483 and the first and second upper inclined portions 474, 484 form first and second groove bottoms 475, 485. When viewed from above, the first and second groove bottoms 475, 485 are formed in the shape of an arc whose radius of curvature is larger than the radius of the semiconductor wafer W.

[0038] In the clamp standby state shown in the upper diagram of Figure 4, the first and second clamp grooves 472, 482 are formed so that the lower ends of the first and second lower inclined portions 473, 483 are located below the front surface W2 of the semiconductor wafer W supported by the support body 42, and the upper ends of the first and second upper inclined portions 474, 484 are located above the back surface W1 of the semiconductor wafer W. 4, the first and second clamp grooves 472, 482 are formed so that the entire peripheral area of ​​the first and second lower inclined portions 473, 483 contacts the outer edge of the front surface W2, and the entire peripheral area of ​​the first and second upper inclined portions 474, 484 contacts the outer edge of the back surface W1. In other words, the first and second clamp portions 47, 48 are configured so that the contact portions with the semiconductor wafer W are arc-shaped when viewed from above (when viewed from a position facing the back surface W1). In the clamped state, the outer edge of the back surface W1 of the semiconductor wafer W rises along the first and second lower inclined portions 473, 483 more than in the clamp standby state, and is separated from the support 42.

[0039] If the total length of the contact portions between all the clamps 44 and the semiconductor wafer W when viewed from above is too short, there is a risk that vibration of the semiconductor wafer W in the clamped state may not be suppressed. Furthermore, it is believed that the longer the total length, the better the vibration suppression performance. From these viewpoints, the first contact ratio calculated by dividing the total length by the diameter of the semiconductor wafer W is preferably 1.21 or more, and more preferably 1.50 or more. Furthermore, if the total length is too long, it will be impossible to provide a sufficient space for arranging the support 42, and therefore the first contact ratio is preferably 3.00 or less.

[0040] If the length of the contact portion between one clamp portion (first clamp portion 47 or second clamp portion 48) and the semiconductor wafer W when viewed from above is too long, the length of the contact portion may be too long, and the actual length of the contact portion may be shorter than the design value due to a shape error of at least one of the clamp portion and the semiconductor wafer W. In this case, there is a risk that sufficient vibration suppression performance may not be obtained. From this viewpoint, it is preferable that one clamp portion is configured so that the second contact ratio, calculated by dividing the length of the contact portion with the semiconductor wafer W by the diameter of the semiconductor wafer W, is 0.70 or less. Furthermore, if the length of the contact portion between one clamp part and the semiconductor wafer W is too short, it will be necessary to provide a large number of first clamp parts 47 or second clamp parts 48 in order to obtain vibration suppression performance, which will complicate the configuration of the measurement stage 4. From this viewpoint, it is preferable that one clamp portion is configured so that the second contact ratio is equal to or greater than 0.13.

[0041] <Method for measuring defect height on semiconductor wafers> Next, a method for measuring the height of a defect on a semiconductor wafer W using the defect height measuring device 1 will be described.

[0042] The transfer robot 6 enters the load port 11 below the semiconductor wafer W and holds the outer edge with a plurality of chucks 62. The transfer robot 6 temporarily places the semiconductor wafer W on the stage 2 with the front surface W2 facing upward. The transfer robot 6 further advances below the semiconductor wafer W placed on the stage 2 and holds the semiconductor wafer W with the front surface W2 facing upward with the multiple chucks 62. The transfer robot 6 transfers the semiconductor wafer W while inverting the arm 61, and places it on the placement section 31 of the aligner 3 with the back surface W1 facing upward. The transfer robot 6 then moves below the semiconductor wafer W whose position has been adjusted by the aligner 3, and holds it with the multiple chucks 62. With each stage lift pin 43 raised, the transfer robot 6 moves the semiconductor wafer W above the measurement stage 4 in a clamp standby state, with the back surface W1 facing upward, while maintaining the state after the position adjustment.

[0043] The transfer robot 6 descends, releases the semiconductor wafer W, and places the semiconductor wafer W on each stage lift pin 43. After placing the semiconductor wafer W, the transfer robot 6 moves to a position away from above the measurement stage 4. Each stage lift pin 43 is lowered to a position lower than each support 42, and the semiconductor wafer W is placed on each support 42, as shown in the upper diagram of FIG.

[0044] The first set of clamps 44A and the second set of clamps 44B move toward each other along the second imaginary line L2. As the clamps 44 move, the semiconductor wafer W rises along the first and second lower inclined portions 473, 483 of the first and second clamp portions 47, 48 and moves away from the supports 42. As the clamps 44 move further, the semiconductor wafer W comes into contact with the first and second upper inclined portions 474, 484, as shown in the lower diagram of FIG. 4. The clamps 44 stop when the semiconductor wafer W comes into contact with the first and second upper inclined portions 474, 484, and enter a clamped state. The control device 7 controls the moving unit to move the measurement stage 4 from the standby position to below the optical microscope 51. The control device 7 controls the moving unit and the optical microscope 51 to acquire an image of the measurement target range of the semiconductor wafer W from the optical microscope 51. The control device 7 sets a review range including the defect based on the image from the optical microscope 51. The control device 7 controls the moving unit to move the measurement stage 4 to below the white light interferometer 52. The control device 7 controls the moving unit and the white light interferometer 52 to acquire an image from the white light interferometer 52 that includes the review range and has a higher magnification than the image from the optical microscope 51. The control device 7 measures the height of the defect present in the semiconductor wafer W based on the image of the review range from the white light interferometer 52. In this way, the observation unit 5 and the control device 7 constitute a measurement unit that measures the height of a defect.

[0045] When the defect height measurement is completed, the control device 7 controls the moving unit to move the measurement stage 4 to a standby position. The first set of clamps 44A and the second set of clamps 44B move along the second imaginary straight line L2 in a direction away from the semiconductor wafer W. As each clamp 44 moves, the semiconductor wafer W descends along the first and second downward inclined portions 473, 483 and is supported by each support 42, as shown in the upper diagram of FIG. 4. Each clamp 44 stops at a position away from the semiconductor wafer W and enters a clamp standby state.

[0046] Each stage lift pin 43 rises to a position higher than the semiconductor wafer W and receives the semiconductor wafer W from each support 42 . The transfer robot 6 enters below the semiconductor wafer W supported by each stage lift pin 43 and holds the semiconductor wafer W with the multiple chucks 62. The transfer robot 6 inverts the arm 61 so that the front surface W2 faces upward, temporarily places the semiconductor wafer W on the stage 2, and then stores the semiconductor wafer W in the load port 11. When the semiconductor wafer W is received, each stage lift pin 43 is lowered to its pre-lift position.

[0047] [Effects of the embodiment] The measurement stage 4 includes a plurality of clamps 44 that clamp the semiconductor wafer W by contacting the outer edges of the back surface W1 and front surface W2 of the semiconductor wafer W. By configuring the clamps 44 not to come into contact with the interior surfaces of the back surface W1 and front surface W2 when the semiconductor wafer W is clamped in this manner, it is possible to prevent dust from the first clamp unit 47 or the second clamp unit 48 from adhering to the front surface W2 and causing scratches. The clamps 44 are configured so that, when viewed from above, the contact portion with the outer edge of the semiconductor wafer W is arc-shaped. This allows the contact length between the clamps 44 and the semiconductor wafer W to be increased, thereby suppressing vibration of the semiconductor wafer W. Therefore, it is possible to provide a measuring stage 4 that can measure the height of defects with high accuracy and that allows the semiconductor wafer W after measurement to be used as a product. By introducing the measurement stage 4 or defect height measurement device 1 of the present invention, not only will semiconductor wafers W be eliminated from disposal due to measurement, but it will also contribute to improving yields in the customer's semiconductor device manufacturing process.

[0048] The measurement stage 4 includes a support 42 that supports the outer edge of the front surface W2 of the semiconductor wafer W from below before it is clamped. Therefore, with a simple configuration in which the support body 42 is simply provided, the semiconductor wafers W can be appropriately positioned before being clamped, and the clamping state of each semiconductor wafer W by the clamps 44 can be stabilized.

[0049] The clamp 44 has first and second clamp grooves 472, 482 that lift the semiconductor wafer W supported by the support body 42 when the semiconductor wafer W is fitted therein. Here, if the first and second clamp grooves 472, 482 are configured so as not to lift the semiconductor wafer W from the support body 42 when the semiconductor wafer W is fitted therein, unless the height position of the support body 42 relative to the first and second clamp grooves 472, 482 is precisely adjusted, the height position of the portion of the semiconductor wafer W supported by the support body 42 will be higher than the height position of the portion fitted into the first and second clamp grooves 472, 482, and there is a risk that the semiconductor wafer W will be deformed and damaged. By configuring the first and second clamp grooves 472, 482 as in this embodiment, damage to the semiconductor wafer W as described above can be suppressed.

[0050] The first set of clamps 44A and the second set of clamps 44B clamp the semiconductor wafer W by moving in a direction toward each other along the second imaginary straight line L2. Here, when moving the four clamps 44 in a direction approaching the wafer center WC, the clamp drive unit needs to be provided with four movement mechanisms for moving the four clamps 44, respectively. On the other hand, in the configuration of this embodiment, it is only necessary to provide the clamp drive unit with two movement mechanisms for moving the two sets of clamps 44 respectively, and the configuration of the measurement stage 4 can be simplified.

[0051] [Variations] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and various improvements and design changes that do not deviate from the gist of the present invention are also included in the present invention.

[0052] The clamp 44 may not be provided with the first and second clamp grooves 472, 482, and the semiconductor wafer W may be clamped by bringing the first and second inner peripheral portions 471, 481 into surface contact with the outer peripheral surface of the semiconductor wafer W. The measurement stage 4 does not need to include the support 42 and the stage lift pins 43. In this case, the transfer robot 6 only needs to transfer the semiconductor wafer W to a position where it can be clamped by the clamps 44. The measurement stage 4 may include the stage lift pins 43 but may not include the support 42. In this case, it is sufficient if the stage lift pins 43 can transport the semiconductor wafer W to a position where it can be clamped by the clamps 44.

[0053] The first and second clamp grooves 472, 482 may be configured so as not to lift the semiconductor wafer W from the support 42 when the semiconductor wafer W is fitted therein. The clamp 44 may be configured such that the first contact ratio does not satisfy the condition of 1.21 or more and 3.00 or less. The first and second clamp grooves 472, 482 may be configured so that the second contact ratio does not satisfy the condition of 0.13 or more and 0.70 or less.

[0054] The configuration for clamping the semiconductor wafer W may be one in which four clamps 44 are moved in a direction approaching the wafer center WC, or one in which two, three, or five or more clamps, each having at least one clamp portion, are moved in a direction approaching the wafer center WC. The number of clamp portions provided in each clamp 44 is not limited to two as illustrated in the above embodiment, but may be one, or three or more. Although the first set of clamps 44A and the second set of clamps 44B each have two clamps each, the first set of clamps 44A and the second set of clamps 44B may each have one clamp or three or more clamps, or may each have a different number of clamps. For example, one clamp having one or more clamps may be provided on one side of the first imaginary straight line L1, and multiple clamps having one or more clamps may be provided on the other side, and the clamp on one side and the clamp on the other side may be brought closer to each other along the second imaginary straight line L2 to clamp the semiconductor wafer W. The semiconductor wafer W may be held on the measurement stage 4 with the back surface W1 facing downward, and the height of the defects may be observed from below the semiconductor wafer W by the observation unit 5. [Example]

[0055] Next, examples of the present invention will be described, but the present invention is not limited to these examples.

[0056] [Experimental Example 1] As Experimental Example 1, an experiment was conducted to examine the relationship between the clamping method for the semiconductor wafer W and the vibration suppression performance during clamping. In Experimental Example 1, a semiconductor wafer W having a diameter of 300 mm was used. Furthermore, measurement stage 8H of Comparative Example 1 and measurement stages 8A and 8B of Examples 1 and 3, which will be described later, each include a support and stage lift pins having the same configurations as support 42 and stage lift pins 43 of measurement stage 4. The support and stage lift pins are positioned so as not to interfere with the operation of clamps 81H, 81A, and 81B, which will be described later, respectively.

[0057] <Device configuration of Comparative Example 1> The defect height measurement device of Comparative Example 1 has a configuration in which a measurement stage 8H as shown in the top diagram of Figure 5 is installed instead of the measurement stage 4 of the defect height measurement device 1 of the above embodiment. The measurement stage 8H has four clamps 81H. Each clamp 81H has a round bar-shaped clamp portion 811H with a diameter of 10 mm. Each clamp 81H is positioned so that when the clamp portion 811H comes into contact with the semiconductor wafer W, the angle between the imaginary line connecting the clamp portion 811H and the wafer center WC and the first imaginary line L1 is approximately 45°. Each clamp 81H approaches the semiconductor wafer W from the clamp standby position indicated by the two-dot chain line along the second imaginary line L2, and clamps the semiconductor wafer W by making point contact with the outer peripheral surface of the semiconductor wafer W as indicated by the solid line when viewed from above. In other words, as shown in Table 1, the first contact ratio on the measurement stage 8H is 0.13. The second contact ratio is less than 1% (less than 0.01).

[0058] <Device Configuration of Example 1> The defect height measurement device of Example 1 has a configuration in which a measurement stage 8A as shown in the second drawing from the top in Fig. 5 is installed instead of the measurement stage 4 in the defect height measurement device 1 of the above embodiment. The measurement stage 8A includes two clamps 81A. Each clamp 81A has one clamp portion 811A having an inner periphery with a radius of curvature smaller than the radius of the semiconductor wafer W. The inner periphery is provided with a clamp groove having the same shape as the first clamp groove 472. Each clamp 81A is disposed so as to sandwich the wafer center WC of the semiconductor wafer W and so that the circumferential center of the inner periphery overlaps with the second imaginary straight line L2. Each clamp 81A approaches the semiconductor wafer W from a clamp standby position indicated by a two-dot chain line along the second imaginary straight line L2, and clamps the semiconductor wafer W by fitting the semiconductor wafer W into the clamp groove as indicated by a solid line. When viewed from above, the length of the contact portion between one clamp 81A and the semiconductor wafer W was 182 mm. Therefore, as shown in Table 1, the first contact ratio of the measurement stage 8A is 1.21 (=(2×182) / 300). Also, the second contact ratio of each clamp portion 811H is 0.61 (=182 / 300).

[0059] <Device configuration of Example 2> The defect height measuring device of Example 2 is the defect height measuring device 1 of the above embodiment equipped with a measurement stage 4, as shown in the third diagram from the top in FIG. When viewed from above, the length of the contact portion between one first clamp part 47 and the semiconductor wafer W was 81.0 mm, and the length of the contact portion between one second clamp part 48 and the semiconductor wafer W was 39.0 mm. In other words, the length of the contact portion between one clamp 44 and the semiconductor wafer W was 120 mm. Therefore, as shown in Table 1, the first contact ratio of the measurement stage 4 is 1.60 (=(4×120) / 300). Also, the second contact ratio of each first clamp portion 47 is 0.27 (=81.0 / 300), and the second contact ratio of each second clamp portion 48 is 0.13 (=39.0 / 300).

[0060] <Device configuration of Example 3> The defect height measurement device of Example 3 has a configuration in which a measurement stage 8B as shown in the fourth drawing from the top in Fig. 5 is installed instead of the measurement stage 4 in the defect height measurement device 1 of the above embodiment. The measurement stage 8B includes two clamps 44 constituting a first set of clamps 44A and one clamp 81B. The clamp 81B includes one third clamp member 811B having an inner periphery with a radius of curvature smaller than the radius of the semiconductor wafer W. The inner periphery is provided with a clamp groove having the same shape as the first clamp groove 472. The clamp 81B is disposed in a region opposite the first set of clamps 44A with respect to the first imaginary straight line L1, so that the circumferential center of the inner periphery overlaps with the second imaginary straight line L2. The first set of clamps 44A and clamp 81B approach the semiconductor wafer W along the second imaginary straight line L2 from a clamp standby position indicated by a two-dot chain line, and the semiconductor wafer W is fitted into the clamp groove as indicated by a solid line, thereby clamping the semiconductor wafer W. When viewed from above, the length of the contact portion between the clamp 81B and the semiconductor wafer W was 209 mm. Therefore, as shown in Table 1, the first contact ratio of the measurement stage 8B is 1.50 (=(209+2×120) / 300). Also, the second contact ratio of the third clamp portion 811B is 0.70 (=209 / 300).

[0061] [Table 1]

[0062] <Evaluation method> Using the defect height measuring devices of Comparative Example 1 and Examples 1 to 3, heights of pin mark defects in three measurement ranges on the backsides W1 of ten semiconductor wafers W were measured. Vibration suppression performance was evaluated as "C" if height measurement was impossible, "B" if height measurement was possible, and "A" if measurements equivalent to manual measurements using a laser microscope were possible. Using this evaluation method, vibration suppression performance was evaluated as "C" if the vibration was too great to measure height, "B" if height measurement was possible despite weak vibration, and "A" if height measurement was possible without vibration.

[0063] <Evaluation results and discussion> As shown in Table 1, the vibration suppression performance was "C" for Comparative Example 1, "B" for Example 1, and "A" for Examples 2 and 3. From a comparison between Comparative Example 1 and Examples 1 to 3, it was confirmed that vibration suppression performance was improved by making the shape of the contact portion between the clamp and the semiconductor wafer W arc-shaped when viewed from above. From a comparison between Comparative Example 1 and Examples 1 to 3, it was confirmed that vibration suppression performance was improved by setting the first contact ratio to 1.21 or more. In Examples 2 and 3, the portion of the semiconductor wafer W near the first imaginary straight line L1 was clamped by the second clamp portion 48, whereas in Example 1, which had lower vibration suppression performance than Examples 2 and 3, the portion near the first imaginary straight line L1 was clamped. From this, it was confirmed that by shortening the interval between adjacent clamps, vibration suppression performance was further improved and measurement was possible in the same way as when the front surface W2 of the semiconductor wafer W was placed in surface contact with the measurement stage.

[0064] [Experimental Example 2] As Experimental Example 2, an experiment was conducted to examine the performance of the measurement stage of the present invention in suppressing the occurrence of LPD (Light Point Defect).

[0065] <Evaluation method> Eighteen semiconductor wafers W each having a diameter of 300 mm were prepared. The LPD was measured on the front surface W2 of each semiconductor wafer W. An SP1-TBI manufactured by KLA Tencor was used as the LPD measuring device. The defect height measuring device of Example 2, i.e., the defect height measuring device 1 of the above embodiment, was used to measure the height of pin mark defects on the back surface W1 of a semiconductor wafer W. The semiconductor wafers W to be measured were sequentially replaced, and defect height measurements were performed 10 times for each. For the semiconductor wafer W on which the defect height measurements were performed 10 times, the LPD on the front surface W2 was measured.

[0066] <Evaluation results and discussion> Figure 6 shows the average increase in LPD per semiconductor wafer W before and after defect height measurement. As shown in FIG. 6, the average increase in LPDs between 45 nm and 200 nm was 0.33, the average increase in LPDs between 200 nm and 1000 nm was 0.06, and the average increase in LPDs over 1000 nm was 0.00. As described in the above embodiment, there is little possibility that dust will adhere to the front surface W2 or that scratches will occur due to contact with the stage 2, aligner 3, and transport robot 6. Since the average increase in LPDs of 1000 nm or more, which affect the quality of the semiconductor wafer W, was 0.00, it was confirmed that by clamping the semiconductor wafer W so that the clamps 44 do not come into contact with the front surface W2, as in the measurement stage of the present invention, it is possible to suppress the adhesion of dust and the occurrence of scratches due to contact with the clamps 44. Therefore, by holding the semiconductor wafer W using the measurement stage of the present invention during defect height measurement, the semiconductor wafer W after measurement could be used as a product. [Explanation of symbols]

[0067] 1...defect height measuring device, 4, 8A, 8B...measurement stage, 5...observation unit (measurement unit), 7...control unit (measurement unit), 42...support, 44, 81A, 81B...clamps, 44A...first set of clamps, 44B...second set of clamps, 47...first clamp unit, 48...second clamp unit, 472...first clamp groove, 473...first lower inclined portion, 474...first upper inclined portion, 482...second clamp groove, 483...second lower inclined portion, 484...second upper inclined portion, 811...third clamp unit, BL1...first virtual straight line, L2...second virtual straight line, W...semiconductor wafer, W1...back surface (other main surface), W2...front surface (one main surface), WC...wafer center, WN...notch.

Claims

1. A semiconductor wafer measurement stage that holds a semiconductor wafer to be measured, a plurality of clamps configured to be movable along the surface direction of the semiconductor wafer and to clamp the semiconductor wafer by contacting the outer edges or outer peripheral surfaces of the two main surfaces of the semiconductor wafer; The semiconductor wafer measurement stage is configured so that the portions of the clamps that come into contact with the semiconductor wafer are arc-shaped when viewed from a position facing the main surface.

2. 2. The semiconductor wafer measurement stage according to claim 1, A semiconductor wafer measurement stage including a support that supports an outer edge of one of the main surfaces of the semiconductor wafer from below.

3. 3. The semiconductor wafer measurement stage according to claim 2, the plurality of clamps each having a clamp groove into which the wafer is fitted; The clamp groove is configured so that the semiconductor wafer supported by the support body rises when the semiconductor wafer is fitted into the clamp groove.

4. 2. The semiconductor wafer measurement stage according to claim 1, the plurality of clamps are configured such that, when viewed from a position facing the main surface, a first contact ratio calculated by dividing the total length of contact portions of all the clamps with the semiconductor wafer by the diameter of the semiconductor wafer is 1.21 or more.

5. 2. The semiconductor wafer measurement stage according to claim 1, the clamp includes at least one clamping portion that contacts the semiconductor wafer; the clamping portion is configured so that, when viewed from a position facing the main surface, a second contact ratio calculated by dividing the length of the contact portion with the semiconductor wafer by the diameter of the semiconductor wafer is 0.70 or less.

6. 6. The semiconductor wafer measurement stage according to claim 5, The plurality of clamps includes a first set of clamps consisting of two or more of the clamps, and a second set of clamps consisting of the same number of clamps as the first set of clamps, a semiconductor wafer measurement stage in which the first set of clamps and the second set of clamps clamp the semiconductor wafer by moving from positions on either side of a first imaginary line including the center of the semiconductor wafer, when viewed from a position facing the main surface, in directions approaching each other along a second imaginary line that is perpendicular to the first imaginary line.

7. a semiconductor wafer measurement stage according to any one of claims 1 to 6; a measuring unit that measures the height of defects on the main surface of the semiconductor wafer clamped by the plurality of clamps.

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