Semiconductor integrated circuit and electronic device

Abstract

To provide a semiconductor integrated circuit and an electronic apparatus which achieve both high quality and high-speed start.SOLUTION: The semiconductor integrated circuit includes a first circuit configured to output a first current based on the first voltage, a second circuit configured to output a second current that is larger than the first current and based on the first voltage, a smoothing circuit including a capacitor and configured to smooth an output of the first circuit, and a third circuit configured to output a third current based on the first voltage. And a control circuit capable of outputting a first current from the first circuit and a second current from the second circuit to the capacitor in parallel, stopping the output of the second current to the capacitor after a lapse of a first time from the output of the second current to the capacitor, and outputting a third current from the third circuit after a lapse of a second time longer than the first time from the stop of the output of the second current to the capacitor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor integrated circuit and an electronic device. [Background technology]

[0002] In semiconductor integrated circuits, BGR (Band Gap Reference) circuits are used to generate reference voltages. BGR circuits generate the reference potential used in semiconductor integrated circuits, so they are required to have low temperature dependency and high voltage stability.

[0003] Mobile communication devices and other devices require fast startup of power supply circuits, including BGR circuits. At the same time, to improve communication quality, the BGR circuits included in the power supply circuits are required to have a high power supply rejection ratio (PSRR).

[0004] Generally, a low-pass filter (LPF) is placed in the output stage to stabilize the power supply voltage generated by the power supply circuit. However, the capacitance component of the LPF causes a delay in the rise of the output voltage (i.e., power supply voltage) of the power supply circuit, making it difficult to achieve fast startup of the power supply circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-114325 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment is to provide a semiconductor integrated circuit and electronic equipment that achieve both high quality and fast startup. [Means for solving the problem]

[0007] A semiconductor integrated circuit of an embodiment is a semiconductor integrated circuit that generates a first voltage of a first value, and includes: a first circuit capable of outputting a first current based on the first voltage; a second circuit capable of outputting a second current that is larger than the first current and based on the first voltage; a smoothing circuit having a capacitor and capable of smoothing the output of the first circuit; a third circuit capable of outputting a third current based on the first voltage; and a control circuit that is capable of outputting a first current from the first circuit and a second current from the second circuit in parallel to the capacitor, stopping the output of the second current to the capacitor a first time after the second current is output to the capacitor, and outputting the third current from the third circuit a second time after the output of the second current to the capacitor is stopped, the second time being longer than the first time. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating an example of a semiconductor integrated circuit according to a first embodiment. [Figure 2] 4 is a flowchart showing an example of a control operation in the semiconductor integrated circuit of the first embodiment. [Figure 3] 4 is a timing chart showing an example of a control operation in the semiconductor integrated circuit of the first embodiment. [Figure 4] FIG. 2 is a circuit diagram illustrating a first state of a control operation in the semiconductor integrated circuit of the first embodiment. [Figure 5] FIG. 4 is a circuit diagram illustrating a second state of the control operation in the semiconductor integrated circuit of the first embodiment. [Figure 6] FIG. 4 is a circuit diagram illustrating a third state of the control operation in the semiconductor integrated circuit of the first embodiment. [Figure 7] FIG. 10 is a circuit diagram illustrating a fourth state of the control operation in the semiconductor integrated circuit of the first embodiment. [Figure 8] 10 is a flowchart showing a control operation of a modified example of the semiconductor integrated circuit of the first embodiment. [Figure 9]6 is a timing chart showing an example of a control operation in a semiconductor integrated circuit according to a modified example of the first embodiment. [Figure 10] FIG. 10 is a block diagram showing the configuration of an electronic device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Configuration of the first embodiment) 1 shows an example of a semiconductor integrated circuit according to a first embodiment. The semiconductor integrated circuit 1 serving as a BGR circuit includes a voltage source circuit 10, a scaling circuit 20, a low-pass filter (LPF) 14, a voltage divider circuit 30, a current mirror circuit 40, and a control circuit 50. The voltage source circuit 10 includes an output circuit 12. The scaling circuit 20 and the current mirror circuit 40 share some of the circuitry. The LPF 14 and the voltage divider circuit 30 share some of the circuitry.

[0010] A voltage source circuit 10 (first circuit) generates a reference voltage. In the example shown in FIG. 1, the voltage source circuit 10 includes MOSFETs Q1, Q2, and Q5, an operational amplifier U, transistors Q3 and Q4, and resistors R1 to R4. The MOSFETs Q1 and Q2 each have a source connected to a power supply line Vdd and gates connected to each other. The MOSFET Q1 has a drain connected to a ground line via a resistor R1. The MOSFET Q2 has a drain connected to a ground line via a resistor R2. The power supply line Vdd is a line that supplies a potential that serves as a power supply voltage when the semiconductor integrated circuit 1 operates. The ground line is a line that supplies a reference potential when the semiconductor integrated circuit 1 operates.

[0011] Op-amp U has an output connected to the gates of MOSFETs Q1 and Q2, an inverting input connected to the drain of MOSFET Q1, and a non-inverting input connected to the drain of MOSFET Q2. Transistor Q3 has a base, an emitter connected to the inverting input and base of op-amp U, and a collector connected to ground. Transistor Q4 has a base, an emitter connected to the base, and a collector connected to ground. The emitter and base of transistor Q4 are connected to the non-inverting input of op-amp U via resistor R3.

[0012] The operational amplifier U negatively feeds back the difference between the drain voltage of the MOSFET Q1 and the drain voltage of the MOSFET Q2 to the gate of the MOSFET Q1 and the gate of the MOSFET Q2. This keeps the drain voltage of the MOSFET Q1 and the drain voltage of the MOSFET Q2 equal. In other words, the operational amplifier U can stabilize the output voltage.

[0013] MOSFET Q5 has a source connected to the power supply line Vdd, a gate connected to the gates of MOSFETs Q1 and Q2, and a drain connected to the ground line via resistor R4. MOSFETs Q1, Q2, and Q5 form a current mirror. This current mirror and operational amplifier U work together as a constant current circuit that keeps the drain currents of MOSFETs Q1, Q2, and Q5 constant. MOSFET Q5 and resistor R4 form output circuit 12 included in voltage source circuit 10.

[0014] In FIG. 1, the drain voltage of MOSFET Q1 and the drain voltage of MOSFET Q2 are equalized and stabilized by the action of the current mirror formed by MOSFETs Q1, Q2, and Q5 and the action of operational amplifier U. Here, the emitter-collector voltage of transistor Q4 has a negative coefficient with respect to temperature, so the current flowing through resistor R2 also has a negative coefficient with respect to temperature. On the other hand, resistor R3 generally has a positive coefficient with respect to temperature. Therefore, the temperature dependence of the current flowing through resistor R2 and the temperature dependence of the current flowing through resistor R3 are canceled out, and the drain current of MOSFET Q5 included in output circuit 12 becomes a current that is independent of temperature. In other words, transistors Q3 and Q4 and resistors R1 to R3 function as a temperature compensation circuit.

[0015] In this way, voltage source circuit 10 can output a stabilized voltage that is not temperature dependent.

[0016] Scaling circuit 20 (fourth circuit) scales the output current of voltage source circuit 10. That is, scaling circuit 20 increases the output current of voltage source circuit 10. In the example shown in FIG. 1, scaling circuit 20 includes MOSFETs Q6a and Q6b, switches SW1a-1c, SW2a-SW2b, and SW3a-SW3d, and resistors R5a and R5b. MOSFET Q6a has a source connected to power supply line Vdd, a gate connected to switches SW1a and SW2a, and a drain connected to ground via resistor R5a and switch SW3a. Similarly, MOSFET Q6b has a source connected to power supply line Vdd, a gate connected to switches SW1b, SW1c, and SW2b, and a drain connected to ground via resistor R5b and switch SW3b. Switches SW1a-SW1c, SW2a-SW2b, and SW3c-SW3d can be realized by, for example, transfer gates. The switches SW3a and SW3b can be realized by switching elements such as MOSFETs.

[0017] The gate of MOSFET Q6a is connected to the gate of MOSFET Q5 of voltage source circuit 10 (output circuit 12) via switch SW1a. That is, when switch SW1a is on, MOSFETs Q1, Q2, Q5, and Q6a form a current mirror. The gate of MOSFET Q6a is connected to power supply line Vdd via switch SW2a. The drain of MOSFET Q6a is connected to the drain of MOSFET Q5 via switch SW3c. The drain of MOSFET Q6a is also connected to LPF 14, which includes switch SW4, via switch SW3c.

[0018] The gate of MOSFET Q6b is connected to the gate of MOSFET Q5 of voltage source circuit 10 (output circuit 12) via switches SW1b and SW1a. That is, when switches SW1a and SW1b are on, MOSFETs Q1, Q2, Q5, Q6a, and Q6b form a current mirror. The gate of MOSFET Q6b is connected to power supply line Vdd via switch SW2b. The gate of MOSFET Q6b is connected to the drain of MOSFET Q6b via switch SW1c. The drain of MOSFET Q6b is connected to the drain of MOSFET Q5 via switch SW3d. The drain of MOSFET Q6b is connected to LPF 14, including switch SW4, via switch SW3d.

[0019] The MOSFETs Q6a and Q6b of the scaling circuit 20 have a larger wiring width than the MOSFET Q5 of the voltage source circuit 10. This means that the MOSFETs Q6a and Q6b can pass a larger current than the MOSFET Q5. In other words, the scaling circuit 20 acts as a circuit that scales the output current of the voltage source circuit 10.

[0020] The LPF14 (smoothing circuit) smoothes the voltage (output voltage) of the output BGRVout of the semiconductor integrated circuit 1. The LPF14 has a switch SW4, a resistor R6, and a capacitor C, and constitutes a so-called CR filter. The switch SW4 and the resistor R6 are connected in parallel. One end of the resistor R6 is connected to the drain of the MOSFET Q5, and the other end of the resistor R6 is connected to one end of the capacitor C. The other end of the capacitor C is connected to the ground wiring. The intersection of the other end of the resistor R6 and one end of the capacitor C is connected to the output BGRVout.

[0021] When switches SW1a, SW1b, SW3a-SW3d, SW4, and SW7b are on and switches SW1c, SW2a, and SW2b are off, the gates of MOSFETs Q6a and Q6b are connected to the gate of MOSFET Q5 in voltage source circuit 10 (output circuit 12), and the drains of MOSFETs Q6a and Q6b are connected to the ground wiring via resistors R5a and R5b. In this state, scaling circuit 20 begins operating, and the outputs of voltage source circuit 10 and scaling circuit 20 are input to capacitor C of LPF 14 via switch SW4. This operation serves to quickly stabilize the output voltage of output BGRVout.

[0022] On the other hand, when switches SW1a, SW1b, SW3a to SW3d, SW4, and SW7b are off and switches SW1c, SW2a, and SW2b are on, scaling circuit 20 stops operating. In this state, the output of voltage source circuit 10 is input directly to resistor R6 of LPF 14.

[0023] The voltage divider circuit 30 (second circuit) quickly raises the output voltage of the output BGRVout. The voltage divider circuit 30 has resistors R7 and R8 connected in series and switches SW5 and SW6. One end of the resistor R7 is connected to one end of the resistor R8. The other end of the resistor R7 is connected to the power supply wiring Vdd. The other end of the resistor R8 is connected to the ground wiring via the switch SW6. The intersection of the resistors R7 and R8 is connected to the intersection of the other end of the resistor R6 in the LPF 14 and one end of the capacitor C via the switch SW5. The switches SW5 and SW6 can be turned on or off by an external control signal.

[0024] When switches SW5 and SW6 are on, resistors R7 and R8 act as voltage dividing resistors for the voltage of the power supply line Vdd, and the divided voltage is input to capacitor C of LPF 14 via switch SW5. This operation acts to quickly raise the output voltage of output BGRVout. Switches SW4 and SW5 can be realized by, for example, transfer gates (transmission gates). Switch SW6 can be realized by, for example, a switching element such as a MOSFET.

[0025] The current mirror circuit 40 (third circuit) is a current source that cooperates with the voltage source circuit 10 to generate a stable current. The current mirror circuit 40 includes MOSFETs Q6a and Q6b, Q7a to Q7d, and switches SW1a to SW1d, SW2a to SW2c, SW7a, and SW7b. The MOSFETs Q7a and Q7b each have a source connected to the power supply line Vdd and a gate connected to the gate of the MOSFET Q6b of the scaling circuit 20 via the switch SW1d. The gates of the MOSFETs Q7a and Q7b are connected to the power supply line Vdd via the switch SW2c. The MOSFET Q7a has a drain that outputs current via the output BGRIout0. The MOSFET Q7b has a drain that outputs current via the output BGRIout1. The switches SW1d and SW2c can be implemented, for example, by transfer gates (transmission gates). The switches SW1d and SW2c are controlled to be exclusively turned on or off.

[0026] MOSFETs Q7c and Q7d have drains connected to the drains of MOSFETs Q6a and Q6b, gates connected to each other, and sources connected to ground. The gate of MOSFET Q7c is connected to the drain of MOSFET Q7c via switch SW7a, and the gate of MOSFET Q7d is connected to ground via switch SW7b. Switches SW7a and SW7b can be realized by, for example, transfer gates.

[0027] When the switches SW1a, SW1c, SW1d, and SW7a are turned on and the switches SW2a to SW2c and SW7b are turned off, the current mirror circuit 40 made up of the MOSFETs Q6a, Q6b, and Q7a to Q7d is activated, that is, a current is output via the outputs BGRIout0 and BGRIout1.

[0028] 1, the current mirror circuit 40 of the first embodiment uses the MOSFETs Q6a to Q6b of the scaling circuit 20. That is, part of the circuit configuration required for the current mirror circuit 40 is shared with part of the circuit configuration of the scaling circuit 20. This contributes to reducing the required area of ​​the semiconductor integrated circuit 1.

[0029] The control circuit 50 generates a plurality of control signals at predetermined timings to control the switches SW1a to SW1d, SW2a to SW2c, SW3a to SW3d, SW4, SW5 and SW6, and SW7a and SW7b. In the semiconductor integrated circuit 1 of the first embodiment, the control circuit 50 generates four states, namely, a control state FWAKE, a control state Bypass, a control state Enable, and a control state Disable, based on the plurality of control signals. The control circuit 50 is, for example, an electronic circuit equipped with a processor or a sequencer.

[0030] The control state FWAKE enables the voltage divider circuit 30. The control circuit 50 generates the control state FWAKE by turning on the switches SW5 and SW6, and activates the voltage divider circuit 30.

[0031] The control state Bypass enables the scaling circuit 20. The control circuit 50 generates the control state Bypass by controlling the switches SW1a and SW1b, SW3a to SW3d, SW4, and SW7b to be on, and starts the scaling circuit 20.

[0032] The control state Enable enables the current mirror circuit 40. The control circuit 50 generates the control state Enable by controlling the switches SW1a, SW1c, SW1d, and SW7a to be on, and starts the current mirror circuit 40.

[0033] The control state Disable disables the current mirror circuit 40. The control circuit 50 controls the switches SW2a to SW2c, and SW7b to be on and the switches SW1a, SW1c, SW1d, and SW7a to be off, thereby generating the control state Disable and disabling the control state Enable, thereby stopping the current mirror circuit 40.

[0034] When the control state Enable that enables the current mirror circuit 40 is in a state other than on, the switch SW2c is controlled to the on state so that no current is output via the outputs BGRIout0 and BGRIout1.

[0035] (Operation of the first embodiment) Next, the operation of the semiconductor integrated circuit 1 of the first embodiment will be described with reference to FIGS. 1 to 7. FIG. 2 is a flowchart showing an example of a control operation in the semiconductor integrated circuit of the first embodiment. FIG. 3 is a timing chart showing an example of a control operation in the semiconductor integrated circuit of the first embodiment. FIG. 4 is a circuit diagram explaining a first state of the control operation in the semiconductor integrated circuit of the first embodiment. FIG. 5 is a circuit diagram explaining a second state of the control operation in the semiconductor integrated circuit of the first embodiment. FIG. 6 is a circuit diagram explaining a third state of the control operation in the semiconductor integrated circuit of the first embodiment. FIG. 7 is a circuit diagram explaining a fourth state of the control operation in the semiconductor integrated circuit of the first embodiment.

[0036] 2 and 3, at time t1 (first state), when the control circuit 50 receives a BGR enable signal that enables circuit operation (S100), the control circuit 50 outputs control signals that enable (ON) the Bypass and FWAKE control states, and control signals that disable (OFF) the Enable and Disable control states (S110). As a result, as shown in FIG. 4, SW1a, SW1b, SW2c, SW3a-SW3d, switch SW4, and switch SW7b are turned on to turn the Bypass control state on, switches SW5 and SW6 are turned on to turn the FWAKE control state on, switches SW1c, SW1d, and SW7a are turned off to turn the Enable control state off, and switches SW2a, SW2b, and SW7b are turned off to turn the Disable control state off. To turn the Enable control state off, switch SW1a is turned off, but to turn the Bypass control state on, switch SW1a is turned on. To turn off the control state Disable, the switches SW2c and SW7b are turned off, but to turn on the control state Bypass, the switches SW2c and SW7b are turned on. In this state, the scaling circuit 20 (Circuit-1) and the voltage dividing circuit 30 (Circuit-2) are activated, and the current mirror circuit 40 (Circuit-3) is in an inactive state because SW2c is on.

[0037] At this time, the voltage source circuit 10 outputs a predetermined voltage, and a current I1 flows from the drain of the MOSFET Q5 to the switch SW4. The current I1 flows to the capacitor C of the LPF 14.

[0038] The scaling circuit 20 starts operating when the Bypass control state is turned on. Furthermore, because the Bypass control state is on, the switch SW4 is turned on. At this time, a current I2 flows from the drains of the MOSFETs Q6a and Q6b to the capacitor C of the LPF 14 via the switch SW4.

[0039] Furthermore, the voltage divider circuit 30 starts operating when the control state FWAKE is turned on. The voltage of the power supply line Vdd is divided by the resistors R7 and R8. At this time, a current I3 flows from the intersection of one end of the resistors R7 and R8 toward the capacitor C of the LPF 14.

[0040] The current mirror circuit 40 is not activated because the control state Enable is off, so no current flows through the outputs BGRIout0 and BGRIout1.

[0041] As shown in FIG. 3, at time t1, when the BGR enable signal goes high, the FWAKE and Bypass control states are turned on. Meanwhile, the Enable control state remains off. The voltage source circuit 10, scaling circuit 20, and voltage divider circuit 30 are activated, and an output voltage appears at the output BGRVout. The current mirror circuit 40 is not activated, and no current flows through the outputs BGRIout0 and BGRIout1. At this time, the current I1 from the voltage source circuit 10 is added to the current I2 from the scaling circuit 20 and the current I3 from the voltage divider circuit 30, and the capacitor C of the LPF 14 is charged.

[0042] As a result, the rise of the output voltage when scaling circuit 20 and voltage divider circuit 30 are activated in parallel approaches the target voltage more quickly than the rise of the output voltage when only voltage source circuit 10 is activated. As shown in Figure 3, when the voltage of power supply wiring Vdd is at the minimum condition (Min) (dashed line in Figure 3), the rise is slower than when the voltage of power supply wiring Vdd is at the maximum condition (Max) (solid line in Figure 3), but it is faster than the rise of the output voltage when only voltage source circuit 10 is activated.

[0043] 2 and 3, at time t2 (second state), the control circuit 50 outputs a control signal that turns off the control state FWAKE, maintains the control signal that turns on the control state Bypass, and maintains the control signals that turn off the control states Enable and Disable (S120). As a result, as shown in FIG. 5, switches SW5 and SW6 turn off, switches SW1a, SW1b, SW2c, SW3a-SW3d, switch SW4, and switch SW7b remain on, switches SW1c, SW1d, and SW7a remain off, and switches SW2a and SW2b remain off. As a result, the voltage-dividing circuit 30 stops operating, current I3 becomes zero, and the current flowing to capacitor C of the LPF 14 decreases.

[0044] As shown in FIG. 3, at time t2, when the control state FWAKE is controlled to be OFF, the current I3 from the voltage divider circuit 30 is no longer added to the current I1 from the voltage source circuit 10. As a result, when the voltage of the power supply wiring Vdd is at the maximum condition (Max), the output voltage of the output BGRVout changes from rising to falling. That is, by controlling the current I3 from the voltage divider circuit 30, the output voltage of the output BGRVout rises quickly, and after exceeding the target voltage, the output voltage drops. The time t during which the control state FWAKE is maintained ON FWAKE is set at a timing that allows the output voltage of the output BGRVout to drop quickly without exceeding the target voltage too much. Also, when the voltage of the power supply wiring Vdd is at the minimum condition (Min), the slope of the rise in the output voltage becomes a little gentler.

[0045] 2 and 3, at time t3 (third state), the control circuit 50 outputs a control signal that turns off the Bypass control state and outputs a control signal that turns on the Enable control state. The control circuit 50 also maintains the control signals that turn off the FWAKE and Disable control states (S130). As a result, as shown in FIG. 6, the switches SW1b, SW2c, SW3a-SW3d, SW4, and SW7b are turned off, while the switches SW2a and SW2b, and the switches SW5 and SW6 are maintained off. The switches SW1a, SW1c, SW1d, and SW7a are also turned on. This causes the scaling circuit 20 to stop operating, so the current I2 becomes zero and the current flowing to the capacitor C of the LPF 14 is further reduced.

[0046] As shown in Figure 3, at time t3, with the control state FWAKE and the control state Disable maintained at OFF, the control state Bypass is controlled to OFF and the control state Enable is controlled to ON, and the drain voltage of the MOSFET Q5 of the voltage source circuit 10 is applied directly to the resistor R6 of the LPF 14, and the only current flowing through the capacitor C of the LPF 14 is the current I1. The output voltage of the output BGRVout, which rose quickly at time t1, begins to decrease or rises slowly at time t2, and converges to the target voltage at time t3. The time t during which the control state Bypass is maintained ON Bypass is set to the timing when the output voltage converges to the target voltage. For example, at time t Bypass is set to a value not exceeding 50 μs. Then, when the control state Enable is turned on, the current mirror circuit 40 is activated.

[0047] 2, at time t3, the control circuit 50 turns off the control state Bypass and the control state FWAKE, and then the semiconductor integrated circuit 1 outputs a stable voltage (S140). At this stage, the scaling circuit 20 and the voltage dividing circuit 30 are not activated, and the current mirror circuit 40 is activated. That is, as shown in FIG. 3, the current mirror circuit 40 acts as a current source and outputs current from the outputs BGRIout0 and BGRIout1.

[0048] 2 and 3, at time t4 (fourth state), the control circuit 50 outputs a control signal that turns off the control state Enable and outputs a control signal that turns on the control state Disable. The control circuit 50 also maintains the control signals that turn off the control state FWAKE and the control state Bypass (S150). As a result, as shown in FIG. 7, the switches SW1a-SW1d, SW3a-SW3d, SW4, and SW7a are turned off, the switches SW2a-SW2c and SW7b are turned on, and the switches SW5 and SW6 are maintained off. This causes the current mirror circuit 40 to stop operating, thereby stopping the currents from the outputs BGRIout0 and BGRIout1.

[0049] The current I1 output from the voltage source circuit 10, the current I2 output from the scaling circuit 20, and the current I3 output from the voltage dividing circuit 30 have the following relationships. I1 <I2<I3 That is, the voltage dividing circuit 30 can most quickly charge the capacitor C of the LPF 14. However, the voltage based on the current I3 output from the voltage dividing circuit 30 varies greatly in value because it is generated by dividing the power supply line Vdd.

[0050] On the other hand, the current I2 output from scaling circuit 20 is smaller than the current I3 output from voltage divider circuit 30, and therefore the charging speed of capacitor C of LPF 14 is not as fast as that of voltage divider circuit 30. However, the output voltage of scaling circuit 20 is obtained by scaling current I1 output from voltage source circuit 10, and therefore the voltage value is stable.

[0051] In the semiconductor integrated circuit 1 of the first embodiment, in order to quickly raise the output voltage of the output BGRVout when the voltage source circuit 10 is started up, FWAKE and time t Bypass During the AND period of time t, the output of the scaling circuit 20 and the output of the voltage divider circuit 30 are both added to the output of the voltage source circuit 10. On the other hand, since the value of the current I3 output from the voltage divider circuit 30 is relatively large, there is a possibility that the output voltage of the output BGRVout will exceed the target voltage. FWAKE After the time has elapsed, the operation of the voltage dividing circuit 30 and its output are stopped.

[0052] The current I2 output from the scaling circuit 20 is smaller than the current I3 output from the voltage divider circuit 30. However, if the rise delay of the output voltage of the output BGRVout is eliminated, a stable output can be achieved by the operation of the voltage source circuit 10 alone, even if the operation of the scaling circuit 20 is stopped. Therefore, the semiconductor integrated circuit 1 determines the timing at which the output voltage of the output BGRVout converges to the target voltage, that is, the time t Bypass After this time has elapsed, the operation of the scaling circuit 20 and its output are stopped.

[0053] Time t Bypass After a lapse of time, that is, at time t3, the control state Bypass is turned off, turning off the switch SW4. Therefore, the output of the voltage source circuit 10 is smoothed by the LPF 14 and output from the output BGRVout.

[0054] As described above, the semiconductor integrated circuit 1 of the first embodiment includes the scaling circuit 20 and the voltage dividing circuit 30 in addition to the voltage source circuit 10, and therefore can quickly raise the output voltage and quickly converge it to the target voltage.

[0055] Furthermore, the semiconductor integrated circuit 1 of the first embodiment transitions sequentially from a first state to a fourth state. In the first state, the scaling circuit 20 and the voltage divider circuit 30 are activated, but the current mirror circuit 40 is not activated. In the second state, the scaling circuit 20 is activated, but the voltage divider circuit 30 and the current mirror circuit 40 are not activated. In the third state, the current mirror circuit 40 is activated, but the scaling circuit 20 and the voltage divider circuit 30 are not activated. In the fourth state, the current mirror circuit 40 is deactivated, and only the voltage source circuit 10 is activated.

[0056] In the semiconductor integrated circuit 1 of the first embodiment, the output voltage of the output BGRVout rises quickly from the first state to the third state.

[0057] On the other hand, in the third state, the scaling circuit 20 and the voltage divider circuit 30 are disabled (do not start operating) and start operating the current mirror circuit 40. In the semiconductor integrated circuit 1 of the first embodiment, in the third state, the operation of the current mirror circuit 40 makes it possible to output stable currents from the outputs BGRIout0 and BGRIout1.

[0058] Furthermore, in the fourth state, the current mirror circuit 40 stops operating. This operation stops the constant current output, making it possible to reduce power consumption.

[0059] (Modification of the operation of the first embodiment) In the first embodiment described above, the outputs of scaling circuit 20 and voltage divider circuit 30 are added to the output of voltage source circuit 10 when voltage source circuit 10 is started up, but this is not limiting. It may also be configured so that only the output of voltage divider circuit 30 is added when voltage source circuit 10 is started up. Below, with reference to Figures 1, 8 and 9, a modified example in which only the output of voltage divider circuit 30 is added when voltage source circuit 10 is started up will be described.

[0060] As shown in Figures 8 and 9, at time t5, when the BGR enable signal becomes H level and the control circuit 50 receives the BGR enable signal (S100), the control circuit 50 outputs a control signal that enables (turns on) the control state FWAKE and also outputs a control signal that turns on the control state Disable to turn off the control state Bypass (S115). At this point, the control circuit 50 does not turn on the control state Bypass and the control state Enable, but keeps them off. The voltage source circuit 10 and the voltage divider circuit 30 start up, and an output voltage appears at the output BGR Vout. At this time, the current I1 from the voltage source circuit 10 is added to the current I3 from the voltage divider circuit 30, and the resulting current flows toward the capacitor C of the LPF 14.

[0061] As a result, the rise of the output voltage when the voltage divider circuit 30 is started in parallel approaches the target voltage more quickly than the rise of the output voltage when only the voltage source circuit 10 is started.

[0062] The current mirror circuit 40 is not activated because the control state Enable is off, so no current flows from the outputs BGRIout0 and BGRIout1.

[0063] Subsequently, at time t6, the control circuit 50 controls the control state FWAKE to be turned off, and the current I3 is no longer added to the current directed to the capacitor C of the LPF 14. Also, at time t6, the control circuit 50 outputs a control signal that enables the control state Bypass and a control signal that disables the control state Disable (S120). As a result, when the voltage of the power supply wiring Vdd is at the maximum condition (Max), the output voltage of the output BGRout changes from rising to falling. That is, by switching to the current I2 from the scaling circuit 20, which is smaller than the current I3 from the voltage dividing circuit 30, the output voltage drops after exceeding the target voltage. The time t during which the control circuit 50 maintains the control state FWAKE on FWAKE is set at a timing that allows the output voltage of the output BGRVout to drop quickly without exceeding the target voltage too much. Also, when the voltage of the power supply wiring Vdd is at the minimum condition (Min), the slope of the rise in the output voltage becomes a little gentler.

[0064] Subsequently, at time t7, when the control circuit 50 outputs a control signal to disable the Bypass control state, the drain voltage of the MOSFET Q5 of the voltage source circuit 10 is applied directly to the resistor R6 of the LPF 14, and the only current flowing through the capacitor C of the LPF 14 is the current I1. The output voltage of the output BGRVout, which rose quickly at time t5, begins to decrease or rises slowly at time t6, and converges to the target voltage at time t7. The time t during which the Bypass control state is maintained on Bypass is set to the timing when the output voltage converges to the target voltage. For example, at time t Bypass is set to a value not exceeding 50 μs.

[0065] Furthermore, at time t7, the control circuit 50 outputs a control signal that enables the control state Enable (S130). As shown in Fig. 9, at time t7, when the control state Bypass and the control state FWAKE are controlled to be OFF and the control state Enable is controlled to be ON, the current mirror circuit 40 is activated and currents are output from the outputs BGRIout0 and BGRIout1.

[0066] 8 and 9, at time t8, the control circuit 50 outputs a control signal to turn off the control state Enable and outputs a control signal to turn on the control state Disable. The control circuit 50 also maintains the control state FWAKE and the control state Bypass in the off state (S150). This causes the current mirror circuit 40 to stop operating, and the currents from the outputs BGRIout0 and BGRIout1 stop.

[0067] This modification also provides the same effects as the first embodiment.

[0068] (Second embodiment) Next, an electronic device according to a second embodiment will be described with reference to Fig. 10. In the following description, elements common to the first embodiment will be denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0069] 10, the electronic device 2 of the second embodiment constitutes a memory system. The electronic device 2 includes a semiconductor integrated circuit 1 as a BGR circuit according to the first embodiment, a controller 200, a memory 210, and a power management IC (PMIC) 220. The electronic device 2 can be connected to a host 3 via a signal line B and a power supply wiring Vdd. The signal line B is, for example, a bus line for transmitting and receiving signals between the electronic device 2 and the host 3. The power supply wiring Vdd is, for example, a power supply line capable of supplying a predetermined voltage from the host 3 to the electronic device 2.

[0070] The controller 200 is a circuit element that receives commands from the host 3 and performs functions such as reading, writing, erasing, and initializing data from and to the memory 210. The controller 200 is, for example, an electronic circuit equipped with a processor that performs the above-mentioned functions, and is configured as, for example, an SoC. The memory 210 is, for example, a semiconductor storage device including a NAND flash memory. The memory 210 is connected to the controller 200 by, for example, a bus line including a signal line C based on a predetermined standard. The controller 200 can receive a current supply from the semiconductor integrated circuit 1 via an output BGRIout1.

[0071] The PMIC 220 is a circuit element capable of generating a plurality of output voltages each having a different voltage value. The PMIC 220 receives the output voltage of the output BGRVout of the semiconductor integrated circuit 1 and the current from the output BGRIout0, generates various output voltages such as V+, and supplies these to the controller 200, the memory 210, etc.

[0072] When receiving a voltage supply via the power supply wiring Vdd, the semiconductor integrated circuit 1 as a BGR circuit, by the operation of the first embodiment or the modified example, supplies a high-quality output voltage from the output BGRVout that rises quickly and a current from the output BGRIout0 to the PMIC 220. Upon receiving the output voltage from the output BGRVout and the current from the output BGRIout0, the PMIC 220 generates an output voltage V+ and the like and supplies them to the controller 200 and the memory cell 210.

[0073] According to the electronic device 2 of the second embodiment, since it is equipped with a semiconductor integrated circuit 1 as a BGR circuit according to the first embodiment or its modified example, it is possible to achieve high quality and fast startup for the power supply voltage used inside the device.

[0074] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0075] 1...semiconductor integrated circuit, 2...electronic device, 3...host, 10...voltage source circuit, 12...output circuit, 14...LPF, 20...scaling circuit, 30...voltage divider circuit, 40...current mirror circuit, 50...control circuit, Q1 to Q2, Q5, Q6a to Q6b, Q7a to Q7b...MOSFETs, Q3 to Q4...transistors, SW1a to SW1d, SW2a to SW2c, SW3a to SW3d, SW4 to SW6, SW7a to SW7b...switches, R1 to R8...resistors, U...op-amp, C...capacitor, 200...controller, 210...memory cell, 220...power management IC

Claims

1. A semiconductor integrated circuit that generates a first voltage of a first value, a first circuit capable of outputting a first current based on the first voltage; a second circuit capable of outputting a second current greater than the first current and based on the first voltage; a smoothing circuit having a capacitor and capable of smoothing the output of the first circuit; a third circuit capable of outputting a third current based on the first voltage; a control circuit that is capable of outputting the first current from the first circuit and the second current from the second circuit in parallel to the capacitor, stopping the output of the second current to the capacitor after a first time has elapsed since the output of the second current to the capacitor, and outputting the third current from the third circuit after a second time, which is longer than the first time, has elapsed since the output of the second current to the capacitor has been stopped; A semiconductor integrated circuit comprising:

2. a fourth circuit capable of outputting a fourth current that is greater than the first current and smaller than the second current and that is based on the first voltage; The control circuit is further configured to output the fourth current from the fourth circuit in parallel to the capacitor in addition to the first current from the first circuit and the second current from the second circuit, and to stop outputting the fourth current after the second time has elapsed.

2. The semiconductor integrated circuit according to claim 1.

3. a fourth circuit capable of outputting a fourth current that is greater than the first current and smaller than the second current and that is based on the first voltage; The control circuit is further configured to output the fourth current from the fourth circuit to the capacitor in parallel with the first current after the first time has elapsed, and to stop outputting the fourth current after the second time has elapsed.

2. The semiconductor integrated circuit according to claim 1.

4. the first circuit includes a constant current circuit and a temperature compensation circuit; The second circuit includes a voltage divider circuit that generates the first voltage from a second voltage that is higher than the first voltage.

2. The semiconductor integrated circuit according to claim 1.

5. 2. The semiconductor integrated circuit according to claim 1, wherein the first time period is determined based on the timing at which the output of the first current from the first circuit exceeds a target voltage.

6. Memory and a memory controller that controls the memory; a semiconductor integrated circuit according to claim 1 , which generates the first voltage as a reference for a power supply voltage supplied to at least one of the memory and the memory controller; An electronic device comprising:

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