Wiring board and method of manufacturing wiring board

Abstract

To improve the quality of a wiring board.SOLUTION: The wiring substrate 1 of the embodiment includes the first conductor layer 11, the insulating layer 20 formed on the first conductor layer 11, the second conductor layer formed on the insulating layer 20, and the via conductors 21 penetrating the insulating layer 20 and connecting the first conductor layer 11 and the second conductor layer. Then, in the first conductive layer 11, the outer edge portions of the side surfaces 115 and the upper surface 110 are covered by the insulating layer 20, the central portion of the upper surface 110 includes the conductive pads (11p) that are in contact with the via conductors 21, and the striped unevenness that is substantially parallel to the thickness direction of the interconnect substrate 1 is formed around the entire circumference of the side surfaces of the conductive pads (11p).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 relates to a printed wiring board and discloses that a chemical conversion coating is formed on the surface of a low-roughness or non-roughness metal wiring layer, and an insulating resin layer is formed on the metal wiring layer via this chemical conversion coating. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-172759 Summary of the Invention [Problem to be solved by the invention]

[0004] In the printed wiring board manufactured by the method disclosed in Patent Document 1, interfacial peeling may occur between the conductive pads included in the metal wiring layer and the resin insulating layer during the manufacturing process of the printed wiring board, which may result in deterioration of the quality of the printed wiring board. [Means for solving the problem]

[0005] The wiring board of the present invention includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, and a via conductor that penetrates the insulating layer and connects the first conductor layer and the second conductor layer. The first conductor layer has a side surface and an outer edge portion of an upper surface covered by the insulating layer, and includes a conductor pad at a central portion of the upper surface that contacts the via conductor, and striped irregularities are formed around the entire periphery of the side surface of the conductor pad that are approximately parallel to the thickness direction of the wiring board.

[0006] A method for manufacturing a wiring board of the present invention includes forming a first conductor layer having a conductor pad on a first insulating layer, forming a second insulating layer on the first conductor layer, forming a second conductor layer on the second insulating layer, and forming a via conductor that penetrates the second insulating layer and connects the conductor pad and the second conductor layer. The forming of the first conductor layer includes forming a conductor pad in the opening using a plating resist having an opening on a side surface with striped irregularities approximately parallel to the thickness direction of the wiring board.

[0007] According to the embodiment of the present invention, deterioration of the quality of the wiring board due to interfacial peeling between the conductor pad and the insulating layer can be suppressed on the side surface of the conductor pad that is in contact with the via conductor that connects the conductor layers together. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a plan view of the contact pad of FIG. 1; [Figure 2B] FIG. 2 is a side view of a portion of the contact pad of FIG. 1; [Figure 3] FIG. 10 is a plan view showing another example of a conductor pad of the wiring board according to one embodiment of the present invention. [Figure 4] FIG. 10 is a plan view showing another example of a conductor pad of the wiring board according to one embodiment of the present invention. [Figure 5A] 2B is a cross-sectional view taken along a cutting line overlapping line AA in FIG. 2A. [Figure 5B] 2B is a cross-sectional view taken along a cutting line overlapping the line BB in FIG. 2A. [Figure 6A] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 6B] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 6C] FIG. 6C is a plan view of the opening of FIG. 6B. [Figure 6D] FIG. 6C is a perspective view of the opening of FIG. 6B. [Figure 6E]5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 6F] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 6G] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of the present invention. [Figure 6H] 5A to 5C are cross-sectional views showing an example of a process of a method for manufacturing a wiring board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] A wiring board according to one embodiment of the present invention will be described with reference to the drawings. The drawings are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention. Wiring board 1, which is an example of a wiring board according to one embodiment, is a wiring board including a laminated structure formed by a plurality of conductor layers and insulating layers alternately stacked. Opposing conductor layers sandwiching an insulating layer are electrically connected by via conductors that penetrate the insulating layer in the thickness direction. The number of conductor layers and insulating layers included in wiring board 1 according to the embodiment is not limited and may be selected as appropriate. The laminated structure of wiring board 1 is also not limited.

[0010] FIG. 1 shows a cross-sectional view of a portion of a wiring board 1, which is an example of a wiring board according to this embodiment. FIG. 2A shows a plan view of a conductor pad 11p shown in FIG. 1. FIG. 2B shows a side view of a portion of the conductor pad 11p shown in FIGS. 1 and 2A. The wiring board 1 of the illustrated example includes an insulating layer 10 (first insulating layer), a conductor layer 11 (first conductor layer) formed on the insulating layer 10, an insulating layer 20 (second insulating layer) formed on the insulating layer 10 and the conductor layer 11, and a via conductor 21 connecting the conductor layer 11 to a conductor layer (second conductor layer, not shown) facing the conductor layer 11 across the insulating layer 20. A conductor pattern including the conductor pad 11p and a wiring pattern 11a is formed on the conductor pad 11p. The via conductor 21 is formed on the conductor pad 11p in contact with the conductor pad 11p. The conductor layer 11 is composed of a metal film layer 12 and a plating film layer 13 on the metal film layer 12. The via conductor 21 is composed of a metal film layer 22 and a plating film layer 23 on the metal film layer 22. The insulating layer 10 is provided with a via conductor 25 that connects the conductor layer 11 to a conductor layer (not shown) that faces the conductor layer 11 across the insulating layer 10.

[0011] In the description of the wiring board 1 of this embodiment, in relation to the insulating layer 10 and the conductor layer 11, the conductor layer 11 side, i.e., the upper side on the paper, is referred to as the "upper side" or simply "top," and the insulating layer 10 side is referred to as the "lower side" or simply "bottom." For example, the upper surface of the insulating layer 10 refers to the first surface 10F of the insulating layer 10.

[0012] The wiring board 1 is merely one example of the wiring board of this embodiment. Although one via conductor 21 and one conductor pad 11p are shown in Fig. 1, the numbers of via conductors 21 and conductor pads 11p are not limited. The via conductors 21 of the wiring board 1 of this embodiment can be formed in any desired position and in any desired number depending on the conductor patterns included in the upper and lower conductor layers to which they are connected.

[0013] The insulating layers 10 and 20 are formed of any insulating resin. Examples of insulating resins include epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin. The insulating layers 10 and 20 may further contain an inorganic filler (not shown) made of fine particles such as silica (SiO2), alumina, or mullite. The number of conductor layers and insulating layers formed below the insulating layer 10 and above the insulating layer 20 in the wiring substrate 1 is not limited. The insulating layer 10 may be a single layer, or may be a build-up layer having a laminated structure, i.e., two or more insulating layers and one or more conductor layers sandwiched between these insulating layers. When the insulating layer 10 is a build-up layer, the insulating layer within the build-up layer may include via conductors connecting the conductor layers on both sides of each insulating layer.

[0014] The conductor layer 11 and the via conductor 21 are formed using any conductive metal such as copper or nickel. Preferably, the conductor layer 11 and the via conductor 21 are formed from copper. The via conductor 21 is formed integrally with the conductor layer to which it is connected on the upper side. The metal film layer 12 and the metal film layer 22 are preferably sputtered film layers or electroless plated film layers, and function as power supply layers when the plated film layer 13 and the plated film layer 23 are formed by electrolytic plating, respectively. The plated film layer 13 and the plated film layer 23 are preferably electrolytic plated film layers.

[0015] The conductor pad 11p is in contact with the via conductor 21 that penetrates the insulating layer 20. In other words, the conductor pad 11p is a conductor pad on which the via conductor 21 is formed, and is a so-called receiving pad for the via conductor 21 that penetrates the insulating layer 20. In the example of FIG. 1, the outer edge portion of the upper surface 110 of the conductor pad 11p and its side surface 115 are covered with the insulating layer 20. The center portion of the upper surface 110 of the conductor pad 11p is in contact with the via conductor 21.

[0016] As shown in FIG. 1, the wiring board 1 may further include an adhesive layer 5 formed on the surface of the conductor layer 11 opposite the insulating layer 10 and on the surface 10F of the insulating layer 10. In this case, the surface of the conductor layer 11 opposite the insulating layer 10 and the surface 10F of the insulating layer 10 may be covered with the adhesive layer 5. In the example shown in FIG. 1, of the conductor patterns included in the conductor layer 11, the wiring pattern 11a is entirely covered with the adhesive layer 5. On the other hand, the conductor pad 11p is partially covered with the adhesive layer 5. The adhesive layer 5 has an opening 5a above the conductor pad 11p, and the adhesive layer 5 covers the conductor pad 11p in the area surrounding the opening 5a.

[0017] In the example shown in FIG. 1 , the adhesive layer 5 covers the surface of the conductor layer 11 and the surface 10F of the insulating layer 10. However, the adhesive layer 5 does not necessarily have to be formed on the surface 10F of the insulating layer 10. In the example shown in FIG. 1 , the adhesive layer 5 is interposed between the conductor layer 11 or the insulating layer 10 and the insulating layer 20. The adhesive layer 5 can improve adhesion between the conductor layer 11 and the insulating layer 20. The adhesive layer 5 is formed, for example, from a material capable of bonding with both organic materials, such as resins, constituting the insulating layer 20, and inorganic materials, such as metals, constituting the conductor layer 11. The adhesive layer 5 is formed, for example, from a material containing both reactive groups capable of chemically bonding with organic materials and reactive groups capable of chemically bonding with inorganic materials. Therefore, the conductor patterns, including the wiring pattern 11a, of the conductor layer 11 covered with the adhesive layer 5 adhere to the insulating layer 20 with sufficient strength. The adhesion between the wiring pattern 11a and the insulating layer 20 is improved compared to when the adhesive layer 5 is not present. It is believed that the insulating layer 20 is less likely to lift or peel off from the wiring pattern 11a.

[0018] An example of the material for the adhesive layer 5 is a silane coupling agent containing an azole silane compound such as a triazole compound. The material for the adhesive layer 5 is not limited to a silane coupling agent as long as it can increase the adhesive strength between the conductor layer 11 and the insulating layer 20 compared to when the insulating layer 20 is formed directly on the conductor layer 11.

[0019] As described above, the adhesive layer 5 partially covers the conductor pad 11p. Specifically, the area of ​​the surface (upper surface 110 and side surface 115) of the conductor pad 11p that faces the insulating layer 20 is covered with the adhesive layer 5. Because the adhesive layer 5 is interposed between the conductor pad 11p and the insulating layer 20, it is believed that the insulating layer 20 is less likely to lift or peel off even on the conductor pad 11p.

[0020] On the other hand, the inner portion (central portion) of the upper surface 110 of the conductive pad 11p is not covered by the adhesive layer 5 and is exposed within the opening 5a of the adhesive layer 5. The portion of the upper surface 110 within the opening 5a is covered by the via conductor 21. That is, the via conductor 21 and the conductive pad 11p are connected in the portion of the surface of the conductive pad 11p that is not covered by the adhesive layer 5. Therefore, the metal such as copper that constitutes the conductive pad 11p and the metal such as copper that constitutes the via conductor 21 are in direct contact with each other without going through an organic material such as a silane coupling agent that constitutes the adhesive layer 5. Therefore, it is believed that a mechanically strong metal-to-metal bond with low electrical resistance is obtained at the interface between the conductive pad 11p and the via conductor 21.

[0021] The surfaces of the conductor pad 11p and the surface 111 of the wiring pattern 11a facing the insulating layer 20 may be roughened. This can provide a so-called anchor effect between the conductor layer and the insulating layer formed thereon. For example, the top surface 110 and side surface 115 of the conductor pad 11p and the surface 111 of the wiring pattern 11a may be roughened to have a surface roughness of 0.05 μm or more and 0.5 μm or less in root-mean-square height (Rq). With such a relatively low surface roughness, problems such as a decrease in high-frequency transmission characteristics due to an increase in effective impedance caused by the skin effect in the wiring pattern 11a are unlikely to occur. For example, such roughening can be achieved by microetching or the like.

[0022] On the other hand, since the anchor effect obtained between a conductor layer having such a surface with a relatively low surface roughness and an insulating layer formed on that surface is considered to be relatively small, there is a risk of peeling between the conductor layer and the insulating layer. However, since the surface 111 of the wiring pattern 11a of this embodiment is covered with the adhesive layer 5, peeling between the wiring pattern 11a and the insulating layer 20 is considered to be unlikely to occur.

[0023] In the conductor pad 11p, peeling between the conductor pad 11p and the insulating layer 20, typically referred to as "haloing," may occur, which may be caused by unintentional infiltration of a liquid into the interface between the conductor pad 11p and the insulating layer 20 during the manufacturing process of the wiring board 1. More specifically, during the manufacturing process of the wiring board 1, the inner walls of the through holes 20a formed in the insulating layer 20 for forming the via conductors 21 may be exposed to various processing solutions, plating solutions, and the like. These liquids may infiltrate the interface between the conductor pad 11p and the insulating layer 20 from the inner walls of the through holes 20a, causing peeling between the conductor pad 11p and the insulating layer 20.

[0024] However, in this embodiment, although not shown in FIG. 1, as shown in FIGS. 2A and 2B, unevenness is formed around the entire periphery of the side surface 115, which is the outer edge of the conductor pad 11p. As will be described in the manufacturing method of the wiring board of the embodiment below, the unevenness is formed only on the side surface 115 of the conductor pad 11p, and not on the side surface of the wiring pattern 11a. The unevenness on the side surface 115 of the conductor pad 11p is formed so as to form striped unevenness that is approximately parallel to the thickness direction of the wiring board 1. Preferably, the unevenness on the side surface 115 of the conductor pad 11p is formed only on the upper plating film layer 13 of the metal film layer 12 and plating film layer 13 that constitute the conductor pad 11p. FIG. 2A shows a plan view of the conductor pad 11p shown in FIG. 1, viewed from the top surface 110 of the conductor pad 11p. Note that "plan view" here means viewing the wiring board 1 along a line of sight that runs along its thickness direction. FIG. 2B shows a side view of the plating film layer 13 portion of the conductor pad 11p shown in FIG. 2A.

[0025] In this embodiment, even if liquid unintentionally penetrates into the interface between the conductor pad 11p and the insulating layer 20, it is believed that the unevenness of the side surface 115 will provide an anchor effect between the conductor pad 11p and the adhesive layer 5 formed on the surface thereof. It is believed that peeling between the conductor pad 11p and the insulating layer 20 at the side surface 115 will be suppressed.

[0026] As shown in FIG. 2A, the unevenness of the side surface 115 is composed of protrusions 15 including ends and tops 15t and recesses 16 including ends and bottoms 16a. The size (pad diameter) of the conductor pad 11p is, for example, 60 μm or more and 120 μm or less. Although the term "diameter" is used, the conductor pad 11p may have any planar shape. The "diameter" refers to the longest distance between any two points on a horizontal cross section of the conductor pad 11p. For example, the protrusions 15 and recesses 16 may be formed in a shape such that, in the unevenness of the side surface 115 in a plan view, the amount of protrusion t of the protrusion 15 from the recess 16 is 2.5 μm or more and 6.0 μm or less, as shown in FIG. 2A. Here, the amount of protrusion t of convex portion 15 from concave portion 16 means the distance t from a straight line connecting bottoms 16a of two concave portions 16 formed on either side of convex portion 15 to top 15t of convex portion 15 in the unevenness of side surface 115 in a plan view. In wiring board 1 of the embodiment, preferably, unevenness having approximately the same amount of protrusion t is formed all around side surface 115.

[0027] As shown in FIGS. 2A and 2B and as described above, the unevenness of the side surface 115 includes multiple protrusions 15 and recesses 16 to form striped unevenness substantially parallel to the thickness direction of the wiring substrate 1. The number of protrusions 15 and recesses 16 constituting the unevenness is not limited to the example of the unevenness shown in FIGS. 2A and 2B, and any number of protrusions 15 and recesses 16 may be included in the unevenness of the side surface 115. It is preferable that the unevenness having the above-mentioned protrusion amount t is formed around the entire periphery of the side surface 115. The planar shape of the unevenness, i.e., the planar shapes of the protrusions 15 and recesses 16, is also not limited to the shape shown in FIG. 2A. It may be preferable that the unevenness of the side surface 115 has protrusions 15 and recesses 16 alternately formed at approximately equal intervals. It is believed that this can provide a good anchoring effect between the conductor pad 11p and the adhesive layer 5.

[0028] 1, 2A, and 2B show an example of a conductor pad 11p that is not connected to a wiring pattern 11a. However, the conductor layer 11 may include a wiring 11b connected to the conductor pad 11p. FIG. 3 shows a plan view of such a conductor pad 11p with wiring, as seen from the top surface 110 of the conductor pad 11p. As shown in FIG. 3, the conductor pad 11p with wiring also has striped irregularities formed around the entire periphery of its side surface 115, which are substantially parallel to the thickness direction of the wiring substrate 1, similar to the irregularities shown in FIG. 2. Here, however, the "entire periphery" of the side surface 115 of the conductor pad 11p with wiring refers to the portion of the side surface 115 of the conductor pad 11p excluding the portion to which the wiring 11b is connected.

[0029] The conductor layer 11 may further include a plane layer 11c. Fig. 4 shows an example of a conductor pad 11p surrounded by the plane layer 11c, viewed from the top surface 110 of the conductor pad 11p in a planar view. Here, the conductor pad 11p is an independent pad that is not electrically connected to the other pads included in the conductor layer 11. The insulating layer 10 is exposed between the independent conductor pad 11p and the plane layer 11c. Striped irregularities that are approximately parallel to the thickness direction of the wiring board 1, similar to the irregularities shown in Fig. 2, are formed all around the side surface 115 of the conductor pad 11p.

[0030] 5A and 5B show cross-sectional views of the conductor pad 11p of the wiring board of this embodiment cut along different cutting lines. FIG. 5A shows a cross-sectional view of a portion of the wiring board 1 of FIG. 1 cut along a cutting line that overlaps with the AA line in FIG. 2A. The AA line in FIG. 2A is a line connecting two of the protrusions 15 included in the irregularities of the side surface 115 so that the distance between the apexes 15t is longest in a plan view. FIG. 5A shows the distance w1 between the two apexes 15t on the AA line. The distance w1 is the pad diameter of the conductor pad 11p, and is, for example, 60 μm or more and 120 μm or less.

[0031] 5B shows a cross-sectional view of a portion of the wiring board 1 of FIG. 1 taken along a cutting line that overlaps the line BB in FIG. 2A. The line BB in FIG. 2A is a line that connects the bottoms 16a of two of the recesses 16 included in the irregularities of the side surface 115 so that the distance between them is the longest in a plan view. FIG. 5B shows the distance w2 between the two bottoms 16a on the line BB. The distance w1 between the tops 15t shown in FIG. 5A is greater than the distance w2 between the bottoms 16a shown in FIG. 5B.

[0032] As described above, it is believed that in the wiring board 1, good transmission characteristics and sufficient adhesion to the insulating layer 20 can be obtained in the wiring pattern 11a. In addition, the irregularities included in the side surface 115 can suppress quality deterioration due to, for example, peeling between the insulating layer 20 and the conductor pad 11p in contact with the via conductor 21. As described above, according to this embodiment, it is possible to ensure the characteristics desired for the wiring pattern and adhesion between the wiring pattern and the insulating layer, and further suppress quality deterioration of the wiring board due to, for example, peeling between the insulating layer and the conductor layer in contact with the via conductor that connects the conductor layers together.

[0033] Next, a method for manufacturing a wiring board according to one embodiment will be described with reference to FIGS. 6A to 6H using wiring board 1 of FIG. 1 as an example.

[0034] The method for manufacturing a wiring board according to this embodiment includes forming a conductor layer 11 including wiring patterns 11a and conductor pads 11p on an insulating layer 10. The conductor layer 11 is formed by any method, such as a semi-additive method. Specifically, as shown in FIG. 6A, a metal film layer 12 is first formed in the through holes 10a and on the surface 10F of the insulating layer 10 by, for example, electroless plating.

[0035] Next, as shown in FIG. 6B, a plating resist 3 having openings 3p corresponding to the conductor pads 11p (see FIG. 1) and openings 3a corresponding to the wiring pattern 11a (see FIG. 1) is provided on the metal film layer 12.

[0036] As shown in Figures 6C and 6D, opening 3p is formed to have a side surface having a shape corresponding to the unevenness of side surface 115 of conductive pad 11p in order to form the unevenness of side surface 115. Figure 6C is a plan view of opening 3p in plating resist 3 provided on metal film layer 12, showing the shape of the side surface of opening 3p. Figure 6D is a perspective view of opening 3p in plating resist 3 provided on metal film layer 12.

[0037] 6E, a plating film layer 13 is formed in the openings 3a, 3p of the plating resist 3 by electrolytic plating using the metal film layer 12 as a power supply layer. A via conductor 25 is formed in the through hole 10a. The side surface of the plating film layer 13 formed in the opening 3p has an unevenness that is a pattern of the unevenness on the side surface of the opening 3p, and is the unevenness shown in FIG. 2A referred to above.

[0038] Thereafter, the plating resist 3 is removed using an alkaline stripping agent such as sodium hydroxide, and further, the exposed portion of the metal film layer 12 that is not covered by the plating film layer 13 is removed by etching or the like. As a result, the conductor layer 11 is formed as shown in Fig. 6F. The side surface 115 of the conductor pad 11p has unevenness formed thereon.

[0039] The method for manufacturing a wiring board according to this embodiment may include partially roughening the exposed surface of the conductor layer 11, which is a region not in contact with the insulating layer 10. In this case, partially roughening the exposed surface of the conductor layer 11 includes roughening the surface of the conductor pad 11p that faces the insulating layer 20 (see FIG. 1) and the surface of the surface 111 of the wiring pattern 11a that faces the insulating layer 20. Roughening can be performed by any method, such as surface oxidation or microetching. For example, the surface of the conductor pad 11p that faces the insulating layer 20 and the surface 111 of the wiring pattern 11a that faces the insulating layer 20 are roughened to have a surface roughness of 0.05 μm or more and 0.5 μm or less in root-mean-square height (Rq). Prior to the roughening step, a resist film (not shown) may be provided on the upper surface 110 of the conductor pad 11p, covering the region that will be covered by the via conductor 21 (see FIG. 1) formed in a subsequent step. The roughening can be performed on the exposed surface of the conductor layer 11 that is exposed from the resist film. In this case, after roughening, the resist film can be removed using an alkaline stripping agent such as sodium hydroxide.

[0040] Next, an adhesive layer 5 is formed to cover the conductor layer 11. As shown in FIG. 6G, the adhesive layer 5 is formed to cover the entire conductor layer 11, including the conductor pads 11p and the wiring pattern 11a, as well as the exposed surface of the insulating layer 10. The adhesive layer 5 improves adhesion between the conductor layer 11 and the insulating layer 20 (see FIG. 6H), which will be formed in a later process. The formation of the adhesive layer 5 for the conductor pads 11p is also thought to further improve adhesion to the insulating layer 20, in addition to the unevenness formed on the side surface 115. The adhesive layer 5 is formed, for example, by immersing the conductor layer 11 and the insulating layer 10 in a liquid containing a material, such as a silane coupling agent, that can bond with both organic and inorganic materials, or by spraying such a liquid. However, any method for forming the adhesive layer 5 is possible and is not limited to immersion in the material that constitutes the adhesive layer 5 or spraying the material.

[0041] Next, as shown in FIG. 6H, an insulating layer 20 is formed on the adhesive layer 5. The insulating layer 20 is formed, similarly to the insulating layer 10, by, for example, laminating a film of epoxy resin and applying heat and pressure. Through holes 20a for forming via conductors 21 are formed in the insulating layer 20 by, for example, irradiation with laser light such as a carbon dioxide laser. The through holes 20a are formed in the insulating layer 20 above the areas of the conductor pads 11p that are to be connected to the via conductors 21. The areas of the adhesive layer 5 on the conductor pads 11p that are to be connected to the via conductors 21 are removed by vaporization, sublimation, or the like, by irradiation with, for example, laser light to form the through holes 20a.

[0042] After the formation of the through hole 20a, a desmearing process may be performed to remove resin residue (smear) generated by the formation of the through hole 20a. For example, the smear inside the through hole 20a can be removed by exposing the inner wall of the through hole 20a to a processing liquid such as an alkaline permanganate solution. When the desmearing process is performed, there is a risk that the processing liquid for the desmearing process will penetrate into the interface between the conductor pad 11p and the insulating layer 20, causing interfacial peeling between the conductor pad 11p and the insulating layer 22 at the side surface 115 of the conductor pad 11p. However, in this embodiment, as described above, the side surface 115 of the conductor pad 11p has unevenness formed thereon, thereby suppressing the occurrence and expansion of interfacial peeling.

[0043] Thereafter, a conductor layer (not shown) is formed on the insulating layer 20 by the same method as for the conductor layer 11, using a metal film layer 22 and a plating film layer 23 (see FIG. 1) on the metal film layer 22. At the same time, the through hole 20a is filled with the metal film layer 22 and the plating film layer 23. A via conductor 21 is formed, which is in contact with the conductor pad 11p and connects the conductor layer 11 and the conductor layer on the insulating layer 20.

[0044] The wiring board of the embodiment is not limited to the structure illustrated in each drawing and the structure, shape, and material illustrated in this specification. The wiring board of the embodiment may include any number of conductor layers and insulating layers. The conductor layer 11 may be present at any layer in the laminated structure of the wiring board. All or some of the conductor layers included in the wiring board may include conductor pads 11p and wiring patterns 11a as included in the conductor layer 11. Furthermore, the manufacturing method of the wiring board of the embodiment is not limited to the method described with reference to each drawing. The conditions and order of the manufacturing method described above may be changed as appropriate. The insulating layers 10 and 20 are not limited to film-like resins and may be formed using any form of resin. Depending on the structure of the wiring board to be manufactured, some of the above-described steps may be omitted, and any other steps may be added in addition to the above-described steps. [Explanation of symbols]

[0045] 1. Wiring board 10 Insulating layer (first insulating layer) 10F Surface of the insulating layer (first insulating layer) 11 Conductor layer (first conductor layer) 11a Wiring pattern 111 Surface of wiring pattern 11p contact pad 110 Top surface of contact pad 115 Side of contact pad 12 Metal film layer 13 Plating film layer 15 Convex part 15t top 16 Recess 16a bottom 20 Insulating layer (second insulating layer) 20a through hole 21 Via conductor 3 Plating resist threesome aperture 5 Adhesive layer w1 Distance between the tops w2 Distance between bottoms

Claims

1. a first conductor layer; an insulating layer formed on the first conductor layer; a second conductor layer formed on the insulating layer; a via conductor that penetrates the insulating layer and connects the first conductor layer and the second conductor layer; A wiring board comprising: the first conductor layer includes a conductor pad whose side surface and an outer edge of its top surface are covered with the insulating layer and whose central portion of its top surface is in contact with the via conductor; Striped irregularities are formed along the entire periphery of the side surface of the conductor pad, and are generally parallel to the thickness direction of the wiring board.

2. 2. The wiring board according to claim 1, wherein an adhesive layer is formed on a surface of the first conductor layer.

3. 2. The wiring board according to claim 1, wherein the surface of the conductor pad facing the insulating layer has a surface roughness of 0.05 [mu]m or more and 0.5 [mu]m or less.

4. 2. The wiring board according to claim 1, wherein the first conductor layer further includes a wiring pattern, and the side surface of the wiring pattern does not have striped irregularities substantially parallel to the thickness direction of the wiring board.

5. 2. The wiring board according to claim 1, wherein the striped irregularities include convex portions and concave portions, and the amount of protrusion of the convex portions from the concave portions is 2.5 [mu]m or more and 6.0 [mu]m or less.

6. 2. The wiring board according to claim 1, wherein the diameter of the conductive pad is not less than 60 [mu]m and not more than 120 [mu]m.

7. 6. The wiring board according to claim 5, wherein the protrusions and the recesses are alternately arranged at substantially equal intervals.

8. 2. The wiring board according to claim 1, wherein the first conductor layer further includes a plane layer, and the conductor pad is an independent pad surrounded by the plane layer.

9. forming a first conductor layer having a conductor pad on the first insulating layer; forming a second insulating layer on the first conductor layer; forming a second conductor layer on the second insulating layer; forming a via conductor that penetrates the second insulating layer and connects the conductive pad and the second conductive layer; A method for manufacturing a wiring board including Forming the first conductor layer includes forming a conductor pad in an opening using a plating resist having an opening on the side surface with striped irregularities that are approximately parallel to the thickness direction of the wiring board.

10. A method for manufacturing a wiring board as described in claim 9, further comprising providing an adhesive layer on the first conductor layer to cover the first conductor layer, and forming the second insulating layer comprises covering the adhesive layer with the second insulating layer.

11. The method for manufacturing a wiring board according to claim 10, forming the via conductor includes forming a through hole in the second insulating layer that exposes a portion of the conductive pad; Forming the through hole includes removing the adhesive layer covering an area of ​​the contact pad that contacts the via conductor.

12. 10. The method for manufacturing a wiring board according to claim 9, further comprising roughening an exposed surface of the first conductor layer that is not in contact with the first insulating layer.

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