Heterogeneous integration of radio frequency transistor chiplets with interconnects to host wafer circuitry to optimize operating conditions

Abstract

To provide an electronic assembly using a host wafer capable of quickly manufacturing a circuit at a low cost.SOLUTION: The devices 500 heterogeneously integrate radio-frequency (RF) transistor chiplets 130a, 130b into a host wafer 110 having at least one host wafer circuit for generating bias conditions that optimize the performances of the HEMT or HBT. The chiplets have interconnections to host wafer circuitry. The host wafer circuitry includes a first circuit that provides a DC bias to the HEMT or HBT or a second circuit that detects an RF operating condition of the HEMT or HBT, and an electrical interconnect 510 is between said chiplet and the host wafer and electrically connects the host wafer circuitry to the chiplet circuitry.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] Copyright and Trade Dress Notice

[0002] A portion of the disclosure of this patent document contains material that is subject to copyright protection. This patent document may illustrate and / or describe matter that is or may become the trade dress of the owner. The copyright and trade dress owner has no objection to the facsimile reproduction by any person of the patent disclosure as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright and trade dress rights in any and all media.

[0003] (Field)

[0004] This disclosure relates to heterogeneous integration of radio frequency (RF) transistor chips (or chiplets) with interconnections to host wafer circuits (or circuitry) that optimize or generate desired operating conditions for the RF transistors. The chiplets can be laterally bonded to sidewalls of cavities in a wafer, such as using a lateral bonding material, and the wafer and chiplets are fabricated separately as a distributed integrated circuit. [Background technology]

[0005] Description of Related Art

[0006] An electronic assembly or hybrid circuit includes microelectronic circuits that are manufactured separately and assembled together to form a single component, which may itself be enclosed in an electronic circuit package. Assembling separately manufactured microelectronic circuits can improve the manufacturing yield of the final component, for example, by allowing all microelectronic circuits to be tested separately before the microelectronic circuits are assembled. This feature is particularly important when some of the separately manufactured microelectronic circuits are difficult and / or expensive to manufacture. Assembling separately manufactured microelectronic circuits also allows microelectronic circuits that themselves use different materials and manufacturing processes to be combined into a single final component. This feature can lead to improved circuit performance.

[0007] There is a need for electronic assemblies that use host wafers with pre-fabricated interconnects and integrated circuits, such as passive and active components that connect to wafer-level microelectronic active chiplets (i.e., having radio frequency transistors) integrated within through-wafer cavities of the host wafer. This need may be, for example, for assemblies for microwave or other radio frequency (RF) integrated circuits that separate the fabrication of the chiplet's active circuitry (e.g., RF transistor fabrication) from the fabrication of the wafer's passive circuitry and transistors (e.g., CMOS transistor, interconnect, resistor, and capacitor fabrication). Meeting this need would allow for both very rapid fabrication of circuits at lower cost and scaling-up of active device technology into circuits without the expense and cycle time. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic top view of a host wafer having cavities for intra-substrate multi-thickness chiplet integration within wafer cavities of the host wafer using lateral dielectric material.

[0009] [Figure 2] 1 is a schematic top view of a first set of multi-thickness chiplets for intra-substrate chiplet integration within a wafer cavity of a host wafer using lateral dielectric material. FIG.

[0010] [Figure 3] FIG. 10 is a schematic top view of a second set of multi-thickness chiplets for intra-substrate chiplet integration within a wafer cavity of a host wafer using lateral dielectric material.

[0011] [Figure 4] 1 is a schematic top view of a metal backfill plug for intra-substrate multi-thickness chiplet integration into a wafer cavity of a host wafer using lateral dielectric material.

[0012] [Figure 5] 1 is a schematic cross-sectional view of a device having intra-substrate multi-thickness chiplets integrated into a wafer cavity of a host wafer using lateral dielectric material.

[0013] [Figure 6] The exploded top view shows two circuits, each containing a CMOS-based wafer and a HEMT or HBT in a chiplet hetero-integrated on the wafer.

[0014] [Figure 7] The exploded top view of two circuits is shown, each containing a CMOS-based wafer with a feedback operational amplifier and a HEMT in a chiplet hetero-integrated on the wafer.

[0015] [Figure 8] 8 shows an exploded top view of a circuit including a CMOS-based wafer with power / voltage detectors and temperature sensors 870 and HEMTs of chiplets hetero-integrated on the wafer.

[0016] [Figure 9A]1 is an exploded top view of a circuit including a CMOS-based wafer with a portion of a temperature sensor and a chiplet HBT heterogeneously integrated on the wafer with another portion of the temperature sensor. [Figure 9B] 1 is an exploded top view of a circuit including a CMOS-based wafer with a portion of a temperature sensor and a chiplet HBT heterogeneously integrated on the wafer with another portion of the temperature sensor.

[0017] [Figure 10] 1 shows a block diagram of a radio receiver including a CMOS-based wafer with chiplet compound semiconductor devices heterogeneously integrated on the wafer.

[0018] [Figure 11] 1 shows a block diagram of an envelope detector (ED) circuit, each including a CMOS-based wafer, each having chiplet compound semiconductor devices hetero-integrated on the wafer.

[0019] [Figure 12] 1 shows a block diagram of a digital pre-distortion circuit including a CMOS-based wafer with a CMOS observation receiver and including chiplet compound semiconductor devices hetero-integrated on the wafer.

[0020] [Figure 13] 1 shows a block diagram of an impedance tuner for an antenna, the tuner including a CMOS-based wafer with a CMOS matching network and including chiplet compound semiconductor devices hetero-integrated on the wafer.

[0021] Throughout this description, elements that appear in the figures are assigned a three or four digit reference designator, where the last two digits are unique to the element and the first one or two digits may be the figure number in which the element is first introduced or created. An element not described in connection with a figure can be assumed to have the same properties and function as an element described earlier or later having the same reference number. DETAILED DESCRIPTION OF THE INVENTION

[0022] (Device Description)

[0023] Described below are improved wafers, dies, and chips, and their fabrication techniques, for electronic assemblies with in-substrate chips (e.g., chiplets) integrated within wafer cavities of a host wafer, including through the use of lateral bonding materials, which can be dielectric. The host wafer can have prefabricated interconnects and integrated circuits, such as passive and active components, that connect to chiplet-level microelectronic transistor chiplets integrated within through-wafer cavities of the wafer. This can form assemblies for integrated circuit devices or diced chips, where the chiplets contain active circuitry from at least one semiconductor technology (often a more expensive and sophisticated RF semiconductor technology) and the wafer contains passive and active circuitry from another semiconductor technology (often a cheaper, larger-scale technology, such as CMOS on a silicon wafer). The use of a low-cost, large-diameter wafer integration platform or interposer for the higher-cost chiplets with active devices allows for the fabrication of assembled circuits on a larger scale, at lower cost, and at much faster speeds.

[0024] Electronic fabrication circuits can integrate chiplets with one type of component onto a carrier wafer with a different type of component. Electronic fabrication circuits can integrate chiplets with high-performance integrated circuits, such as gallium nitride (GaN) radio frequency (RF) integrated circuits (ICs), onto a host wafer with other integrated circuits, such as silicon-based integrated circuits, in a manner that is inexpensive, has high manufacturing yields, and has short manufacturing cycles. High-performance RF ICs, chips (or chiplets), can have III-V or other types of transistors and passives, integrated with host wafer CMOS devices, resistors, inductors, capacitors, and matching networks from another semiconductor technology. For example, an RF IC can be a type of semiconductor technology integrated with CMOS transistors, resistors, inductors, capacitors, and matching networks from another semiconductor technology that is part of the host wafer. A chiplet can also be a chip containing the circuits, materials, and / or devices described herein as a chiplet. A chiplet can also be a chip or small chip with active microelectronic (i.e., transistor) devices, CMOS devices, microwave IC devices, and / or radio frequency (RF) IC devices. A chiplet may also be a chip or miniature chip having a SAW, BAW, or other acoustic wave device. A chiplet is defined by a surface area, such as less than 500 μm on a side.

[0025] FIG. 1 is a schematic top view 100 of a host wafer 110 having cavities 120a and 120b for intra-substrate, multi-thickness chiplet integration within wafer cavities 120a and 120b of the host wafer 110, such as using a lateral bonding material. The host wafer 110 has a back surface 112 and a front surface 114, as shown in FIG. 5. The host wafer 110 and each of the cavities 120a and 120b have side surfaces 116a and 116b, respectively. Each of the side surfaces 116a and 116b may be vertical or sidewall surfaces between the back surface 112 and the front surface 114. Each of the cavities may have three, four, or more side surfaces 116a and 116b. Typically, each of the cavities has four sides. Each cavity 120a and 120b may have a minimum of one side (which may be circular, for example) or up to an infinite number of sides, but preferably has four sides.

[0026] The wafer 110 may be or include (e.g., as a mixture of materials or as a material layer) silicon, silicon germanium, silicon-on-insulator, gallium arsenide, indium phosphide, aluminum nitride, diamond, silicon carbide, quartz, or alumina. If the wafer includes only interconnects and passive components, the wafer can be a dielectric such as glass, quartz, alumina, or another ceramic. The host wafer 110 may be a Si CMOS wafer. The host wafer 110 may have one or more layers of these materials in the form of oxide, crystalline, and polycrystalline and / or amorphous materials. The wafer 110 may include at least one of resistors, capacitors, inductors, through-substrate vias, dielectric layers, and metal layers (e.g., signal traces or signal planes). The wafer 110 may include at least one layer of silicon, silicon carbide (SiC), quartz, or another semiconductor wafer material.

[0027] The wafer 110 may include an area to be diced into integrated circuits, each having passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors, and / or capacitors) and at least two multi-thickness chiplets, each having a single transistor and / or multiple transistors. Silicon is an advantageous choice for the wafer 110 because of its lower cost than other materials and / or the advantages of known microelectronics manufacturing processes and scaling and manufacturability.

[0028] FIG. 2 is a schematic top view 200 of a first set of multi-thickness chiplets 130a for intra-substrate multi-thickness chiplet integration within a wafer cavity 120a of a host wafer 110, such as using a lateral bonding material. The chiplets 130a have a front side 132a (e.g., front surface), a back side 134a (e.g., back surface), and a thickness twa, as shown in FIG. 5 . Each chiplet 130a has a side surface 136a, such as a vertical surface or a sidewall surface, between the front surface 132a and the back side 134a. The chiplets 130a can have from zero (e.g., having a curved periphery, being circular, being elliptical, etc.) to several tens of side surfaces 136a. There may be three, four, or more side surfaces 136a. There may also be four side surfaces. The number of side surfaces 136a of each chiplet 130a may be the same as the number of surfaces 116a.

[0029] FIG. 3 is a schematic top view 300 of a second set of multi-thickness chiplets 130b for intra-substrate multi-thickness chiplet integration within a wafer cavity 120b of a host wafer 110, such as using a lateral bonding material. The chiplets 130b have a front side 132b, a back side 134b, and a thickness t b , as shown in FIG. 5 . Each chiplet 130b has a side surface 136b, such as a vertical surface or a sidewall surface, between the front surface 132b and the back side 134b. The chiplets 130b can have from zero to an infinite number of side surfaces 136b. There may be three, four, or more side surfaces 136b. The number of side surfaces 136b of each chiplet 130b may be the same as the number of surfaces 116b.

[0030] Chiplets 130a and 130b may each be or include (e.g., as a mixture of materials or as a layer of materials) silicon, silicon germanium, silicon-on-insulator, gallium arsenide, indium phosphide, aluminum nitride, quartz, alumina, gallium nitride, or silicon carbide. Chiplets 130a and 130b may each have one or more layers of these materials in the form of oxide, crystalline, polycrystalline, and / or amorphous materials. Different electrical components or types may be present in each of chiplets 130a and 130b that are fabricated separately from one another. That is, each of chiplets 130a may be fabricated separately from one another, and each of chiplets 130b may be fabricated separately from one another. Also, chiplet 130a may be fabricated separately from chiplet 130b. Each of chiplets 130a and 130b may include GaN, InP, or GaAs, or any other electrical components known in the industry, and may be fabricated on a substrate such as Si, SiGe, InP, GaAs, SiC, alumina, or diamond, or any other substrate known in the industry.

[0031] The chiplets 130a and 130b or types of chiplets 130a and 130b may include RF switches, transmit and / or receive circuits, power switches, amplifiers and circuits using GaAs, InP, GaN, etc., and / or transistors, such as Si CMOS transistors. They may have smaller and more expensive electrical components than those in the wafer 110. There may be hundreds, thousands, or tens of thousands of chiplets 130a and 130b embedded in a single wafer 110. The wafer 110 may have more passive components, less expensive components, and routing (e.g., traces, conductive vias, and interconnects) than the chiplets 130a and 130b. The wafer 110 may be fabricated using a different microelectronic fabrication technology or process than those used to fabricate the chiplets 130a and 130b.

[0032] Chiplets 130a and 130b can be made of a different material than wafer 110. For example, wafer 110 can be a silicon wafer, and chiplets 130a and 130b can be III-nitride material component chips. Chiplets 130a and 130b can each be or include integrated circuits having passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors, and / or capacitors), single transistors, and / or multiple transistors.

[0033] Chiplets 130a and 130b may be or include at least one of transistor circuitry and interconnects to contact pads on the front sides 132a and 132b of chiplets 130a and 130b, respectively. Chiplets 130a and 130b may be high-end pre-fabricated active device chiplets that are integrated into wafer 110 through pick-and-place assembly, onto a temporary wafer with an adhesive laminate, or simply on top of the adhesive laminate, e.g., into cavities 120a and 120b.

[0034] Chiplets 130a and 130b may each be a compound semiconductor wafer used as a transistor building block for heterogeneous integrated silicon circuits that comprise wafer 110. Chiplets 130a and 130b may be obtained from wafers processed at a foundry using a suitable process and then diced into chiplets before heterogeneous integration. Depending on the chiplet technology (e.g., InP, GaAs, GaN, etc.) and the casting utilized, the final chiplet thickness may range from 50 microns (2 mils thick) to 150 microns (6 mils thick). In some cases, one or more chiplets 130b may be half as thick as one or more chiplets 130.

[0035] FIG. 4 is a schematic top view 400 of a metal backfill plug 133 for intra-substrate, multi-thickness chiplet integration within a wafer cavity 120b of a host wafer 110, such as using a lateral bonding material. The plug 133 has a front side 135, a back side 137, and a thickness tec, as shown in FIG. 5 . Each plug 133 has a side surface 139, such as a vertical surface or a sidewall surface, between the front surface 135 and the back surface 137. The plug 133 can have zero to an infinite number of side surfaces 139. There may be three, four, or more side surfaces 139. The number of side surfaces 139 for each plug 133 may be the same as the number of surfaces 116b or 136b. In some cases, the plug 133 is a “backside metal fill” to thicken the chiplets 130b. This allows for good thermal conductivity for all embedded chiplets 130b, regardless of their original thickness.

[0036] 5 is a schematic cross-sectional view of a device 500 having in-substrate chiplets 130a and 130b integrated in wafer cavities 120a and 120b of a host wafer 110 using lateral bonding material 360. Device 500 may include the devices of FIGS. 1-4. As shown, thickness t b of chiplet 130b is less than thickness t w of chiplet 130a, and a metal backfill plug 133 is formed on backside 134b of chiplet 130b.

[0037] A chiplet 130a, such as several chips, has a backside 134a and a frontside 132a, and the backside 134a of the chiplet 130a is directly bonded to at least a portion 378a of a plurality of regions 376a on a top surface 372 of a backside capping layer 370. The portions 378a may be the footprint of the chiplet 130a on the top surface 372 within the cavity 120a. A gap gwa between the sides 116a and 136a may be the difference between the regions 376a and the portions 378a. The backside 134a may be directly attached to and in contact with the top surface 372. The bond between the backside 134a and the top surface 372 may be a covalent bond, a chemical bond, or an atomic bond. The regions 376a and the portions 378a have a thickness "t" of the backside capping layer 370.

[0038] Cavity 120a may be a substrate through-hole or may be a substrate through-hole etched into the wafer in area 376a. Chiplet 130a may be embedded in wafer 110 in the substrate hole or cavity 120a.

[0039] Lateral bonding material 360 extends between side 136a of chiplet 130a and side 116a of the wafer or cavity. Lateral bonding material 360 may mechanically and chemically bond side 136a of chiplet 130a to side 116a of the wafer. Lateral bonding material 360 may form a mechanical and / or chemical bond to side 136a and side 116a. The bond may be a mechanical-chemical bond. In some cases, lateral bonding material 360 is a molding compound molded between chiplet 130b and wafer 110 within cavity 120b. In some cases, dielectric material 360 has a thermal expansion coefficient that is between or equal to the thermal expansion coefficient of wafer 110 and that of chiplets 130a and / or 360b.

[0040] Chiplet 130b, such as some chips, has a backside 134b and a frontside 132b, and the backside 134b of chiplet 130b is bonded to at least a portion 378b of multiple regions 376b of top surface 372 of backside capping layer 370.

[0041] The backside 134b of chiplet 130b may be directly bonded to a metal backfill plug 133, which is then directly bonded to portion 378b of backside capping layer 370. A plug 133, such as a plurality of metal backfill materials, has a backside 137 and a front side 135, with the front side 135 bonded to the backside 134b of chiplet 130b and the backside 137 bonded to at least portion 378b of backside capping layer 370. The backside 134b may be bonded to a surface of the metal backfill plug 133 that is the same size as portion 378b. The plug 133 may have an outer perimeter the same as the outer perimeter of portion 378b. The plug 133 may have an outer perimeter smaller than the outer perimeter of chiplet 130b, as shown. In other cases, the two outer perimeters are the same. In other cases, the plug 133 may have an outer perimeter larger than the outer perimeter of chiplet 130b.

[0042] Portion 378a may be the footprint of chiplet 130a or plug 133 on top surface 372 within cavity 120b. Gap gwb is between side 116b and side 136b. Gap gwc is between side 139 of plug 133 and side 139 of plug 136b. Gap gwc may be the difference between region 376b and portion 378b. As shown, gap gwc is larger than gap gwb. In other cases, these gaps may be the same. In other cases, gap gwc is smaller than gap gwb.

[0043] The backside 134b may be directly attached to and in contact with the front side 135, and the backside 137 may be directly attached to and in contact with the top surface 372. The bonds between the backside 134b and the front side 135 and between the backside 137 and the top surface 372 may be covalent, chemical, or atomic. Portion 378b has a thickness "teb," which is the thickness "tea" of the backside capping layer 370 plus the thickness "tec" of the plug 133. Thickness "teb" may be the thickness of the backside capping layer 370 because the plug 133 is a metal backfill plug. Thickness "teb" may be the thickness of the backside capping layer 370 because the plug 133 is the same material as layer 370.

[0044] The metal backfill plug 133 may be formed or deposited on the backside 134b of the chiplet 130b, consisting of a copper metal deposition layer, an electroplated metal layer, and / or a sputtered metal seed layer (e.g., titanium (Ti) and / or copper (Cu)) plated with a plating metal such as copper. The seed layer may be a Ti / Cu 200 / 2,000 angstrom (Å) wafer-level backside sputtering on the backside 134b of the chip 103b. The plug 133 may be a backside metal backfill tailored to a width, length, and thickness ranging from 0.1 μm to 1,000 μm thick using an electroplating process. The plug 133 may be 5 to 60 μm thick, and the chiplet 130b may be 200 × 200 μm thick.

[0045] In some cases, plug 133 is formed from a metal such as copper, gold, silver, titanium, or tungsten. Plug 133 may be formed from a material including or a combination of the above metals. Plug 133 may be formed from an alloy or ceramic. Plug 133 may have a footprint of 20 microns by 20 microns to 5,000 microns by 5,000 microns, or an area ranging from 0.04 mm to 25 mm. Chiplets 130a and 130b may have a footprint of 100 microns by 100 microns to 5,000 microns by 5,000 microns, or an area ranging from 0.1 mm to 25 mm.

[0046] The layer 370 may be formed from a metal such as copper, gold, silver, titanium, or tungsten. The layer 370 may be formed from a material containing the above metals or a material consisting of a combination of the above metals. The layer 370 may be formed from an alloy or a ceramic. The layer 370 and the plug 133 may be the same material. The layer 370 and the plug 133 may be different materials.

[0047] As shown, thickness twa of chiplet 130a is greater than thickness twb of chiplet 130b, and thickness "tea" of the metallization under chiplet 130a is less than thickness "teb" of the metallization under chiplet 130b. Backside capping layer 370, or thickness teb of the metallization under chiplet 130b, may be described as including metal backfill plug 133 between backside 134b of chiplet 130b and thickness "tea" of backside capping layer 370.

[0048] The lateral bonding material 360 extends between the side 136b of the chiplet 130b and the side 116b of the wafer or cavity. The lateral bonding material 360 may mechanically and chemically bond the side 136b of the chiplet 130b to the side 116b of the wafer. The lateral bonding material 360 may form a mechanical and / or chemical bond to the side 136b and the side 116b. The bond may be a mechanical-chemical bond. In some cases, the lateral bonding material 360 is a molding material molded between the chiplet 130b and the wafer 110 within the cavity 120b.

[0049] The lateral bonding material 360 extends between the side 139 of the plug 133 and the side 116b of the wafer or cavity. The lateral bonding material 360 may mechanically and chemically bond the side 139 of the plug 133 to the side 116b of the wafer. The lateral bonding material 360 may form a mechanical and / or chemical bond to the side 139 and the side 116b. The bond may be a mechanical-chemical bond. In some cases, the lateral bonding material 360 is a molding material that is molded between the plug 133 and the wafer 110 within the cavity 120b.

[0050] Each of chiplets 130a and 130b may have between three and six sides. They may also have four sides. The sides may have a straight, curved, or wavy profile when viewed from a top perspective. Cavities 120a and 120b may have the same number and sides corresponding to the shape of the sides of chiplets 130a and 130b, respectively. In some cases, chiplet 130a is formed by a different foundry process than chiplet 130b.

[0051] The interconnects 510 may be formed directly on the lateral bonding material 360 and may connect the electrical (e.g., power, ground, and / or signal) contacts 138 of the chiplets 130a and 130b to the contacts 118 of the wafer 110. The interconnects 510 may be formed directly on the lateral bonding material (e.g., no dielectric / air gap) and may include direct interconnect routing or traces extending from the chiplets to the wafer electrical routing. The interconnects 510 may be bonded to the material 360, may be directly attached to the material 360, may contact the material 360, and / or may have no gap between the interconnect and the material 360. The interconnect routing may include low-loss, high-performance DC, RF, and mmWave routing from the chiplets 130a and 130b directly on the lateral bonding material and to the wafer electrical routing. The interconnects 510 may be directly on the material 360 by being bonded to and / or directly attached to (eg, contacting) the top surface of the lateral bonding material 360 .

[0052] Each chiplet 130a and 130b may include at least one of active device circuitry and interconnects 510 to contact pads 138 on the front surface of the chiplet 130a and 130b. Each chiplet 130a and 130b may be a prefabricated transistor chiplet. Figure 5 may show how the interconnect structure 510 sits directly on the dielectric bonding material 360 between the chiplet 130a or 130b and the wafer 110.

[0053] Each of the chiplets 130a and 130b may include one or more transistors, each having its terminal connected to at least one integrated circuit contact 138 (e.g., a contact pad) by, for example, a conductive via (not shown). Each of the chiplets 130a and 130b may include a substrate and an integrated circuit layer formed on the substrate, the thickness of which is, for example, a small fraction of the thickness of the substrate (e.g., 1 / 10 to 1 / 1000 of the thickness of the substrate). In some cases, the total thickness of each of the chiplets 130a and 130b is less than the total thickness of the host wafer 110. In some cases, the lateral bonding material 360 contacts the side surface 136a of the chiplet 130a along a majority of its height (at least 50% of the height starting near the top surface of the chiplet 130a). Preferably, the lateral bonding material 360 contacts essentially all of the side surfaces 136a, 136b, and 139. Preferably, the lateral bonding material 360 completely fills the gaps gwa, gwb, and gwc to a level essentially flush with the front surface 114 of the host wafer 110.

[0054] It is contemplated that the host wafer 110 can be vertically diced along dicing lines (shown by vertical bars in FIG. 5 ) along the wafer's perimeter 386 a and / or 386 b around at least one chiplet to form a chip having at least one chiplet and an area of ​​the wafer surrounding the at least one chiplet. In some cases, the wafer 110 is vertically diced along dicing lines along the perimeter 386 a and 386 b around at least one of each of the chiplets 130 a and 130 b to form at least two chips, each having at least one chiplet 130 a or 130 b and an area of ​​the wafer surrounding at least two chiplets. The wafer 110 may also be vertically diced along the perimeter 386 a and 386 b around many or all of the chiplets 130 a and 130 b to form a chip, each having at least one chiplet 130 a or 130 b and an area of ​​the wafer surrounding the chiplet. The wafer 110 may be diced vertically along the perimeter around two or more of the chiplets 130a or 130b to form areas of the wafer surrounding the chips and chiplets. The wafer 110 may be diced vertically along the perimeter around two or more of the chiplets 130a and 130b to form areas of the wafer surrounding the chips and chiplets.

[0055] Diced chips with chiplets may each be structured such that the chiplets are embedded within the volume of the silicon / CMOS wafer 110 using dielectric sidewall bonding techniques to form material 360. Diced chips may also be structured such that chiplets of different thicknesses can be co-integrated on the same silicon wafer 110 using the same dielectric sidewall bonding techniques of material 360 while maintaining high thermal conductivity on the backside of all chiplets.

[0056] In some cases, the description of Figures 1-5 can also be used to describe a single thickness of chiplets, such as only either chiplet 130a or 130b incorporated into wafer 110. This description can be either the two chiplets 130a on the left side of Figures 1 and 2 and Figure 5, or the two chiplets 130b on the right side of Figures 1 and 3-4 and Figure 5.

[0057] 6-13 disclose microwave, analog, and digital circuits that are incorporated into a co-located or co-planar substrate (e.g., wafer 110) with a collection of compound semiconductor transistors (e.g., chiplets and wafers) to optimize the operation of each transistor (e.g., adjust the operating bias conditions of each transistor). Optimizing the operating conditions may be or may include creating desired operating conditions of or for the RF transistors, creating bias conditions that optimize the performance of the RF transistors, and / or optimizing the RF characteristics of the RF transistors.

[0058] This technology may rely on designing and supplying compound semiconductor wafer chiplets, which are primarily used as transistor building blocks in a hetero-integrated silicon wafer 110. The wafers that produce the chiplets may be processed in separate foundries using qualified processes and then diced into chiplets before hetero-integration into wafers. Depending on the chiplet technology (e.g., indium phosphide, gallium arsenide, gallium nitride), the thickness of the final wafer 110 may range from 50 microns (2 mils thick) to 150 microns (6 mils thick). In some cases, one or more different semiconductor chiplets (e.g., chiplets 130a and 130b) are embedded within the volume of the silicon / CMOS wafer 110 using dielectric sidewall bonding 360 technology. In some cases, compound semiconductor transistors are embedded as chiplets in a substrate containing silicon complementary metal-oxide semiconductor (CMOS), which can be used to realize microwave, analog, and digital circuits. In some cases, matching to the compound semiconductor transistors is performed using a silicon substrate with interconnected tuning circuits. In some cases, CMOS transistors embedded in silicon substrates are used to verify the manufacturing and yield of chiplets, such as by forming a built-in self-test for heterogeneous integrated radio frequency chiplets.

[0059] Thus, while multiple compound semiconductor chiplet transistors can be integrated on the same wafer of alternative semiconductor materials as described above, the use of multiple technologies requires the ability to optimize and / or adjust (e.g., sense and adapt) the operating conditions or bias of each chiplet transistor in situ. This enables heterogeneous integration of radio frequency (RF) transistor chips (or chiplets) with interconnections to host wafer circuitry such as CMOS, allowing the operating conditions of the RF transistors to be optimized (e.g., adjusted).

[0060] For example, FIG. 5 can show a cross section of a device 500 having a wafer 110 with embedded compound semiconductor chiplets 130a and 130b with RF chiplet transistors (e.g., compound semiconductors) and a wafer 110 with CMOS transistors that optimize the operating conditions of the RF transistors. Here, the thicker chiplets 130a may each include one or more heterojunction bipolar transistors (HBTs), and the thinner chiplets 130b may each include one or more high electron mobility transistors (HEMTs), while the wafer has an active CMOS transistor for sensing and adapting the operating conditions or bias of each chiplet transistor in situ. In some cases, wafers or chiplets with separate HEMT and HBT devices require separate bias circuits and / or voltages. In some cases, the HEMT and HBT devices require separate bias circuits and / or voltages.

[0061] In some cases, FIG. 5 may show a cross-sectional rendering filled with chiplets 130a each having at least one HBT and chiplets 130b each having at least one HEMT, each sourced from a different compound semiconductor foundry and formed from or on different semiconductor materials or wafers, which are integrated together or individually into the host wafer 110 using sidewall bonding material 360. One or more of the chiplets may be diced into a portion of the wafer 110 that includes the CMOS technology described herein. In this cross-section of FIG. 5, one feature shown is the integration of different chiplets 130a and 130b of different thicknesses into the same host wafer 110. As an example, the thickness of chiplet 130b may be the same as or half the thickness of chiplet 130a. The die 110 with chiplets 130a and 130b may represent different compound semiconductor devices or different types of semiconductor devices.

[0062] 6 shows a top view of exploded circuits 600 and 602, each of which includes a CMOS-based wafer 110 (e.g., a silicon interposer) and a HEMT in the left chiplet 130b in circuit 600 or an HBT in the right chiplet 130a in circuit 602. Note that the positions of chiplets 130b and 130a in FIG. 6 are reversed compared to the embodiment of FIG. 5. The HEMT or HBT may represent any suitable chiplet transistor in FIGS. 1-5.

[0063] A HEMT may be a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which are field-effect transistors (FETs) that utilize a heterojunction of materials with different band gaps. They offer improved performance in high-frequency applications. A heterojunction is the interface between two heterogeneous semiconductors, which lowers the band gap and helps prevent charge carrier recombination due to the presence of multiple valence and conduction bands. By simple definition, a homojunction is a junction between the same materials with the same crystal structure. A heterojunction is a junction between different materials or the same materials, but with different crystal structures. An HBT may be a type of bipolar junction transistor (BJT) that uses different semiconductor materials for the emitter and base regions, creating a heterojunction. HBTs improve on BJTs in that they can handle very high-frequency signals, up to several hundred GHz. HBTs may have a forward-biased base-emitter junction and a reverse-biased collector-base junction. The balance is dispersed, and electrons are injected from the emitter into the base. The HEMT is shown with a gate G, a source S, and a drain D. The HBT is shown with a base B, a collector C, and an emitter E.

[0064] Circuit 600 shows compound semiconductor chiplet 130b bonded to chiplet 110 by lateral bonding material 360. Circuit 600 shows interconnect 510 over or on material 360 connecting the HEMT (e.g., the circuitry of chiplet 130b) to the circuitry of wafer 110.

[0065] Circuit 600 shows wafer 110 with matching network 612, such as passive capacitors, inductors, resistors, and connections to ground, connected to HEMTs (e.g., the circuitry of chiplet 130b) via hetero-interconnect 510. Network 612 may include one or more matching networks or tuning circuits, such as passive tuning circuits, that reduce electrical mistuning of transistors caused by electrical interconnects that degrade transistor performance and increase uncertainty in chiplet circuit operation.

[0066] The wafer 110 of the circuit 600 is shown to have an RF input signal line 642 and an RF output signal line 644 connected (e.g., via network 612) to the gate G and drain D of the HEMT, respectively, via interconnect 510. The wafer 110 of the circuit 600 is shown to have a CMOS PMOS1 having its source SP1 connected to a voltage source 622, its gate GP1 connected to a drain control signal line 624, and its drain DP1 connected (e.g., via network 612) to the drain D of the HEMT. The wafer 110 of the circuit 600 is shown to have a CMOS NMOS1 having its drain DN1 connected to a gate voltage source 632, its gate GP1 connected to a gate control signal line 634, and its source SN1 connected (e.g., via network 612) to the gate G of the HEMT.

[0067] Circuit 602 shows compound semiconductor chiplet 130a bonded to chiplet 110 by lateral bonding material 360. Circuit 602 shows interconnect 510 over or on material 360 connecting the HBT (e.g., the circuitry of chiplet 130a) to the circuitry of wafer 110. Wafer 110 of circuit 602 is shown to have a matching network 652, such as passive capacitors, inductors, resistors, and a connection to ground, connected to the HBT (e.g., the circuitry of chiplet 130a) via hetero interconnect 510. Wafer 110 of circuit 602 is shown to have an RF input signal line 682 and an RF output signal line 684 connected (e.g., via network 652) to the base B and collector C of the HBT, respectively, via interconnect 510.

[0068] The wafer 110 of the circuit 602 is shown to have a CMOS PMOS2 with its source SP2 connected to a collector voltage source 662, its gate GP2 connected to a collector control signal line 664, and its drain DP2 connected (e.g., via network 652) to the collector C of the HBT. The wafer 110 of the circuit 602 is shown to have a CMOS NMOS2 with its drain DN2 connected to a base voltage source 672, its gate GP2 connected to a base control signal line 674, and its source SN2 connected to the base B of the HBT (e.g., via network 652).

[0069] References herein to "connected" circuitry are or include circuitry that is electrically connected to transfer RF and / or DC bias signals, possibly using interconnects, pads, traces, and / or wires. Being electrically connected may include having electrical connections through a printed circuit board, an interposer, a chiplet, a chip, a wafer, and / or a lateral bonding material.

[0070] The interconnects 510 may be shown as dark squares or rectangles representing all of the interconnects 510 between the RF transistors (e.g., HEMT or HBT) and the network 612 or 652, as shown in the figure, where the connecting lines are thickened in the lateral material 360 between the RF transistors (e.g., HEMT or HBT) and the network 612 or 652.

[0071] In some cases, the HEMT chiplets 130b and HBT chiplets 130a are interconnected to the circuitry of the wafer 110 (e.g., fabricated in the silicon wafer) via metal bridge interconnects 510 with passive elements forming optional matching networks 612 and 652 at the input and output of the chiplet's RF circuitry. Several HEMTs and / or HBTs may be connected within a single integrated circuit or diced chip with the CMOS circuitry of the wafer 110, such as to optimize (e.g., tune) the operating conditions of the chiplet RF transistors. CMOS transistors NMOS1 and NMOS2 are used to moderate the gate G and base B voltages by providing more stable, noise-free DC bias voltages to the gate G and base B. CMOS transistors PMOS1 and PMOS2 are used to set the voltages of the drain D and collector C by providing more stable, noise-free DC bias voltages to the drain D and collector C, such as through the action of a feedback circuit that compares the desired voltage to a reference value.

[0072] The use of the CMOS transistors of Figure 6 is important because different chiplet RF transistor devices (e.g., HEMTs and HBTs) require different DC bias conditions, and on-chiplet monitoring of the RF transistors is essential to obtain the best performance from each RF transistor device. The passive elements for the matching networks 612 and 652 are designed to produce the desired circuit response of the RF transistor devices in terms of gain, bandwidth, noise, linearity, output power, and / or noise.

[0073] The HEMT source S and HBT emitter E signals are split (e.g., to ground) between two matching networks 612 and 652, respectively, to reduce the inductance at each of these transistor terminals. The gate G and base B signals are connected to left-side inputs 642 and 682 through matching networks 612 and 652. The drain D and collector C signals are connected to right-side outputs 644 and 684 through matching networks 612 and 652. DC bias current signals are introduced to the gate G and base B. The drain D and collector C signals are connected through inductors connected to separate supply voltages 622 and 662. Alternatively, a choke circuit element, such as a quarter-wave transmission line or a large DC resistor, may be introduced as a DC circuit element. The choke circuit creates a large impedance at a fixed frequency and harmonics of the fixed frequency, but allows DC voltage and / or current to pass unimpeded from the power supply. While active bias generation creates a small impedance near DC or at low frequencies, the choke circuit creates a large impedance.

[0074] In some cases, silicon-based NMOS transistors (e.g., NMOS1 and 2) can be used to buffer gate and base voltages, and silicon-based PMOS transistors (e.g., PMOS1 and 2) can be used to buffer drain and collector voltages. One purpose of the NMOS transistors is to present a "voltage source" local to the wafer 110 (e.g., silicon interposer) and in close proximity to the HEMT or HBT (e.g., within 100 μm), which proximity introduces low impedance from DC to frequencies near or below the signal bandwidth of the RF chiplet transistors, e.g., from DC to frequencies between 100 and 10,000 MHz. The purpose of the PMOS transistor may be to instantiate or provide a "current source" local to the silicon wafer 110 (e.g., within 100 μm distance) and in close proximity to the HEMT or HBT (e.g., within 100 μm distance), which proximity introduces a high impedance from DC to frequencies near or below the signal bandwidth of the RF chiplet transistor, e.g., from DC to frequencies between 100 and 10,000 MHz.

[0075] In some cases, NMOS1 can be implemented using a PMOS transistor to perform the same function as NMOS1.

[0076] FIG. 7 illustrates exploded top views of circuits 700 and 702, each including a CMOS-based wafer 110 (e.g., a silicon interposer) with at least one of feedback operational amplifiers 720 and 730, and a HEMT in chiplet 130b on the left side of circuit 700 or an HBT in chiplet 130a on the right side of circuit 702, heterogeneously integrated on wafer 110. Circuit 700 may be similar to circuit 600, except that circuit 700 also includes feedback operational amplifiers 720 and 730 having outputs O1 and O2 connected to gates GP1 and G, respectively. Circuit 702 may be similar to circuit 602, except that circuit 702 also includes feedback operational amplifiers 720 and 730 having outputs O1 and O2 connected to gates GP1 and GN1, respectively. Note that the NMOS1 and PMOS1 transistors in FIG. 7 are shown inverted orientation compared to those shown in FIG. 6.

[0077] The wafer 110 of the circuit 700 has an output O1 connected to the gate GP1 and a drain reference voltage V REF,D and a negative input connected to the output of a resistor 724. The input of resistor 724 is connected to a ground signal via resistor 726, to the drain D of the HEMT (e.g., via network 612) and to the ground signal, and directly to the source SP1 of PMOS1.

[0078] The wafer 110 of circuit 700 eliminates the need for NMOS1 because the gate of the HEMT does not need current. Thus, the wafer 110 of circuit 700 is shown as having an op-amp 730 with an output O2 connected to the gate G of the HEMT (e.g., via network 612). Here, op-amp 730 is connected to a gate reference voltage V REF,Gand a negative input connected to the output of resistor 734. The input of resistor 734 is connected to a ground signal via resistor 736, to the gate G of the HEMT (e.g., via network 612) and to a ground signal, and directly to the output O2 of operational amplifier 730.

[0079] The wafer 110 of the circuit 702 has an output O1 connected to the gate GP2 and a drain reference voltage V REF,D and a negative input connected to the output of a resistor 734. The input of resistor 734 is connected to a ground signal through resistor 736, to the collector C of the HBT (e.g., via network 612) and to the ground signal, and directly to the source SP2 of PMOS2.

[0080] The wafer 110 of the circuit 702 has an output O2 connected to the gate GN2 and a gate reference voltage V REF,G and a negative input connected to the output of a resistor 744. The input of resistor 744 is connected to a ground signal through resistor 746, to the base B of the HBT (e.g., via network 612) and to a ground signal, and directly to the drain DN2 of NMOS2.

[0081] The operational amplifiers 730 and / or 720 of circuits 700 and 702 provide feedback elements for sensing the gate / base and drain / collector DC bias voltages of the HEMTs and HBTs. The drain / collector voltages at the negative input of the operational amplifier 720 and the reference voltage V at the positive input of the operational amplifier 720 are REF,DThe error signal between is amplified in an OP amp 720, and the resulting OP amp output O1 is used to generate a DC bias for the drain D or collector C using the source SP1 or SP2 of the PMOS1 or PMOS2 transistor. The error voltage signal at OP amp 720 may cause output O1 to generate a change in the gate GP1 or GP2 of PMOS1 or PMOS2 to adjust the perturbation in the error signal of the DC bias for the HEMT drain or HBT collector. In other words, if the drain voltage supply 622 of circuit 700 drops locally on the wafer 110 (or at drain D), feedback amplifier OP amp 720 senses the drop and feeds back an increased or sufficiently high voltage that increases the drain voltage delivered at D to compensate for the drop and keep the DC bias drain voltage stable during the drop. If the collector voltage source 662 of circuit 702 drops locally on the wafer 110 (or at collector C), the feedback amplifier OPAMP 720 senses the drop and feeds back an increased or sufficiently high voltage that increases the collector voltage delivered at C to compensate for the drop and keep the DC bias collector voltage stable during the drop. The impedance presented by the PMOS is low because the effect of the feedback is to change the current generated in response to sensing the voltage.

[0082] Also, or separately, the gate at the negative input of the operational amplifier 730 and the reference voltage V REF、G The error signal of circuit 700 between is amplified in op amp 730 and the resulting op amp output O2 is used to generate the DC bias for gate G.

[0083] Also, or separately, the base at the negative input of the operational amplifier 730 and the reference voltage V at the positive input of the operational amplifier 730 REF、G The error signal of circuit 702 between is amplified in op amp 730 and the resulting op amp output O2 is used to generate the DC bias for base B using the drain DN2 of NMOS2.

[0084] The error voltage signal at the OP amp 730 of circuit 700 may cause output O2 to generate a change in gate G that adjusts the perturbation in the DC bias error signal for the HEMT gate. In other words, if the gate voltage supply 632 drops locally on the wafer 110 (or at gate G), the feedback amplifier OP amp 730 senses the drop and feeds back an increased or sufficiently high voltage that increases the gate voltage delivered at G to compensate for the drop and keep the DC bias gate voltage stable during the drop. The error voltage signal at the OP amp 730 of circuit 702 may cause output O2 to generate a change in gate GN2 of NMOS2 that adjusts the perturbation in the DC bias error signal for the HBT base. In other words, if the base voltage supply 672 drops locally on the wafer 110 (or at base B), the feedback amplifier OP amp 730 senses the drop and feeds back an increased or sufficiently high voltage that increases the base voltage delivered at B to compensate for the drop and keep the DC bias base voltage stable during the drop. The gate and / or base voltage may be regulated according to (e.g., to compensate for) changes in device temperature, shifts in transistor parameters or characteristics, input or output power reflecting the linear region of operation of the transistor, and other performance characteristics directly affected by gate bias.

[0085] Advantages of using op amps 730 and / or 720 include their proximity to the chiplet transistors on wafer 110, as described for the CMOS transistors in Figure 6. That is, op amps 730 and / or 720 may be local to chiplet 130b or 130a, such as within 50-400 microns (or, for example, within 100 microns) of the chiplet. This locality reduces undesirable impedance, noise, capacitance, and inductance in the signal lines or signals from the op amps at frequencies near the signal bandwidth of the RF chiplet transistors.

[0086] In some cases, CMOS transistors in the wafer 110 may be hybridized with RF transistors in the chiplets, substituting a low-dropout voltage regulator for any or all of the illustrated PMOS1 or 2, NMOS1 or 2, gate, drain, base, and / or collector voltage supplies. In this case, the low-dropout voltage regulator may control the DC bias voltage supplies for the gate / drain and / or base / collector of compound semiconductor device HEMT and / or HBT transistors integrated in the chiplets in the same substate of the wafer 110. The low-dropout regulator reduces DC power dissipated in the drain D or collector C while creating a low impedance at the drain or collector, optimizing the transistor's ability to respond to voltage perturbations within the signal bandwidth without altering the supply presented to the transistor. The low-dropout regulator may similarly reduce DC power dissipated in the gate G or base B.

[0087] FIG. 8 shows an exploded top view of circuit 800, which includes a CMOS-based wafer 110 (e.g., a silicon interposer) with power detectors 810 and 820, and potentially voltage or current detectors, and a temperature sensor 870, and a HEMT from chiplet 130b heterogeneously integrated on wafer 110. Circuit 800 includes feedback operational amplifiers 720 and 730 with outputs O1 and O2 connected to gates GP1 and GN1, respectively. Circuit 800 may be similar to circuit 700, except that circuit 800 uses power / voltage detector 810 instead of resistors 724 and 726 for the negative input to operational amplifier 720, power / voltage detector 820 instead of resistors 734 and 736 for the negative input to operational amplifier 730, and includes temperature sensor 870. Either or both of detectors 810 and 820 may be power detectors or voltage / current detectors. Any power / voltage detector can replace the conventional resistor setup in Figure 7. A temperature sensor may be optional and can be used with the V REF,G and / or VREF,D It provides a reference that can be applied to the signal.

[0088] Power / voltage detector 810 has an input I1 connected to RF output 644 and an output VO1 connected to the negative input to operational amplifier 720. Power / voltage detector 820 has an input I2 connected to RF input 642 and an output VO2 connected to the negative input to operational amplifier 730.

[0089] Each of the power / voltage detectors 810 and 820 is represented by an expanded circuit diagram 830. For detectors 810 and 820, the "RF input" in diagram 830 is either RF output 644 or RF input 624, and the "V PD " is the negative input VO1 or VO2 to the op amp 720 or 730, respectively.

[0090] Circuit 800 includes power or voltage detectors 810 and 820 that use feedback elements, such as operational amplifiers 720 and 730, to generate a desired voltage V REF,D and V REF,G 10 shows how the difference between the measured voltages VO1 and VO2 can be amplified and connected through the CMOS transistors of wafer 110 at the drain D of the HEMT chiplet for PMOS1 and the gate G of the HEMT chiplet for NMOS1, respectively.

[0091] Diagram 830 shows how each power detector 810 and 820 is constructed from a diode-connected transistor M1 driven through a high-frequency capacitor C1. Based on the ratio of the capacitance of capacitor C1 compared to the gate-to-source capacitance of transistor M1, V PDThe voltage change at (e.g., VO1 and VO2) will be stronger or weaker at certain power levels at the RF input. Transistor M1 may be an NMOS transistor such as NMOS1. Circuit 800 and diagram 830 show how an RF block such as a power detector or voltage detector 810 or 820 can be integrated as part of the matching network 612 or bonding interface. A feedback element such as operational amplifier 720 or 730 can amplify the error signal between the desired (reference) voltage and the measured voltage VO1 or VO2 and apply a correction via transistor PMOS1 or NMOS1 at either the drain D or gate G.

[0092] The reference voltage for sensing RF power may be derived from a bandgap reference, as shown in diagram 870 or 880. The principle of a bandgap voltage reference is to balance the negative temperature coefficient of a PN junction, such as an op-amp and / or a HEMT, with the positive temperature coefficient of the thermal voltage (Vt = kT / q). The bandgap reference generates a voltage that exhibits no more than 3-5 mV variation over a temperature range of -70 to 250°C. The desired voltage variation coefficient as a function of temperature is achieved by balancing the positive and negative temperature coefficients. This power detector implementation is extremely compact and has the advantage of low capacitance, allowing it to be incorporated in many locations along the RF signal path 642 or 644. The extremely small area may have a length and width between 10 and 100 microns, depending on the operating frequency.

[0093] Advantages of using detectors 810 and 820 include their proximity to the chiplet transistors on wafer 110, as described for the CMOS transistors in FIG. 6. That is, detectors 810 and 820 may be local to chiplet 130b, such as within 50-400 microns (or, for example, within 100 microns) of chiplet 130b. This locality reduces undesirable impedance, noise, capacitance, and inductance in the signal lines or signals from the detectors and op amps, such as at frequencies near the signal bandwidth of the RF chiplet transistors. Sensing power and voltage as close as possible to the transistors on chiplet 130b improves the RF characteristics of the circuit, such as output power, gain, and efficiency.

[0094] Either or both of the FET transistors M1 can be replaced with a bipolar junction transistor (BJT) having its base directly coupled to its collector, as well as the M1 gate coupled to its source.

[0095] Temperature sensor 870 is represented by an expanded circuit diagram 880. Diagram 880 shows the reference voltage V output by op amp 872 using different diodes D1 and D2, along with feedback resistors R1 and R2. REF 8 shows how a temperature sensor 870 can be constructed from an op amp input. The pn diodes D1 and D2 are different because diode D1 has a larger geometry than diode D2, but they have approximately the same current. Diodes have a negative temperature coefficient for the forward voltage across the diode for a fixed current. The larger diode D1 has a smaller forward voltage than diode D2, and the difference in voltage across the diode has a positive temperature coefficient. Resistor RB compensates for the smaller voltage across diode D1 relative to diode D2. The op amp forces the voltage input terminals to the same voltage, so the connections of the different diodes to the emitter signal lines may be electrical and / or thermal. Voltage V REF is the voltage V REF,Dand / or V REF,G It may also be used as

[0096] The sensor 870 may be an environmental detector that senses the temperature of the compound semiconductor transistors of the chiplets in the silicon substrate wafer 110. Here, the reference voltage V REF is generated from a silicon-based temperature sensor 870 on wafer 110 using differential pn diodes D1 and D2 with a feedback operational amplifier OPAMP 872 to supply current to the two diodes. This circuit 870 may be a bandgap reference adopted from other circuit technologies, such as Widlar bandgap, which may be adapted to measure the temperature of the HEMT or HBT of chiplet 130b or 130a due to the ability to integrate this sensor within wafer 110 near the chiplets.

[0097] Advantages of using sensor 870 include its proximity to the chiplet transistors on wafer 110, as described for the CMOS transistors in FIG. 6. That is, sensor 870 may be local to the chiplet, such as within 50-400 microns (or, for example, within 100 microns) of the chiplet. This locality reduces the error between the temperature detected by sensor 870 and the actual temperature of the chiplet or chiplet transistor, so that the DC bias reference voltage V REF The accuracy of the

[0098] The techniques of circuit 800 can be used to improve the accuracy of the DC bias of the HBTs of chiplet 130a. For example, power / voltage detectors 810 and 820 can provide feedback elements to provide negative inputs to operational amplifiers 720 and 730, respectively, to improve the accuracy of the HBT's base and collector DC bias voltages. Temperature sensor 870 can also provide feedback elements to provide positive reference voltage inputs to operational amplifiers 720 and 730 to improve the accuracy of the HBT's base and collector DC bias voltages.

[0099] 9A shows an exploded top view of circuit 900 including CMOS-based wafer 110 (e.g., silicon interposer) with a portion of temperature sensor 970 and an HBT of chiplet 130a heterogeneously integrated with wafer 110 with another portion of temperature sensor 970. Circuit 900 includes feedback operational amplifiers 720 and 730 with outputs O1 and O2 connected to gates GP2 and GN2 of PMOS2 and NMOS2, respectively, and power / voltage detectors 810 and 820 that output VO1 and VO2 to the negative inputs of amplifiers 720 and 730. Circuit 900 may be similar to circuit 602, except that circuit 900 uses operational amplifiers 720 and 730, power / voltage detectors 810 and 820, and temperature sensor 970. Circuit 900 may be similar to circuit 800, except that circuit 900 uses an HBT instead of a HEMT and sensor 970 instead of sensor 870.

[0100] Temperature sensor 970 uses differential diodes D3 and D4 connected to the HBT emitter E signal line on chiplet 130a along with feedback resistors R1 and R2 to generate a reference voltage V output by op amp 972. REF can be constructed from the op amp input of the temperature sensor 970. The pn diodes D3 and D4 are not equal because diode D3 has a larger geometry than diode D4. Diode D3 may be 4, 8, or 16 times larger than diode D4. Considering similar currents in D3 and D4, the larger diode D3 has a smaller forward voltage than diode D4, and resistor RB may be used to cancel out the voltage difference. The connections of the different diodes to the emitter signal lines may be electrical and / or thermal connections. The voltage V REF is the voltage V REF,D and / or V REF,G The diodes sense temperature differences on the chiplet while the feedback circuitry is located on the host CMOS wafer.

[0101] 9B shows an exploded top view of circuit 950 including a CMOS-based wafer 110 (e.g., a silicon interposer) with a portion of temperature sensor 980 and an HBT from chiplet 130a heterogeneously integrated on wafer 110 with another portion of temperature sensor 980. Diodes D3 and D4 are electrically isolated from the signal line connected to HBT emitter E. That is, no signal is present on the signal line between the diodes and the emitter or from the emitter to ground. Circuit 950 thus reduces or eliminates the capacitance that diodes D3 and D4 add to emitter E. This reduction or elimination results in cleaner, better HBT performance and / or reduced noise.

[0102] Temperature sensor 980 uses differential diodes D3 and D4, which are not connected to the HBT emitter E signal line on chiplet 130a, along with feedback resistors R1 and R2, to measure the reference voltage V output by op amp 972. REF Figure 9 shows how a temperature sensor 980 can be constructed from the op amp inputs. The pn diodes D3 and D4 are unequal; the larger diode D3 has a smaller forward voltage than diode D4; a resistor RB may be used to cancel the voltage difference. There are no connections to the different diodes to the emitter signal lines, so there is no electrical or thermal connection. The diodes sense temperature differences on the chiplet while the feedback circuit is located on the host CMOS wafer. The signal line from the diode to ground may be attached to a thermal pad on the chiplet.

[0103] Using sensor 970 or 980 instead of sensor 870 provides an improvement over temperature sensor 870 because different diodes D3 and D4 are implemented on the chiplet, increasing the accuracy of temperature monitoring by sensor 970 or 980 compared to diodes D1 and D2 on wafer 110. The reference voltage V generated from temperature center 970 or 980 REF is the reference voltage V REF,D and V REF,Gcan be used to provide both drain and gate bias circuits, such as the positive inputs of op amps 720 and 730.

[0104] 9A-9B, the techniques of circuits 900 and 950 can also or alternatively be used to improve the accuracy of the DC bias of the HEMT of chiplet 130b. For example, temperature sensor 970 or 980 can provide a feedback element to provide a positive input to operational amplifiers 720 and 730 to improve the accuracy of the DC bias voltages of the drain D and gate G of the HEMT.

[0105] Using sensor 970 or 980 instead of sensor 870 offers an improvement over temperature sensor 870 and other temperature sensors because sensor 970 or 980 leverages heterogeneous devices on wafer 110 and chiplets, moving the pn unequal diode from CMOS on wafer 110 to compound semiconductor chiplet 130a or 130b. The advantage of this approach is that the pn diode is closer to the chiplet transistors and therefore represents the temperature on the chiplet much more accurately. Here, feedback amplifier 972 is realized using silicon CMOS transistors on wafer 110 and reflects the same core operation as bandgap reference circuit 800. Having amplifier 972 and sensor 970 or 980 resistors on wafer 110 provides the advantages described herein for on-wafer CMOS devices local to the chiplets and their transistors, allowing for the inexpensive fabrication of Si wafer CMOS devices instead of more expensive CMOS devices using area 1 and fabricating CMOS on the chiplet semiconductor material.

[0106] FIG. 10 shows a block diagram 1000 of a wireless receiver 1002 (e.g., a product) including a CMOS-based wafer 1010 (e.g., a silicon interposer) with chiplet compound semiconductor devices 1031, 1032, and 1033 (and optionally a local oscillator driver or amplifier—LO amplifier 1007) heterogeneously integrated on the wafer 1010. The wafer 1010 may be a chip or integrated circuit diced from the wafer 110. Each of the device blocks 1031, 1032, and 1007 may be a chiplet 130a and / or 130b. Each of the device blocks 1031, 1032, and 1007 may be a low-noise RF amplifier. Each block other than the device blocks 1031, 1032, and 1007 may be CMOS or other wafer 110-based technology.

[0107] Diagram 1000 may be or may include a radio frequency (RF) or millimeter wave receiver 1002, which may be fully integrated in a chip or integrated circuit or may be diced from a wafer 110. The receiver 1002 has an RF input 1042, such as may be connected to an RF antenna, and an output 1044, such as may be configured to provide a baseband output.

[0108] The blocks of receiver 1002 or wafer 1010 would ideally be selected for performance constraints such as gain, noise, linearity, power consumption, and / or bandwidth, and using the embedding approach illustrated in FIG. 6 . The blocks of receiver 1002 or wafer 1010 may be used to incorporate a diverse portfolio of device technologies, such as GaN, GaAs, or InP HEMT, for the first 1-3 stages of the low-noise amplifier, shown as blocks 1031 and 1032 (and optionally 1007). The amplifier stages may be constructed from two different technologies. Other device technologies, such as GaN, GaAs, or InP HBT, may be integrated for higher gain or output power RF amplifier blocks. For example, blocks 1031 and 1032 may be InP HEMT chiplets, and LO amplifier 1007 may be an InP HBT amplifier or an InP HEMT amplifier. In some cases, blocks 1031 and 1032 may be in one or more chiplets 130b, while LO amplifier 1007 may be in chiplet 130a. Block diagram 1000 shows how the components previously described in Figures 6-9, including bias generators such as PMOS1-2 and NMOS1-2, feedback circuits such as OP amps 720 and 730, and power detectors such as detectors 810 and 820 (and temperature sensors such as sensors 870 and / or 970), may be organized into receiver product 1002 that is fully integrated on a single substrate 1010 with chiplet compound semiconductor transistor devices.

[0109] Bias generators, such as PMOS1-2 and NMOS1-2 in FIGS. 6-9, may be shown as blocks “bias” and “BG” for improving the DC bias of the transistors in chiplet blocks 1031, 1032, and 1033. Feedback circuits, such as OP amps 720 and 730 in FIGS. 7-9, may be shown as blocks “power supply modulator,” “LDO,” and “BG” for improving the DC bias of the transistors in chiplet blocks 1031, 1032, and 1033. Power detectors, such as detectors 810 and 820 in FIGS. 8-9, may be shown as block “PD” for improving the DC bias of the transistors in chiplet blocks 1031, 1032, and 1033. Temperature sensors, such as sensors 870 and / or 970 in FIGS. 8-9, may be part of either the chiplet blocks and / or wafer blocks for improving the DC bias of the transistors in chiplet blocks 1031, 1032, and 1033.

[0110] Furthermore, the CMOS mixer 1004 and the multiplier 1006 may be realized as radio frequency blocks supporting heterogeneous integration of transistor technologies into complex circuits such as the receiver 1002 or transmitter, i.e., concepts similar to those described for the diagram 1000 may be used to design a corresponding transmitter.

[0111] Diagram 1000 includes a close-up view 1040 of a CMOS mixer 1004. Diagram 1040 shows mixer 1004 with "RF," "IF," "LO," and "Vg" inputs that separately bias the gate and drain of the FET. In some cases, "Vg" provides bias Vg and Vd separately to the gate and drain of the HEMT. Diagram 1040 shows mixer 1004 with inputs at RF, LO, LO+, and LO-, and an IF. Mixer 1004 may be a frequency downconversion mixer that steps down from 80 GHz to a lower band around 9 GHz. Receiver 1002 has input IN1 connected to mixer 1004. The output of mixer 1004 is connected to baseband amplifier 1008, which provides output 1044.

[0112] Diagram 1000 includes a close-up view 1060 of a CMOS multiplier 1006. Diagram 1060 shows multiplier 1006 having "X2" or "2LO" and "X3" or "3LO" circuit sections connected by an OP local oscillator amplifier, cascading or multiplying the input LO frequency (IN1) by two and then three times to produce a six-times frequency multiplied output. Diagram 1000 shows a six-times multiplier 1006 that can be developed from two separate multipliers (X2) and (X3) with separate multiplication ratios (2x) and (3x) with phase inputs of 0 and 180 degrees for the X2 multiplier and 0, 120, and 240 degrees for the X3 multiplier. Diagram 1000 shows multiplier 1006 with an output of approximately 71 GHz. This allows for frequency conversion from 80 GHz to 9 GHz. The output of multiplier 1006 is connected to LO amplifier 1007, which generates enough power to drive the input of mixer 1004. This connection includes trap 1012, which extracts the output signal from multiplier 1006 that goes to mixer 1004 and passes it to a power detector PD. Similarly, the output of block 1031 is input to trap 1014, which extracts the output signal and passes it to a power detector PD.

[0113] Diagram 1000 shows the "CMOS blocks" including the power detector mixer, LDO, BG, bias circuitry, and frequency multiplier, as well as the BB amplifier.

[0114] Diagram 1000 shows "III-V chiplet" blocks such as low noise amplifier blocks 1031 and 1032 and LO driver amplifier blocks within amplifier 1007.

[0115]

[0033] Having the radio receiver 1002 on the wafer 110 or chip 1010 provides the advantages described herein for CMOS devices on the wafer that are local to the chiplets and their transistors, allowing for the inexpensive fabrication of Si wafer CMOS devices and the fabrication of CMOS on the chiplet semiconductor material instead of CMOS devices that use the more expensive area 1.

[0116] FIG. 11 shows a block diagram 1100 of envelope detector (ED) circuits 1100 and 1102, each including a CMOS-based wafer 1110 and 1120 (e.g., a silicon interposer) with chiplet compound semiconductor devices 1131 and 1132 hetero-integrated on the wafers 1110 and 1120. Each circuit 1100 and 1102 may be part of a radio (e.g., a product), such as part of a radio receiver 1002. Each of wafers 1110 and 1120, or the radios that are part of them, may be chips or integrated circuits diced from wafer 110. Each of device blocks 1131 and 1132 may be chiplets 130a and / or 130b. Each of device blocks 1131 and 1132 may be a low-noise RF amplifier. Block 1131 may be an RF driver, and block 1132 may be an RF power amplifier. Any of the chiplet power amplifiers 1132 and drivers 1131 of circuits 1100 and 1102 may be any of the circuits of Figures 6 to 9. Each block other than device blocks 1131 and 1132 may be CMOS or other wafer 110-based technology.

[0117] Circuits 1100 and 1102 may represent two alternative schemes or heterogeneous circuits for power amplifiers, using a CMOS envelope detector (ED) in circuit 1100 to extract or separately input into circuit 1102 the time-varying amplitude envelope of RF signal 1142, amplify the envelope in envelope amplifier 1114, and use the amplified envelope to modulate an envelope modulator, shown here as a power supply modulator such as a low-dropout regulator (LDO). The power supply modulator receiving the output of amplifier 1114 may be an envelope modulator respectively connected to each of amplifiers 1132 to modulate the envelope output by amplifiers 1132, such as by driving the supply of amplifier 1132 (or providing a bias signal to amplifier 1132). Thus, these power supply modulators may function or appear as LDOs.

[0118] Circuit 1100 illustrates envelope modulation, which traps an input RF signal in trap 1112 and extracts the envelope of the signal via an envelope detector ED to block 1131. The envelope at ED is amplified via a CMOS envelope amplifier 1114 and fed to a DC bias power supply, such as a power supply modulator. The output of the power supply modulator and block 1131 are input to block 1132, which provides output 1144 based on these inputs. Amplifier 1114 and / or ED may include Si CMOS transistors within wafer 110. The power supply modulator may include Si CMOS transistors within wafer 110.

[0119] Circuit 1102 illustrates an alternative to envelope modulation in circuit 1100 called envelope removal. In circuit 1102, time-varying amplitude information 1162 is provided separately from the phase information of amplifier 1114 from RF input 1142, which is provided to block 1131. The envelope or amplitude information 1162 is amplified through CMOS envelope amplifier 1114 and provided to a DC bias supply, such as a power supply modulator. The output of the power supply modulator and block 1131 is input to block 1132, which provides output 1164 based on these inputs.

[0120] Circuits 1100 and 1102 use wafer CMOS envelope signal circuits to improve the efficiency and linearity of chiplet compound semiconductor transistor performance. A typical problem with power supply modulators, LDOs, EDs, and power amplifier drains is their long wire bond lengths, which lead to parasitic inductance and / or capacitance. However, in circuits 1100 and 1102, the wafer CMOS power supply modulators, EDs, and amplifiers 1114 are very close to the chiplets, resulting in shorter interconnects 510, which significantly reduces the parasitic inductance and / or capacitance between those components and the chiplet transistors. In some cases, the length or distance of the interconnects 510 is four times shorter than a typical corresponding circuit that does not use the wafer and chiplet technology herein, such as using interconnects 510 directly to one of the lateral bonding materials 360. The four times shorter interconnect length or distance can linearly reduce the parasitic inductance and / or capacitance, e.g., four times lower parasitic inductance and / or capacitance. It should be noted that this reduction in parasitic inductance and / or capacitance is applicable to all of the embodiments of FIGS.

[0121] The length of the interconnect 510 may be in the range of 10-80 μm, or may be a few microns. The length may be less than 80 μm. The parasitic inductance may be proportional to the length of the interconnect on the lateral bonding material or the total length of the interconnect. As a result, the parasitic inductance may correspondingly be in the range of 10-80 picohenries (H), or may be less than 80 picohenries. Note that this reduction in parasitic inductance may apply to all of the embodiments of FIGS. 6-13.

[0122] Also, the CMOS power modulator, ED and amplifier 1114 on the wafer are very close to each other, which keeps the interconnects short to each other and reduces parasitic inductance and / or capacitance.

[0123] Furthermore, because they are fabricated from or on a Si wafer, the CMOS power modulators, EDs, and amplifiers 1114 are smaller and closer together than if they were fabricated on a chiplet or chiplet semiconductor material. Being smaller and closer together results in less parasitic inductance and / or capacitance between them.

[0124] 12 includes a CMOS-based wafer 1210 (e.g., a silicon interposer) with a CMOS observation receiver 1220, and shows a block diagram 1200 of a digital pre-distortion circuit 1202 including chiplet compound semiconductor devices 1131 and 1132 heterogeneously integrated on the wafer 1210. The circuit 1202 may be part of a radio (e.g., a product), such as part of the radio receiver 1002. The wafer 1210 or the radio of which it is a part may be a chip or integrated circuit diced from the wafer 110. Each block other than the device blocks 1131 and 1132 may be CMOS or other wafer 110-based technology.

[0125] Circuit 1200 illustrates another use of a heterogeneous integration approach for implementing digital predistortion. The output of power amplifier 1132 is tapped by tap 1212, and the tapped signal is used to feed back through a CMOS observation receiver 1220 to generate digital I and Q signals 1244. Receiver 1220 may be an analog / digital I / Q receiver. The I and Q signals 1244 are 90 degrees out of phase, referred to as "quadrature." The I signal may be a cosine waveform, and the Q signal may be a sine waveform. The I / Q receiver provides baseband information that can be sampled or subsampled at the Nyquist rate, and its output digital I and Q signals 1244 can be provided to a digital signal processor (DSP) (not shown), which can provide adaptation of input signal 1142 via feedback from the DSP. Tap 1212 and / or receiver 1220 may include Si CMOS transistors within wafer 110.

[0126] Circuit 1200 may be a heterodyne circuit for power amplifier 1132 that uses a CMOS observation receiver 1220 that monitors the complex signal generated by power amplifier 1132 and feeds this signal back to a digital signal processor as output digital I and Q signals 1244 to ensure that the complex signal meets the linearity requirements of the wireless physical layer specification. Here, the output of compound semiconductor device 1132 is tapped at tap 1212 to monitor the output signal of block 1132. The -30 dB tap value of the output signal of block 1132 is introduced by tap 1212 to I / Q mixers 1214 and 1216 of receiver 1220, each with a different frequency, to convert the complex signal into I and Q baseband signal components. Mixers 1214 and 1216 have LO signal inputs, and mixer 1216 phase-shifts the LO signal by 90 degrees. Relatively low sampling rate analog-to-digital (ADC) converters 1218 and 1219 may also be used to subsample each of the received (I and Q baseband signal components) signal bandwidths and reconstruct the linearity of the signals to output digital I and Q signals 1244. Converters 1218 and 1219 have low pass filters at their signal inputs.

[0127] Having receiver 1220 as a Si CMOS transistor in wafer 110 is very beneficial because there may be tens or hundreds of CMOS transistors in receiver 1220. Having these transistors in wafer 1210 can provide the same benefits as mentioned in FIG. 11 with respect to having the power supply modulator, ED, and trap 1112 in wafer 1110.

[0128] In a sense, this observation receiver 1220, which provides outputs I and Q to baseband, is the "Holy Grail" because it has on a single wafer 1202 or diced chip the power amplifier 1132 (and optionally driver 1131) to provide outputs to baseband, the coupler or tap 1212, and the observation receiver 1220. Having these on the same chip as all the CMOS transistors of the bottom receiver 1220 and the top two chiplets allows for a significant reduction in parasitic inductance and / or capacitance.

[0129] Having receiver 1220 as a Si CMOS transistor within wafer 110 is highly beneficial because the lengths of interconnects 510 between receiver 1220 and components of blocks 1131 and 1132 can be in the range of 10-80 μm or a few microns. The lengths may be less than 80 μm. The parasitic inductance in these interconnects 510 may be proportional to the length of the interconnect on the lateral junction material or the total length of the interconnect. As a result, the parasitic inductance of these interconnects 510 may correspondingly be in the range of 10-80 picohenries (H) or less than 80 picohenries.

[0130] FIG. 13 shows a block diagram 1300 of an impedance tuner 1302 for an antenna 1305, the tuner 1302 including a CMOS-based wafer 1310 (e.g., a silicon interposer) with a CMOS matching network 1312 and chiplet compound semiconductor devices 1132 and 1332 heterogeneously integrated on the wafer 1310. The circuit 1302 may be part of a radio (e.g., a product), such as part of a radio receiver 1002. The wafer 1310 or the radio of which it is a part may be a chip or integrated circuit diced from the wafer 110. Any of the blocks 1132 and 1332 may be any of the circuits of FIGS. 6-9. Each component or block other than the device blocks 1132 and 1332 may be CMOS or other wafer 110-based technology.

[0131] Each of device blocks 1132 and 1332 may be chiplets 130a and / or 130b. Block 1132 may be a low-noise RF amplifier. Block 1132 may be an RF driver or an RF power amplifier. Block 1332 may be a high-Q tuning capacitor formed on a composite semiconductor chiplet integrated on wafer 1310.

[0132] Circuit 1300 illustrates another use of a heterogeneous integration approach using chiplets 1131 and 1332 integrated on a wafer 1310 to perform impedance tuning between a power amplifier (1131) and an antenna 1305. Tuner 1302 has an RF input 1142 to block 1131, a tuning voltage input 1342 to a resistor, and an output 1344 to antenna 1305. The output of chiplet power amplifier 1131 is coupled to a passive matching network 1312 and chiplet block 1332 on silicon interposer or wafer 1310. Block 1332 is a high-Q tuning capacitor formed as an alternative compound semiconductor chiplet device integrated on wafer 1310. Impedance tuner 1302 is shown as a capital T-network with an inductor and block 1332.

[0133] Circuit 1300 may be a heterogeneous RF circuit for power amplifier 1131 that performs tuning of the impedance presented to power amplifier 1131 by antenna 1305. The tuning impedance can be generated using CMOS transistors in chiplet block 1332, such as SOI switches that provide tunable capacitors. These chiplet tunable capacitors can adjust the impedance match between antenna 1305 and power amplifier 1131 and are shown as T-networks formed with series inductors and shunt variable capacitors 1332. Other network implementations are possible, such as a π-network formed with a pair of shunt variable capacitors (e.g., the pair in block 1332) and a series inductor, or a π-network formed with a series inductor and a shunt capacitor. Chiplet stacked FET SOI transistors can also be used to improve the power handling of tuning element 1332.

[0134] Network 1312 may be or be included as part of network 612, network 652 or another matching network on wafer 1310 or 110, such as having passive capacitors, inductors, resistors and connections to ground connected to devices 1132 and / or 1332 via hetero interconnect 510.

[0135] Having a tuner 1302 with better semiconductor chiplet devices and blocks 1332 of networks 1312 on a Si wafer 1310 is highly beneficial because it allows for higher quality factors (high Q) and lower losses when combining chiplets with on-wafer CMOS in block 1332. Other designs that do not use chiplet-based blocks 1332 typically must use stacked FETs and switches.

[0136] 6-13, the wafer CMOS transistors, diced chip CMOS transistors, tuning circuits, matching network circuits, DC bias CMOS, feedback op amps, power detectors, and temperature sensors of the wafer may be on the same vertical layer as the chiplet RF transistors. Being on the same vertical level allows for shorter connections between the CMOS transistors and the RF transistors, such as using interconnects 510 that may be horizontal and / or require shorter vertical interconnect or connection pad distances, thereby reducing noise, improving DC bias accuracy, and significantly reducing parasitic inductance and / or capacitance.

[0137] 6-13 can show in-substrate circuitry for optimizing heterogeneous device operating conditions. Advantages of this approach over other designs include the use of lateral mechanochemical chiplet bonding material 360 to form a low-cost, scalable volume, the use of wafer CMOS circuitry to control chiplet operating conditions, and the use of wafer CMOS circuitry directly to control HEMTs and / or HBTs integrated on the interposer / wafer used for chiplet integration without degrading the performance of the chiplets or diced chips.

[0138] First, Figures 6-13 can illustrate CMOS transistors realized in a juxtaposed silicon substrate (e.g., a wafer or a diced chip having wafer 110 and chiplets) to activate DC biasing of the compound semiconductor transistors of the chiplets to optimize mm-wave operation. The gate (or base) bias of the HEMT or HBT is provided to optimize the performance of the integrated chiplet transistors by maintaining maximum gain, output power, noise, and / or efficiency. Additionally, the described embodiments provide drain (or collector) bias of the HEMT (or HBT) to moderate the voltage supply. CMOS transistors realized in a juxtaposed silicon substrate can be used for power management of intra-wafer integrated chiplet III-V devices via analog or digital feedback that can adjust the voltage or current applied to the transistor.

[0139] Second, Figures 7-13 show that a CMOS transistor implemented in a juxtaposed silicon substrate senses the operating conditions of the HEMT (or HBT). The CMOS transistor is designed to generate a voltage or current in response to RF power incident on the gate (or base) of the HEMT (or HBT) and generated on the drain (or collector) of the transistor. Furthermore, the CMOS transistor monitors the operating temperature of the compound semiconductor transistor through a circuit that generates a voltage or current that is constant and / or proportional to temperature.

[0140] 10-13 can illustrate that CMOS transistors implemented in collocated silicon substrates can be used to generate analog and RF blocks in transmitter or receiver chains, including frequency multipliers, frequency mixers, phase shifters, signal attenuators, and even radio frequency, intermediate frequency, or baseband amplifiers. Advantages of this collocation include the proximity between CMOS and HEMT or HBT chiplet transistors to avoid losses in parasitic elements.

[0141] Fourth, Figures 10-13 and / or 8-9B can illustrate the applicability of the unique combination of CMOS and HEMT / HBT for RF applications in monolithic wafers to extreme conditions, such as high or low temperatures, such as may be found in satellite electronics or cryogenic environments, where the heterogeneous integration of chiplets with the wafer allows temperature sensors on the wafer, or partially on the wafer and chiplets, to survive and operate properly in these extreme conditions.

[0142] The embodiments of Figures 10-13 disclose methods, devices, and systems that integrate wafer-based CMOS and chiplet-based HEMT or HBT transistors and utilize wafer-based CMOS transistors to achieve digital and analog behavior for sensing, actuating, and improving RF circuits, such as chiplets, at much lower power and cost.

[0143] In some cases, embodiments herein include an electronic assembly having one or more RF transistor chiplets, each having chiplet circuitry including a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT); a host wafer having at least one host wafer circuit intended to generate bias conditions that optimize the performance of the HEMT or HBT, the at least one host wafer circuit including either a first circuit for providing a DC bias to the HEMT or HBT or a second circuit configured to sense radio frequency operating conditions, such as the DC bias and / or operating temperature, of the HEMT or HBT; and electrical interconnects between the chiplet and the host wafer that electrically connect the host wafer circuitry to the chiplet circuitry. The host wafer circuit can include the first circuit for providing a DC bias to the HEMT or HBT and the second circuit configured to sense an operating state of the HEMT or HBT.

[0144] One or more chiplets can have one or more HEMTs or one or more HBTs. One or more chiplets can have one or more HEMTs and one or more HBTs. One chiplet is formed from (e.g., with, using, so, or on) a first semiconductor material, another chiplet is formed from a second semiconductor material, and the wafer is formed from a third semiconductor material. The first and second semiconductor materials can be different materials from the third semiconductor material, or the first, second, and third semiconductor materials can all be different materials from each other.

[0145] The first circuit may be configured to provide a DC bias for the HEMT or HBT, such as by actuating the DC bias of the HEMT or HBT to optimize millimeter-wave operation of the HEMT or HBT. The first circuit may include at least one CMOS transistor configured to optimize the performance of the HEMT or HBT by maintaining maximum gain, output power, noise, and / or efficiency, provide a gate or base bias for the HEMT or HBT (e.g., an NMOS transistor having a drain electrically connected to the gate or base of the HEMT or HBT and a source electrically connected to a gate or base voltage source of the HEMT or HBT), and / or provide a drain or collector bias for the HEMT or HBT to moderate a voltage supply, such as on a wafer.

[0146] The second circuit may be configured to sense an operating condition, such as the DC bias of the HEMT or HBT, or may comprise an NMOS transistor (e.g., having a drain electrically connected to the gate or base of the HEMT or HBT and a source electrically connected to a gate or base voltage source for the HEMT or HBT, one input electrically connected to a gate or base reference voltage and / or current signal, a second input electrically connected to the gate or base of the HEMT or HBT, and an output electrically connected to the gate of the NMOS transistor) for generating a voltage or current signal at the gate or base of the HEMT or HBT (e.g., at, on, at, coupled to, towards, the signal may pass through other circuitry such as an inductor) in response to RF power incident on the gate or base of the HEMT or HBT. and a feedback element including an operational amplifier having a gate connected to the drain or collector of the HEMT or HBT, and a drain electrically connected to a drain or collector voltage source for the HEMT or HBT; one input electrically connected to a drain or collector reference voltage and / or current signal, a second input electrically connected to the drain or collector of the HEMT or HBT, and an output electrically connected to the gate of a PMOS transistor), and / or at least one CMOS transistor configured to generate a voltage or current at the drain or collector of the HEMT or HBT in response to RF power incident on the drain or collector of the HEMT or HBT.

[0147] In some cases, the second circuit includes at least one temperature sensor configured to monitor or sense an operating temperature of the HEMT or HBT and generate a reference voltage or current that is constant and / or proportional to the monitored / sensed temperature. The temperature sensor may include a first P / N diode and a second P / N diode on the chiplet electrically coupled to the HEMT or HBT (e.g., its source or emitter), the second diode having electrical characteristics / resistance unequal to the electrical characteristics / resistance of the first diode. The temperature sensor may include an operational amplifier, a first feedback resistor between the output of the operational amplifier (the first input of the operational amplifier and the first diode), and a second feedback resistor between the output of the operational amplifier, the second input of the operational amplifier, and the second diode.

[0148] In some cases, one host wafer circuit has a third circuit configured to generate analog and / or RF blocks (e.g., using or within a HEMT or HBT) in either the transmitter or receiver chain including one of a frequency multiplier, a frequency mixer, a phase shifter, a signal attenuator, an RF intermediate frequency or baseband amplifier.

[0149] "Being for," "for," "toward," or "performing" an action may include being capable of performing or configured to perform that action. Connecting to another device may include being coupled to, electrically connected to, and / or electrically coupled to the other device.

[0150] (Conclusion)

[0151] Throughout this description, the embodiments and examples shown should be considered exemplars, not limitations, on the devices and procedures disclosed or claimed. While many of the examples presented herein include specific combinations of method acts or system elements, it should be understood that those acts and their elements can be combined in other ways to achieve the same purpose. With respect to flowcharts, additional steps may be included or fewer steps may be performed, and the steps shown may be combined or further modified to achieve the methods described herein. Acts, elements, and features discussed only in connection with one embodiment are not intended to be excluded from a similar role in other embodiments.

[0152] As used herein, "plurality" means two or more. As used herein, a "set" of an item may include one or more such items. As used herein, whether in the written specification or claims, terms such as "comprising," "including," "carrying," "having," "containing," "involving," and the like, are to be understood to be open, i.e., including, but not limited to. With respect to the claims, only the transitional phrases "consisting of" and "consisting essentially of," respectively, are closed or semi-closed transitional phrases. The use of ordinal numbers such as "first," "second," "third," etc. to modify claim elements in the claims does not, of itself, imply any priority, precedence, or ordering of a claim element relative to other elements, nor any chronological order in which acts of a method are performed, but is merely used as a label to distinguish claim elements with a certain name from other elements with the same name (other than the use of ordinal numbers). As used herein, "and / or" means that the listed items are in the alternative, and that these alternatives also include any combination of the listed items.

Claims

1. 1. An electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets with interconnections to host wafer circuitry, said assembly comprising: at least one RF transistor chiplet, each having chiplet circuitry including a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT); a host wafer having at least one host wafer circuit for generating bias conditions that optimize performance of the HEMTs or HBTs, the at least one host wafer circuit including either a first circuit that provides a DC bias to the HEMTs or HBTs or a second circuit configured to sense radio frequency operating conditions of the HEMTs or HBTs; electrical interconnects between the chiplets and the host wafer that electrically connect the host wafer circuitry to the chiplet circuitry; An electronic assembly comprising:

2. 2. The electronic assembly of claim 1, wherein the at least one chiplet comprises at least two chiplets including a first chiplet having first chiplet circuitry with the high electron mobility transistor (HEMT) and a second chiplet having second chiplet circuitry with the heterojunction bipolar transistor (HBT).

3. 10. The electronic assembly of claim 1, wherein the at least one chiplet comprises at least two chiplets including a first chiplet having the high electron mobility transistor (HEMT) and a second chiplet having another high electron mobility transistor (HEMT).

4. 10. The electronic assembly of claim 1, wherein the at least one chiplet comprises at least two chiplets including a first chiplet having the heterojunction bipolar transistor (HBT) and a second chiplet having another heterojunction bipolar transistor (HBT).

5. 10. The electronic assembly of claim 1, wherein the at least one chiplet includes at least two chiplets each including one of a chiplet circuit including at least one high electron mobility transistor (HEMT) and at least one heterojunction bipolar transistor (HBT), a chiplet circuit including at least two high electron mobility transistors (HEMT), or a chiplet circuit including at least two heterojunction bipolar transistors (HBT).

6. the at least one chiplet includes at least two chiplets including a first chiplet formed from a first semiconductor material and a second chiplet formed from a second semiconductor material, and the host wafer is formed from a third semiconductor material; 2. The electronic assembly of claim 1, wherein either the first semiconductor material and the second semiconductor material are different materials from the third semiconductor material, or the first semiconductor material, the second semiconductor material, and the third semiconductor material are all different from each other.

7. the first circuit is configured to activate a DC bias of the HEMT or HBT to optimize RF characteristics of the HEMT or HBT; providing a gate or base bias for the HEMT or HBT to optimize the ability of the HEMT or HBT to maintain maximum gain, output power, noise or efficiency; or Providing a bias to the drain or collector of the HEMT or HBT to moderate the voltage supply.

10. The electronic assembly of claim 1, comprising at least one CMOS transistor configured to perform at least one of:

8. providing the gate or base bias includes an NMOS transistor having a source electrically connected to the gate or base of the HEMT or HBT and a drain electrically connected to a gate or base voltage source for the HEMT or HBT to provide the gate or base bias of the HEMT or HBT; 8. The electronic assembly of claim 7, wherein providing the drain or collector bias includes a PMOS transistor having a source electrically connected to a drain or collector of the HEMT or HBT to buffer a voltage supply on the host wafer, and a drain electrically connected to a drain or collector voltage source for the HEMT or HBT to provide a drain or collector bias for the HEMT or HBT.

9. the second circuit is configured to sense a DC bias of the HEMT or HBT; generating a voltage or current at the gate or base of the HEMT or HBT in response to RF power incident on the gate or base of the HEMT or HBT; or generating a voltage or current at the drain or collector of the HEMT or HBT in response to the RF power incident on the drain or collector of the HEMT or HBT; 10. The electronic assembly of claim 1, comprising at least one CMOS transistor configured to perform at least one of:

10. generating a voltage or current at the gate or base includes an NMOS transistor having a source electrically connected to the gate or base of the HEMT or HBT and a drain electrically connected to the gate or base voltage source of the HEMT or HBT; and a feedback element including an operational amplifier having one input electrically connected to a gate or base reference voltage or current signal, a second input electrically connected to the gate or base of the HEMT or HBT, and an output electrically connected to the gate of the NMOS transistor; 10. The electronic assembly of claim 9, wherein generating the voltage or current at the drain or collector includes a PMOS transistor having a source electrically connected to the drain or collector of the HEMT or HBT and a drain electrically connected to a drain or collector voltage source of the HEMT or HBT, and a feedback element including an operational amplifier having one input electrically connected to a drain or collector reference voltage or current signal, a second input electrically connected to the drain or collector of the HEMT or HBT, and an output electrically connected to a gate of the PMOS transistor.

11. The second circuit includes at least one temperature sensor configured to sense an operating temperature of the HEMT or HBT and generate a reference voltage or current that is constant and / or proportional to the monitored temperature, the temperature sensor comprising: a first P / N diode and a second P / N diode on the at least one chiplet electrically coupled to the HEMT or HBT, the second diode having electrical characteristics / resistance not equal to the electrical characteristics / resistance of the first diode; an operational amplifier; a first feedback resistor between the output of the operational amplifier and the first input of the operational amplifier and the first diode; a second feedback resistor between the output of the operational amplifier and a second input of the operational amplifier and the second diode; The electronic assembly of claim 1 , comprising:

12. a third circuit configured to generate either an analog or RF block in either the transmitter chain or the receiver chain, including one of a frequency multiplier, a frequency mixer, a phase shifter, a signal attenuator, an RF intermediate frequency or a baseband amplifier; The electronic assembly of claim 1 further comprising:

13. a backside capping layer having a top surface and a back surface; a back surface of the host wafer formed on first and second regions of the top surface of the backside capping layer and bonded to the top surface of the backside capping layer except for a first cavity and a second cavity in the host wafer, the first cavity and the second cavity having a first side and a second side, respectively; Furthermore, the at least one chiplet includes at least two first chiplets each including a first chiplet circuit having one of the high electron mobility transistors (HEMTs) and at least two second chiplets each including a second chiplet circuit having one of the heterojunction bipolar transistors (HBTs); the HBT includes a first chiplet thickness, a first backside, and a first frontside, the first backside of the first chiplet directly bonded to at least a first portion of a first region of the top surface of the backside capping layer, the first portion having a first capping layer thickness of the backside capping layer; the HEMT includes a second chiplet thickness, a second backside, and a second frontside, the second backsides of the at least two second chiplets directly bonded to at least a second portion of a second region of the top surface of the backside capping layer, the second portion having a second capping layer thickness of the backside capping layer; a lateral bonding material between sides of the first and second chiplets and the first and second sides of the first and second cavities; the first chiplet thickness is greater than the second chiplet thickness; the first capping layer thickness of the backside capping layer is less than the second capping layer thickness of the backside capping layer; 2. The electronic assembly of claim 1, wherein the second capping layer thickness of the backside capping layer includes a metal backfill plug between the second backside of the at least two second chiplets and the first capping layer thickness of the backside capping layer.

14. 10. The electronic assembly of claim 1, wherein the host wafer is diced vertically along a periphery of the host wafer around at least one chiplet to form chips, each of the chips comprising the at least one chiplet, interconnects, and an area of ​​the host wafer surrounding the at least one chiplet and having the at least one wafer circuit.

15. 1. An electronic assembly for heterogeneous integration of radio frequency (RF) transistor chiplets with interconnections to host wafer circuitry, said assembly comprising: at least one RF transistor chiplet, each having chiplet circuitry including a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT); a host wafer having at least one host wafer circuit for optimizing the operating conditions of the HEMTs or HBTs, the at least one host wafer circuit including either a first circuit for providing a DC bias to the HEMTs or HBTs or a second circuit configured to sense radio frequency operating conditions of the HEMTs or HBTs; a lateral bonding material disposed between a side surface of the at least one RF transistor chiplet and a side surface of a cavity in the host wafer; an electrical interconnect between the at least one chiplet and the host wafer, the electrical interconnect electrically connecting the host wafer circuitry to the chiplet circuitry; An electronic assembly comprising:

16. 16. The electronic assembly of claim 15, wherein the at least one chiplet comprises at least two chiplets including a first chiplet having first chiplet circuitry with the high electron mobility transistor (HEMT) and a second chiplet having second chiplet circuitry with the heterojunction bipolar transistor (HBT).

17. 16. The electronic assembly of claim 15, wherein the at least one chiplet includes at least two chiplets each including one of a chiplet circuit including at least one high electron mobility transistor (HEMT) and at least one heterojunction bipolar transistor (HBT), a chiplet circuit including at least two high electron mobility transistors (HEMT), or a chiplet circuit including at least two heterojunction bipolar transistors (HBT).

18. the at least one chiplet includes a first chiplet and a second chiplet, the first chiplet being formed from a first semiconductor material, the second chiplet being formed from a second semiconductor material, and the host wafer being formed from a third semiconductor material; 16. The electronic assembly of claim 15, wherein either the first semiconductor material and the second semiconductor material are different materials from the third semiconductor material, or the first semiconductor material, the second semiconductor material, and the third semiconductor material are all different from each other.

19. 16. The electronic assembly of claim 15, wherein the second circuit is for performing in extreme conditions, including temperatures found in satellite electronics or cryogenic environments.

20. 16. The electronic assembly of claim 15, wherein the interconnect has a length in the range of 10 to 80 μm and a parasitic inductance of the interconnect in the range of 10 to 80 picohenries (H).

21. 16. The electronic assembly of claim 15, wherein the HEMT is a high electron mobility field effect transistor that utilizes a heterojunction of materials with different band gaps to improve performance in high frequency applications, and the HBT is a type of bipolar junction transistor (BJT) that uses different semiconductor materials for the emitter and base regions to create a heterojunction, improving the BJT by handling very high frequency signals up to several hundred GHz.

22. 16. The electronic assembly of claim 15, wherein the host wafer includes at least one layer of silicon (Si), each chiplet including at least two HEMTs or HBTs and the interconnects from the transistors to contact pads on a front surface of the chiplet, each chiplet being a prefabricated transistor chiplet.

23. 1. An electronic assembly comprising: a plurality of RF transistor chiplets, each having chiplet circuitry including a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT); a host wafer having at least one host wafer circuit for adjusting operating bias conditions of the HEMTs or HBTs, the at least one host wafer circuit including a first circuit for providing a DC bias to the HEMTs or HBTs and a second circuit configured to sense radio frequency operating conditions of the HEMTs or HBTs; a lateral bonding material between a side surface of the plurality of RF transistor chiplets and a side surface of a cavity in the host wafer; electrical interconnects between the chiplets and the host wafer that electrically connect the host wafer circuitry to the chiplet circuitry; An electronic assembly comprising:

24. a first chiplet of the plurality of chiplets is formed from a first semiconductor material, a second chiplet of the plurality of chiplets is formed from a second semiconductor material, and the host wafer is formed from a third semiconductor material; 24. The electronic assembly of claim 23, wherein either the first semiconductor material and the second semiconductor material are different materials from the third semiconductor material, or the first semiconductor material, the second semiconductor material, and the third semiconductor material are all different from each other.

Images