Display device and method for controlling display device

Abstract

To provide a display device capable of reducing the amount of transmission data per unit time while maintaining image quality, and a control method of the display device.SOLUTION: The display device includes a control circuit. The control circuit transmits the gate control signal to the gate driving circuit such that a part of a first period GL1 in which the gate signal is supplied to the gate line P1 overlaps a part of a second period GL2 in which the gate signal is supplied to the gate line P1, the second period P1 starting at a time point after a start time point of the first period P1. The control circuit transmits a source control signal to the source drive circuit such that each of the first switch and the second switch is turned on once in one cycle of the horizontal synchronization signal. The control circuit transmits the source control signal to the source drive circuit such that one of the first switch and the second switch is turned on in a period P1 in which the first period P2 and the second period R1 overlap each other.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present disclosure relates to a display device and a method for controlling the display device. [Background technology]

[0002] The liquid crystal display driver described in Patent Document 1 is configured to perform double-vertical display operation. Double-vertical display operation involves outputting a display control signal including two basic clock signals from the controller while the latch signal is at a high level. The display control signal is input to a shift register. As a result, two rows of row electrodes are selected in the liquid crystal display while the latch signal is at a high level, and one row of display data is displayed on two rows of pixels in the liquid crystal display. Furthermore, if the number of basic clock signals is three or more while the latch signal is at a high level, it is possible to perform n-times vertical display (n is an integer greater than or equal to 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 5-150749 Summary of the Invention [Problem to be solved by the invention]

[0004] The liquid crystal display driver described in Patent Document 1 is configured to enable an integer multiple of vertical double-width display according to the number (integer) of base clock signals during the period when the latch signal is at a high level. This allows the amount of display data to be reduced. However, for example, a vertical n-fold display may result in too low image quality, while a vertical n-1-fold display (or a normal display at 1x) may result in image quality that is higher than necessary. As such, the liquid crystal display driver described in Patent Document 1 has the problem of making it difficult to reduce the amount of data transmitted per unit time while maintaining image quality.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a display device and a control method for a display device that can reduce the amount of data transmitted per unit time while maintaining image quality. [Means for solving the problem]

[0006] In order to solve the above problems, a display device according to a first aspect includes a plurality of transistors, a plurality of gate lines connected to the plurality of transistors, a plurality of source lines connected to the plurality of transistors, a gate drive circuit that supplies gate signals to the plurality of gate lines, a source drive circuit that supplies source signals to the plurality of source lines, and a control circuit that sends gate control signals to the gate drive circuit and sends source control signals to the source drive circuit. The source drive circuit includes an output unit that outputs the source signals, a first switch arranged between the output unit and a first group of source lines of the plurality of source lines, and a second switch arranged between the output unit and a second group of source lines of the plurality of source lines. The control circuit transmits the gate control signal to the gate drive circuit so that a portion of a first period in which the gate signal is supplied to a first gate line among the plurality of gate lines overlaps with a portion of a second period in which the gate signal is supplied to a second gate line adjacent to the first gate line, the second period starting later than the start of the first period, so that, where n is a natural number and m is a natural number greater than n, the gate signals are supplied from the gate drive circuit to m gate lines within n periods of a horizontal synchronization signal and m divided by n is a rational number other than an integer. The control circuit transmits the source control signal to the source drive circuit so that the first switch and the second switch are each turned on once within one period of the horizontal synchronization signal, and transmits the source control signal to the source drive circuit so that one of the first switch and the second switch is turned on during the period in which the first period and the second period overlap.

[0007] A second aspect of the present invention provides a method for controlling a display device comprising: a plurality of transistors; a plurality of gate lines connected to the plurality of transistors; a plurality of source lines connected to the plurality of transistors; a gate drive circuit that supplies gate signals to the plurality of gate lines; and a source drive circuit that supplies source signals to the plurality of source lines, wherein the source drive circuit includes an output section that outputs the source signals; a first switch that is arranged between the output section and a first group of source lines among the plurality of source lines; and a second switch that is arranged between the output section and a second group of source lines among the plurality of source lines, wherein, where n is a natural number and m is a natural number greater than n, the method comprises: the gate drive circuit is operated so that a part of a first period in which the gate signal is supplied to a first gate line of the plurality of gate lines overlaps with a part of a second period in which the gate signal is supplied to a second gate line adjacent to the first gate line, the second period starting at a point after the start of the first period, so that the gate signal is supplied to m gate lines and m divided by n is a rational number other than an integer; the source drive circuit is operated so that the first switch and the second switch are each turned on once within one cycle of a horizontal synchronization signal; and the source drive circuit is operated so that one of the first switch and the second switch is turned on within the period in which the first period and the second period overlap. [Effects of the Invention]

[0008] According to the above configuration, it is possible to reduce the amount of data transmitted per unit time while maintaining image quality. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of the display panel 10. As shown in FIG. [Figure 3]FIG. 3 is a diagram showing a part of the configuration of the source driver circuit 3. As shown in FIG. [Figure 4] FIG. 4 is a timing chart for explaining normal display (single-size vertical display) of the source drive circuit 3 according to the first embodiment. [Figure 5] FIG. 5 is a diagram for explaining an example of normal display (vertical single-size display) of the source driving circuit 3. In FIG. [Figure 6] FIG. 6 is a schematic diagram showing the correspondence between transmission data and on-screen display in normal display. [Figure 7] FIG. 7 is a timing chart for explaining the operation of the source drive circuit 3 according to the first embodiment for double-height display. [Figure 8] FIG. 8 is a diagram for explaining an example of double-height display of the source driving circuit 3. In FIG. [Figure 9] FIG. 9 is a schematic diagram showing the correspondence between transmitted data and on-screen display in double-height display. [Figure 10] FIG. 10 is a timing chart for explaining the operation of the source drive circuit 3 according to the first embodiment for displaying a 1.5x vertical size image. [Figure 11] FIG. 11 is a diagram for explaining an example of a 1.5x vertical display by the source driving circuit 3. In FIG. [Figure 12] FIG. 12 is a schematic diagram showing the correspondence between transmitted data and on-screen display in a 1.5x vertical size display. [Figure 13] FIG. 13 is a block diagram showing the configuration of a display device 200 according to the second embodiment. [Figure 14] FIG. 14 is a diagram showing a part of the configuration of a source driver circuit 203 according to the second embodiment. [Figure 15] FIG. 15 is a timing chart for explaining the operation of the source driving circuit 203 according to the second embodiment for displaying a 1.5 times vertical size image. [Figure 16] FIG. 16 is a diagram for explaining an example of a 1.5x vertical display of the source driving circuit 203 according to the second embodiment. [Figure 17]FIG. 17 is a timing chart for explaining the operation of the source driver circuit 203 according to the second embodiment for displaying a 1.33x vertical size image. [Figure 18] FIG. 18 is a diagram for explaining an example of a 1.33x vertical display size of the source driver circuit 203 according to the second embodiment. [Figure 19] FIG. 19 is a block diagram showing the configuration of a display device 300 according to the third embodiment. [Figure 20] FIG. 20 is a diagram for explaining areas A1 to A5 of the screen according to the third embodiment. [Figure 21] FIG. 21 is an example of a table stored in the setting register 344. [Figure 22] FIG. 22 is a diagram for explaining supply of gate signals according to the third embodiment. [Figure 23] FIG. 23 is a timing chart according to a modification of the first to third embodiments. [Figure 24] FIG. 24 is a diagram showing a display example according to a modification of the first to third embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications can be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in common between different drawings for identical parts or parts having similar functions, and repeated description thereof will be omitted. The configurations described in the embodiments and modifications may be combined or modified as appropriate within the scope of the gist of the present disclosure. To facilitate understanding of the description, the drawings referred to below show simplified or schematic configurations, and some components may be omitted.

[0011] [First embodiment] (Overall configuration of the display device) Fig. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. Fig. 2 is a block diagram showing the internal configuration of a display panel 10.

[0012] A display device 100 according to the first embodiment is configured as a head-mounted display worn on a person's head. As shown in FIG. 1, the display device 100 includes a display panel 10 and a backlight 5. The backlight 5 irradiates the display panel 10 with light, and a user visually recognizes the light transmitted through the display panel 10. In the display device 100, the display panel 10 includes a display section 1, which is an area where an image is displayed, a gate drive circuit 2, a source drive circuit 3, and a control circuit 4. While FIG. 1 shows an example in which the control circuit 4 is disposed outside the display panel 10 (on a substrate separate from the display panel 10), the control circuit 4 may also be disposed on the display panel 10. The control circuit 4 includes a timing controller 41, an image compression calculation unit 42, and a backlight control unit 43. The timing controller 41, the image compression calculation unit 42, and the backlight control unit 43 may be configured as a common integrated circuit, or may be configured as separate circuits for each function.

[0013] The timing controller 41 receives timing signals (horizontal synchronization signal, vertical synchronization signal, data enable signal, etc.) and video signals, and generates part of the source control signals (digital video signal, source start pulse signal, and source clock signal) and gate control signals (gate start pulse signal, gate clock signal, etc.) based on the received signals. The image compression calculation unit 42 also generates part of the source control signals (switch control signals SWA and SWB). The timing controller 41 and the image compression calculation unit 42 supply the source control signals to the source drive circuit 3. The timing controller 41 also supplies the gate control signals to the gate drive circuit 2. The backlight control unit 43 turns off the backlight 5 while the pixel electrodes 14 (see FIG. 2) are being charged, and transmits a signal to the backlight 5 to turn on the backlight 5 after charging of the pixel electrodes 14 is complete.

[0014] 2, a display panel 10 is provided with a plurality of gate lines 11 connected to a gate drive circuit 2 and a plurality of source lines 12 connected to a source drive circuit 3. The gate lines 11 and the source lines 12 are arranged to intersect with each other, and pixels are arranged in each region defined by the gate lines 11 and the source lines 12. The pixels are arranged in a matrix on the display panel 10.

[0015] Each pixel is provided with a transistor 13 and a pixel electrode 14. The gate electrode of the transistor 13 is connected to a gate line 11. The source electrode of the transistor 13 is connected to a source line 12. The drain electrode of the transistor 13 is connected to the pixel electrode 14.

[0016] When the transistor 13 is turned on by a drive signal (gate signal) supplied via the gate line 11, the source signal supplied via the source line 12 is written to (charged into) the pixel electrode 14. This generates an electric field between the pixel electrode 14 and a common electrode 15 disposed opposite the pixel electrode 14. The display unit 1 also includes a liquid crystal layer (not shown). The liquid crystal layer is driven by the electric field generated between the pixel electrode 14 and the common electrode 15, causing an image to be displayed on the display unit 1.

[0017] (Configuration of source driver circuit 3) FIG. 3 is a diagram showing a portion of the configuration of the source driving circuit 3. As shown in FIG. 3, the source driving circuit 3 includes an output unit 31 that outputs a source signal, and a signal distribution unit 32. The source lines 12 include a source line 12a and a source line 12b. For example, as shown in FIG. 3, in a display device 100, two source lines 12a and two source lines 12b are alternately arranged. The multiple source lines 12a form a first source line group. The multiple source lines 12b form a second source line group. The output unit 31 outputs source signals having different voltage values ​​(gradations) for each cycle of the horizontal synchronization signal, based on a digital video signal, a source start pulse signal, and a source clock signal. The output unit 31 includes multiple output terminals 31a (half the number of source lines 12). The multiple output terminals 31a output source signals having different gradations.

[0018] The signal distribution unit 32 is a demultiplexer that distributes the source signals output from the output unit 31 to a first group of source lines and a second group of source lines. Specifically, the signal distribution unit 32 includes a switch 32a arranged between the source line 12a and the output terminal 31a, and a switch 32b arranged between the source line 12b and the output terminal 31a. When a switch control signal SWA is input, the switch 32a is turned on and supplies the source signal from the output terminal 31a to the source line 12a. When a switch control signal SWB is input, the switch 32b is turned on and supplies the source signal from the output terminal 31a to the source line 12b. One output terminal 31a is connected to one source line 12a via the switch 32a and one source line 12b via the switch 32b.

[0019] 3, a pixel (sub-pixel) having a red color filter disposed therein is labeled "R," a pixel (sub-pixel) having a green color filter disposed therein is labeled "G," and a pixel (sub-pixel) having a blue color filter disposed therein is labeled "B." For example, source line 12a on the left side of the paper in FIG. 3 is connected to the source electrodes of transistors 13 in multiple "R" pixels (referred to as "R1") arranged in a column on the left side of the paper.

[0020] (Operation of source driver circuit 3) <Normal display> 4 is a timing chart illustrating normal display (vertical single-size display) of the source driving circuit 3 according to the first embodiment. FIG. 5 is a diagram illustrating an example of normal display (vertical single-size display) of the source driving circuit 3. "Normal display" is a method of displaying an image on the display unit 1 by supplying a gate signal to one gate line 11 and supplying source signals to multiple source lines 12 within one cycle of the horizontal synchronization signal (period T1 in FIG. 4). In other words, normal display is a method in which the gate lines 11 are scanned one by one.

[0021] 4, the switch control signals SWA and SWB each have a high voltage level once within one cycle (period T1) of the horizontal synchronization signal. As a result, the switches 32a and 32b of the source drive circuit 3 are turned on once within one cycle (period T1) of the horizontal synchronization signal. Note that "A" in the figure indicates a period during which the switch 32a is on, and "B" in the figure indicates a period during which the switch 32b is on.

[0022] As a result of the switches 32a and 32b operating as described above, in normal display, the source signal V output within one cycle of the horizontal synchronization signal charges a plurality of pixel electrodes 14 (for one row) via a plurality of transistors 13 (for one row) connected to one gate line 11. For example, in the case of a source signal V having a gradation that alternates between light and dark for each period T1 as shown in FIG. 4, the pixels connected to odd-numbered gate lines 11 ("GL1", "GL3", ...) become "bright" (a state in which light from the backlight 5 is transmitted), and the pixels connected to even-numbered gate lines 11 ("GL2", "GL4", ...) become "dark" (a state in which light from the backlight 5 is blocked), as shown in FIG.

[0023] 6 is a schematic diagram showing the correspondence between transmission data and on-screen display in normal display. Transmission data is the total amount of source signals (video signals) required to display one screen (one frame). In normal display, one row of pixel electrodes 14 is charged for each cycle (period T1) of the horizontal synchronization signal, so one row of transmission data (source signals) corresponds to one row of on-screen display.

[0024] <Double vertical display> 7 is a timing chart illustrating the operation of the source drive circuit 3 according to the first embodiment for double-height display. FIG. 8 is a diagram illustrating an example of double-height display by the source drive circuit 3. "Double-height display" is a method of displaying an image on the display unit 1 by supplying gate signals to two gate lines 11 and source signals to multiple source lines 12 within one cycle of the horizontal synchronization signal (period T1 in FIG. 7). In other words, double-height display is a method in which two gate lines 11 (twice the number of lines in normal display) are scanned at a time.

[0025] 7, the switch control signals SWA and SWB each go high in voltage once within one cycle (period T1) of the horizontal synchronization signal, as in normal display, which causes the switches 32a and 32b of the source drive circuit 3 to turn on once within one cycle (period T1) of the horizontal synchronization signal.

[0026] As a result of the switches 32a and 32b operating as described above, in double-height display, the source signal output within one cycle of the horizontal synchronization signal charges a plurality of pixel electrodes 14 (for two rows) via a plurality of transistors 13 (for two rows) connected to two gate lines 11. For example, in the case of a source signal V having a gradation that alternates between light and dark every period T1 as shown in FIG. 7, the pixels connected to gate lines 11 "GL1," "GL2," "GL5," "GL6," ... become "light," and the pixels connected to gate lines 11 "GL3," "GL4," "GL7," "GL8," ... become "dark," as shown in FIG.

[0027] 9 is a schematic diagram showing the correspondence between transmitted data and on-screen display in double-vertical-size display. In double-vertical-size display, two rows of pixel electrodes 14 are charged per cycle (period T1) of the horizontal synchronization signal, so one row of transmitted data (source signal) corresponds to two rows of on-screen display. As a result, the amount of transmitted data in double-vertical-size display is half the amount of transmitted data in normal display. For example, in the case of an image requiring a low level of image quality (numbers (indicating information) in the example of FIG. 9), the amount of transmitted data can be reduced by displaying in double-vertical-size display.

[0028] <1.5x vertical display> Fig. 10 is a timing chart illustrating the operation of the source drive circuit 3 according to the first embodiment for performing 1.5x vertical size display. Fig. 11 is a diagram illustrating an example of 1.5x vertical size display by the source drive circuit 3. "1.5x vertical size display" is a method of displaying an image on the display unit 1 by supplying gate signals to three gate lines 11 and source signals to multiple source lines 12 within two cycles of the horizontal synchronization signal (two periods T1 in Fig. 10). In other words, 1.5x vertical size display is a method in which 1.5 gate lines 11 (1.5 times the number of lines in normal display) are scanned at a time.

[0029] 10, the switch control signals SWA and SWB each go high in voltage once within one cycle (period T1) of the horizontal synchronization signal, as in normal display, which causes the switches 32a and 32b of the source drive circuit 3 to turn on once within one cycle (period T1) of the horizontal synchronization signal.

[0030] As a result of the operation of switches 32a and 32b as described above, in a 1.5x vertical display, the source signal output within two cycles of the horizontal synchronization signal charges a plurality of pixel electrodes 14 (for three rows) via a plurality of transistors 13 (for three rows) connected to three gate lines 11. For example, as shown in FIG. 10, in the case of a source signal V having a gradation that alternates between light and dark every period T1, half of the pixels connected to gate lines 11 "GL1" to "GL3" become "light" and the remaining half become "dark," as shown in FIG. 11. Furthermore, half of the pixels connected to gate lines 11 "GL4" to "GL6" become "light" and the remaining half become "dark."

[0031] As shown in FIG. 10, the period during which a gate signal is supplied to the gate line 11 of "GL1" is referred to as the first period P1, the period during which a gate signal is supplied to the gate line 11 of "GL2" is referred to as the second period P2, the period during which a gate signal is supplied to the gate line 11 of "GL3" is referred to as the third period P3, and the period during which a gate signal is supplied to the gate line 11 of "GL4" is referred to as the fourth period P4. In a 1.5x vertical display, the second period P2 starts at time t2, which is later than the start time t1 of the first period P1. The third period P3 starts at time t3, which is later than the start time t2 of the second period P2. The fourth period P4 starts at time t4, which is later than the start time t3 of the third period P3.

[0032] Furthermore, part of the first period P1 overlaps with part of the second period P2. Part of the second period P2 overlaps with part of the third period P3. However, the third period P3 does not overlap with the fourth period P4. In other words, the gate drive circuit 2 supplies gate signals to the gate lines 11 "GL1" to "GL3" so that part of the first period P1 overlaps with part of the second period P2, and part of the second period P2 overlaps with part of the third period P3, during two cycles of the horizontal synchronization signal.

[0033] 10, during a period R1 in which the first period P1 and the second period P2 overlap, a switch control signal SWB is supplied to the switch 32b, and the switch 32b is turned on during the period R1. As a result, the source signal of the first period P1 is supplied to the transistors 13 connected to the gate line 11 of "GL2" and connected to the second group of source lines (the group of source lines to which the source signal is supplied when the switch 32b is on). Also, during a period R2 in which the second period P2 and the third period P3 overlap, a switch control signal SWA is supplied to the switch 32a, and the switch 32a is turned on during the period R2. As a result, the source signal of the second period P2 is supplied to the transistors 13 connected to the gate line 11 of "GL2" and connected to the first group of source lines (the group of source lines to which the source signal is supplied when the switch 32a is on). As a result, as shown in FIG. 11, half of the pixels connected to the gate line 11 of "GL2" become "bright" and the other half become "dark."

[0034] As described above, periods R1 and R2 are each shorter than one cycle of the horizontal synchronization signal, but one of switches 32a and 32b is turned on during periods R1 and R2. As a result, the source signal V is supplied to either the first source line group or the second source line group during periods R1 and R2, allowing the display device 100 to display an image. As a result, gate signals can be supplied to 1.5 gate lines 11 (not an integer number) per cycle of the horizontal synchronization signal (enabling 1.5x vertical display).

[0035] FIG. 12 is a schematic diagram showing the correspondence between transmission data and on-screen display in a 1.5x vertical display. In a 1.5x vertical display, three rows of pixel electrodes 14 are charged every two cycles of the horizontal synchronization signal (two periods T1), so one row of transmission data (source signal) corresponds to 1.5 rows of on-screen display. As a result, the amount of transmission data in a 1.5x vertical display is two-thirds the amount of transmission data in a normal display. Here, in a double-vertical display, the image quality may be too low, while in a normal display, the image quality may be higher than necessary. In contrast, in a 1.5x vertical display, gate signals can be supplied to 1.5 gate lines 11 per one cycle of the horizontal synchronization signal, so the amount of transmission data per unit time (per frame) can be reduced compared to a normal display while maintaining image quality (ensuring that the image quality is neither too low nor too high).

[0036] [Second embodiment] Next, the configuration of a display device 200 according to a second embodiment will be described with reference to Figures 13 to 18. In the second embodiment, switches 232a to 232c are provided in a source drive circuit 203, and the switches 232a to 232c are connected to one output unit 231. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0037] 13 is a block diagram showing the configuration of a display device 200 according to the second embodiment. As shown in FIG. 13, the display device 200 according to the second embodiment includes a source driving circuit 203 and a control circuit 204. The control circuit 204 includes a timing controller 241 and an image compression calculation unit 242. The image compression calculation unit 242 generates a switch control signal SWA that controls the operation of the switch 232a, a switch control signal SWB that controls the operation of the switch 232b, and a switch control signal SWC that controls the operation of the switch 232c. The image compression calculation unit 242 then transmits the switch control signals SWA to SWC to the source driving circuit 203.

[0038] (Configuration of the source driving circuit 203 according to the second embodiment) FIG. 14 is a diagram showing a portion of the configuration of a source driving circuit 203 according to the second embodiment. As shown in FIG. 14, the source driving circuit 203 includes an output unit 231 that outputs a source signal and a signal distribution unit 232. The source lines 212 include a source line 212a, a source line 212b, and a source line 212c. For example, as shown in FIG. 14, in a display device 200, two source lines 212a, two source lines 212b, and two source lines 212c are arranged repeatedly in this order. The multiple source lines 212a constitute a first source line group. The multiple source lines 212b constitute a second source line group. The multiple source lines 212c constitute a third source line group. The output unit 231 outputs source signals having different voltage values ​​(gradations) for each cycle of the horizontal synchronization signal, based on a digital video signal, a source start pulse signal, and a source clock signal. The output unit 231 includes a plurality of output terminals 231a (one third the number of source lines 212). The plurality of output terminals 231a output source signals having different gradations from each other.

[0039] The signal distribution unit 232 distributes the source signals output from the output unit 231 to a first group of source lines, a second group of source lines, and a third group of source lines. Specifically, the signal distribution unit 232 includes a switch 232a arranged between the source line 212a and the output terminal 231a, a switch 232b arranged between the source line 212b and the output terminal 231a, and a switch 232c arranged between the source line 212c and the output terminal 231a. When a switch control signal SWA is input, the switch 232a is turned on and supplies the source signal from the output terminal 231a to the source line 212a. When a switch control signal SWB is input, the switch 232b is turned on and supplies the source signal from the output terminal 231a to the source line 212b. When a switch control signal SWC is input, the switch 232c is turned on and supplies the source signal from the output terminal 231a to the source line 212c. Furthermore, one output terminal 231a is connected to one source line 212a via a switch 232a, one source line 212b via a switch 232b, and one source line 212c via a switch 232c.

[0040] (Operation of the source driving circuit 203 according to the second embodiment) <1.5x vertical display according to the second embodiment> Fig. 15 is a timing chart for explaining the operation of the source driving circuit 203 according to the second embodiment for displaying a 1.5 times larger vertical size. Fig. 16 is a diagram for explaining an example of displaying a 1.5 times larger vertical size by the source driving circuit 203 according to the second embodiment.

[0041] 15, the voltages of the switch control signals SWA, SWB, and SWC each become high level once within one cycle (period T1) of the horizontal synchronization signal, which causes the switches 232a to 232c of the source drive circuit 203 to turn on once within one cycle (period T1) of the horizontal synchronization signal.

[0042] As a result of the switches 232a to 232c operating as described above, in a 1.5x vertical size display, the source signal output within four cycles of the horizontal synchronization signal (from time t11 to time t12) charges a plurality of pixel electrodes 14 (for six rows) via a plurality of transistors 13 (for six rows) connected to six gate lines 11. For example, as shown in FIG. 15, in the case of a source signal V having a gradation in which light and dark alternate every period T1, the display will be light and dark as shown in FIG. 16.

[0043] As shown in Figure 15, the period during which a gate signal is supplied to gate line 11 of "GLn (n is a natural number)" is referred to as the nth period P1n. In a 1.5x vertical display, the n+1th period P1n+1 starts later than the start of the nth period Pn. Furthermore, part of the n+1th period P1n+1 overlaps with part of the nth period Pn. The gate drive circuit 202 supplies gate signals to the multiple gate lines 11 (GLn to GLn+6) so that, during four cycles of the horizontal synchronization signal, part of the nth period P1n overlaps with part of the n+1th period Pn+1, part of the n+1th period P1n+1 overlaps with part of the n+2th period Pn+2, part of the n+2th period P1n+2 overlaps with part of the n+3th period Pn+3, part of the n+3rd period P1n+3 overlaps with part of the n+4th period Pn+4, part of the n+4th period P1n+4 overlaps with part of the n+5th period Pn+5, and part of the n+5th period P1n+5 overlaps with part of the n+6th period Pn+6.

[0044] 15, during a period R11 in which the first period P11 and the second period P12 overlap, a switch control signal SWC is supplied to the switch 232c, and the switch 232c is turned on during the period R11. As a result, the source signal of the first period P11 is supplied to the transistors 13 connected to the third source line group (the source line group to which the source signal is supplied when the switch 232c is on) among the plurality of transistors 13 connected to the gate line 11 of “GL2.” Furthermore, during a period R12 in which the second period P12 and the third period P13 overlap, a switch control signal SWB is supplied to the switch 232b, and the switch 232b is turned on during the period R12. Furthermore, during a period R13 in which the third period P13 and the fourth period P14 overlap, a switch control signal SWA is supplied to the switch 232a, and the switch 232a is turned on during the period R13.

[0045] As described above, periods R11 to R13 are each shorter than one cycle of the horizontal synchronization signal, but one of switches 232a, 232b, and 232c is turned on during periods R11, R12, and R13. As a result, the source signal V is supplied to one of the first to third source line groups during periods R11 to R13, and the display device 200 can display an image. As a result, gate signals can be supplied to 1.5 gate lines 11, which is not an integer, per cycle of the horizontal synchronization signal (allowing for a 1.5x vertical display).

[0046] <1.33x vertical display according to the second embodiment> Fig. 17 is a timing chart for explaining the operation of the source driving circuit 203 according to the second embodiment for performing 1.33x vertical size display. Fig. 18 is a diagram for explaining an example of 1.33x vertical size display by the source driving circuit 203 according to the second embodiment.

[0047] 17, in a 1.33x vertical display, a source signal output within three cycles of the horizontal synchronization signal (from time t21 to time t22) charges a plurality of pixel electrodes 14 (for four rows) via a plurality of transistors 13 (for four rows) connected to four gate lines 11. For example, as shown in FIG. 17, in the case of a source signal V having a gradation that alternates between light and dark every period T1, a light and dark display such as that shown in FIG. 18 is obtained.

[0048] 17, even in a 1.33x vertical size display, the (n+1)th period P1n+1 starts later than the start of the nth period Pn. In a 1.33x vertical size display, part of the second period P22 overlaps part of the first period P21. Part of the third period P23 overlaps part of the second period P22. Part of the fourth period P24 overlaps part of the third period P23. The fifth period P25 does not overlap the fourth period P24. This allows gate signals to be supplied to a non-integer number of 1.33 (three-quarters) gate lines 11 per cycle of the horizontal synchronization signal (making it possible to achieve a 1.33x vertical size display).

[0049] [Third embodiment] Next, the configuration of a display device 300 according to a third embodiment will be described with reference to Fig. 19 to Fig. 22. In the third embodiment, the display device 300 performs k-fold vertical display for each area of ​​the screen, where k is a positive rational number. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0050] Fig. 19 is a block diagram showing the configuration of a display device 300 according to a third embodiment. As shown in Fig. 19, the display device 300 according to the third embodiment includes a source drive circuit 303 and a control circuit 304. The control circuit 304 includes a timing controller 341 and a setting register 344 (storage circuit). The setting register 344 is configured so that a table stored therein is rewritten by a setting signal supplied from a host controller (not shown) or an external device that supplies a video signal to the display device 300. In other words, the tables (each of "area," "definition," and "setting") stored in the setting register 344 shown in Fig. 21 are configured to be updated according to the content of the video (image).

[0051] FIG. 20 is a diagram illustrating areas A1 to A5 of a screen according to the third embodiment. FIG. 21 is an example of a table stored in the setting register 344. As shown in FIG. 20, areas A1 to A5 of the screen are divided into vertical rows. For example, when an image of an animal with a face image in the center shown in FIG. 20 is displayed on the display device 300, the screen is divided into five areas as shown in FIG. 21. In this case, area A1 is an area where pixels connected to gate lines GL1 to GL200 are arranged. area A2 is an area where pixels connected to gate lines GL201 to GL400 are arranged. area A3 is an area where pixels connected to gate lines GL401 to GL1200 are arranged. area A4 is an area where pixels connected to gate lines GL1201 to GL1400 are arranged. area A5 is an area where pixels connected to gate lines GL1401 to GL2000 are arranged.

[0052] The setting register 344 stores setting information (for example, the table shown in FIG. 21) that associates each of a plurality of gate line groups with the number of gate lines 11 to which a gate signal is supplied within one cycle of a horizontal synchronization signal (in FIG. 21, "setting") The timing controller 341 references the setting information (the "setting" value) corresponding to the region to which the gate line 11 that transmits the gate control signal belongs from the setting register 344, and performs double-height display based on the setting information.

[0053] FIG. 22 is a diagram illustrating the supply of gate signals according to the third embodiment. As shown in FIG. 22, when driving the gate line group in region A1 (GL1 to GL200), the timing controller 341 supplies gate control signals to the gate drive circuit 2 so as to execute the double-vertical-size display described in the first embodiment. Note that at this time (when driving the gate line group from GL1 to GL200), the source signal is composed of transmission data for double-vertical-size display, which has half the data amount of normal display. Also, when driving the gate line group up to region A2 (GL201 to GL400), the timing controller 341 supplies gate control signals to the gate drive circuit 2 so as to execute the 1.5-vertical-size display described in the first or second embodiment. Note that at this time (when driving the gate line group from GL201 to GL400), the source signal is composed of transmission data for 1.5-vertical-size display, which has two-thirds the data amount of normal display. Furthermore, when driving the gate line group up to area A3 (GL401 to GL1200), the timing controller 341 supplies gate control signals to the gate drive circuit 2 so as to execute the normal display described in the first embodiment. At this time (when driving the gate line group from GL401 to GL1200), the source signal is configured from transmission data for normal display.

[0054] According to the third embodiment, the image quality can be changed depending on the display area (gate line group). This allows the number of gate lines 11 to which gate signals are supplied within one cycle of the horizontal synchronization signal to be increased in areas where high image quality is not required (e.g., areas A1 or A5), and the number of gate lines 11 to which gate signals are supplied within one cycle of the horizontal synchronization signal to be decreased in areas where high image quality is required (e.g., area A3). As a result, even when both areas where high image quality is not required and areas where high image quality is required exist within a single screen, the amount of transmitted data can be reduced while satisfying the required image quality. Furthermore, by arranging areas A2 and A4, which have image quality intermediate between area A3 with high image quality and areas A1 and A5 with low image quality, the boundary between the area with high image quality and the area with low image quality can be made less noticeable to the user. This allows the user to view the image without feeling uncomfortable, even when the image quality is changed depending on the area.

[0055] [Variations] Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the invention. Therefore, the present invention is not limited to the above-described embodiments, and can be modified as appropriate within the scope of the spirit of the invention. Modifications of the above-described embodiments will be described below.

[0056] (1) In the first to third embodiments, the display device is configured as a liquid crystal display device having a liquid crystal layer, but the present disclosure is not limited to this. For example, the display device may be configured as an organic EL display device, a micro LED display device, or the like.

[0057] (2) In the first to third embodiments, examples have been shown in which the display device performs 1.33x vertical size display and 1.5x vertical size display, but the present disclosure is not limited thereto. For example, the display device may be configured to perform rational number multiple display other than 1.33x vertical size display and 1.5x vertical size display. That is, the display device may be operated such that n is an arbitrary natural number, m is an arbitrary natural number greater than n, gate signals are supplied from the gate drive circuit to m gate lines within n cycles of the horizontal synchronization signal, and the number obtained by dividing m by n is a rational number other than an integer.

[0058] (3) In the first embodiment, the switch control signal SWA and the switch control signal SWB are set to high level in this order within one cycle of the horizontal synchronization signal, and in the second embodiment, the switch control signals SWA to SWC are set to high level in this order within one cycle of the horizontal synchronization signal, but the present disclosure is not limited to this. For example, the order in which the switch control signals are set to high level may be changed for each cycle of the horizontal synchronization signal. For example, the switch control signals may be generated so that SWA, SWB, and SWC are set to high level in this order, and then SWC, SWB, and SWA are set to high level in this order.

[0059] (4) In the first to third embodiments, examples have been shown in which one source signal is distributed to two or three source line groups (distribution unit: demultiplexer), but the present disclosure is not limited to this. That is, the distribution unit of the source driver circuit may be configured to distribute one source signal to four or more source line groups.

[0060] (5) In the first embodiment, an example was shown in which gate signals were simultaneously supplied to two gate lines within one cycle of the horizontal synchronization signal to achieve double-width vertical display. However, the present disclosure is not limited to this. As in the modified example of double-width display shown in FIG. 23, where f is a natural number, a gate signal may be supplied to gate line GLf+1 after the period in which a gate signal is supplied to gate line GLf. In this case, gate signals are supplied to six gate lines (GL3 to GL7, half of GL2, and half of GL8) within three cycles of the horizontal synchronization signal (between time t41 and time t42 in FIG. 23). When the source signal V has a gradation that alternates between light and dark every period T1, the display shown in FIG. 24 results.

[0061] The above-described configuration can also be explained as follows.

[0062] A display device according to a first configuration includes a plurality of transistors, a plurality of gate lines connected to the plurality of transistors, a plurality of source lines connected to the plurality of transistors, a gate drive circuit that supplies gate signals to the plurality of gate lines, a source drive circuit that supplies source signals to the plurality of source lines, and a control circuit that transmits gate control signals to the gate drive circuit and transmits source control signals to the source drive circuit, wherein the source drive circuit includes an output section that outputs the source signals, a first switch that is arranged between the output section and a first group of source lines among the plurality of source lines, and a second switch that is arranged between the output section and a second group of source lines among the plurality of source lines, and wherein the control circuit controls the gate drive circuit to output the source signals within n periods of a horizontal synchronization signal, where n is a natural number and m is a natural number greater than n. the gate control signal is transmitted to the gate drive circuit so that the gate signal is supplied to m gate lines and a part of a first period in which the gate signal is supplied to a first gate line among the plurality of gate lines overlaps with a part of a second period in which the gate signal is supplied to a second gate line adjacent to the first gate line, the second period starting at a point after the start of the first period, so that m divided by n is a rational number other than an integer; the source control signal is transmitted to the source drive circuit so that the first switch and the second switch are each turned on once within one cycle of a horizontal synchronization signal; and the source control signal is transmitted to the source drive circuit so that one of the first switch and the second switch is turned on within a period in which the first period and the second period overlap (first configuration).

[0063] According to the first configuration, the period during which the first period and the second period starting at a time point after the start time point of the first period overlap is shorter than one cycle of the horizontal synchronization signal. However, within the overlapping period, one of the first switch and the second switch is in the on state. As a result, even within the overlapping period described above, a source signal is supplied to either the first source line group or the second source line group, and the display device can display an image. As a result, it is possible to supply a gate signal to m / n gate lines that are not integers per one cycle of the horizontal synchronization signal (vertical m / n times magnification display can be performed).

[0064] Here, if m / n < k < (m / n) + 1 and k is an integer of 2 or more, when supplying a gate signal to k integer gate lines per one cycle of the horizontal synchronization signal (vertical k times magnification display), the image quality is too low. On the other hand, in the case of vertical (k - 1) times magnification display (or normal display of 1 time), the image quality may be too high. In contrast, according to the first configuration, since it is possible to supply a gate signal to m / n gate lines that are not integers per one cycle of the horizontal synchronization signal (vertical m / n times magnification display can be performed), it is possible to reduce the amount of transmission data per unit time (per frame) compared to normal display of 1 time while maintaining the image quality (maintaining a state where the image quality is not too low and not too high).

[0065] In the first configuration, the control circuit may be configured to transmit the gate control signal to the gate drive circuit so that, within two cycles of the horizontal synchronization signal, a part of the second period and a part of the third period in which the gate signal is supplied to the third gate line adjacent to the second gate line and the third period starting at a time point after the start time point of the second period overlap so that the gate signal is supplied to three gate lines from the gate drive circuit (second configuration).

[0066] Here, when gate signals are supplied to two gate lines per cycle of the horizontal synchronization signal (double-vertical display), the image quality may be too low, while in normal display at 1x, the image quality may be higher than necessary. In contrast, with the second configuration, gate signals are supplied from the gate drive circuit to three gate lines within two cycles of the horizontal synchronization signal. That is, gate signals can be supplied to 1.5 gate lines per cycle of the horizontal synchronization signal (allowing for 1.5x vertical display), so the amount of data transmitted per unit time (per frame) can be reduced compared to normal display at 1x while maintaining image quality.

[0067] In the first or second configuration, the source driver circuit may further include a third switch arranged between the output section and a third group of source lines of the plurality of source lines. The control circuit may be configured to: transmit the gate control signal to the gate drive circuit so that part of the first period overlaps part of the second period, so that the gate signals are supplied from the gate drive circuit to m gate lines within n periods of the horizontal synchronization signal, and so that m divided by n is a rational number other than an integer; transmit the gate control signal to the gate drive circuit so that part of the second period overlaps with a fourth period in which the gate signal is supplied to a fourth gate line adjacent to the second gate line, the fourth period starting later than a start of the second period; transmit the source control signal to the source drive circuit so that the first switch, the second switch, and the third switch are each turned on once within one period of the horizontal synchronization signal; and transmit the source control signal to the source drive circuit so that the third switch is turned on within a period in which the second period and the fourth period overlap (third configuration).

[0068] According to the third configuration, the overlapping period between the second period and the fourth period is shorter than one cycle of the horizontal synchronization signal, but the third switch is turned on during this overlapping period. As a result, even during the overlapping period, source signals are supplied to the third source line group, and the display device can display an image. This makes it possible to supply gate signals to a non-integer number m / n of gate lines per cycle of the horizontal synchronization signal (enabling m / n-times vertical image display).

[0069] In a third configuration, the control circuit may be configured to transmit the gate control signal to the gate drive circuit so that a part of the fourth period overlaps with a part of a fifth period, in which the gate signal is supplied to a fifth gate line adjacent to the fourth gate line and the fifth period starts later than the start of the fourth period, so that the gate signal is supplied to four gate lines from the gate drive circuit within three periods of the horizontal synchronization signal; transmit the source control signal to the source drive circuit so that the first switch is turned on within a period in which the first period and the second period overlap; and transmit the source control signal to the source drive circuit so that the second switch is turned on within a period in which the fourth period and the fifth period overlap (fourth configuration).

[0070] According to the fourth configuration, gate signals are supplied from the gate drive circuit to four gate lines within three cycles of the horizontal synchronization signal. That is, gate signals can be supplied to 4 / 3 (1.33) gate lines per cycle of the horizontal synchronization signal (allowing for a 1.33x vertical display), which allows the amount of data transmitted per unit time (per frame) to be reduced compared to normal 1x display while maintaining image quality.

[0071] In any one of the first to fourth configurations, the plurality of gate lines may include a plurality of gate line groups. The display device may further include a memory circuit that stores setting information that associates each of the plurality of gate line groups with the number of gate lines to which the gate signal is supplied within one cycle of the horizontal synchronization signal. The control circuit may be configured to refer to the setting information and change the number of gate lines to which the gate signal is supplied within one cycle of the horizontal synchronization signal in correspondence with each of the plurality of gate line groups (fifth configuration).

[0072] According to the fifth configuration, the image quality can be changed depending on the display area (gate line group). As a result, in an area (gate line group) where high image quality is not required, the number of gate lines to which gate signals are supplied within one cycle of the horizontal synchronization signal can be increased, and in an area (gate line group) where high image quality is required, the number of gate lines to which gate signals are supplied within one cycle of the horizontal synchronization signal can be decreased. As a result, even if a single screen contains both areas where high image quality is not required and areas where high image quality is required, the amount of transmission data can be reduced while satisfying the required image quality.

[0073] A sixth configuration of a control method for a display device includes a plurality of transistors, a plurality of gate lines connected to the plurality of transistors, a plurality of source lines connected to the plurality of transistors, a gate drive circuit that supplies gate signals to the plurality of gate lines, and a source drive circuit that supplies source signals to the plurality of source lines, wherein the source drive circuit includes an output section that outputs the source signal, a first switch that is arranged between the output section and a first source line group of the plurality of source lines, and a second switch that is arranged between the output section and a second source line group of the plurality of source lines, wherein, where n is a natural number and m is a natural number greater than n, the control method includes: The gate drive circuit is operated so that a part of a first period during which the gate signal is supplied to a first gate line among the plurality of gate lines overlaps with a part of a second period during which the gate signal is supplied to a second gate line adjacent to the first gate line, the second period starting later than the start of the first period, so that m divided by n is a rational number other than an integer; the source drive circuit is operated so that the first switch and the second switch are each turned on once within one cycle of a horizontal synchronization signal; and the source drive circuit is operated so that one of the first switch and the second switch is turned on within the period during which the first period and the second period overlap (sixth configuration).

[0074] According to the sixth configuration, it is possible to provide a control method for a display device that can reduce the amount of data transmitted per unit time while maintaining image quality. [Explanation of symbols]

[0075] 1: display unit, 2: gate drive circuit, 3: source drive circuit, 4: control circuit, 5: backlight, 10: display panel, 11: gate line, 12: source line, 12a: source line, 12b: source line, 13: transistor, 14: pixel electrode, 15: common electrode, 23: last page, 31: output unit, 31a: output terminal, 32: signal distribution unit, 32a: switch, 32b: switch, 41: timing controller, 42: image compression calculation unit, 43: backlight control unit, 100: display device, 200: display device, 202: gate drive circuit, 203: source drive circuit, 204: control circuit, 212: source line, 212a: source line, 212b: source line, 212c: source line, 231: output section, 231a: output terminal, 232: signal distribution section, 232a: switch, 232b: switch, 232c: switch, 241: timing controller, 242: image compression calculation section, 300: display device, 303: source drive circuit, 304: control circuit, 341: timing controller, 344: setting register

Claims

1. a plurality of transistors; a plurality of gate lines connected to the plurality of transistors; a plurality of source lines connected to the plurality of transistors; a gate drive circuit for supplying gate signals to the plurality of gate lines; a source driver circuit for supplying source signals to the plurality of source lines; a control circuit that transmits a gate control signal to the gate drive circuit and a source control signal to the source drive circuit; The source driving circuit includes: an output unit that outputs the source signal; a first switch disposed between the output section and a first group of source lines among the plurality of source lines; a second switch disposed between the output section and a second group of source lines among the plurality of source lines; The control circuit When n is a natural number and m is a natural number greater than n, the gate signals are supplied from the gate drive circuit to m gate lines within n periods of the horizontal synchronization signal, and the number obtained by dividing m by n is a rational number other than an integer. transmitting the gate control signal to the gate drive circuit so that a portion of a first period during which the gate signal is supplied to a first gate line among the plurality of gate lines overlaps with a portion of a second period during which the gate signal is supplied to a second gate line adjacent to the first gate line, the second period starting at a point in time later than the start point of the first period; transmitting the source control signal to the source driving circuit so that the first switch and the second switch are each turned on once within one cycle of a horizontal synchronization signal; the display device transmitting the source control signal to the source drive circuit so that one of the first switch and the second switch is turned on during a period in which the first period and the second period overlap.

2. The control circuit The gate signal is supplied from the gate drive circuit to three gate lines within two periods of the horizontal synchronization signal.

2. The display device according to claim 1, wherein the gate control signal is sent to the gate drive circuit so that a portion of the second period overlaps with a portion of a third period in which the gate signal is supplied to a third gate line adjacent to the second gate line, the third period starting at a point after the start of the second period.

3. the source driver circuit further includes a third switch arranged between the output unit and a third source line group of the plurality of source lines; The control circuit The gate signal is supplied from the gate drive circuit to m gate lines within n periods of the horizontal synchronization signal, and m divided by n is a rational number other than an integer. transmitting the gate control signal to the gate drive circuit so that a portion of the first period and a portion of the second period overlap; transmitting the gate control signal to the gate drive circuit so that a part of the second period overlaps with a fourth period in which the gate signal is supplied to a fourth gate line adjacent to the second gate line, the fourth period starting at a point in time later than a start point of the second period; transmitting the source control signal to the source driving circuit so that the first switch, the second switch, and the third switch are each turned on once within one cycle of a horizontal synchronization signal; The display device according to claim 1 , wherein the source control signal is transmitted to the source drive circuit so that the third switch is turned on during a period in which the second period and the fourth period overlap.

4. The control circuit The gate signal is supplied from the gate drive circuit to four gate lines within three periods of the horizontal synchronization signal. transmitting the gate control signal to the gate drive circuit so that a portion of the fourth period overlaps with a portion of a fifth period in which the gate signal is supplied to a fifth gate line adjacent to the fourth gate line, the fifth period starting at a point in time after the start of the fourth period; transmitting the source control signal to the source driving circuit so that the first switch is turned on during a period in which the first period and the second period overlap; The display device according to claim 3 , wherein the source control signal is transmitted to the source drive circuit so that the second switch is turned on during a period in which the fourth period and the fifth period overlap.

5. the plurality of gate lines includes a plurality of gate line groups, a memory circuit that stores setting information that associates each of the plurality of gate line groups with the number of gate lines to which the gate signal is supplied within one cycle of the horizontal synchronization signal; 2. The display device according to claim 1, wherein the control circuit refers to the setting information and changes the number of gate lines to which the gate signal is supplied within one cycle of the horizontal synchronization signal, corresponding to each of the plurality of gate line groups.

6. a plurality of transistors; a plurality of gate lines connected to the plurality of transistors; a plurality of source lines connected to the plurality of transistors; a gate drive circuit for supplying gate signals to the plurality of gate lines; a source driver circuit for supplying a source signal to the plurality of source lines; The source driving circuit includes: an output unit that outputs the source signal; a first switch disposed between the output section and a first group of source lines among the plurality of source lines; a second switch disposed between the output unit and a second group of source lines among the plurality of source lines, When n is a natural number and m is a natural number greater than n, the gate signals are supplied from the gate drive circuit to m gate lines within n periods of the horizontal synchronization signal, and the number obtained by dividing m by n is a rational number other than an integer. operating the gate drive circuit so that a part of a first period during which the gate signal is supplied to a first gate line among the plurality of gate lines overlaps with a part of a second period during which the gate signal is supplied to a second gate line adjacent to the first gate line, the second period starting at a point in time later than the start point of the first period; operating the source drive circuit so that the first switch and the second switch are each turned on once within one cycle of a horizontal synchronization signal; A method for controlling a display device, comprising: operating the source driving circuit so that one of the first switch and the second switch is in an on state during a period in which the first period and the second period overlap.

Images