Module and inter-device communication method

Abstract

To quickly retransmit a command area from a master side device to a slave side device in SPI communication.SOLUTION: An input device 12 has a first FPGA121 and a second FPGA122 for performing SPI communication with each other using a frame having a command area and a response area, and performs field communication with a field device 20. When a status indicating whether an error check result for a command area transmitted from a first FPGA122 is normal or abnormal indicates normal, a second FPGA121 arranges the status before read-data read from a memory according to a read address included in the command area in a response area to be transmitted to the first FPGA121. Further, the input module 12 uses a frame in which the configuration of the response area is different between the case where the status indicates normality and the case where the status indicates abnormality.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to modules and methods of communication between devices. [Background technology]

[0002] SPI (Serial Peripheral Interface) communication is one of the bidirectional communication methods commonly used for communication between devices such as MCUs (Micro Controller Units), FPGAs (Field Programmable Gate Arrays), and memories.

[0003] FIG. 1 shows a typical lead frame configuration for SPI communication.

[0004] As shown in FIG. 1, a typical lead frame is formed, for example, from a command area RC used by a master device and a response area RR0 used by a slave device.

[0005] The command area RC has an R / W flag, a read address, a read data length, and a CRC (Cyclic Redundancy Code). The R / W flag indicates whether the command sent from the master device is a read command or a write command, and the R / W flag in the command area RC of the read frame is set to "R." The CRC in the command area RC is calculated from the values ​​of the R / W flag, read address, and read data length. When reading data, the master device uses the command area RC to send the R / W flag, read address, read data length, and CRC (Cyclic Redundancy Code) to the slave device in that order.

[0006] On the other hand, the response area RR0 contains read data, a read status, and a CRC (Cyclic Redundancy Code). Upon receiving the command area RC, the slave device first reads data from memory according to the R / W flag, read address, and read data length in the command area RC, and transmits the read data (read data) to the master device using the response area RR0. The slave device then performs a CRC (Cyclic Redundancy Check) on the received command area RC and transmits a read status indicating the CRC check result to the master device using the response area RR0. The read status is set to either "normal" or "abnormal" based on the CRC check result. The slave device then calculates a CRC (Cyclic Redundancy Code) from the values ​​of the read data and the read status, and transmits the calculated CRC to the master device using the response area RR0. If the read status in the response area RR0 indicates "abnormal," the master device resends the command area RC to the slave device.

[0007] FIG. 2 is a diagram showing a typical write frame configuration in SPI communication.

[0008] As shown in FIG. 2, a typical write frame is formed, for example, from a command field WC used by a master device and a response field WR0 used by a slave device.

[0009] The command area WC has an R / W flag, a write address, a write data length, the write data, and a CRC (Cyclic Redundancy Code). The R / W flag in the command area WC of a write frame is set to "W." The CRC in the command area WC is calculated from the values ​​of the R / W flag, the write address, the write data length, and the write data. When writing data, the master device uses the command area WC to send the R / W flag, the write address, the write data length, the write data, and the CRC (Cyclic Redundancy Code) in that order to the slave device.

[0010] On the other hand, the response area WR0 contains a write status and a CRC (Cyclic Redundancy Code). A waiting time TW, which corresponds to the time it takes to write write data having a data length LW to memory, occurs in the response area WR0. Upon receiving the command area WC, the slave device first performs a CRC (Cyclic Redundancy Check) on the command area WC at time t2, after the waiting time TW has elapsed since time t1 when the command area WC is received. The slave device then transmits a write status indicating the CRC check result to the master device using the response area WR0. The write status is set to either "normal" or "abnormal" based on the CRC check result. The slave device then calculates a CRC (Cyclic Redundancy Code) from the value of the write status and transmits the calculated CRC to the master device using the response area WR0. If the write status in the response area WR0 indicates "abnormal," the master device resends the command area WC to the slave device. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-312201 Summary of the Invention [Problem to be solved by the invention]

[0012] As shown in Figure 1, when reading data, the slave device sends the read status to the master device after sending the read data. Therefore, if an error occurs in the command area RC (i.e., if the read status indicates "abnormal"), the retransmission of the command area RC from the master device to the slave device is delayed by the time equivalent to the data length of the read data.

[0013] 2, when writing data, the slave device transmits the write status to the master device at time t2, after the waiting time TW has elapsed since the time t1 when the command area WC is received. Therefore, if an error occurs in the command area WC (i.e., if the write status indicates "abnormal"), the retransmission of the command area WC from the master device to the slave device is delayed by the waiting time TW.

[0014] Therefore, the present disclosure proposes a technique that enables a command field to be quickly retransmitted from a master device to a slave device in SPI communication. [Means for solving the problem]

[0015] A module disclosed herein has a master device and a slave device that perform SPI communication with each other using a frame having a command field and a response field, and performs field communication with a field instrument. When a status indicating whether an error check result for the command field transmitted from the master device is normal or abnormal indicates normal, the slave device places the status in the response field transmitted to the master device before read data read from a memory according to the read address included in the command field. [Effects of the Invention]

[0016] According to the present disclosure, it is possible to quickly retransmit a command field from a master device to a slave device in SPI communication. [Brief explanation of the drawings]

[0017] [Figure 1] Diagram showing a typical lead frame configuration for SPI communication [Figure 2] A diagram showing a typical write frame configuration for SPI communication [Figure 3] FIG. 1 is a diagram illustrating a configuration example of a field communication system according to a first embodiment of the present disclosure. [Figure 4] FIG. 1 is a diagram showing a configuration example of a first lead frame according to a first embodiment of the present disclosure; [Figure 5] FIG. 1 is a diagram showing a configuration example of a second lead frame according to a first embodiment of the present disclosure; [Figure 6] FIG. 10 is a diagram illustrating a configuration example of a first light frame according to a second embodiment of the present disclosure. [Figure 7] FIG. 10 is a diagram illustrating a configuration example of a second light frame according to a second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, the same components or processes will be denoted by the same reference numerals, and redundant description may be omitted.

[0019] [Example 1] <Field communication system configuration> 3 is a diagram illustrating a configuration example of a field communication system according to the first embodiment of the present disclosure. In FIG. 3, the field communication system 1 includes a programmable logic controller (PLC) 10 and a field device 20.

[0020] The field device 20 has a sensor 21 and a controlled device 22. Examples of the field device 20 include a thermometer, a light actinometer, a displacement meter, a pressure meter, and a vibration meter. Examples of the sensor 21 include a temperature sensor, a light sensor, a displacement sensor, a pressure sensor, and a vibration sensor. The sensor 21 transmits data indicating a physical quantity detected by the sensor 21 (hereinafter, sometimes referred to as "sensor data") to the PLC 10. The controlled device 22 is controlled in accordance with control data transmitted from the PLC 10. Examples of control performed by the controlled device 22 include temperature control, pressure control, flow rate control, motor control, and valve control.

[0021] The PLC 10 includes a CPU (Central Processing Unit) 11, an input module 12, and an output module 13. The input module 12 includes a first FPGA 121 and a second FPGA 122. The output module 13 includes a third FPGA 131 and a fourth FPGA 132. The field communication system 1 may include a DCS (Distributed Control System) including the CPU 11, the input module 12, and the output module 13, instead of the PLC 10. In the PLC 10 or the DCS, the first FPGA 121 may be included in a module different from the input module 12, and the third FPGA 131 may be included in a module different from the output module 13. The PLC and the DCS are examples of control devices including the input module 12, the output module 13, and other modules.

[0022] The CPU 11 and the first FPGA 121 communicate with each other using an inter-module communication bus. The first FPGA 121 and the second FPGA 122 perform SPI communication. The second FPGA 122 and the sensor 21 perform field communication.

[0023] The first FPGA 121 and the third FPGA 131 communicate with each other using an inter-module communication bus. The third FPGA 131 and the fourth FPGA 132 perform SPI communication. The fourth FPGA 132 and the controlled device 22 perform field communication.

[0024] <Field communication system operation> In FIG. 3, first, the second FPGA 122 acquires the sensor data transmitted from the sensor 21, and temporarily stores the acquired sensor data in a memory included in the second FPGA 122.

[0025] Next, the CPU 11 transmits a request to read the sensor data to the first FPGA 121.

[0026] Next, the first FPGA 121 sends a read command for the sensor data to the second FPGA 122 in response to the read request from the CPU 11.

[0027] 3, the first FPGA 121 corresponds to a master device in SPI communication, and the second FPGA 122 corresponds to a slave device in SPI communication. The first FPGA 121 is an example of a master device in SPI communication, and the second FPGA 122 is an example of a slave device in SPI communication.

[0028] If the check result of the CRC (Cyclic Redundancy Check) for the sensor data read command is "normal," the second FPGA 122 reads the sensor data from the memory included in the second FPGA 122. On the other hand, if the check result of the CRC (Cyclic Redundancy Check) for the sensor data read command is "abnormal," the second FPGA 122 does not read the sensor data from the memory included in the second FPGA 122. The CRC (Cyclic Redundancy Check) is an example of an error check for a read command.

[0029] Below, the configuration of the lead frame in Example 1 will be explained separately as the configuration of the first lead frame used when the read status indicates "normal" and the configuration of the second lead frame used when the read status indicates "abnormal".

[0030] <Configuration of first lead frame> 4 is a diagram illustrating a configuration example of a first lead frame according to the first embodiment of the present disclosure. As illustrated in FIG. 4, the first lead frame is formed of a command area RC used by the first FPGA 121, which is a master device, and a response area RR1 used by the second FPGA 122, which is a slave device. The command area RC corresponds to a command to read sensor data.

[0031] The configuration of the command area RC shown in FIG. 4 is the same as the configuration of the command area RC shown in FIG. 1, so a description of the command area RC shown in FIG. 4 will be omitted.

[0032] On the other hand, in FIG. 4, the response area RR1 includes a read status, read data, and a CRC (Cyclic Redundancy Code).

[0033] The second FPGA 122, upon receiving the command area RC, first performs a CRC (Cyclic Redundancy Check) on the received command area RC, and then transmits the read status set to "normal" based on the CRC check result to the first FPGA 121 using the response area RR1.

[0034] Next, the second FPGA 122 reads the sensor data from the memory according to the R / W flag, the read address, and the read data length in the command area RC, and transmits the read sensor data (read data) to the first FPGA 121 using the response area RR1.

[0035] Next, the second FPGA 122 calculates a CRC (Cyclic Redundancy Code) from the values ​​of the read status and the sensor data (read data), and transmits the calculated CRC to the first FPGA 121 using the response region RR1.

[0036] Then, since the read status indicates “normal”, the first FPGA 121 transfers the sensor data received from the second FPGA 122 to the CPU 11.

[0037] As described above, in the response area RR0 shown in FIG. 1, the read data is arranged at the beginning of the response area RR0, and the read status is arranged after the read data. In other words, in the response area RR0 shown in FIG. 1, the read status is arranged after the read data. In contrast, in the response area RR1 shown in FIG. 4, the read status is arranged at the beginning of the response area RR1, and the read data is arranged after the read status. In other words, in the response area RR1 shown in FIG. 4, the read status is arranged before the read data. Note that in the response area RR1, data other than the read data may be inserted between the read status and the read data.

[0038] <Configuration of the second lead frame> 5 is a diagram illustrating a configuration example of a second lead frame according to the first embodiment of the present disclosure. As illustrated in FIG. 5, the second lead frame is formed of a command area RC used by the first FPGA 121, which is a master device, and a response area RR2 used by the second FPGA 122, which is a slave device.

[0039] The configuration of the command area RC shown in FIG. 5 is the same as the configuration of the command area RC shown in FIG. 1, so a description of the command area RC shown in FIG. 5 will be omitted.

[0040] On the other hand, in FIG. 5, the response area RR2 includes a read status and a CRC (Cyclic Redundancy Code).

[0041] The second FPGA 122, upon receiving the command area RC, first performs a CRC (Cyclic Redundancy Check) on the received command area RC, and then transmits the read status set to "abnormal" based on the CRC check result to the first FPGA 121 using the response area RR2.

[0042] Next, the second FPGA 122 calculates a CRC (Cyclic Redundancy Code) from the value of the read status, and transmits the calculated CRC to the first FPGA 121 using the response region RR2.

[0043] Then, the first FPGA 121 resends the command field RC to the second FPGA 122 because the read status indicates “abnormal”.

[0044] In this way, in the response area RR0 shown in Fig. 1, the read data is placed at the beginning of the response area RR0, and the read status is placed after the read data. In contrast, in the response area RR2 shown in Fig. 5, the read status is placed at the beginning of the response area RR2, and no read data is placed there.

[0045] 1 is used both when the read status indicates "normal" and when the read status indicates "abnormal." In contrast, the configuration of the response area RR1 shown in FIG. 4 and the configuration of the response area RR2 shown in FIG. 5 are different from each other.

[0046] The first embodiment has been described above.

[0047] [Example 2] <Field communication system operation> In FIG. 3, first, the CPU 11 transmits control data and a write request to the third FPGA 131 via the first FPGA 121.

[0048] Next, in response to the write request from the CPU 11, the third FPGA 131 transmits the control data and a write command for the control data to the fourth FPGA 132.

[0049] 3, the third FPGA 131 corresponds to a master device in SPI communication, and the fourth FPGA 132 corresponds to a slave device in SPI communication. The third FPGA 131 is an example of a master device in SPI communication, and the fourth FPGA 132 is an example of a slave device in SPI communication.

[0050] If the check result of CRC (Cyclic Redundancy Check) for the write of the control data is "normal", the fourth FPGA 132 writes the control data to a memory included in the fourth FPGA 132 and then transmits the control data to the controlled device 22. On the other hand, if the check result of CRC (Cyclic Redundancy Check) for the write command of the control data is "abnormal", the fourth FPGA 132 does not write the control data to the memory included in the fourth FPGA 132 or transmit the control data to the controlled device 22. The CRC (Cyclic Redundancy Check) is an example of an error check for a write command.

[0051] Below, the configuration of the light frame in Example 2 will be explained separately as the configuration of the first light frame used when the light status indicates "normal" and the configuration of the second light frame used when the light status indicates "abnormal".

[0052] <Configuration of the first light frame> 6 is a diagram illustrating a configuration example of a first write frame according to a second embodiment of the present disclosure. As illustrated in Fig. 6, the first write frame is formed of a command area WC used by the third FPGA 131, which is a master device, and a response area WR1 used by the fourth FPGA 132, which is a slave device. The command area WC corresponds to a write command for control data.

[0053] The configuration of the command area WC shown in FIG. 6 is the same as the configuration of the command area WC shown in FIG. 2, and therefore a description of the command area WC shown in FIG. 6 will be omitted.

[0054] On the other hand, in FIG. 6, the response area WR1 has a first write status, a first CRC (Cyclic Redundancy Code), a second write status, and a second CRC (Cyclic Redundancy Code).

[0055] When the fourth FPGA 132 receives the command area WC, it first performs a CRC (Cyclic Redundancy Check) on the received command area WC, and then sends the first write status set to "normal" based on the CRC check result to the third FPGA 131 using the response area WR1.

[0056] Next, the fourth FPGA 132 calculates a first CRC (Cyclic Redundancy Code) from the value of the first write status, and transmits the calculated first CRC to the third FPGA 131 using the response area WR1.

[0057] Here, a waiting time TW occurs, which corresponds to the time required to write the control data (write data) having a data length LW into the memory, starting from the time t1 when the fourth FPGA 132 has completed receiving the command area WC. During the waiting time TW, the fourth FPGA 132 transmits the first write status and the first CRC in parallel with writing the control data (write data) into the memory.

[0058] Furthermore, at time t2 after the waiting time TW has elapsed, the fourth FPGA 132 transmits a second write status indicating that writing of the control data (write data) to the memory has been completed to the third FPGA 131 using the response area WR1.

[0059] Next, the fourth FPGA 132 calculates a second CRC (Cyclic Redundancy Code) from the value of the second write status, and transmits the calculated second CRC to the third FPGA 131 using the response area WR1.

[0060] In this way, in the response area WR0 shown in Fig. 2, a write status indicating the check result of the CRC (Cyclic Redundancy Check) is placed at time t2 after the waiting time TW has elapsed from time t1 when the reception of the command area WC is completed. In contrast, in the response area WR1 shown in Fig. 6, a first write status indicating the check result of the CRC (Cyclic Redundancy Check) is placed at the beginning of the response area WR1.

[0061] <Configuration of the second light frame> 7 is a diagram illustrating a configuration example of a second write frame according to the second embodiment of the present disclosure. As illustrated in Fig. 7, the second write frame is formed of a command region WC used by the third FPGA 131, which is a master device, and a response region WR2 used by the fourth FPGA 132, which is a slave device.

[0062] The configuration of the command area WC shown in FIG. 7 is the same as the configuration of the command area WC shown in FIG. 2, and therefore a description of the command area WC shown in FIG. 7 will be omitted.

[0063] On the other hand, in FIG. 7, the response area WR2 has a first write status and a first CRC (Cyclic Redundancy Code).

[0064] When the fourth FPGA 132 receives the command area WC, it first performs a CRC (Cyclic Redundancy Check) on the received command area WC, and then sends the first write status set to "abnormal" based on the CRC check result to the third FPGA 131 using the response area WR2.

[0065] Next, the fourth FPGA 132 calculates a first CRC (Cyclic Redundancy Code) from the value of the first write status, and transmits the calculated first CRC to the third FPGA 131 using the response area WR2.

[0066] Then, the third FPGA 131 resends the command field WC to the fourth FPGA 132 because the first write status indicates “abnormal”.

[0067] 2, a write status indicating the CRC (Cyclic Redundancy Check) check result is placed at time t2 after the waiting time TW has elapsed from time t1 when the command area WC is received. In contrast, in the response area WR2 shown in FIG. 7, a first write status indicating the CRC (Cyclic Redundancy Check) check result is placed at the beginning of the response area WR2. Therefore, in the response area WR2, the first write status is transmitted to the third FPGA 131 before the waiting time TW has elapsed from time t1 when the command area WC is received.

[0068] 2 is used both when the write status indicates "normal" and when the write status indicates "abnormal." In contrast, the configuration of the response area WR1 shown in FIG. 6 and the configuration of the response area WR2 shown in FIG. 7 are different from each other.

[0069] The second embodiment has been described above.

[0070] As described above, the modules (input module 12 and output module 13 of the embodiment) of the present disclosure have a master-side device (first FPGA 121 and third FPGA 131 of the embodiment) and a slave-side device (second FPGA 122 and fourth FPGA 132 of the embodiment) that perform SPI communication with each other using a frame having a command field and a response field, and perform field communication with a field device (field device 20 of the embodiment). When the status indicating whether the error check result for the command field transmitted from the master-side device is normal or abnormal indicates normal, the slave-side device places the status in the response field transmitted to the master-side device before the read data read from the memory according to the read address included in the command field.

[0071] In this way, by placing the status indicating the error check result for the command area before the read data in the response area, the master device can quickly detect that the status indicates an abnormality, and can quickly resend the command area from the master device to the slave device in SPI communication.

[0072] In addition, some examples of combinations in the techniques of the present disclosure are described below.

[0073] (1) A module that performs field communication with a field device, the module having a master-side device and a slave-side device that perform SPI communication with each other using a frame having a command field and a response field, wherein the slave-side device places a status indicating whether the error check result for the command field transmitted from the master-side device is normal or abnormal at the beginning of the response field transmitted to the master-side device.

[0074] (2) The module according to (1), wherein the frame has a different configuration of the response area when the status indicates normal and when the status indicates abnormal.

[0075] (3) The module described in (1), wherein the command area includes a read address, and when the status indicates normal, the slave side device places the status before the read data read from the memory according to the read address.

[0076] (4) The module described in (1), wherein the command area includes a read address, and when the status indicates an abnormality, the slave-side device places the status in the response area, but does not place read data in the response area.

[0077] (5) The module according to (3) or (4), wherein the read data is data indicating a physical quantity detected by a sensor included in the field device.

[0078] (6) The module described in (1), wherein the command area includes write data, and when the status indicates normal, the slave-side device transmits the status using the response area in parallel with writing the write data to memory.

[0079] (7) The module described in (1), wherein the command area includes write data, and when the status indicates normal, the slave-side device transmits the status using the response area and also transmits another status using the response area indicating that writing of the write data to memory has been completed.

[0080] (8) The module described in (1), wherein the command area includes write data, and when the status indicates an abnormality, the slave-side device transmits the status using the response area before a waiting time equivalent to the time it takes to write the write data to memory from the time the command area is completely received has elapsed.

[0081] (9) The module according to any one of (6) to (8), wherein the write data is control data transmitted from a PLC having the module to the field device.

[0082] (10) The module according to (1), wherein the master device and the slave device are FPGAs.

[0083] (11) A device-to-device communication method in a module that has a master device and a slave device that perform SPI communication with each other using a frame having a command field and a response field, and that performs field communication with a field instrument, in which the slave device places a status indicating whether the error check result for the command field transmitted from the master device is normal or abnormal at the beginning of the response field transmitted to the master device. [Explanation of symbols]

[0084] 1. Field communication system 10 PLC 20 Field Devices 21 Sensors 22 Controlled device 11 CPU 12 Input Modules 13 Output Module 121 First FPGA 122 Second FPGA 131 Third FPGA 132 Fourth FPGA

Claims

1. A module for performing field communication with a field device, the module having a master device and a slave device that perform SPI communication with each other using a frame having a command area and a response area, When a status indicating whether an error check result for the command field transmitted from the master device is normal or abnormal indicates normal, the slave-side device places the status in the response field transmitted to the master-side device before the read data read from the memory in accordance with the read address included in the command field. Module.

2. A module for performing field communication with a field device, the module having a master device and a slave device that perform SPI communication with each other using a frame having a command area and a response area, when a status indicating whether an error check result for the command field transmitted from the master device is normal or abnormal indicates an abnormality, the slave-side device places the status in the response field transmitted to the master-side device, but does not place read data in the response field transmitted to the master-side device; Module.

3. The read data is data indicating a physical quantity detected by a sensor included in the field device.

3. A module according to claim 1 or 2.

4. A module for performing field communication with a field device, the module having a master device and a slave device that perform SPI communication with each other using a frame having a command area and a response area, When a status indicating whether an error check result for the command field transmitted from the master device is normal or abnormal indicates normal, the slave device transmits the status using the response field in parallel with writing the write data included in the command field to a memory. Module.

5. When the status indicates normal, the slave device transmits the status using the response area, and also transmits another status using the response area indicating that writing of the write data into the memory has been completed. The module of claim 4.

6. the write data is control data transmitted from a PLC having the module to the field device; 6. A module according to claim 4 or 5.

7. A module for performing field communication with a field device, the module having a master device and a slave device that perform SPI communication with each other using a frame having a command field and a response field, When a status indicating whether an error check result for the command field transmitted from the master device is normal or abnormal indicates normal, the slave device places the status in the response field transmitted to the master device before the read data read from the memory in accordance with the read address included in the command field. Inter-device communication methods.

8. A module for performing field communication with a field device, the module having a master device and a slave device that perform SPI communication with each other using a frame having a command field and a response field, When a status indicating whether an error check result for the command field transmitted from the master device is normal or abnormal indicates an abnormality, the slave device places the status in the response field transmitted to the master device, but does not place read data in the response field transmitted to the master device. Inter-device communication methods.

9. A module for performing field communication with a field device, the module having a master device and a slave device that perform SPI communication with each other using a frame having a command field and a response field, When a status indicating whether an error check result for the command field transmitted from the master device is normal or abnormal indicates normal, the slave device transmits the status using the response field in parallel with writing the write data included in the command field to a memory. Inter-device communication methods.

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