Multilayer ceramic capacitor and circuit board

Abstract

To provide a multilayer ceramic capacitor having improved bonding strength with a circuit board, and to provide a circuit board mounted with the multilayer ceramic capacitor.SOLUTION: The multilayer ceramic capacitor 100 includes a plurality of terminals 40a and 40b that are disposed apart from each other on a mounting surface that faces a circuit substrate when mounted on the circuit substrate and are electrically connected to the internal electrodes. When a first straight line and a second straight line extending in the L direction and the W direction without touching any of the terminal electrodes are drawn, a region of the mounting surface where the terminal electrodes are not disposed has a mounting surface side intersecting portion 111 where an intersection of the first straight line and the second straight line is formed and a mounting surface side non-intersecting portion 112 where no intersection of the first straight line and the second straight line is formed, the element body 10 satisfies T1 <T2, where T1 is the size of the laminated body in the lamination direction measured with reference to the mounting surface side intersection part, and T2 is the size of the laminated body in the lamination direction measured with reference to the mounting surface side non-intersection part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a circuit board. [Background technology]

[0002] A wide variety of ceramic electronic components are used in high-frequency communication systems, such as mobile phones. These ceramic electronic components are required to be smaller and thinner, and efforts are being made to make them smaller and thinner in multilayer ceramic capacitors as well.

[0003] Patent Document 1 discloses a thin, break-resistant multilayer ceramic capacitor in which via-hole electrodes that electrically connect internal electrode layers to each other and internal electrode layers to terminal electrodes have voids formed therein. In the multilayer ceramic capacitor disclosed in Patent Document 1, terminal electrodes are formed on the flat upper surface of the element body. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-72263 Summary of the Invention [Problem to be solved by the invention]

[0005] Multilayer ceramic capacitors are mounted on circuit boards by soldering terminal electrodes to pads on the circuit board. In this case, the exposed portions of the top surface of the element body on which the terminal electrodes are arranged, which are not covered by the terminal electrodes, have a flat shape and therefore contribute very little to the development of joint strength with the solder. Therefore, when a circuit board on which a multilayer ceramic capacitor is mounted is subjected to bending deformation, stress concentrates at the interface between the terminal electrodes and the solder, particularly at the corners of the terminal electrodes, which have a small area. This causes peeling at the interface starting from the corners, resulting in poor contact between the multilayer ceramic capacitor and the circuit board.

[0006] The present invention has been made to solve the above problems, and has an object to provide a multilayer ceramic capacitor having improved bonding strength with a circuit board, and a circuit board on which the multilayer ceramic capacitor is mounted. [Means for solving the problem]

[0007] The inventors have conducted various studies to solve the above-mentioned problems, and have found that the above-mentioned object can be achieved by making a specific portion of the area on the mounting surface of the element body of a multilayer ceramic capacitor, i.e., the surface that faces the circuit board when mounted on the circuit board, where no terminal electrodes are arranged, more recessed than other portions, and have thus completed the present invention.

[0008] That is, a first aspect of the present invention for solving the above problems is a laminate in which a ceramic layer formed of ceramic and an internal electrode mainly composed of metal are alternately laminated, a pair of cover portions disposed at both ends in the lamination direction of the laminate and covering the surface of the laminate, and a margin portion that covers at least a part of the end portion of the ceramic layer and the end portion of the internal electrode in the laminate and connects the pair of cover portions, and a rectangular parallelepiped-shaped element having a plurality of terminal electrodes that are arranged apart from each other on a mounting surface that is a surface facing the circuit board when mounted on the circuit board among the surfaces forming the surface of the element and are electrically connected to the internal electrodes. The plurality of terminal electrodes are arranged in m numbers in a first direction on the mounting surface and n numbers in a second direction orthogonal to the first direction (where m is a natural number of 2 or more and n is a natural number). When a first straight line that extends in the first direction without touching any of the terminal electrodes and a second straight line that extends in the second direction without touching any of the terminal electrodes are drawn in a region of the mounting surface where the terminal electrodes are not arranged, a mounting surface-side intersection portion where an intersection of the first straight line and the second straight line is formed, and a mounting surface-side non-intersection portion where an intersection of the first straight line and the second straight line is not formed are provided. The element is a multilayer ceramic capacitor that satisfies T1 < T2, where T1 is the dimension of the laminate in the lamination direction measured with reference to the mounting surface-side intersection portion, and T2 is the dimension of the laminate in the lamination direction measured with reference to the mounting surface-side non-intersection portion.

[0009] Further, a second aspect of the present invention for solving the above problems is a circuit board on which the multilayer ceramic capacitor according to the first aspect is mounted.

Effect of the Invention

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor with improved bonding strength to a circuit board, and a circuit board on which the multilayer ceramic capacitor is mounted.

Brief Description of the Drawings

[0011] [Figure 1]1 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 2 is a cross-sectional view taken along line AA (LT cross-sectional view) in FIG. 1. [Figure 3] FIG. 2 is a top view (LW plan view) of FIG. [Figure 4] 1 is a schematic diagram (LT cross-sectional view) showing a preferred shape of the mounting surface of the multilayer ceramic according to the first embodiment. [Figure 5] FIG. 10 is a schematic diagram (LT plan view) showing the structure of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a schematic view (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Figure 7] FIG. 10 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] The configuration and effects of the present invention will be described below, along with the technical concept, with reference to the drawings. However, the mechanism of action includes assumptions, and the correctness of such assumptions does not limit the present invention.

[0013] [Multilayer ceramic capacitors] First Embodiment 1 to 3 show an embodiment of a multilayer ceramic capacitor according to a first aspect of the present invention as a first embodiment. The multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and includes a pair of faces perpendicular to three mutually orthogonal axes, i.e., the L-axis, which is the length direction, the W-axis, which is the width direction, and the T-axis, which is the height direction. The rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, but may have any shape that is recognized as a rectangular parallelepiped when observed as a whole. Therefore, a rectangular parallelepiped in the present disclosure also includes a capacitor with slightly rounded edges or corners, a capacitor with slightly curved edges, and a capacitor with curved faces with a small curvature. The length (L), width (W), and height (T) dimensions of the ceramic capacitor 100 can each independently take any value.

[0014] The dimensions of the multilayer ceramic capacitor 100 are, for example, an L-direction dimension of 200 μm to 2000 μm, a W-direction dimension of 100 μm to 2000 μm, and a T-direction dimension of 30 μm to 220 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.3 to 1.0. It is preferable that the L-direction dimension be 400 μm to 1200 μm, the W-direction dimension be 400 μm to 1200 μm, and the T-direction dimension be 40 μm to 150 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.4 to 1.0. It is more preferable that the T-direction dimension be 100 μm or less, as this is less subject to design constraints on the circuit board on which it is mounted.

[0015] 2, the multilayer ceramic capacitor 100 according to the first embodiment includes an element body 10 having a laminate 20 in which ceramic layers 21 made of ceramic and internal electrodes 22 mainly composed of metal are alternately stacked in the T direction, a pair of cover portions 31 covering the surface of the laminate 20, and margin portions 32 that cover at least a portion of the ends of the ceramic layers 21 and the internal electrodes 22 in the laminate 20 and connect the pair of cover portions 31 to each other. The internal electrodes 22 include internal electrodes 22a of one polarity that are electrically connected to each other, and internal electrodes 22b of a polarity different from that of the internal electrodes 22a that are electrically connected to each other.

[0016] There is no particular limitation on the method for electrically connecting the internal electrodes 22a to each other and the internal electrodes 22b to each other. Fig. 2 shows a mode in which the internal electrodes are connected by via conductors 23 (23a, 23b) that are arranged inside the element body 10 so as to penetrate the ceramic layers 21 in the stacking direction of the laminate 20 and have at least one end reaching the surface of a cover portion 31, which will be described later. However, as in a second embodiment, which will be described later, the internal electrodes may be extended to the end faces of the element body and connected by external conductors. Note that although the multilayer ceramic capacitor 100 shown in Fig. 2 has two via conductors 23, the number of via conductors in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0017] On the surface of the element body 10, a cover portion 31 is arranged on a surface perpendicular to the T direction of the laminate 20, and margin portions 32 are arranged on surfaces perpendicular to the W direction and the L direction of the laminate. When the internal electrodes are drawn out to the end faces of the element body as in the second embodiment described later, no margin portions are arranged on the end faces (drawing faces) from which the internal electrodes are drawn out.

[0018] The multilayer ceramic capacitor 100 according to the first embodiment includes a plurality of terminal electrodes 40 (40a, 40b) that are arranged apart from one another on a mounting surface 11, which is one of the surfaces that form the surface of the element body 10 and faces the circuit board when the element body 10 is mounted on the circuit board, and are electrically connected to internal electrodes 22 (22a, 22b). The plurality of terminal electrodes 40 (40a, 40b) are arranged m in number in a first direction (L direction) on the mounting surface 11, and n in number in a second direction (W direction) perpendicular to the first direction (where m is a natural number greater than or equal to 2, and n is a natural number). Here, the first direction and the second direction are determined by a straight line obtained by projecting each terminal electrode 40 (40a, 40b) perpendicular to the mounting surface 11 and fitting the center of gravity of each projected figure using the least squares method. The method for electrically connecting the terminal electrodes 40 (40a, 40b) and the internal electrodes 22 (22a, 22b) is not particularly limited. FIG. 2 shows a mode in which the connection is made through via conductors 23 (23a, 23b), but the connection may also be made through external conductors as in the second embodiment described below. Note that the multilayer ceramic capacitor 100 shown in FIG. 2 includes two terminal electrodes 40, which corresponds to the case where m=2 and n=1, but the number of terminal electrodes in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0019] As shown in FIG. 3, the multilayer ceramic capacitor 100 according to the first embodiment has a mounting surface side intersection portion 111 and a mounting surface side non-intersection portion 112 in a region of the mounting surface 11 of the body 10 where the terminal electrodes 40 (40a, 40b) are not arranged. The mounting surface side intersection portion 111 is a portion where an intersection of a first straight line l1 extending without touching any of the terminal electrodes 40 (40a, 40b) in a first direction (L direction) which is one of the arrangement directions of the terminal electrodes 40 (40a, 40b) and a second straight line l2 extending without touching any of the terminal electrodes 40 (40a, 40b) in a second direction (W direction) which is the other arrangement direction of the terminal electrodes 40 (40a, 40b) (a direction orthogonal to the first direction) is formed when each is drawn on the mounting surface 11. On the other hand, the mounting surface side non-intersection portion 112 is a portion where no intersection of the first straight line l1 and the second straight line l2 is formed. When the dimension of the laminate 20 in the lamination direction (T direction) measured with reference to the mounting surface side intersection portion 111 is T1 and the dimension in the T direction measured with reference to the mounting surface side non-intersection portion 112 is T2, the body 10 satisfies T1 < T2.

[0020] The maximum thickness of the body 10 obtained by subtracting the thickness of the terminal electrodes 40 (40a, 40b) from the dimension in the T direction of the multilayer ceramic capacitor 100 described above is, for example, 20 μm or more and 200 μm or less, and preferably 30 μm or more and 180 μm or less.

[0021] Hereinafter, each part constituting the multilayer ceramic capacitor 100 according to the first embodiment will be described in detail.

[0022] (Ceramic layer) The ceramic layer 21 is formed of ceramic. The composition of the ceramic is not particularly limited as long as a dense ceramic layer 21 can be formed by co-firing with the internal electrode 22 described later, and may be appropriately selected according to the characteristics required for the multilayer ceramic capacitor. Examples of the composition of the ceramic include those having barium titanate (BaTiO3) as a main component, those having strontium titanate (SrTiO3) as a main component, and Ba having a perovskite structure 1-x-y Ca xSr y Ti 1-z Zr z Examples of such ceramics include those containing O3 as a main component. The ceramic may contain an additive element in addition to the main component. Examples of the additive element include at least one selected from Mo, Nb, Ta, W, Mg, Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), and Co, Ni, Li, B, Na, K, and Si. The additive element may be contained as a simple element or in the form of a compound such as an oxide, nitride, or carbide. The additive element may exist in a solid solution state in the main component, or may form a different phase from the elements constituting the main component or other additive elements.

[0023] (Internal electrode) The internal electrodes 22 (22a, 22b) are primarily composed of a metal. The type of metal is not particularly limited, and nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof can be used. Among these, nickel (Ni) is preferred as the primary element because of its high heat resistance, which allows the firing temperature to be increased when co-firing with the ceramic layer 21 to form a dense ceramic layer 21, and it is relatively inexpensive. Here, the term "primary element" as used herein refers to the element with the highest content expressed in atomic percentage (atomic %).

[0024] The internal electrodes 22 (22a, 22b) may contain, in addition to metal, ceramic particles having the same composition as the ceramic constituting the ceramic layer 21, or a glass component.

[0025] (Cover and margin) Both the cover portion 31 and the margin portion 32 have the function of protecting the ceramic layer 21 and the internal electrode 22. The material of the cover portion 31 and the margin portion 32 is not limited as long as it has high electrical insulation and low permeability to deterioration factors such as moisture. From the viewpoints of making shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 uniform and alleviating internal stress within the multilayer ceramic capacitor 100, it is preferable that the main component of the cover portion 31 and the margin portion 32 be the same as the ceramic that forms the ceramic layer 21.

[0026] (Via conductor) Like the internal electrodes 22 (22a, 22b), the via conductors 23 (23a, 23b) are primarily composed of metal. Usable metals include those similar to those of the internal electrodes 22 (22a, 22b) described above. The composition of the via conductors may be different from that of the internal electrodes 22 (22a, 22b), but is preferably the same as that of the internal electrodes 22 (22a, 22b). By making the via conductors (23a, 23b) and the internal electrodes 22 (22a, 22b) the same composition, the magnitude of shrinkage caused by firing during manufacturing of the multilayer ceramic capacitor 100 is uniform, suppressing deformation, and the resistivity of the conductive paths of the multilayer ceramic capacitor 100 is uniform, suppressing localized heat generation during use.

[0027] The diameter of the via conductors (23a, 23b) is not particularly limited, but in order to ensure the capacity of the multilayer ceramic capacitor 100 while reducing electrical resistance and suppressing heat generation during circuit operation, it is preferable to make it 5 μm or more and 100 μm or less, and more preferably 10 μm or more and 50 μm or less.

[0028] (terminal electrode) The material of the terminal electrodes 40 (40a, 40b) is not limited as long as it is conductive, and examples of the material include metals such as nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys containing any of these as a main component, and conductive resins.

[0029] The terminal electrodes 40 (40a, 40b) may have an underlying conductor 41 in contact with the element body 10 and a plated conductor 42 formed on the surface of the underlying conductor 41. The terminal electrodes 40 (40a, 40b) having such a structure can improve adhesion to the element body 10 by the underlying conductor 41, and can improve solder wettability by the plated conductor 42 when mounted on a circuit board.

[0030] Ni is an example of the material of the underlying conductor 41. The thickness of the underlying conductor 41 can be set to 0.1 μm or more and 10 μm or less, and preferably 0.5 μm or more and 5 μm or less.

[0031] The plated conductor 42 may be formed of a single layer or multiple layers. When the plated conductor 42 is formed of multiple layers, the number of layers is preferably two to four. An example of the material and structure of the plated conductor 42 is one formed of Cu, Ni, and Sn in this order. The thickness of the plated conductor 42 can be 1 μm to 20 μm, and preferably 3 μm to 10 μm.

[0032] The area of ​​the terminal electrodes 40 (40a, 40b), i.e., the area of ​​the terminal electrodes 40 (40a, 40b) observed when the multilayer ceramic capacitor 100 is viewed from a direction perpendicular to the mounting surface, is not particularly limited, as long as it is large enough to facilitate mounting on a circuit board and small enough to prevent short-circuiting between electrodes having opposite polarities. Preferably, the ratio of the total area of ​​the terminal electrodes 40 to the area of ​​the mounting surface 11 is 0.2 to 0.9, more preferably 0.3 to 0.8.

[0033] (Mounting surface of the element) In the region on the mounting surface 11 of the element body 10 where the terminal electrodes 40 (40a, 40b) are not arranged, as described above, there are the mounting surface side intersection portion 111 and the mounting surface side non - intersection portion 112. When the dimension in the T direction of the element body 10 measured based on the mounting surface side intersection portion 111 is T1, and the dimension in the T direction of the element body 10 measured based on the mounting surface side non - intersection portion 112 is T2, T1 < T2 is satisfied. As a result, when mounting the multilayer ceramic capacitor 100 on a circuit board, a part of the melted solder flows from the corner of the terminal electrode 40 (40a, 40b) into the mounting surface side intersection portion 111 and solidifies. As a result, the contact area between the surface of the element body 10 and / or the terminal electrode 40 (40a, 40b) increases, and the bonding strength between the multilayer ceramic capacitor 100 and the solder is improved.

[0034] Preferably, the aforementioned T1 and T2 satisfy 0.1μm ≦ (T2 - T1) ≦ 10μm. When the value of (T2 - T1) is 0.1μm or more, solder easily flows into the mounting surface side intersection portion 111 during circuit board mounting. From this point, the value of (T2 - T1) is more preferably 0.3μm or more, and even more preferably 0.5μm or more. On the other hand, when the value of (T2 - T1) is 10μm or less, the thickness of the cover portion 31 or the margin portion 32 can be ensured without increasing the dimension of the multilayer ceramic capacitor 100 in the T direction, and the intrusion of deterioration factors such as moisture into the laminate 20 can be effectively suppressed. From this point, the value of (T2 - T1) is more preferably 9μm or less, and even more preferably 8μm or less. From the above, the value of (T2 - T1) more preferably satisfies 0.3μm ≦ (T2 - T1) ≦ 9μm, and even more preferably satisfies 0.5μm ≦ (T2 - T1) ≦ 8μm.

[0035] When the terminal electrodes 40 (40a, 40b) have the base conductor 41 and the plating conductor 42, when the dimension in the T direction measured based on the region where the base conductor 41 is arranged on the mounting surface 11 of the element body 10 is Tb1, and the dimension in the T direction measured based on the region in contact with the plating conductor 42 on the mounting surface 11 is Tp1, as shown in FIG. 4, it is preferable to satisfy T2 ≤ Tp1 < Tb1. By this, the contact area between the element body 10 and the plating conductor 42 increases, and the bonding strength between the two increases.

[0036] The arithmetic mean roughness Ra of the mounting surface side intersection 111 is preferably 0.01 μm or more and 1 μm or less. Since Ra is 0.01 μm or more, when mounting the multilayer ceramic capacitor 100 on the circuit board, it is possible to suppress the spread of the solder flowing from the terminal electrodes 40 (40a, 40b) to the mounting surface side intersection 111 to the other adjacent terminal electrodes 40 (40a, 40b). Also, when resin filling is performed between the terminal electrodes 40 (40a, 40b) during mounting of the multilayer ceramic capacitor 100 on the circuit board, there is also an advantage that the adhesion strength with the resin is improved. From these points, Ra is more preferably 0.05 μm or more, and even more preferably 0.1 μm or more. On the other hand, since Ra is 1 μm or less, it is possible to secure the thickness of the cover portion 31 or the margin portion 32 without increasing the T-direction dimension of the multilayer ceramic capacitor 100, and effectively suppress the intrusion of deterioration factors such as moisture into the laminate 20. From this point, Ra is more preferably 0.9 μm or less, and even more preferably 0.8 μm or less. From the above, Ra is more preferably 0.1 μm or more and 0.9 μm or less, and even more preferably 0.15 μm or more and 0.8 μm or less.

[0037] Here, the determination that T1 < T2 and the calculation of the arithmetic mean roughness Ra of the mounting surface side intersection portion 111 are performed using a laser microscope. That is, the unevenness of the mounting surface 11 of the multilayer ceramic capacitor 100 is measured with a laser microscope, and it is determined that T1 < T2 when the average value of the height of the mounting surface side intersection portion 111 becomes smaller than the average value of the height of the mounting surface side non-intersection portion 112. Further, the arithmetic mean roughness Ra of the mounting surface side intersection portion 111 is obtained by analyzing the measurement result of the unevenness in the mounting surface side intersection portion 111 with the software attached to the laser microscope.

[0038] Also, T1, T2, Tb1, and Tp1 are calculated by the following procedures respectively. First, in the measurement using the above-described laser microscope, the multilayer ceramic capacitor 100 determined to have T1 < T2 is cut at two locations: one in either the first direction or the second direction in which the terminal electrodes 40 (40a, 40b) are arranged, and in a direction parallel to the T direction and passing near the center of gravity of the terminal electrodes 40 (40a, 40b) when viewed from a direction perpendicular to the mounting surface 11, and a plane parallel to this plane and passing near the center of gravity of the mounting surface side intersection portion 111, thereby exposing a cross section including the terminal electrodes 40 (40a, 40b) and a cross section including the mounting surface side intersection portion 111 respectively. Here, the vicinity of the center of gravity means a region within a distance of w / 6 from the center of gravity, where w is the dimension in the direction perpendicular to each cutting plane in the terminal electrodes 40 (40a, 40b) or the mounting surface side intersection portion 111. Basically, the cutting direction can be arbitrarily selected as either the first direction or the second direction. However, when n = 1, that is, the number of terminal electrodes 40 (40a, 40b) arranged in the second direction is 1 and the distance between the terminal electrodes 40 (40a, 40b) and the periphery of the mounting surface 11 is close, the second direction is selected so as to easily expose the cross section including the mounting surface side intersection portion 111. Next, a conductive substance such as carbon is vapor-deposited on each of the exposed cross sections, and each cross section is observed with a scanning electron microscope (SEM). Next, in the SEM image of the cross section including the mounting surface side intersection portion 111, five arbitrary points located in the mounting surface side intersection portion 111 are selected, and the distances from each of these points to the opposing surface 12 are measured respectively, and the average value is calculated. Then, the value obtained by dividing the calculated average value by the observation magnification of the SEM is taken as T1. Next, in the SEM image of the cross section including the mounting surface side intersection portion 111, five arbitrary points located in the mounting surface side non-intersection portion 112 are selected, and the distances from each of these points to the opposing surface 12 are measured respectively, and the average value is calculated. Then, the value obtained by dividing the calculated average value by the observation magnification of the SEM is taken as T2. Next, in the SEM image of the cross section including the terminal electrodes 40 (40a, 40b), five arbitrary points located at the boundary between the base conductor 41 and the element body 10 are selected, and the distances from each of these points to the opposing surface 12 are measured respectively, and the average value is calculated. Then, the value obtained by dividing the calculated average value by the observation magnification of the SEM is taken as Tb1.Next, in the SEM image of the cross section including the terminal electrode 40 (40a, 40b), five arbitrary points located at the boundary between the plated conductor 42 and the element body 10 are selected, the distance from each point to the opposing surface 12 is measured, and the average value is calculated. The calculated average value is then divided by the observation magnification of the SEM, and the value Tp1 is defined.

[0039] <Second embodiment> Another embodiment (the second embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention has terminal electrodes disposed on the opposing surface facing the mounting surface of the body. An example of the multilayer ceramic capacitor 200 according to the second embodiment is shown in FIG. 5. In the multilayer ceramic capacitor 200, p terminal electrodes 40 are arranged in a lattice pattern in the third direction (L direction) on the opposing surface 12, and q terminal electrodes 40 are arranged in the fourth direction (W direction) orthogonal to the third direction (where p is a natural number of 2 or more and q is a natural number). In the region where the terminal electrodes 40 are not arranged, there are an opposing surface side intersection portion 121 and an opposing surface side non-intersection portion 122 having a higher height than this. The opposing surface side intersection portion 121 is a third straight line that extends on the opposing surface 12 without touching any of the terminal electrodes 40 in the third direction (L direction), which is one of the arrangement directions of the terminal electrodes 40, and a fourth straight line that extends on the opposing surface 12 without touching any of the terminal electrodes 40 in the fourth direction (W direction), which is the other arrangement direction of the terminal electrodes 40 (a direction orthogonal to the third direction). When the third straight line and the fourth straight line are each drawn on the opposing surface 12, it is a portion where an intersection of the third straight line and the fourth straight line is formed. On the other hand, the opposing surface side non-intersection portion 122 is a portion where an intersection of the third straight line and the fourth straight line is not formed. The positional relationship between the opposing surface side opposing portion 121 and the opposing surface side non-opposing portion 122, as well as the third straight line and the fourth straight line, can be described by replacing the mounting surface side opposing portion 111 with the opposing surface side opposing portion 121, the mounting surface side non-opposing portion 112 with the opposing surface side non-opposing portion 122, the first straight line l1 with the third straight line, and the second straight line l2 with the fourth straight line in FIG. 3. Further, that the height of the opposing surface side non-intersection portion 122 is higher than that of the opposing surface side intersection portion 121 means that when the dimension of the body 10 in the T direction measured with reference to the opposing surface side intersection portion 111 is T3 and the dimension of the body 10 in the T direction measured with reference to the opposing surface side non-intersection portion 122 is T4, T3 < T4 is satisfied. Note that the multilayer ceramic capacitor 200 has p = 2 and q = 1, but the number of terminal electrodes arranged on the opposing surface in the multilayer ceramic capacitor according to the second embodiment is not limited to this.The multilayer ceramic capacitor 200 has irregularities on the opposing surface 12 side due to the convex portions formed by the terminal electrodes 40 and the concave portions present at the opposing surface intersection portion 121. Therefore, it has the advantage of reducing the contact area with other members and elements and suppressing the amount of static electricity generated during handling.

[0040] For the aforementioned T3 and T4, for the same reasons as the aforementioned T1 and T2, it is preferably 0.1 μm ≤ (T4 - T3) ≤ 10 μm, more preferably 0.3 μm ≤ (T4 - T3) ≤ 9 μm, and even more preferably 0.5 μm ≤ (T4 - T3) ≤ 8 μm.

[0041] When the terminal electrode 40 disposed on the opposing surface 12 of the multilayer ceramic capacitor 200 has a base conductor 41 and a plated conductor 42, when the dimension of the element body 10 in the T direction measured based on the region where the base conductor 41 is disposed on the opposing surface 12 is defined as Tb2, and the dimension of the element body 10 in the T direction measured based on the region in contact with the plated conductor 42 on the opposing surface 12 is defined as Tp2, for the same reasons as the aforementioned Tb1 and Tp1, it is preferable to satisfy T4 ≤ Tp2 < Tb2.

[0042] The arithmetic mean roughness Ra of the opposing surface side intersection portion 121 is preferably 0.05 μm or more and 1 μm or less. When Ra is 0.05 μm or more, the amount of static electricity generated when handling the multilayer ceramic capacitor 100 can be effectively suppressed. From this point, Ra is more preferably 0.1 μm or more, and even more preferably 0.15 μm or more. On the other hand, when Ra is 1 μm or less, the thickness of the cover portion 31 or the margin portion 32 can be ensured without increasing the dimension of the multilayer ceramic capacitor 100 in the T direction, and the intrusion of deterioration factors such as moisture into the laminate 20 can be effectively suppressed. From this point, Ra is more preferably 0.9 μm or less, and even more preferably 0.8 μm or less. From the above, Ra is more preferably 0.1 μm or more and 0.9 μm or less, and even more preferably 0.15 μm or more and 0.8 μm or less.

[0043] Here, the determination that T3 < T4 and the calculation of the arithmetic mean roughness Ra of the opposing surface side intersection portion 121 are each performed by applying the procedures for the determination that T1 < T2 and the calculation of the arithmetic mean roughness Ra of the mounting surface side intersection portion 111 described above to the opposing surface 12. Further, the calculations of T3, T4, Tb2, and Tp2 are performed by replacing the mounting surface 11 with the opposing surface 12 and implementing the procedures for the calculations of T1, T2, Tb1, and Tp1 described above.

[0044] <Third Embodiment> Another embodiment (third embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention has internal electrodes electrically connected to each other by external conductors. An example of the multilayer ceramic capacitor 300 according to the third embodiment is shown in FIG. 6. In the multilayer ceramic capacitor 300, internal electrodes 22 (22a, 22b) drawn out to the lead-out surface 13 of the element body 10 are electrically connected to each other by external conductors 50 (50a, 50b), and the external conductors 50 (50a, 50b) are electrically connected to terminal electrodes 40 (40a, 40b) disposed on the mounting surface 11. Note that, although the external conductors 50 (50a, 50b) of the multilayer ceramic capacitor 300 are formed on a pair of end faces facing each other, the multilayer ceramic capacitor according to the third embodiment may have external conductors formed only on one end face, or may be formed on the lead-out surface 13 without extending onto the opposing surface 12.

[0045] <Fourth Embodiment> In another embodiment (fourth embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the number m of terminal electrodes arranged in the first direction on the mounting surface and the number n of terminal electrodes arranged in the second direction are both 2 or more. Therefore, the total number of terminal electrodes arranged on the mounting surface is 4 or more. An example of a multilayer ceramic capacitor 400 according to the fourth embodiment is shown in FIG. 7. Note that the multilayer ceramic capacitor 400 has four terminal electrodes 40 arranged on the mounting surface 11, but the number of terminal electrodes arranged on the mounting surface is not limited to this. The multilayer ceramic capacitor 400 has the advantage of reducing resistance heat generation because it can suppress the amount of current flowing through the via conductors 23 (23a, 23b) electrically connected to each terminal electrode 40 (40a, 40b). In addition, when the polarities of the terminal electrodes 40 (40a, 40b) closest to each other on the mounting surface are different, the directions of the currents flowing through the via conductors 23 (23a, 23b) electrically connected to each terminal electrode 40 (40a, 40b) are opposite to each other in the closest via conductors 23 (23a, 23b), which results in the magnetic fields generated by the currents canceling each other out, thereby reducing the equivalent series inductance (ESL). The aforementioned ESL reduction effect is remarkable when the multilayer ceramic capacitor 400 has two pairs of opposing surfaces parallel to the stacking direction of the laminate, with the distance between one pair, i.e., the L-direction dimension, being L μm and the distance between the other pair, i.e., the W-direction dimension, being W μm (where L≧W), where W / L, the ratio of W to L, is 0.8 to 1, i.e., when the mounting surface 11 has a shape close to a square.

[0046] [Manufacturing method for multilayer ceramic electronic components] The multilayer ceramic capacitor according to the first aspect of the present invention can be manufactured by the procedure described below.

[0047] (A) Preparation of ceramic powder First, ceramic powder is prepared. Commercially available ceramic powders can be used as appropriate. When producing ceramic powder in-house, various raw material powders containing the constituent elements are mixed in a predetermined ratio and pre-fired (calcined). When mixing the various raw material powders in a predetermined ratio, various additives such as the above-mentioned additive elements and sintering aids may be further added, or these various additives may be further added to the powder after calcination.

[0048] (B) Preparation of raw sheets Next, the ceramic powder is mixed with a binder and a dispersion medium to prepare a slurry, and the slurry is formed into a sheet to obtain a green sheet.

[0049] The binder used should be one that can maintain the shape of the green sheet and volatilizes without leaving behind carbon or other residues during the binder removal process prior to firing. Examples of binders that can be used include polyvinyl alcohol, polyvinyl butyral, cellulose, urethane, and vinyl acetate. There are no particular restrictions on the amount of binder used, but since it will be removed in a later process, it is preferable to use as little as possible within the range that achieves the desired formability and shape retention, in order to reduce raw material costs.

[0050] The dispersion medium used is one that does not cause aggregation of the calcined powder and binder and can be easily removed by volatilization or the like after forming into a green sheet, as described below. Examples of the dispersion medium that can be used include water and alcohol-based solvents.

[0051] Components for adjusting the properties of the slurry, such as dispersants, plasticizers, and thickeners, may be added to the slurry.

[0052] The method for mixing the mixed powder with the binder and the dispersion medium is not particularly limited as long as the components are mixed uniformly while preventing the inclusion of impurities. One example is ball mill mixing.

[0053] The prepared slurry can be formed into a sheet to obtain a green sheet by a commonly used method such as a doctor blade method or a die coating method.

[0054] ((C) Formation of internal electrode pattern) Next, an internal electrode pattern containing metal is formed on the green sheet. The internal electrode pattern can be formed by printing or applying an internal electrode paste in a predetermined pattern, or by forming a metal film in a predetermined pattern by vapor deposition or sputtering. The internal electrode pattern is formed with a sufficient margin to ensure electrical insulation with the via conductor patterns that will be formed later and that will not come into contact with the via conductor patterns.

[0055] When forming an internal electrode pattern using an internal electrode paste, the internal electrode paste used is obtained by mixing metal particles and a vehicle in a triple roll mill. The internal electrode paste may contain glass frit and ceramic powder in addition to the above-mentioned components.

[0056] The type and amount of binder and solvent contained in the vehicle used are not limited, and may be selected appropriately taking into consideration the viscosity of the internal electrode paste, ease of handling, compatibility with the green sheet, and the like.

[0057] The internal electrode paste can be printed on the green sheet using, for example, a screen mask on which a predetermined internal electrode pattern is formed. When printing, a space may be left to become a margin when the multilayer ceramic capacitor is completed.

[0058] (D) Preparation of green laminate Next, a predetermined number of green sheets on which the internal electrode patterns have been formed are stacked and the green sheets are pressure-bonded together to obtain a green laminate. The stacking and pressure-bonding can be performed by a conventional method, such as pressing the stacked green sheets together in the stacking direction while heating them, and thermocompression bonding using the action of a binder. At this time, a mold with convex portions on its surface may be pressed against the green sheets to form concave portions in the areas that will become the intersections on the mounting surface.

[0059] During lamination and compression bonding, a green sheet that will become a cover when the multilayer ceramic capacitor is completed may be added to the end portion in the lamination direction. In this case, the green sheet to be added may have the same composition as the green sheet on which the internal electrode pattern is printed, or a different composition. From the viewpoint of making the shrinkage rate during firing uniform, it is preferable that the composition of the green sheet to be added is the same as or similar to the green sheet on which the above-mentioned internal electrode precursor is arranged.

[0060] ((E) Formation of via conductor pattern) When manufacturing the multilayer ceramic capacitor according to the first embodiment, holes are then formed in the green laminate and filled with a conductive paste to form a via conductor pattern. Conventional methods such as drilling or lasers can be used to form the holes. Lasers are preferred because they can produce smooth surfaces. Conventional methods such as syringe injection and metal mask printing can be used to fill the holes with the conductive paste. Metal mask printing is preferred because it is superior in filling small holes. The components of the conductive paste can be the same as those of the internal electrode paste described above, and the amounts of each component can be determined taking into account the hole filling ability.

[0061] ((F) Formation of terminal electrode pattern) Next, a terminal electrode pattern is formed on at least one of the surfaces (mounting surface) perpendicular to the lamination direction of the green laminate. A green sheet, which will serve as a cover when the laminate is completed, may be crimped onto the surface on which the terminal electrode pattern is not formed, covering the via conductor pattern. The terminal electrode pattern can be formed by printing or applying a terminal electrode paste, or by forming a metal film by vapor deposition or sputtering. The terminal electrode pattern can be formed using a mask with a predetermined pattern. Alternatively, the terminal electrode pattern can be formed by first forming a paste film or metal film on the entire mounting surface of the green laminate and then removing the portions other than the terminal electrode pattern. Face milling, barrel polishing, etc. can be used to remove the portions other than the terminal electrode pattern. By also removing a portion of the surface of the green laminate when removing the portions other than the terminal electrode pattern, recesses can be formed at positions corresponding to the intersections on the mounting surface. When using a terminal electrode paste to form the terminal electrode pattern, the components can be the same as those of the internal electrode paste described above. The blending amounts of each component can be determined to obtain a uniform pattern with a predetermined thickness.

[0062] (G) Preparation of pre-fired chips Next, the green laminate is divided into individual pieces to obtain pre-fired chips. For the division, a commonly used means such as a dicing saw or a laser cutting machine can be used. After dividing the green laminate into individual pieces to form surfaces on which the internal electrode precursors are exposed, the surfaces may be coated with a material for forming margins to obtain pre-fired chips.

[0063] (H) Removal of binder Next, the resulting pre-fired chips are heated to volatilize and remove the binder. The heating conditions can be set appropriately taking into account the volatilization temperature and content of the binder. For example, the chips are held in a nitrogen (N2) atmosphere at a temperature of 200 to 500°C for 5 to 20 hours.

[0064] (I) Firing of pre-fired chips Next, the pre-fired chip from which the binder has been removed is heated to a predetermined temperature and fired. When setting the firing conditions, it is preferable to consider the sinterability of the ceramic powder, as well as the heat resistance and oxidation resistance of the metals contained in the internal electrode pattern, via conductor pattern, and terminal electrode pattern. An example of firing conditions is holding the chip at a temperature of 1100°C to 1400°C for 10 minutes to 2 hours in a reducing atmosphere containing a mixture of nitrogen (N2), hydrogen (H2), and water vapor (H2O). After firing, a reoxidation treatment may be performed in which the chip is held at 600°C to 1000°C in a nitrogen (N2) gas atmosphere or a low-oxygen atmosphere.

[0065] ((J) Formation of outer conductor and terminal electrode) When manufacturing the multilayer ceramic capacitor according to the second embodiment, the external conductor is formed following the step (I) without performing the step (E), or the external conductor and terminal electrodes are formed following the step (I) without performing the steps (E) and (F). Examples of methods for forming the external conductor and terminal electrodes include a method in which a conductive paste is applied by printing or dipping and then baked, and a method in which a metal film is formed by physical vapor deposition (PVD) such as evaporation.

[0066] The sintered body thus obtained may be used as a multilayer ceramic capacitor as it is, or may be used as a multilayer ceramic capacitor after forming a conductive layer on the surface of the terminal electrode pattern by plating.

[0067] [Circuit board] A circuit board according to a second aspect of the present invention is a circuit board having the multilayer ceramic capacitor according to the first aspect mounted thereon, and since the bonding strength of the multilayer ceramic capacitor is improved, this circuit board has excellent durability.

[0068] This specification also discloses the following techniques.

[0069] (Appendix 1) a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a pair of cover portions disposed at both ends of the laminate in the stacking direction and covering the surface of the laminate; and a margin portion that covers at least a portion of the ends of the ceramic layers and the ends of the internal electrodes in the laminate and connects the pair of cover portions to each other; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes arranged apart from one another on a mounting surface that faces a circuit board when mounted on the circuit board, among the surfaces that form the surface of the element body, and electrically connected to the internal electrodes; Equipped with the plurality of terminal electrodes are arranged in groups of m in a first direction on the mounting surface and in groups of n in a second direction perpendicular to the first direction (where m is a natural number equal to or greater than 2, and n is a natural number); The area of ​​the mounting surface where the terminal electrodes are not arranged is a mounting surface side intersection portion where an intersection point between a first straight line extending in the first direction without touching any of the terminal electrodes and a second straight line extending in the second direction without touching any of the terminal electrodes is formed; and a mounting surface-side non-intersecting portion where no intersection is formed between the first straight line and the second straight line; and When the dimension of the element body in the stacking direction of the laminate measured with the mounting surface side intersection portion as a reference is T1 and the dimension of the laminate in the stacking direction of the element body measured with the mounting surface side non-intersection portion as a reference is T2, T1 <T2 Multilayer ceramic capacitors meet these requirements.

[0070] (Appendix 2) The T1 and the T2 0.1μm≦(T2-T1)≦10μm The multilayer ceramic capacitor according to (Appendix 1) satisfies the above.

[0071] (Appendix 3) the terminal electrode has an underlying conductor in contact with the element body and a plated conductor formed on the surface of the underlying conductor, When the dimension of the element body in the stacking direction of the laminate measured using the region of the mounting surface where the base conductor is arranged as a reference is defined as Tb1, and the dimension of the laminate in the stacking direction of the laminate measured using the region of the mounting surface that contacts the plated conductor as a reference is defined as Tp1, T2≦Tp1 <Tb1 The multilayer ceramic capacitor according to (Appendix 1) or (Appendix 2), which satisfies the above.

[0072] (Appendix 4) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 3), wherein the arithmetic mean roughness Ra of the intersection on the mounting surface side is 0.05 μm or more and 1 μm or less.

[0073] (Appendix 5) a plurality of terminal electrodes arranged in a grid pattern on a surface of the element body facing the mounting surface and electrically connected to the internal electrodes; On the opposing surface, the plurality of terminal electrodes are arranged in a p-numbered array in a third direction on the opposing surface and in a q-numbered array in a fourth direction perpendicular to the third direction (where p is a natural number equal to or greater than 2, and q is a natural number); The area of ​​the opposing surface where the terminal electrodes are not arranged is an opposing surface side intersection portion where an intersection point of the third straight line and the fourth straight line is formed when a third straight line extending in the third direction without touching any of the terminal electrodes and a fourth straight line extending in the fourth direction without touching any of the terminal electrodes are respectively drawn; and an opposing surface-side non-intersecting portion where no intersection is formed between the third straight line and the fourth straight line; and When the dimension of the element body in the stacking direction of the laminate measured with the opposing surface side intersection portion as a reference is T3 and the dimension of the element body in the stacking direction of the laminate measured with the opposing surface side non-intersecting portion as a reference is T4, T3 <T4 fulfill A multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 4).

[0074] (Appendix 6) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 5), wherein n is a natural number of 2 or more.

[0075] (Appendix 7) The multilayer ceramic capacitor according to (Appendix 6), wherein each of the terminal electrodes has a polarity different from that of another terminal electrode that is closest to the terminal electrode on the mounting surface.

[0076] (Appendix 8) A circuit board on which the multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 7) is mounted. [Industrial Applicability]

[0077] According to the present invention, it is possible to provide a multilayer ceramic capacitor having improved bonding strength with a circuit board, and a circuit board on which the multilayer ceramic capacitor is mounted. Therefore, the present invention is useful in that it can provide a circuit board with excellent durability. [Explanation of symbols]

[0078] 100, 200, 300, 400 Multilayer ceramic capacitors 10 Base 11 Mounting surface 111 Mounting surface side intersection 112 Non-intersecting part on mounting surface 12 Opposite surface 121 Opposite side intersection 122 Opposite surface non-intersecting portion 13 Drawer surface 20 laminate 21 ceramic layer 22(22a, 22b) Internal electrode 23(23a, 23b) Via conductor 31 Cover 32 Margin 40(40a, 40b) terminal electrode 41 Undercoat conductor 42 Plated conductor 50(50a, 50b) Outer conductor

Claims

1. a laminate in which ceramic layers formed of ceramic and internal electrodes mainly composed of metal are alternately stacked; a pair of cover portions disposed at both ends of the laminate in the stacking direction and covering the surface of the laminate; and a margin portion that covers at least a portion of the ends of the ceramic layers and the ends of the internal electrodes in the laminate and connects the pair of cover portions to each other; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes arranged apart from one another on a mounting surface that faces a circuit board when mounted on the circuit board, among the surfaces that form the surface of the element body, and electrically connected to the internal electrodes; Equipped with the plurality of terminal electrodes are arranged in groups of m in a first direction on the mounting surface and in groups of n in a second direction perpendicular to the first direction (where m is a natural number of 2 or more, and n is a natural number); The area of ​​the mounting surface where the terminal electrodes are not arranged is a mounting surface-side intersection portion where an intersection point between a first straight line extending in the first direction without touching any of the terminal electrodes and a second straight line extending in the second direction without touching any of the terminal electrodes is formed; and a mounting surface-side non-intersecting portion where no intersection is formed between the first straight line and the second straight line; and When the dimension of the element body in the stacking direction of the laminate measured with the mounting surface side intersection portion as a reference is T1 and the dimension of the laminate in the stacking direction of the element body measured with the mounting surface side non-intersection portion as a reference is T2, T1<T2 Multilayer ceramic capacitors meet these requirements.

2. The T1 and the T2 0.1μm≦(T2-T1)≦10μm The multilayer ceramic capacitor according to claim 1 , which satisfies the above.

3. the terminal electrode has an underlying conductor in contact with the element body and a plated conductor formed on the surface of the underlying conductor, When the dimension of the element body in the stacking direction of the laminate measured using the region of the mounting surface where the base conductor is arranged as a reference is defined as Tb1, and the dimension of the laminate in the stacking direction of the element body measured using the region of the mounting surface that contacts the plated conductor as a reference is defined as Tp1, T2≦Tp1<Tb1 The multilayer ceramic capacitor according to claim 1 , which satisfies the above.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the arithmetic mean roughness Ra of the intersections on the mounting surface side is 0.01 μm or more and 1 μm or less.

5. a plurality of terminal electrodes arranged in a grid pattern on a surface of the element body facing the mounting surface and electrically connected to the internal electrodes; On the opposing surface, the plurality of terminal electrodes are arranged in a p-number of rows in a third direction on the opposing surface and in a q-number of rows in a fourth direction perpendicular to the third direction (where p is a natural number of 2 or more, and q is a natural number); The area of ​​the opposing surface where the terminal electrodes are not arranged is an opposing surface side intersection portion where an intersection point of the third straight line and the fourth straight line is formed when a third straight line extending in the third direction without touching any of the terminal electrodes and a fourth straight line extending in the fourth direction without touching any of the terminal electrodes are respectively drawn; and an opposing surface-side non-intersecting portion where no intersection is formed between the third straight line and the fourth straight line; and When the dimension of the element body in the stacking direction of the laminate measured with the opposing surface side intersection portion as a reference is T3 and the dimension of the element body in the stacking direction of the laminate measured with the opposing surface side non-intersecting portion as a reference is T4, T3 < T4 fulfill The multilayer ceramic capacitor according to claim 1 .

6. 2. The multilayer ceramic capacitor according to claim 1, wherein n is a natural number of 2 or more.

7. 7. The multilayer ceramic capacitor according to claim 6, wherein each of said terminal electrodes has a polarity different from that of the other terminal electrode closest to said terminal electrode on said mounting surface.

8. A circuit board having the multilayer ceramic capacitor according to any one of claims 1 to 7 mounted thereon.

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