Switching circuit

Abstract

To provide a switching circuit capable of detecting an open failure of a plurality of switching elements connected in parallel.SOLUTION: A switching circuit includes a drive circuit, a delay circuit, and a controller. The drive circuit includes a plurality of switching elements connected in parallel, each of which is switched between conduction and interruption by a drive signal. The delay circuit is connected to an input terminal of a drive signal in the switching element, and delays a switching timing of the switching element. The controller disables the delay circuit of the switching element to be inspected, enables the delay circuits of the remaining switching elements, and detects an open failure of the switching element to be inspected according to the time from the input of the drive signal to the conduction of the drive circuit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The disclosed embodiments relate to a switching circuit. [Background technology]

[0002] Inverters and DC-DC converters include switching circuits including switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) (see, for example, Patent Document 1).

[0003] When a large current needs to be passed through a switching circuit, the circuit is configured, for example, by connecting multiple MOSFETs in parallel, which are driven by the same gate signal.

[0004] In a switching circuit, if one of the multiple switching elements connected in parallel experiences an open circuit fault, an overcurrent exceeding the rated current may flow through the normal switching elements. For this reason, it is desirable for the switching circuit to detect the open circuit fault before driving, for example. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-72503 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in a switching circuit, even if an open circuit fault occurs in one switching element, the current value of the output current does not change, making it difficult to detect the open circuit fault.

[0007] One aspect of the embodiment has been made in view of the above, and aims to provide a switching circuit that can detect open circuit failures in multiple switching elements connected in parallel. [Means for solving the problem]

[0008] According to one aspect of the embodiment, a switching circuit includes a drive circuit, a delay circuit, and a controller. The drive circuit includes a plurality of switching elements connected in parallel, each of which is switched between conductive and non-conductive states by a drive signal. The delay circuit is connected to an input terminal of the drive signal for the switching elements and delays the switching timing of the switching elements. The controller disables the delay circuit of a switching element under test and enables the delay circuits of the remaining switching elements, and detects an open circuit failure of the switching element under test based on the time from input of the drive signal to when the drive circuit becomes conductive. [Effects of the Invention]

[0009] In one embodiment, a switching circuit disables the delay circuit of a switching element under test and enables the delay circuits of the remaining switching elements. When a drive signal is input to the drive circuit in this state, if all switching elements are normal, the switching element under test immediately becomes conductive, and the remaining switching elements become conductive with a delay from the switching element under test. Therefore, the time from input of the drive signal to the drive circuit becoming conductive is the shortest time that depends on the switching timing of the switching element under test.

[0010] On the other hand, if the switching element under test has an open circuit fault and the remaining switching elements are normal, the switching element under test will not be turned on, and the remaining switching elements will be turned on at a timing delayed by the delay circuit. As a result, the time from input of the drive signal until the drive circuit is turned on will be longer than when the switching element under test is normal.

[0011] Therefore, the switching circuit can detect an open circuit failure of the switching element being inspected based on the length of time from when the drive signal is input until the drive circuit becomes conductive. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is an explanatory diagram showing the configuration of a general switch circuit. [Figure 2] FIG. 2 is an explanatory diagram showing the configuration of a general switch circuit. [Figure 3] FIG. 3 is an explanatory diagram showing a state when an open circuit failure occurs in a general switch circuit. [Figure 4] FIG. 4 is an explanatory diagram illustrating an example of the configuration of a switching circuit according to the embodiment. [Figure 5] FIG. 5 is an explanatory diagram showing an example of an operation of detecting an open circuit failure by the controller according to the embodiment. [Figure 6] FIG. 6 is an explanatory diagram showing an example of an operation of detecting an open circuit failure by the controller according to the embodiment. [Figure 7] FIG. 7 is a flowchart illustrating an example of processing executed by the controller according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of a switching circuit will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below.

[0014] ≪1. General switch circuit≫ First, the configuration of a general switch circuit provided in an inverter, a DC-DC converter, etc. will be described with reference to Figures 1 and 2. Figures 1 and 2 are explanatory diagrams showing the configuration of a general switch circuit. In the following, a case will be described in which the switching element included in the switch circuit is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but the switching element may also be an IGBT (Insulated Gate Bipolar Transistor).

[0015] 2. Typical switch circuit configuration A switching circuit with the simplest configuration includes a drive circuit 101 shown in Fig. 1. The drive circuit 101 includes a high-side MOSFET (hereinafter referred to as "HMOS") 10 and a low-side MOSFET (hereinafter referred to as "LMOS") 20 connected in series between a power supply VCC and ground.

[0016] The drain of the HMOS 10 is connected to the power supply VCC, and the source is connected to the drain of the LMOS 20. The source of the LMOS 20 is connected to ground. A connection point A between the HMOS 10 and the LMOS 20 is connected to the output terminal OUT of the drive circuit 101.

[0017] A square wave (pulse wave) drive signal is input to the gates of HMOS 10 and LMOS 20. HMOS 10 and LMOS 20 change from a cutoff state to a conductive state when the signal level of the drive signal changes from low to high. Also, HMOS 10 and LMOS 20 change from a conductive state to a cutoff state when the signal level of the drive signal changes from high to low.

[0018] In the following, the term "ON" may be used to refer to switching a MOSFET from a cutoff state to a conductive state. The term "OFF" may be used to refer to switching a MOSFET from a conductive state to a cutoff state. The gate of LMOS 20 receives an inverted signal of the drive signal input to the gate of HMOS 10. In other words, HMOS 10 and LMOS 20 are alternately turned ON.

[0019] A controller (not shown) that controls the drive circuit 101 controls the voltage output from the output terminal OUT by controlling the duty ratio of the drive signal input to the gate of the HMOS 10 using PWM (Pulse Width Modulation).

[0020] Furthermore, when the controller outputs a current of 100 A from the output terminal OUT, for example, it inputs a high-level drive signal to the gate of HMOS10 and a low-level drive signal to the gate of LMOS20. This turns HMOS10 ON and LMOS20 OFF. At this time, a current of 100 A flows from the power supply VCC to HMOS10, and a current of 100 A is output from the output terminal OUT.

[0021] When the rated current of HMOS10 and LMOS20 shown in Fig. 1 is 100 A, the switching circuit shown in Fig. 1 cannot output a current exceeding 100 A. For this reason, for example, when it is necessary to output a current of 300 A using HMOS10 and LMOS20 shown in Fig. 1, a switching circuit including a drive circuit 102 shown in Fig. 2 may be adopted.

[0022] The driver circuit 102 shown in FIG. 2 includes a first HMOS 11, a second HMOS 12, and a third HMOS 13 connected in parallel, and a first LMOS 21, a second LMOS 22, and a third LMOS 23 connected in parallel.

[0023] The drains of the first HMOS 11, the second HMOS 12, and the third HMOS 13 are connected to the power supply VCC. The sources of the first HMOS 11, the second HMOS 12, and the third HMOS 13 are connected to the drains of the first LMOS 21, the second LMOS 22, and the third LMOS 23 and the output terminal OUT. The sources of the first LMOS 21, the second LMOS 22, and the third LMOS 23 are connected to ground.

[0024] The same drive signal is input to the gates of the first HMOS 11, the second HMOS 12, and the third HMOS 13. The same drive signal is input to the gates of the first LMOS 21, the second LMOS 22, and the third LMOS 23.

[0025] The gates of the first LMOS 21, the second LMOS 22, and the third LMOS 23 receive inverted signals of the drive signals input to the gates of the first HMOS 11, the second HMOS 12, and the third HMOS 13.

[0026] When a controller (not shown) that controls the drive circuit 102 outputs a current of 300 A from the output terminal OUT, the controller inputs a high-level drive signal to the gates of the first HMOS 11, the second HMOS 12, and the third HMOS 13. At the same time, the controller inputs a low-level drive signal to the gates of the first LMOS 21, the second LMOS 22, and the third LMOS 23.

[0027] As a result, the first HMOS 11, the second HMOS 12, and the third HMOS 13 are turned ON, and the first LMOS 21, the second LMOS 22, and the third LMOS 23 are turned OFF. At this time, a current of 100 A flows from the power supply VCC to each of the first HMOS 11, the second HMOS 12, and the third HMOS 13, and a current of 300 A is output from the output terminal OUT.

[0028] ≪3. Condition when open fault occurs≫ Next, a state when an open circuit failure occurs in the switching element of the drive circuit 102 shown in Fig. 2 will be described with reference to Fig. 3. Fig. 3 is an explanatory diagram showing a state when an open circuit failure occurs in a general switch circuit.

[0029] 3, there is a case where an open circuit fault occurs in the first HMOS 11 of the drive circuit 102. In this case, when a high-level drive signal is input to the first to third HMOSs 11 to 13 and a low-level drive signal is input to the first to third LMOSs 21 to 23, the drive circuit 102 outputs a current of 300 A from the output terminal OUT, just as in the normal state.

[0030] However, in the drive circuit 102, because the first HMOS 11 has an open fault, no current flows through the first HMOS 11, and a current of 150 A flows through the second HMOS 12 and the third HMOS 13. In this case, if the rated current of the second HMOS 12 and the third HMOS 13 is 100 A, there is a risk of damage if a current of 150 A flows through them.

[0031] Therefore, a controller (not shown) that controls the drive circuit 102 needs to detect open circuit failures in the first to third HMOSs 11 to 13 and the first to third LMOSs 21 to 23, for example, before starting control.

[0032] However, even if the first HMOS 11 has an open circuit fault, the drive circuit 102 outputs a current of 300 A in the same way as when there is no open circuit fault, so the controller cannot detect the open circuit fault of the first HMOS 11 from the output current.

[0033] Therefore, the switching circuit according to the embodiment has a configuration capable of detecting an open circuit failure of a switching element included in a drive circuit. The configuration and operation of the switching circuit according to the embodiment will be specifically described below.

[0034] 4. Configuration Example of Switching Circuit According to Embodiment Fig. 4 is an explanatory diagram showing an example of the configuration of a switching circuit 1 according to an embodiment. Note that, among the components shown in Fig. 4, the components shown in Fig. 2 and Fig. 3 are denoted by the same reference numerals as those shown in Fig. 2 and Fig. 3, and some of the overlapping descriptions will be omitted. Also, Fig. 4 shows a configuration in which three switch circuits, each including an HMOS and an LMOS connected in series, are connected in parallel as the drive circuit 2, but the number of switch circuits connected in parallel is not limited to three.

[0035] As shown in Fig. 4, the switching circuit 1 according to the embodiment includes a drive circuit 2 and a controller 3. The controller 3 includes a microcomputer having a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc., and various other circuits. The controller 3 controls the operation of the drive circuit 2 by having the CPU execute a control program stored in the ROM using the RAM as a working area. The control program may be stored in a storage device from an external source via a communication line, etc.

[0036] Furthermore, the controller 3 enters a test mode before starting to control the drive circuit 2, and detects an open circuit failure in a switching element included in the drive circuit 2. A specific example of the operation of the controller 3 to detect an open circuit failure will be described later with reference to FIGS. 5 and 6.

[0037] The drive circuit 2 includes a circuit in which a plurality of switching elements, which are switched between conductive and non-conductive states by a drive signal, are connected in parallel.

[0038] Specifically, the drive circuit 2 includes a first HMOS 11, a second HMOS 12, a third HMOS 13, a first LMOS 21, a second LMOS 22, and a third LMOS 23. The drive circuit 2 further includes first to sixth delay circuits 31 to 36. The first to sixth delay circuits 31 to 36 are connected to input terminals of drive signals of the switching elements, and delay the switching timing of the switching elements.

[0039] Specifically, the first delay circuit 31 is connected to the gate of the first HMOS 11. The second delay circuit 32 is connected to the gate of the second HMOS 12. The third delay circuit 33 is connected to the gate of the third HMOS 13.

[0040] The fourth delay circuit is connected to the gate of the first LMOS 21. The fifth delay circuit 35 is connected in series to the gate of the second LMOS 22. The sixth delay circuit is connected in series to the gate of the third LMOS .

[0041] The first to sixth delay circuits 31 to 36 each include a capacitor provided at the input terminal of the switching element, and further include a switch connected in series with each capacitor.

[0042] Specifically, the first delay circuit 31 includes a first switch 41 and a first capacitor 51 connected in series between the gate of the first HMOS 11 and the input terminal of the drive circuit 2 for the drive signal for the HMOS. The second delay circuit 32 includes a second switch 42 and a second capacitor 52 connected in series between the gate of the second HMOS 12 and the input terminal of the drive circuit 2 for the drive signal for the HMOS. The third delay circuit 33 includes a third switch 43 and a third capacitor 53 connected in series between the gate of the third HMOS 13 and the input terminal of the drive circuit 2 for the drive signal for the HMOS.

[0043] The fourth delay circuit 34 includes a fourth switch 44 and a fourth capacitor 54 connected in series between the gate of the first LMOS 21 and the input terminal of the drive circuit 2 for the drive signal for the LMOS. The fifth delay circuit 35 includes a fifth switch 45 and a fifth capacitor 55 connected in series between the gate of the second LMOS 22 and the input terminal of the drive circuit 2 for the drive signal for the LMOS. The sixth delay circuit 36 ​​includes a sixth switch 46 and a sixth capacitor 56 connected in series between the gate of the third LMOS 23 and the input terminal of the drive circuit 2 for the drive signal for the LMOS.

[0044] The switching circuit 1 also includes a resistor 62 connected between the output terminal of the drive signal in the controller 3 and the input terminal of the drive signal for the HMOS in the drive circuit 2. The switching circuit 1 also includes a resistor 66 connected between the output terminal of the drive signal in the controller 3 and the input terminal of the drive signal for the LMOS in the drive circuit 2.

[0045] The drive circuit 2 also includes resistors 63 to 65 connected between an input terminal for a drive signal for HMOS and the gates of the first to third HMOSs 11 to 13. The drive circuit 2 also includes resistors 67 to 69 connected between an input terminal for a drive signal for LMOS and the gates of the first to third LMOSs 21 to 23.

[0046] The switching circuit 1 also includes a voltage sensor 5 provided between the drains of the first to third HMOSs 11 to 23 and the first to third LMOSs 21 to 23 and the output terminal OUT. A resistor 60 is connected between the voltage sensor 5 and a power supply VCC. A resistor 61 is connected between the voltage sensor 5 and ground. The voltage sensor 5 detects the voltage output from the output terminal OUT and outputs the detection result to the controller 3.

[0047] In the inspection mode, the controller 3 detects open circuit failures in the first HMOS 11, the second HMOS 12, the third HMOS 13, the first LMOS 21, the second LMOS 22, and the third LMOS 23 based on the voltage at the output terminal OUT detected by the voltage sensor 5.

[0048] When the first to third HMOSs 11 to 13 and the first to third LMOSs 21 to 23 are all OFF, the voltage of the output terminal OUT becomes an intermediate voltage determined by the resistance values ​​of the resistors 60 and 61. When the first to third HMOSs 11 to 13 are all ON and the first to third LMOSs 21 to 23 are all OFF, the voltage of the output terminal OUT becomes the voltage of the power supply VCC.

[0049] The voltage of the output terminal OUT becomes the ground voltage when the first to third HMOSs 11 to 13 are all OFF and the first to third LMOSs 21 to 23 are all ON. Furthermore, when the first to third HMOSs 11 to 13 and the first to third LMOSs 21 to 23 are all ON, the voltage of the output terminal OUT becomes the ground voltage, causing a short circuit between the power supply VCC and ground and a large current to flow. For this reason, the switching circuit 1 prohibits the setting of the first to third HMOSs 11 to 13 and the first to third LMOSs 21 to 23 to all be ON.

[0050] 5. Open fault detection by the controller 5 and 6 are explanatory diagrams showing an example of an operation of detecting an open circuit failure by the controller 3 according to the embodiment. Note that the first to sixth switches shown in Fig. 5 correspond to the first to sixth switches 41 to 46 shown in Fig. 4.

[0051] In the test mode, the controller 3 disables the delay circuit of the switching element to be tested and enables the delay circuits of the remaining switching elements, and detects an open circuit failure of the switching element to be tested based on the time from when the drive signal is input until the drive circuit becomes conductive.

[0052] 5, the controller 3 controls the ON / OFF of the first to sixth switches 41 to 46 depending on which switching element is the switching element being tested. When the switching element being tested is an HMOS, the controller 3 inputs a drive signal to the drive circuit 2 and detects the occurrence of an open circuit fault according to the time (t1 or t2) it takes for the voltage at the output terminal OUT to change from the intermediate voltage to the voltage of the power supply VCC (power supply voltage). When the switching element being tested is an LMOS, the controller 3 inputs a drive signal to the drive circuit 2 and detects the occurrence of an open circuit fault according to the time (t1 or t2) it takes for the voltage at the output terminal OUT to change from the intermediate voltage to the ground voltage (0V).

[0053] For example, when the switching element to be tested is the first HMOS 11, the controller 3 turns off the first switch 41 to disable the first delay circuit 31, as shown in Figures 5 and 6. Furthermore, the controller 3 turns on the second switch 42 and the third switch 43 to enable the second delay circuit 32 and the third delay circuit 33.

[0054] At this time, the controller 3 turns off the fourth to sixth switches 44 to 46 to disable the fourth to sixth delay circuits 34 to 36. Then, the controller 3 inputs a high-level drive signal to the first to third HMOSs 11 to 13. At this time, a low-level drive signal is input to the first to third LMOSs 21 to 23, turning them off.

[0055] If the first to third HMOSs 11 to 13 are all normal, the first HMOS 11 under test immediately becomes conductive. In contrast, the remaining second to third HMOSs 12 to 13 do not become conductive until the second capacitor 52 and the third capacitor 53 are fully charged, and therefore become conductive with a delay after the first HMOS 11 becomes conductive.

[0056] Therefore, as shown in FIG. 5, the time from the input of the drive signal until the drive circuit 2 becomes conductive is the shortest time t1 that depends on the switching timing of the first HMOS 11 under test.

[0057] On the other hand, if the first HMOS 11 to be tested has an open circuit fault and the remaining second to third HMOSs 12 to 13 are normal, the first HMOS 11 will not be conductive. In contrast, the remaining second to third HMOSs 12 to 13 will be conductive at timings delayed by the second and third delay circuits 32 to 33. Therefore, as shown in FIG. 5, the time from input of the drive signal to when the drive circuit 2 is turned on is a longer time t2 than when the first HMOS 11 to be tested is normal.

[0058] Therefore, the controller 3 can detect an open circuit fault in the first HMOS 11 under test based on the length of time between the input of the drive signal and the turn-on of the drive circuit 2. Specifically, if the time between the input of the drive signal and the turn-on of the drive circuit 2 is the shortest time t1, the controller 3 can determine that the first HMOS 11 does not have an open circuit fault. Furthermore, if the time between the input of the drive signal and the turn-on of the drive circuit 2 is a time t2 that is longer than normal, the controller 3 can determine that the first HMOS 11 has an open circuit fault.

[0059] The controller 3 controls the first to sixth switches 41 to 46 as shown in FIG. 5, and can determine whether or not an open circuit failure has occurred in the second to third HMOSs 12 to 13 and the first to third LMOSs 21 to 23 depending on whether the time from the input of the drive signal to the time the drive circuit 2 becomes conductive is t1 or t2.

[0060] Specifically, when the switching element to be inspected is the second HMOS 12, the controller 3 turns on the first switch 41 and the third switch 43 to enable the first delay circuit 31 and the third delay circuit 33, as shown in Fig. 5. Furthermore, the controller 3 turns off the second switch 42 to disable the second delay circuit 32.

[0061] Then, the controller 3 inputs a high-level drive signal to the first to third HMOSs 11 to 13. At this time, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t1, the controller 3 determines that the second HMOS 12 is normal. Furthermore, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t2, the controller 3 determines that the second HMOS 12 has an open circuit failure.

[0062] 5, when the switching element to be inspected is the third HMOS 13, the controller 3 turns on the first switch 41 and the second switch 42 to enable the first delay circuit 31 and the second delay circuit 32. Furthermore, the controller 3 turns off the third switch 43 to disable the third delay circuit 33.

[0063] Then, the controller 3 inputs a high-level drive signal to the first to third HMOSs 11 to 13. At this time, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t1, the controller 3 determines that the third HMOS 13 is normal. Furthermore, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t2, the controller 3 determines that the third HMOS 13 has an open circuit failure.

[0064] 5, when the switching element to be tested is the first LMOS 21, the controller 3 turns off the fourth switch 44 to disable the fourth delay circuit 34. Furthermore, the controller 3 turns on the fifth switch 45 and the sixth switch 46 to enable the fifth delay circuit 35 and the sixth delay circuit 36. At this time, the controller 3 turns off the first to third switches 41 to 43 to disable the first to third delay circuits 31 to 33.

[0065] The controller 3 then inputs a high-level drive signal to the first to third LMOSs 21 to 23. At this time, a low-level drive signal is input to the first to third LMOSs 11 to 13, turning them off. If the time from input of the drive signal until the drive circuit 2 becomes conductive is t1, the controller 3 determines that the first LMOS 21 is normal. If the time from input of the drive signal until the drive circuit 2 becomes conductive is t2, the controller 3 determines that the first LMOS 21 has an open circuit failure.

[0066] 5, when the switching element to be tested is the second LMOS 22, the controller 3 turns on the fourth switch 44 and the sixth switch 46 to enable the fourth delay circuit 34 and the sixth delay circuit 36. Furthermore, the controller 3 turns off the fifth switch 45 to disable the fifth delay circuit 35.

[0067] The controller 3 then inputs a high-level drive signal to the first to third LMOSs 21 to 23. At this time, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t1, the controller 3 determines that the second LMOS 22 is normal. Furthermore, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t2, the controller 3 determines that the second LMOS 22 has an open circuit failure.

[0068] 5, when the switching element to be tested is the third LMOS 23, the controller 3 turns on the fourth switch 44 and the fifth switch 45 to enable the fourth delay circuit 34 and the fifth delay circuit 35. Furthermore, the controller 3 turns off the sixth switch 46 to disable the sixth delay circuit 36.

[0069] The controller 3 then inputs a high-level drive signal to the first to third LMOSs 21 to 23. At this time, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t1, the controller 3 determines that the third LMOS 23 is normal. Furthermore, if the time from input of the drive signal to the drive circuit 2 becoming conductive is t2, the controller 3 determines that the third LMOS 23 has an open circuit failure.

[0070] When the inspection is completed and normal control is to be performed, the controller 3 turns off all of the first switch 41 to the sixth switch 46, and disables all of the first delay circuit 31 to the sixth delay circuit 36.

[0071] As described above, the first to sixth delay circuits 31 to 36 of the switching circuit 1 can delay the timing at which the first HMOSs 12 to 13 and the first to third LMOSs 21 to 23 turn ON from when the drive signal is input until charging of the first to sixth capacitors 51 to 56 is completed. In this way, the first to sixth delay circuits 31 to 36 can delay the switching timing of each switching element with a simple configuration in which a capacitor is connected to the input terminal of the drive signal of each switching element.

[0072] Furthermore, the controller 3 can enable each delay circuit (first to sixth delay circuits 31 to 36) simply by turning on each switch (first to sixth switches 41 to 46). Furthermore, the controller 3 can disable each delay circuit (first to sixth delay circuits 31 to 36) simply by turning off each switch (first to sixth switches 41 to 46). With such a simple configuration, the controller 3 can enable and disable each delay circuit (first to sixth delay circuits 31 to 36).

[0073] 6. Processes executed by the controller Next, a process executed by the controller 3 according to the embodiment will be described with reference to Fig. 7. Fig. 7 is a flowchart showing an example of a process executed by the controller 3 according to the embodiment. When started up, the controller 3 repeatedly executes the process shown in Fig. 7.

[0074] 7, when the controller 3 is started, it determines whether or not it is in the inspection mode (step S101). The controller 3 determines that it is in the inspection mode when it is started, or when it stops operating after being started and then starts operating again.

[0075] If the controller 3 determines that it is not in the test mode (step S101, No), it executes normal control (step S111) and ends this processing. In normal control, the first to sixth switches 41 to 46 are all turned OFF to disable the first to sixth delay circuits 31 to 36. If the controller 3 determines that it is in the test mode (step S101, Yes), it disables the delay circuit of the HMOS to be tested (step S102) and enables the delay circuits of the remaining HMOSs (step S103). At this time, the controller 3 disables the delay circuits of all LMOSs.

[0076] Next, the controller 3 inputs a high level drive signal to all HMOS (step S104). Next, the controller 3 determines whether the voltage convergence time of the output terminal OUT is longer than a threshold value (step S105).

[0077] At this time, the controller 3 measures the time from when the drive signal is input until the drive circuit 2 becomes conductive, based on the change in voltage at the output terminal OUT. This allows the controller 3 to accurately measure the time from when the drive signal is input until the drive circuit 2 becomes conductive.

[0078] Then, the controller 3 determines whether the time from when the drive signal is input to the drive circuit 2 until the drive circuit 2 becomes conductive and the voltage at the output terminal OUT changes from the intermediate potential to the power supply voltage VCC is longer than a threshold (e.g., t2) or less than the threshold (e.g., t1).

[0079] If the controller 3 determines that the voltage convergence time of the output terminal OUT is longer than the threshold value (step S105, Yes), it determines that the HMOS being tested has an open circuit failure (step S106), limits the output current of the drive circuit 2 (step S107), and moves the process to step S109.

[0080] At this time, the controller 3 adjusts the duty ratio of the drive signal so that the current flowing through each HMOS and LMOS does not exceed the rated current, thereby limiting the output current of the drive circuit 2. In this way, the controller 3 can prevent normal switching elements from being damaged when an open circuit fault occurs in some switching elements.

[0081] Note that, in the event of a failure, the controller 3 may not transition to normal control instead of limiting the output current of the drive circuit 2. In this way, when an open circuit failure occurs in any of the switching elements, the controller 3 can prevent an unexpectedly large current from flowing through a normal switching element by transitioning to normal control.

[0082] Furthermore, if the controller 3 determines that the voltage convergence time of the output terminal OUT is not longer than the threshold value, that is, that the voltage convergence time of the output terminal OUT is equal to or shorter than the threshold value (step S105, No), it determines that the HMOS being tested is normal (step S108) and proceeds to step S109.

[0083] In step S109, the controller 3 determines whether or not the testing of all HMOSs has been completed. If the controller 3 determines that the testing of all HMOSs has not been completed (step S109, No), the controller 3 moves the process to step S102, and performs the same testing on the next HMOS in steps S102 to S108.

[0084] In this way, the controller 3 sequentially selects HMOSs to be inspected from a plurality of HMOSs and detects open circuit defects in all HMOSs. This allows the controller 3 to detect open circuit defects in all HMOSs.

[0085] Furthermore, when the controller 3 determines that the inspection of all HMOSs has been completed (step S109, Yes), it executes an open circuit fault inspection of the LMOSs (step S110). In the open circuit fault inspection of the LMOSs, the controller 3 executes a process in which the HMOSs in the processes of steps S102 to S110 are replaced with the LMOSs, and the voltage convergence time of step S105 is replaced with the time it takes for the voltage to converge from the intermediate potential to the ground potential. Then, when the open circuit fault inspection of all LMOSs has been completed, the controller 3 ends this process.

[0086] Further advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described above. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. [Explanation of symbols]

[0087] 1 Switching circuit 2. Drive circuit 3 Controller 5 Voltage Sensor 31-36 1st to 6th delay circuits 41~46 1st~6th switches 51~56 1st~6th capacitors

Claims

1. a drive circuit including a plurality of switching elements connected in parallel, the switching elements being switched between conductive and non-conductive states by a drive signal; a delay circuit connected to an input terminal of the switching element for receiving the drive signal, the delay circuit delaying the switching timing of the switching element; a controller that disables the delay circuit of the switching element to be inspected and enables the delay circuits of the remaining switching elements, and detects an open circuit failure of the switching element to be inspected based on the time from when the drive signal is input until when the drive circuit becomes conductive; A switching circuit comprising:

2. The delay circuit is a capacitor provided at the input terminal of the switching element.

2. The switching circuit of claim 1, comprising:

3. the delay circuit includes a switch connected in series with the capacitor; The controller turns on the switch when the delay circuit is enabled, and turns off the switch when the delay circuit is disabled.

3. The switching circuit of claim 2.

4. The controller sequentially selects the switching element to be inspected from the plurality of switching elements and detects open circuit failures in all of the switching elements.

2. The switching circuit of claim 1.

5. The controller measures the time from the input of the drive signal to the time the drive circuit becomes conductive based on a change in voltage at the output terminal of the drive circuit.

2. The switching circuit of claim 1.

6. The controller does not transition to normal control when an open fault is detected in any switching element.

2. The switching circuit of claim 1.

7. The controller limits the current output from the drive circuit when an open circuit fault is detected in any switching element.

2. The switching circuit of claim 1.

8. The controller adjusts the duty ratio of the drive signal to limit the current.

8. The switching circuit of claim 7.

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