Power conversion device

Abstract

The degree of damage related to the power semiconductor devices Q1 to Q6 is quantitatively presented to the user in an easy-to-understand manner.SOLUTION: The power conversion device 11 includes the temperature history calculation unit 31 that acquires the information of the junction temperature history Tjr of the power semiconductor devices Q1 to Q6 based on the predetermined junction temperature functions Ftj correlated with the junction temperatures Tj of the power semiconductor devices Q1 to Q6; The damage calculator 39 calculates the damage degree DD of the power semiconductor devices Q1 to Q6 for each of the plurality of patterns of failure rates FR by referring to the tolerance characteristic table 41 in which the tolerance characteristic of the power semiconductor devices Q1 to Q6 is associated with each of the plurality of patterns of failure rates FR. Q1 Q6.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power conversion device that outputs AC power to a load such as a motor. [Background technology]

[0002] Inverters, a type of power conversion device, are widely used in industry as motor drive devices in manufacturing equipment, elevators, transport equipment, etc. In these various applications, inverters are required to operate stably. If an inverter were to fail, it would cause factory production to stop and equipment operation to stop, resulting in a huge impact.

[0003] Inverters use power semiconductor devices such as IGBTs and diodes to control the flow and interruption of current and perform the desired power conversion. The power semiconductor devices are soldered via wire bonding or copper foil patterns formed on insulating substrates, etc. This allows the power semiconductor devices to be electrically connected to external circuits.

[0004] When a power semiconductor device performs switching operations, it generates heat, which causes a temperature difference ΔT between the junction of the power semiconductor device and the fin (metal base with a cooling structure).

[0005] At the junctions of power semiconductor devices, materials with different thermal expansion coefficients are joined. As a result, fluctuations in the temperature difference ΔT cause thermal stress at the junctions. Repeated fluctuations in the temperature difference ΔT can cause peeling or cracks at the junctions, leading to failure. Such failures in power semiconductor devices due to repeated thermal expansion and contraction are generally called power cycle failures.

[0006] It is desirable for inverter users to be able to grasp the degree of damage and remaining life of power semiconductor devices before they reach a power cycle failure. In order to meet such user needs, Patent Document 1 discloses a power conversion device that drives a motor, calculates the temperature change amplitude of a power semiconductor device from the current flowing through the power semiconductor device, the operating frequency, and the carrier frequency, calculates thermal stress from power cycle curve data and the temperature change amplitude, estimates the remaining life of the power semiconductor device based on this thermal stress signal, and outputs the estimated remaining life on a display unit.

[0007] Patent Document 2 discloses a power conversion device that drives a motor, and calculates the temperature history of a power semiconductor device from the current flowing through the power semiconductor device, the carrier frequency, etc., and calculates damage to the power semiconductor device from the results of the temperature history calculation.

[0008] According to the techniques disclosed in Patent Documents 1 and 2, the remaining life of the power semiconductor device and an alarm signal can be displayed on an operation panel, thereby providing the user of the power conversion device with information for determining when to replace the power conversion device. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] International Publication No. 2004 / 082114 [Patent Document 2] Japanese Patent Publication No. 2022-25408 Summary of the Invention [Problem to be solved by the invention]

[0010] However, the power conversion devices according to Patent Documents 1 and 2 have room for improvement in that they only handle one power cycle curve based on one failure rate (see, for example, Figure 5 of Patent Document 1 and Figure 14 of Patent Document 2). Generally, power cycle curves are derived using methods such as Weibull analysis based on the actual measurement results of power cycle tests. Naturally, this does not mean that power semiconductor devices will not break down at all until their remaining life reaches 0, nor does it mean that all of them will break down when their remaining life reaches 0.

[0011] Therefore, when dealing with only a power cycle curve at one failure rate, as in the power conversion devices of Patent Documents 1 and 2, there is a problem in that the user cannot quantitatively grasp how many failures should be expected before the expected lifespan ends, or how much lifespan extension can be expected after the remaining lifespan reaches zero.

[0012] The present invention has been made in view of the above-described circumstances, and has an object to provide a power conversion apparatus that can quantitatively present the degree of damage to a power semiconductor device in an easily understandable manner to a user. [Means for solving the problem]

[0013] In order to solve the above problem, a power conversion device according to the present invention includes: A power conversion device that performs required power conversion by controlling the flow and interruption of current using an inverter unit equipped with a power semiconductor device, an information acquisition unit that acquires information on a junction temperature history of the power semiconductor device based on a predetermined junction temperature function that correlates with a junction temperature of the power semiconductor device; a damage calculation unit that calculates a damage degree related to the power semiconductor device based on the junction temperature history acquired by the information acquisition unit, The most important feature of the damage calculation unit is that it calculates the degree of damage to the power semiconductor device for each of the plurality of failure rate patterns by referring to a tolerance characteristic table that associates tolerance characteristic data for the power semiconductor device for each of the plurality of failure rate patterns. [Effects of the Invention]

[0014] According to the power conversion device of the present invention, the degree of damage to the power semiconductor device can be quantitatively presented to the user in an easily understandable manner. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic configuration diagram of a power conversion device according to a first embodiment. [Figure 2] FIG. 2 is an explanatory diagram exemplarily showing a power cycle characteristic diagram of the power conversion device according to the first embodiment. [Figure 3] 3 is a block diagram of a damage calculation unit provided in the power conversion device according to the first embodiment. FIG. [Figure 4] 3 is an explanatory diagram exemplarily showing a damage level-failure rate characteristic diagram of the power conversion device according to the first embodiment. FIG. [Figure 5] 3 is an explanatory diagram illustrating an example of a display on a display unit provided in the power conversion device according to the first embodiment. FIG. [Figure 6] FIG. 10 is a block diagram of a damage calculation unit provided in a power conversion device according to a second embodiment. [Figure 7] FIG. 10 is an explanatory diagram illustrating a display example of a display unit provided in a power conversion device according to a second embodiment. [Figure 8] FIG. 10 is a schematic configuration diagram of a power conversion device according to a third embodiment. [Figure 9] FIG. 11 is a block diagram of a damage calculation unit provided in a power conversion device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Power conversion devices according to a plurality of embodiments of the present invention will be described in detail with reference to the appropriate drawings. In the drawings shown below, components having a common function or components having corresponding functions are generally assigned the same reference numerals, and redundant explanations will be omitted. For the sake of convenience, the size and shape of components may be exaggerated or distorted to show a schematic representation.

[0017] [Power conversion device 11 according to the first embodiment] First, a power conversion device 11 according to the first embodiment will be described with reference to FIG. FIG. 1 is a schematic configuration diagram of a power conversion device 11 according to a first embodiment of the present invention. As shown in FIG. 1, the power conversion device 11 according to the first embodiment includes a rectifier unit 101 that inputs an AC voltage and outputs a DC voltage, a smoothing capacitor 103 that smooths the DC voltage, an inverter unit 105 that converts the DC voltage into an AC voltage, a voltage detection unit 111 that detects the DC voltage, current detection units 113 and 115 that detect the current flowing through the motor M, a gate driver 121 that outputs a gate signal to the inverter unit 105, a control device 131 that outputs a drive signal to the gate driver 121, a damage calculation device 133 that includes a damage calculation unit 39 (see FIG. 3) that calculates damage levels DD for the power semiconductor devices Q1 to Q6 provided in the inverter unit 105, and a display unit 143 that outputs the calculation results by the damage calculation device 133 (damage calculation unit 39).

[0018] Rectifier 101 is configured by connecting multiple diodes D1 to D6 in a bridge configuration. Rectifier 101 converts the AC voltage input from the input terminal into a DC voltage and outputs it to both electrodes of smoothing capacitor 103. The rectification action of diodes D1 to D6 provided in rectifier 101 generates a DC voltage that exhibits a positive voltage on the DC voltage wiring on the node P side and a negative voltage on the DC voltage wiring on the node N side.

[0019] Smoothing capacitor 103 is connected to the DC voltage wiring at nodes P and N, and smoothes the DC voltage rectified by rectifier 101 .

[0020] The inverter unit 105 is configured by providing a plurality of power semiconductor devices Q1 to Q6, each of which is made up of an IGBT and an anti-parallel diode, in a bridge configuration. When the motor 141 is in power running mode, the inverter unit 105 converts the DC voltage smoothed by the smoothing capacitor 103 into AC power and outputs it to the motor 141. When the motor 141 is in regenerative operation mode, the inverter unit 105 operates to charge the smoothing capacitor 103 with regenerative energy from the motor 141.

[0021] The gate driver 121 outputs a gate signal to each of the plurality of power semiconductor devices Q1 to Q6 provided in the inverter unit 105. Each of the plurality of power semiconductor devices Q1 to Q6 provided in the inverter unit 105 performs a switching operation in accordance with the gate signal from the gate driver 121.

[0022] The voltage detection unit 111 detects the DC voltage between the node P and the node N by resistor division using a pair of resistors R1 and R2. In the following description, the voltage detection value related to the voltage detection unit 111 will be referred to as Vdc.

[0023] The current detection units 113 and 115 use current sensors such as shunt resistors and current transformers to detect the current flowing through the motor 141. In the following description, the current detection values ​​of the current detection units 113 and 115 will be referred to as IU and IW, respectively.

[0024] The control device 131 calculates a set speed command and a gate signal at a carrier frequency using the voltage detection value Vdc of the voltage detection unit 111 and the current detection values ​​IU and IW of the current detection units 113 and 115, and outputs them to the gate driver 121. In the following description, the carrier frequency is referred to as fc, and the on-period of the gate relative to the carrier cycle is referred to as Duty.

[0025] In the power semiconductor devices Q1 to Q6 provided in the inverter section 105, the junction temperature Tj rises due to switching loss during the turn-on / turn-off switching period and conduction loss in the conductive state (ON state). It is known that the junction temperature Tj is correlated with the detected voltage value Vdc, the detected current values ​​IU and IW, the carrier frequency fc, and the on-period duty. In the following explanation, the detected voltage value Vdc, the detected current values ​​IU and IW, the carrier frequency fc, and the on-period duty may be collectively referred to as the "junction temperature function Ftj." However, when the power semiconductor devices Q1 to Q6 are in a cutoff state (off state), no loss occurs. Therefore, in the cutoff state (off state), the junction temperature Tj drops due to the cooling effect of the fins, etc.

[0026] According to research by the present inventors, it has been found that the junction temperature history Tjr, which is a history related to the junction temperature Tj, is correlated with the damage level DD in the power cycle of the power semiconductor devices Q1 to Q6 provided in the inverter unit 105. Here, the power cycle (number of power cycles) is a concept that correlates with, for example, the thermal stress related to the power semiconductor devices Q1 to Q6, and can be calculated based on the rise and fall of the junction temperature Tj and the power cycle tolerance provided by the power semiconductor device manufacturer or the like.

[0027] The damage calculation device 133 (damage calculation unit 39) uses a junction temperature function Ftj including the voltage detection value Vdc, the current detection values ​​IU and IW, the carrier frequency fc, and the on-period Duty to calculate the junction temperature history Tjr, i.e., the damage degree DD in the power cycle of the power semiconductor devices Q1 to Q6 provided in the inverter unit 105.

[0028] The display unit 143 notifies the user of the damage degree DD in the power cycle of the power semiconductor devices Q1 to Q6 calculated by the damage calculation device 133 (damage calculation unit 39) by displaying it on an operation panel or using a 7-segment lighting pattern.

[0029] 2 shows a characteristic diagram showing the correlation between the number of power cycles and the junction temperature change width ΔTj for the power semiconductor devices Q1 to Q6 provided in the inverter section 105. This characteristic diagram is generally called a power cycle tolerance curve.

[0030] As mentioned above, the junction temperatures Tj of the power semiconductor devices Q1 to Q6 repeatedly rise and fall depending on the operating conditions. The junction temperature change range ΔTj, which is the range of change between the rise and fall of the junction temperature Tj, is shown on the horizontal axis (logarithmic axis) of Figure 2. The vertical axis of Figure 2 indicates the number of power cycles allowed for each junction temperature change range ΔTj. As shown in FIG. 2, the larger the junction temperature change width ΔTj, the greater the thermal stress that the power semiconductor devices Q1 to Q6 are subjected to, and therefore the number of allowable power cycles (a function of current-carrying time) decreases.

[0031] The power cycle tolerance curve shown in Figure 2 shows an example where three patterns of failure rate (FR = A% / B% / C%) are used as parameters. Here, the failure rate FR represents the probability of failure when the junction temperature change width ΔTj on the horizontal axis in Figure 2 occurs the same number of power cycles on the vertical axis.

[0032] For example, on the characteristic line of the lowest failure rate (FR=A%) among the three patterns of failure rate shown in Figure 2, it is shown that when a junction temperature change range (ΔTj=X[K]) occurs α times in power semiconductor devices Q1 to Q6, there is a high probability that power semiconductor devices Q1 to Q6 will experience a power cycle failure with a probability of A / 100[units].

[0033] Figure 2 also shows how the failure rate FR increases (A → B → C [%]) as the number of power cycles allowed increases (α → β → γ [times]) under operating conditions that result in the same junction temperature change range (ΔTj = X [K]).

[0034] Here, the designer of the power semiconductor devices Q1 to Q6 aims to have all of the power semiconductor devices Q1 to Q6 fail at the same time when the operating conditions cause the same junction temperature change width ΔTj. In other words, the designer aims to design the devices so that the characteristic line of a failure rate FR of 1% and the characteristic line of a failure rate FR of 100% are as close as possible to each other. Generally, under operating conditions that cause the same junction temperature change width ΔTj, even if the failure rate FR increases from 1% to 10%, the allowable number of power cycles does not increase tenfold, but becomes a value less than tenfold.

[0035] FIG. 3 shows a block diagram of the damage calculation device 133 provided in the power conversion device 11 according to the first embodiment. The damage calculation device 133 receives as input the voltage detection value (Vdc) of the voltage detection unit 111, the current detection values ​​(IU, IW) of the current detection units 113, 115, and the junction temperature function Ftj including the internal values ​​(Duty, fc) of the control device 131. The damage calculation device 133 acquires the junction temperature history Tjr for the power semiconductor devices Q1 to Q6 provided in the inverter unit 105 based on the junction temperature function Ftj, and calculates the damage degree DD in the power cycle of the power semiconductor devices Q1 to Q6 based on the information of the acquired junction temperature history Tjr.

[0036] In order to realize the above function, the damage calculation device 133 is configured with a temperature history calculation unit 31, an electrical characteristic table 33, a thermal characteristic table 35, a temperature history memory unit 37, a damage calculation unit 39, a tolerance characteristic table 41, cumulative damage calculation units 51, 53, 55 for each different failure rate FR (A% / B% / C%), and cumulative damage memory units 61, 63, 65.

[0037] The temperature history calculation unit 31 calculates and obtains the junction temperature history Tjr for the power semiconductor devices Q1 to Q6 based on the junction temperature variable PVtj. Specifically, the temperature history calculation unit 31 estimates the losses of the power semiconductor devices Q1 to Q6 by referring to an electrical characteristics table 33 including the voltage-current characteristics of the power semiconductor devices Q1 to Q6, and calculates and obtains the junction temperature history Tjr for the power semiconductor devices Q1 to Q6 using the estimated losses and a thermal characteristics table 35 including the thermal impedance-time characteristics for the power semiconductor devices Q1 to Q6. The information on the junction temperature history Tjr thus obtained is stored in a temperature history storage unit 37 and is also output to a damage calculation unit 39. The temperature history calculation unit 31 corresponds to the "information acquisition unit."

[0038] The damage calculation unit 39 reads the junction temperature history Tjr for the power semiconductor devices Q1 to Q6 from the temperature history memory unit 37, and based on the read junction temperature history Tjr, extracts the extreme values ​​(maximum points, minimum points) of the rise and fall of the junction temperature Tj for the power semiconductor devices Q1 to Q6.

[0039] The damage calculation unit 39 counts the number of times the junction temperature change width ΔTj occurs using a method such as the rainflow method based on the extracted extreme values, and calculates the damage level DD based on the junction temperature history Tjr by referring to the tolerance characteristics table 41. Here, the tolerance characteristic table 41 is a collection of data in which tolerance characteristic data relating to the power semiconductor devices Q1 to Q6 is described in a tabular format. The tolerance characteristic table 41 is created based on the power cycle tolerance curve shown in FIG.

[0040] The most important feature of the power conversion device 11 according to this embodiment is that it includes a tolerance characteristic table 41 in which tolerance characteristic data for the power semiconductor devices Q1 to Q6 are associated in tabular form with each of a plurality of patterns of failure rates FR.

[0041] The damage calculation unit 39 calculates the damage degree DD for the power semiconductor devices Q1 to Q6 for each failure rate FR across multiple patterns based on the tolerance characteristic data for the power semiconductor devices Q1 to Q6 for each failure rate FR across multiple patterns described in the tolerance characteristic table 41 for the extreme values ​​of the junction temperature change range ΔTj extracted by the damage calculation unit 39.

[0042] In cases where the same junction temperature change width ΔTj occurs, the damage degree DD for the power semiconductor devices Q1 to Q6 generally tends to decrease as the failure rate FR increases. However, when there is only one condition for the failure rate FR, as in the power conversion devices disclosed in Patent Documents 1 and 2, it is not easy to determine how much the damage degree DD is quantitatively reduced. In this regard, the power conversion device 11 according to the present invention can quantitatively show how much the damage levels DD of the power semiconductor devices Q1 to Q6 are reduced in accordance with the failure rates FR across a plurality of patterns.

[0043] The method for calculating the junction temperature history Tjr and the damage degree DD for the power semiconductor devices Q1 to Q6 described above is disclosed in detail in Patent Document 2 (JP 2022-25408 A). The disclosures of Patent Document 2 (paragraphs 0011-0049) are incorporated herein by reference.

[0044] The plurality of damage degrees DD calculated by the damage calculation unit 39 according to the failure rates FR across the plurality of patterns are output to cumulative damage calculation units 51, 53, and 55 according to the failure rates FR across the plurality of patterns, respectively.

[0045] Each of the cumulative damage calculation units 51, 53, and 55 adds a plurality of damage degrees DD corresponding to the failure rates FR across a plurality of patterns calculated by the damage calculation unit 39 to the cumulative damage value read from each of the cumulative damage storage units 61, 63, and 65. The cumulative damage degrees (damage degrees DD) corresponding to the failure rates FR across a plurality of patterns thus calculated are output to the cumulative damage storage units 61, 63, and 65.

[0046] Each of the cumulative damage storage units 61, 63, 65 outputs to the display unit 143 a plurality of cumulative damage levels (damage levels DD) corresponding to the updated failure rates FR across a plurality of patterns.

[0047] The display unit 143 displays the degree of cumulative damage (damage level DD) of the power semiconductor devices Q1 to Q6 included in the inverter unit 105 in a format that is easy for the user of the power conversion device 11 to understand.

[0048] Fig. 4 is an explanatory diagram exemplarily showing a damage level-failure rate characteristic diagram of the power conversion device 11 according to the first embodiment. The horizontal axis of Fig. 4 represents the cumulative damage level (damage level DD) of the power semiconductor devices Q1 to Q6 at a failure rate (FR=1%), and the vertical axis of Fig. 4 represents the failure rate FR, which is the probability that the power semiconductor devices Q1 to Q6 will actually fail.

[0049] The solid line in Fig. 4 shows an example of the damage level-failure rate characteristics for the power semiconductor devices Q1 to Q6. As mentioned above, the designers of the power semiconductor devices Q1 to Q6 aim to have all of the power semiconductor devices Q1 to Q6 fail at the same time when the operating conditions cause the same junction temperature change width ΔTj. Therefore, it is known that the failure rate FR of the power semiconductor devices Q1 to Q6 does not increase linearly with an increase in the cumulative damage level (damage level DD), but increases exponentially, as shown by the solid line in Fig. 4. In addition, the steeper the slope of the damage level-failure rate characteristic diagram shown by the solid line in Fig. 4, the more the characteristics desired by the designer of the power semiconductor devices Q1 to Q6 are achieved.

[0050] A first characteristic point M on the damage level-failure rate characteristic diagram shown by a solid line in Fig. 4 indicates that when the cumulative damage level (damage level DD) at the failure rate (FR = 1%) is 100%, the probability of actual failure (failure rate FR) is 1%. Here, when the cumulative damage level (damage level DD) at the failure rate (FR = 1%) becomes 200%, the damage level-failure rate characteristic of the power semiconductor devices Q1 to Q6 moves from the first characteristic point M to a second characteristic point N on the damage level-failure rate characteristic diagram shown by a solid line in Fig. 4. In other words, when the cumulative damage level (damage level DD) at the failure rate (FR = 1%) is 200%, the probability of actual failure (failure rate FR) becomes 10%.

[0051] Here, the first characteristic point M shown in Fig. 4 is the point where the cumulative damage level (damage level DD) at a failure rate FR of 10% is 50%. The second characteristic point N shown in Fig. 4 is the point where the cumulative damage level (damage level DD) at a failure rate FR of 10% is 100%. If only a power cycle curve based on a failure rate (FR=1%) is used as an example, as in the prior art documents, it is difficult to quantitatively understand that the actual failure probability (failure rate FR) is 200% when the calculation result of the cumulative damage level (damage level DD) at a failure rate (FR=1%) is 200%.Furthermore, if only a power cycle curve based on a failure rate (FR=10%) is used as an example, there is a concern that it is difficult to quantitatively understand that the actual failure probability (failure rate FR) is 1% when the calculation result of the cumulative damage level (damage level DD) at a failure rate (FR=10%) is 50%.

[0052] Fig. 5 is an explanatory diagram showing a display example of the display unit 143 provided in the power conversion device 11 according to the first embodiment. The example shown in Fig. 5 shows that if there are 100 power conversion devices 11, there is a high probability that one out of the 100 will fail. Here, for a user who tolerates failures in, for example, 10 of the 100 power conversion devices 11, a damage degree DD corresponding to a failure rate (FR = 10%) is more useful than a damage degree DD corresponding to a failure rate (FR = 1%).

[0053] According to the power conversion device 11 of the first embodiment, for example, a configuration is adopted in which a damage degree DD corresponding to a failure rate (FR=1%), a damage degree DD corresponding to a failure rate (FR=5%), and a damage degree DD corresponding to a failure rate (FR=10%) are calculated, so that damage degrees DD corresponding to a plurality of patterns of failure rates FR can be quantitatively presented (displayed) together. As a result, the damage degrees DD related to the power semiconductor devices Q1 to Q6 can be presented (displayed) in a form that meets various user needs.

[0054] [Power conversion device 11 according to the second embodiment] Next, a power conversion device 11 according to a second embodiment will be described with reference to FIGS. 6 and 7 as appropriate. FIG. 6 is a block diagram of a damage calculation device 133 provided in the power conversion device 11 according to the second embodiment. As shown in Figure 6, the damage calculation device 133 provided in the power conversion device 11 of the second embodiment differs from the damage calculation device 133 provided in the power conversion device 11 of the first embodiment shown in Figure 3 in that a life estimation device 135 is added.

[0055] The life estimation apparatus 135 includes life estimation units 61, 63, and 65 that correspond to a plurality of patterns of failure rates FR. Each of the life estimation units 61, 63, and 65 estimates a remaining life RL for each of the power semiconductor devices Q1 to Q6 based on a plurality of accumulated damages (damage degrees DD) that correspond to the plurality of patterns of failure rates FR calculated by the accumulated damage calculation units 51, 53, and 55.

[0056] Each of the life estimation units 61, 63, 65 provided in the life estimation device 135 estimates the remaining life RL taking into consideration that, for example, when the cumulative damage (damage level DD) is 0%, the remaining life RL is 100%, and when the cumulative damage (damage level DD) is 100%, the remaining life RL is 0%. The unit of the remaining life RL is not limited to a percentage (%), and may be expressed in other units, such as a length of time including years and months.

[0057] Some users may find it easier to intuitively understand the remaining life RL when it is presented (displayed) in units of [years] or [hours], compared to the damage level DD [%] calculated by the damage calculation device 133 included in the power conversion device 11 according to the first embodiment. Therefore, the power conversion device 11 according to the second embodiment has the effect of promoting user understanding, compared to the power conversion device 11 according to the first embodiment.

[0058] Fig. 7 is a display example of the display unit 143 provided in the power conversion device 11 according to the second embodiment. The representative example shown in Fig. 7 indicates that under the condition of a failure rate (FR = 1%), the damage degree DD is 100% and the remaining life RL is 0 years.

[0059] In the representative example shown in FIG. 7, an example pattern of the failure rate FR (FR=1%) has been described, but as with the power conversion device 11 according to the first embodiment, it is also possible to adopt a mode in which the damage level DD and the remaining life RL are displayed together for each of a plurality of patterns of failure rates FR.

[0060] [Power conversion device 13 according to the third embodiment] Next, a power conversion device 13 according to a third embodiment will be described with reference to FIGS. 8 and 9 as appropriate. Fig. 8 is a schematic configuration diagram of the power conversion device 13 according to the third embodiment. Fig. 9 is a block diagram of a damage calculation device 137 provided in the power conversion device 13 according to the third embodiment. As shown in Figures 8 and 9, the damage calculation device 137 provided in the power conversion device 13 according to the third embodiment differs from the damage calculation device 133 provided in the power conversion device 11 according to the first embodiment shown in Figure 3 in that a failure rate setting unit 77 is added.

[0061] When a user selects a desired failure rate FR from among the failure rates FR for the power semiconductor devices Q1 to Q6 across multiple patterns, the failure rate setting unit 77 provided in the damage calculation device 137 sets (i.e., selectively sets) the damage degree DD for the power semiconductor devices Q1 to Q6 corresponding to the failure rate FR according to this failure rate selection signal SEL as the display target and outputs it to the display unit 143.

[0062] In the power conversion device 11 shown in the first embodiment, the display unit 143 displays a plurality of damage levels DD for each of the failure rates FR of the power semiconductor devices Q1 to Q6 across a plurality of patterns, as shown in FIG.

[0063] In contrast, in the power conversion device 13 according to the third embodiment, the display unit 143 displays only the damage degree DD corresponding to the failure rate FR selected by the user among the damage degrees DD for the power semiconductor devices Q1 to Q6 corresponding to the failure rates FR across multiple patterns.

[0064] It is assumed that there may be cases where it is difficult to display all the information on the display unit 143 due to dimensional restrictions on the operation panel, etc. In such cases, it is preferable to display only the damage level DD corresponding to the failure rate FR selected by the user, which is the required information according to the user's needs, on the display unit 143.

[0065] According to the power conversion device 13 of the third embodiment, only the damage level DD corresponding to the failure rate FR in line with the user needs is presented (displayed), so that the required information in line with the user needs can be presented (displayed) in a clear and easy-to-understand manner.

[0066] [Configuration, Function and Effects of Power Conversion Devices 11 and 13 According to the Present Invention] The power conversion device 11 according to the first aspect comprises: A power conversion device (11) that performs required power conversion by controlling current flow and cutoff using an inverter unit (105) that includes power semiconductor devices (Q1 to Q6), a temperature history calculation unit (information acquisition unit) 31 that acquires information on junction temperature history Tjr related to the power semiconductor devices Q1 to Q6 based on a predetermined junction temperature function Ftj that correlates with the junction temperature Tj related to the power semiconductor devices Q1 to Q6; a damage calculation unit (39) that calculates a damage degree (DD) for the power semiconductor devices (Q1 to Q6) based on the junction temperature history (Tjr) acquired by the temperature history calculation unit (information acquisition unit) (31), The damage calculation unit 39 calculates the damage level DD for the power semiconductor devices Q1 to Q6 for each of the failure rates FR across multiple patterns by referring to a tolerance characteristic table 41 that associates tolerance characteristic data for the power semiconductor devices Q1 to Q6 with each of the failure rates FR across multiple patterns.

[0067] According to the power conversion device 11 based on the first aspect, the degree of damage to the power semiconductor devices Q1 to Q6 can be quantitatively presented to the user in an easily understandable manner. Furthermore, according to the power conversion device 11 based on the first aspect, multiple damage levels DD are presented (displayed) according to multiple patterns of failure rates FR, so that the user can quantitatively grasp the degree to which a failure is likely to occur before the expected lifespan (remaining lifespan RL) and the degree to which the device will continue to operate without failure after the remaining lifespan RL becomes zero.

[0068] The power conversion device 11 according to the second aspect is the power conversion device 11 according to the first aspect, Further provided is a life estimation unit (61, 63, 65) that estimates a remaining life (RL) of the power semiconductor devices (Q1 to Q6) based on the damage degree (DD) of the power semiconductor devices (Q1 to Q6) calculated by the damage calculation unit (39), The life estimation units 61, 63, and 65 may be configured to estimate the remaining life RL of the power semiconductor devices Q1 to Q6 for each of the plurality of patterns of failure rates FR.

[0069] According to the power conversion device 11 based on the second aspect, the damage level DD and remaining life RL of the power semiconductor devices Q1 to Q6 can be quantitatively presented to the user in an easily understandable manner.

[0070] A power conversion apparatus 11 according to a third aspect is the power conversion apparatus 11 according to the first aspect, A display unit 143 is further provided which displays a damage level DD relating to the power semiconductor devices Q1 to Q6, A configuration may be adopted in which the display unit 143 is used to display the damage level DD of the power semiconductor devices Q1 to Q6 for each of the plurality of patterns of failure rates FR.

[0071] According to the power conversion device 11 based on the third aspect, like the power conversion device 11 based on the first aspect, the damage level DD of the power semiconductor devices Q1 to Q6 can be quantitatively displayed in a manner that is easy for the user to understand.

[0072] A power conversion apparatus 11 according to a fourth aspect is the power conversion apparatus 11 according to the second aspect, A display unit 143 is further provided which displays a damage level DD relating to the power semiconductor devices Q1 to Q6, The display unit 143 may be configured to display the damage level DD and remaining life RL of the power semiconductor devices Q1 to Q6 for each of the plurality of patterns of failure rates FR.

[0073] According to the power conversion device 11 based on the fourth aspect, like the power conversion device 11 based on the second aspect, the damage level DD and remaining life RL of the power semiconductor devices Q1 to Q6 can be quantitatively displayed in an easy-to-understand manner for the user.

[0074] A power conversion apparatus 11 according to a fifth aspect is the power conversion apparatus 11 according to the third aspect, a failure rate setting unit (77) that selectively sets a desired failure rate (FR) from among the plurality of patterns of failure rates (FR), A configuration may be adopted in which the display unit 143 is used to display the damage level DD of the power semiconductor devices Q1 to Q6 corresponding to the failure rate FR set by the failure rate setting unit 77.

[0075] Compared to the power conversion device 11 based on the third aspect, the power conversion device 11 based on the fifth aspect can quantitatively display the damage degree DD of the power semiconductor devices Q1 to Q6 corresponding to the failure rate FR in line with the user needs in a manner that is easy for the user to understand.

[0076] A power conversion apparatus 11 according to a sixth aspect is the power conversion apparatus 11 according to the fourth aspect, a failure rate setting unit (77) that selectively sets a desired failure rate (FR) from among the plurality of patterns of failure rates (FR), The display unit 143 may be configured to display the damage level DD and remaining life RL of the power semiconductor devices Q1 to Q6 corresponding to the failure rate FR set by the failure rate setting unit 77 together.

[0077] Compared to the power conversion device 11 based on the fourth aspect, the power conversion device 11 based on the sixth aspect can quantitatively display the damage degree DD and remaining life RL of the power semiconductor devices Q1 to Q6 corresponding to the failure rate FR in line with the user needs in a manner that is easy for the user to understand.

[0078] Other Embodiments The above-described embodiments and modifications are illustrative of the present invention. Therefore, the technical scope of the present invention should not be construed as being limited by these descriptions. The present invention can be embodied in various forms without departing from the spirit or main characteristics thereof.

[0079] It is also possible to replace part of the configuration of one embodiment described here with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment.It is also possible to add, delete, or replace part of the configuration of each embodiment with another configuration.

[0080] Furthermore, the control lines and information lines shown are those that are considered necessary for the explanation, and do not necessarily show all the control lines and information lines in the product. In reality, it can be assumed that almost all components are interconnected.

[0081] For example, the rectifier unit 101 shown in FIG. 1 shows a system for full-wave rectifying three-phase AC as a representative example, but it may also be configured as a system for full-wave rectifying single-phase AC or a system for voltage-doubler rectifying single-phase AC.

[0082] In addition, in the explanation of the first to third embodiments of the present invention, the combination of an IGBT and an anti-parallel diode is used as the power semiconductor devices Q1 to Q6, but the present invention is not limited to this example. MOSFETs or the like may be used as the power semiconductor devices Q1 to Q6 as appropriate.

[0083] Furthermore, in the explanation of the first to third embodiments of the present invention, a configuration for supplying power to a motor has been exemplified as a power conversion device, but the present invention may also be applied to any device that outputs three-phase AC voltage, such as a regenerative converter or a grid-connected inverter.

[0084] Finally, some or all of the components, functions, processing units, etc. included in the power conversion device 11 according to the embodiment of the present invention may be implemented in hardware, for example, by designing them as integrated circuits. Furthermore, the components, functions, processing units, etc. described above may be implemented in software by a processor interpreting and executing a program that implements each function. Information such as the programs, tables, and files that implement each function may be stored in a storage device such as a memory, a hard disk, or an SSD (Solid State Drive), or in a storage medium such as an IC card, an SD card, or a DVD (Digital Versatile Disk). [Explanation of symbols]

[0085] 11 Power conversion devices according to first and second embodiments 13 Power conversion device according to the third embodiment 31 Temperature history calculation unit (information acquisition unit) 33 Electrical Characteristics Table 35 Thermal Properties Table 37 Temperature history memory section 39 Damage calculation section 41 Withstand characteristics table 51, 53, 55 Cumulative damage calculation section 61, 63, 65 Cumulative damage memory section 71, 73, 75 Life estimation section 77 Failure rate setting section 105 Inverter section 121 Gate Driver 131 Control device 133 Damage calculation device according to the first and second embodiments 135 Life estimation device 137 Damage calculation device according to the third embodiment DD Damage level related to power semiconductor devices FR Failure rate of power semiconductor devices Q1~Q6 Power semiconductor devices RL Remaining life of power semiconductor devices Ftj Junction temperature function Tj Junction temperature of power semiconductor device Tjr Junction temperature history of power semiconductor devices

Claims

1. A power conversion device that performs required power conversion by controlling current flow and interruption using an inverter unit equipped with a power semiconductor device, an information acquisition unit that acquires information on a junction temperature history of the power semiconductor device based on a predetermined junction temperature function that correlates with a junction temperature of the power semiconductor device; a damage calculation unit that calculates a damage degree related to the power semiconductor device based on the junction temperature history acquired by the information acquisition unit, The damage calculation unit calculates the degree of damage to the power semiconductor device for each of the plurality of failure rates by referring to a tolerance characteristic table in which tolerance characteristic data for the power semiconductor device is associated with each of the plurality of failure rates. A power conversion device characterized by:

2. The power conversion device according to claim 1, a life estimation unit that estimates a remaining life of the power semiconductor device based on the damage level of the power semiconductor device calculated by the damage calculation unit, The life estimation unit estimates a remaining life of the power semiconductor device for each of the plurality of patterns of failure rates. A power conversion device characterized by:

3. The power conversion device according to claim 1, a display unit that displays a damage level of the power semiconductor device, The display unit is used to display the degree of damage to the power semiconductor device for each of the plurality of patterns of failure rates. A power conversion device characterized by:

4. The power conversion device according to claim 2, a display unit that displays a damage level of the power semiconductor device, The display unit is used to display the degree of damage and remaining life of the power semiconductor device for each of the plurality of patterns of failure rates. A power conversion device characterized by:

5. The power conversion device according to claim 3, a failure rate setting unit that selectively sets a desired failure rate from among the plurality of patterns of failure rates; The display unit displays the degree of damage to the power semiconductor device corresponding to the failure rate set by the failure rate setting unit. A power conversion device characterized by:

6. The power conversion device according to claim 4, a failure rate setting unit that selectively sets a desired failure rate from among the plurality of patterns of failure rates; The display unit is used to display the degree of damage and remaining life of the power semiconductor device corresponding to the failure rate set by the failure rate setting unit. A power conversion device characterized by:

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