Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing reaction between a semiconductor material of a semiconductor region and a metal material of an electrode, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a second electrode, and a third electrode. The second semiconductor region is provided on the first region of the first semiconductor region. The gate electrode faces the second semiconductor region via the gate insulating layer. The fourth semiconductor region is provided on the second region of the first semiconductor region. The second electrode is provided on the second and third semiconductor regions via the first contact. The third electrode is provided on the fourth semiconductor region via a second contact. The first contact and the second contact include a titanium-containing layer, a titanium nitride-containing layer provided on the titanium-containing layer, and a tungsten-containing layer provided on the titanium nitride-containing layer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices such as insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion. Semiconductor devices include semiconductor regions, electrodes, and contacts that connect the semiconductor regions and the electrodes. There is a demand for technology that can suppress reactions between the semiconductor material of the semiconductor region and the metal material of the electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6344483 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress reaction between the semiconductor material of the semiconductor region and the metal material of the electrode. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a second electrode, and a third electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes a first region and a second region located around the first region along a first plane perpendicular to a first direction extending from the first electrode toward the first region. The second semiconductor region is provided on the first region. The third semiconductor region is provided on the second semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction. The fourth semiconductor region is provided on the second region and is spaced apart from the second semiconductor region. The second electrode is provided on the second semiconductor region and the third semiconductor region via a first contact. The first contact includes a first titanium-containing layer containing titanium, a first titanium-nitride-containing layer containing titanium nitride and disposed on the first titanium-containing layer, and a first tungsten-containing layer containing tungsten and disposed on the first titanium-nitride-containing layer. The third electrode is disposed on the fourth semiconductor region via a second contact. The second contact includes a second titanium-containing layer containing titanium, a second titanium-nitride-containing layer containing titanium nitride and disposed on the second titanium-containing layer, and a second tungsten-containing layer containing tungsten and disposed on the second titanium-nitride-containing layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is an enlarged cross-sectional view of a part of FIG. [Figure 6] FIG. 6 is an enlarged cross-sectional view of a part of FIG. [Figure 7] FIG. 7 is an enlarged cross-sectional view of a part of FIG. [Figure 8] 8(a) to 8(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] 9(a) to 9(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] 10(a) to 10(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 11] 11(a) to 11(d) are cross-sectional views showing a manufacturing method according to a first reference example. [Figure 12] 12(a) to 12(d) are cross-sectional views showing a manufacturing method according to a second reference example. [Figure 13] 13(a) and 13(b) are cross-sectional views showing a manufacturing method according to the second reference example. [Figure 14] FIG. 14 is a cross-sectional view showing another example of the second contact. [Figure 15] 15(a) to 15(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 16] 16(a) and 16(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 17] FIG. 17 is a perspective cross-sectional view showing a part of a semiconductor device according to a modification of the embodiment. [Figure 18] FIG. 18 is a perspective cross-sectional view showing a part of a semiconductor device according to a modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate. In the following description and drawings, n + , n, n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] Fig. 1 is a plan view showing a semiconductor device according to an embodiment, Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1, and Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 1. The semiconductor device 100 according to the embodiment is an IGBT. As shown in FIGS. - p-type (first conductivity type) semiconductor region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + p-type source region 3 (third semiconductor region), p-type guard ring region 4 (fourth semiconductor region), p + Shape contact area 5, p +The semiconductor device includes a collector region 6, an n-type buffer region 7, a gate electrode 10, a gate insulating layer 11, an insulating layer 15, a lower electrode 21 (first electrode), an upper electrode 22 (second electrode), a guard ring electrode 23 (third electrode), a gate pad 24, a gate wiring 25, a first contact 31, a second contact 32, and a third contact 33.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the first region 1a of the semiconductor region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). For the sake of explanation, the direction from the lower electrode 21 toward the first region 1a is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the lower electrode 21 and the first region 1a and are unrelated to the direction of gravity.

[0010] 1, an upper electrode 22, a guard ring electrode 23, and a gate pad 24 are provided on the upper surface of the semiconductor device 100. The upper electrode 22, the guard ring electrode 23, and the gate pad 24 are spaced apart from one another. The guard ring electrode 23 is positioned around the upper electrode 22 and the gate pad 24 along the XY plane.

[0011] As shown in FIGS. 2 to 4, a lower electrode 21 is provided on the lower surface of the semiconductor device 100. + The n-type collector region 6 is provided on the lower electrode 21 and is electrically connected to the lower electrode 21. The n-type buffer region 7 is + The collector region 6 is provided on the substrate.

[0012] n - The n-type semiconductor region 1 is provided on the n-type buffer region 7. - The n-type impurity concentration in the n-type semiconductor region 1 is lower than the n-type impurity concentration in the n-type buffer region 7. -As shown in FIGS. 1 to 4, the semiconductor region 1 includes a first region 1a, a second region 1b, and a third region 1c. The second region 1b is located around the first region 1a in the XY plane (first surface). The first region 1a is located in the cell region. The cell region is a region through which current mainly flows when the semiconductor device 100 is in operation. The second region 1b is located in the termination region. The termination region is a region through which a depletion layer extends toward the periphery of the semiconductor device 100 when the semiconductor device 100 is at its breakdown voltage. The third region 1c is provided between a part of the first region 1a and a part of the second region 1b, and is located below the gate pad 24.

[0013] As shown in FIG. 2, the p-type base region 2 is provided on the first region 1a. + Shape source region 3 and p + The p-type contact region 5 is provided on the p-type base region 2. The gate electrode 10 faces the p-type base region 2 in the X direction via a gate insulating layer 11. The gate electrode 10 is electrically connected to a gate pad 24.

[0014] A plurality of p-type base regions 2 are provided in the X direction. + Shape source region 3 and p + The p-type contact regions 5 are arranged alternately in the Y direction. + Only the contact region 5 is provided, and + For example, as shown in FIG. + Shape source region 3 and p + The p-type base region 2 is provided with both a p-type contact region 5 and a p-type + and p-type base regions 2 provided only with p-type contact regions 5, are arranged alternately in the X direction.

[0015] The upper electrode 22 is connected to the p-type base region 2, + Shape source region 3, and p + The upper electrode 22 is provided on the p-type contact region 5 via a first contact 31. The upper electrode 22 is connected to the p-type base region 2, the n-type+ Shape source region 3, and p + The gate electrode 10 is electrically connected to the contact region 5. The insulating layer 15 is provided between the gate electrode 10 and the upper electrode 22. The gate electrode 10 and the upper electrode 22 are electrically isolated from each other by the insulating layer 15.

[0016] As shown in FIG. 3, the p-type guard ring region 4 is provided on the second region 1b. The p-type guard ring region 4 is located around the plurality of p-type base regions 2 along the XY plane. The guard ring electrode 23 is provided on the p-type guard ring region 4 via a second contact 32. The guard ring electrode 23 is located around the upper electrode 22 along the XY plane. The guard ring electrode 23 is electrically connected to the p-type guard ring region 4 via the second contact 32.

[0017] A plurality of p-type guard ring regions 4 are provided at intervals in the direction from the first region 1a to the second region 1b. A plurality of guard ring electrodes 23 are also provided at intervals in the direction from the first region 1a to the second region 1b. The plurality of guard ring electrodes 23 are provided on the plurality of p-type guard ring regions 4 via the plurality of second contacts 32, respectively.

[0018] Above the second region 1b, n - The upper surface of the p-type semiconductor region 1 is covered with an insulating layer 15. The thickness in the Z direction of the insulating layer 15 provided above the second region 1b is greater than the thickness in the Z direction of the insulating layer 15 provided above the first region 1a. The second contact 32 is aligned with the insulating layer 15 in the direction from the first region 1a to the second region 1b. A portion of the insulating layer 15 is located between a portion of the p-type guard ring region 4 and a portion of the guard ring electrode 23.

[0019] As shown in Fig. 4, above the third region 1c, no p-type semiconductor region such as the p-type base region 2 or the p-type guard ring region 4 is provided. -The upper surface of the semiconductor region 1 is covered with an insulating layer 15. The thickness in the Z direction of the insulating layer 15 provided above the third region 1c is greater than the thickness in the Z direction of the insulating layer 15 provided above the first region 1a.

[0020] Moreover, above the third region 1c, a gate wiring 25 is provided in the insulating layer 15. The gate wiring 25 is electrically connected to the plurality of gate electrodes 10. The gate pad 24 is located above the gate wiring 25 and is electrically connected to the gate wiring 25 via a third contact 33.

[0021] FIG. 5 is an enlarged cross-sectional view of a part of FIG. As shown in FIG. 5, the first contact 31 includes a first titanium-containing layer 31a, a first titanium nitride-containing layer 31b, and a first tungsten-containing layer 31c.

[0022] The first titanium-containing layer 31a contains titanium. The first titanium-containing layer 31a is n + The top surface of the source region 3, p + The first titanium-containing layer 31a is formed along the upper surface of the contact region 5 and the surface of the insulating layer 15. For example, the first titanium-containing layer 31a is formed along the upper surface of the contact region 5 and the surface of the insulating layer 15. + The top surface of the source region 3 and the p + The contact region 5 is in contact with the upper surface of the contact region 5 .

[0023] The first titanium nitride-containing layer 31b contains titanium nitride and is provided on the first titanium-containing layer 31a. The thickness of each portion of the first titanium nitride-containing layer 31b is substantially uniform, and the first titanium nitride-containing layer 31b is provided along the first titanium-containing layer 31a.

[0024] The first tungsten-containing layer 31c contains tungsten and is provided on the first titanium nitride-containing layer 31b. The first tungsten-containing layer 31c is thicker than the first titanium-containing layer 31a and the first titanium nitride-containing layer 31b, and fills the opening formed in the insulating layer 15. The first tungsten-containing layer 31c is in contact with the upper electrode 22.

[0025] FIG. 6 is an enlarged cross-sectional view of a part of FIG. As shown in FIG. 6, the second contact 32 includes a second titanium-containing layer 32a, a second titanium nitride-containing layer 32b, and a second tungsten-containing layer 32c.

[0026] The second titanium-containing layer 32a contains titanium. The second titanium-containing layer 32a is provided along the upper surface of the p-type guard ring region 4 and the surface of the insulating layer 15. For example, the second titanium-containing layer 32a is in contact with the upper surface of the p-type guard ring region 4.

[0027] The second titanium nitride-containing layer 32b contains titanium nitride and is provided on the second titanium-containing layer 32a. The thickness of each portion of the second titanium nitride-containing layer 32b is substantially uniform, and the second titanium nitride-containing layer 32b is provided along the second titanium-containing layer 32a.

[0028] The second tungsten-containing layer 32c contains tungsten and is provided on the second titanium nitride-containing layer 32b. The second tungsten-containing layer 32c is formed thicker than the second titanium-containing layer 32a and the second titanium nitride-containing layer 32b. The second tungsten-containing layer 32c is in contact with the guard ring electrode 23.

[0029] FIG. 7 is an enlarged cross-sectional view of a part of FIG. As shown in FIG. 7, the third contact 33 includes a third titanium-containing layer 33a, a third titanium nitride-containing layer 33b, and a third tungsten-containing layer 33c.

[0030] The third titanium-containing layer 33a contains titanium. The third titanium-containing layer 33a is provided along the upper surface of the gate wiring 25 and the surface of the insulating layer 15. For example, the third titanium-containing layer 33a is in contact with the upper surface of the gate wiring 25.

[0031] The third titanium nitride-containing layer 33b contains titanium nitride and is provided on the third titanium-containing layer 33a. The thickness of each portion of the third titanium nitride-containing layer 33b is substantially uniform, and the third titanium nitride-containing layer 33b is provided along the third titanium-containing layer 33a.

[0032] The third tungsten-containing layer 33c contains tungsten and is provided on the third titanium nitride-containing layer 33b. The third tungsten-containing layer 33c is formed thicker than the third titanium-containing layer 33a and the third titanium nitride-containing layer 33b. The third tungsten-containing layer 33c is in contact with the gate pad 24.

[0033] As shown in FIGS. 5 to 7, the bottom of the first contact 31 is + Shape source region 3 and p + The bottom of the second contact 32 contacts the p-type contact region 5. The bottom of the third contact 33 contacts the gate wiring 25. The width W2 of the bottom of the second contact 32 and the width W3 of the bottom of the third contact 33 are wider than the width W1 of the bottom of the first contact 31. "Width" refers to the length in one direction perpendicular to the Z direction, and in the illustrated example, corresponds to the length in the X direction. For example, the width W2 and the width W3 are greater than 1.4 times and less than or equal to 2 times the width W1.

[0034] The third contact 33 may have the same structure as the second contact 32. For example, the specific structure of the second contact 32 described below can also be applied to the third contact 33.

[0035] 6, the second contact 32 may include a first portion P1 and a second portion P2. The first portion P1 contacts the p-type guard ring region 4 and is located between the p-type guard ring region 4 and the guard ring electrode 23 in the Z direction. The second portion P2 contacts the insulating layer 15 and is located between the insulating layer 15 and the guard ring electrode 23 in the X direction. A thickness T2 of the second portion P2 in the X direction is greater than a thickness T1 of the first portion P1 in the Z direction.

[0036] For example, the thickness T4 in the X direction of the second tungsten-containing layer 32c included in the second portion P2 is greater than the thickness T3 in the Z direction of the second tungsten-containing layer 32c included in the first portion P1. The thickness T5 in the Z direction of the second titanium nitride-containing layer 32b included in the first portion P1 is smaller than the thickness T6 in the X direction of the second titanium nitride-containing layer 32b included in the second portion P2.

[0037] An example of the material for each component is explained below. - p-type semiconductor region 1, p-type base region 2, n + p-type source region 3, p-type guard ring region 4, p + Shape contact area 5, p + The n-type collector region 6 and the n-type buffer region 7 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as p-type impurities. The gate electrode 10 and the gate wiring 25 contain a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 15 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The bottom electrode 21, the top electrode 22, the guard ring electrode 23, and the gate pad 24 contain a metal material such as aluminum or copper.

[0038] The first titanium-containing layer 31a, the second titanium-containing layer 32a, and the third titanium-containing layer 33a may be composed of titanium alone or may contain a metal other than titanium. + Shape source region 3 or p +The portion of the second titanium-containing layer 32a in contact with the p-type contact region 5 may contain titanium silicide formed by a reaction between titanium and silicon. The portion of the second titanium-containing layer 32a in contact with the p-type guard ring region 4 may contain titanium silicide. The first titanium nitride-containing layer 31b, the second titanium nitride-containing layer 32b, and the third titanium nitride-containing layer 33b may be composed of titanium nitride alone or may contain a metal compound other than titanium nitride. The first tungsten-containing layer 31c, the second tungsten-containing layer 32c, and the third tungsten-containing layer 33c may be composed of tungsten alone or may contain a metal other than tungsten. Preferably, the first titanium nitride-containing layer 31b, the second titanium nitride-containing layer 32b, and the third titanium nitride-containing layer 32c are composed substantially only of titanium nitride, and the first tungsten-containing layer 31c, the second tungsten-containing layer 32c, and the third tungsten-containing layer 33c are composed substantially only of tungsten.

[0039] The operation of the semiconductor device 100 will now be described. When the semiconductor device 100 is turned on, a voltage equal to or greater than the threshold is applied to the gate electrode 10 with respect to the upper electrode 22 and a positive voltage being applied to the lower electrode 21. A channel (inversion layer) is formed in the p-type base region 2, and electrons pass through the channel to form an n-type inversion layer. + Shape source region 3 to n - The holes are injected into the semiconductor region 1. + Collector region 6 to n - The n-type semiconductor region 1 is injected with - A conductivity modulation occurs in the p-type semiconductor region 1, reducing the electrical resistance of the semiconductor device 100. When the voltage applied to the gate electrode 10 then falls below the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 enters an off state.

[0040] Figures 8(a) to 10(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. Figures 8(a), 8(c), 9(a), 9(c), 10(a), and 10(c) show the manufacturing steps taken along line II-II in Figure 1. Figures 8(b), 8(d), 9(b), 9(d), 10(b), and 10(d) show the manufacturing steps taken along line III-III in Figure 1.

[0041] First, n - A semiconductor substrate including a semiconductor region 1 is prepared. - On top of the p-type semiconductor region 1, a p-type base region 2 and an n-type + p-type source region 3, p-type guard ring region 4, p + A contact region 5, a gate electrode 10, a gate insulating layer 11, and an insulating layer 15 are formed. As a result, the structure ST shown in FIGS. 8(a) and 8(b) is obtained. - The p-type semiconductor region 1 includes a first region 1a and a second region 1b. The direction from the first region 1a toward the p-type base region 2 is parallel to the Z direction.

[0042] As shown in FIGS. 8(c) and 8(d), a first opening OP1 and a second opening OP2 are formed in the insulating layer 15 by photolithography and reactive ion etching (RIE). The first opening OP1 has a thickness of n + Shape source region 3 and p + The first opening OP1 is formed on the p-type contact region 5. The second opening OP2 is formed on the p-type guard ring region 4. The width W4 of the second opening OP2 is wider than the width W3 of the first opening OP1.

[0043] A titanium-containing layer 30a containing titanium is formed along the inner surface of the first opening OP1 and the inner surface of the second opening OP2 by chemical vapor deposition (CVD). A titanium nitride-containing layer 30b containing titanium nitride is formed on the titanium-containing layer 30a by CVD. A tungsten-containing layer 30c containing tungsten is formed on the titanium nitride-containing layer 30b by CVD. As shown in FIGS. 9(a) and 9(b), the first opening OP1 is filled with the tungsten-containing layer 30c. The second opening OP2 is wider than the first opening OP1 and is therefore not filled with the tungsten-containing layer 30c.

[0044] The upper portion of the tungsten-containing layer 30c is removed by RIE, and the upper surface of the tungsten-containing layer 30c is recessed. As shown in FIG. 9(c), above the first region 1a, the tungsten-containing layer 30c formed on the insulating layer 15 is removed, while the first opening OP1 remains filled with the tungsten-containing layer 30c. As shown in FIG. 9(d), above the second region 1b, the tungsten-containing layer 30c formed on the insulating layer 15 and at the bottom of the second opening OP2 is removed. Furthermore, a portion of the titanium nitride-containing layer 30b is removed at the bottom of the second opening OP2. As a result, the thickness of the titanium nitride-containing layer 30b formed at the bottom of the second opening OP2 becomes smaller than the thickness of the titanium nitride-containing layer 30b formed at the bottom of the first opening OP1.

[0045] The tungsten-containing layer 30c is formed again by CVD. As a result, the thickness of the tungsten-containing layer 30c increases, as shown in Figures 10(a) and 10(b). The tungsten-containing layer 30c is also formed again at the bottom of the second opening OP2 where the titanium nitride-containing layer 30b was previously exposed.

[0046] A metal layer is formed on the tungsten-containing layer 30c by sputtering. The metal layer, tungsten-containing layer 30c, titanium nitride-containing layer 30b, and titanium-containing layer 30a are patterned by RIE. The titanium-containing layer 30a, titanium nitride-containing layer 30b, and tungsten-containing layer 30c formed above the second region 1b are separated from the titanium-containing layer 30a, titanium nitride-containing layer 30b, and tungsten-containing layer 30c formed above the first region 1a. Above the second region 1b, the titanium-containing layer 30a, titanium nitride-containing layer 30b, and tungsten-containing layer 30c are separated into multiple layers. This forms a first contact 31 and a second contact 32. The metal layer is patterned to form an upper electrode 22, a guard ring electrode 23, and a gate pad 24.

[0047] n - until the semiconductor region 1 reaches a predetermined thickness, - The bottom surface of the semiconductor region 1 is ground. - An n-type impurity is ion-implanted into the lower surface of the n-type semiconductor region 1 to form an n-type buffer region 7. A p-type impurity is ion-implanted into the lower surface of the n-type buffer region 7 to form a p-type + As shown in FIG. 10(c) and FIG. 10(d), a p + A lower electrode 21 is formed in contact with the collector region 6. In this way, the semiconductor device 100 according to the embodiment is manufactured.

[0048] 11(a) to 11(d) are cross-sectional views showing a manufacturing method according to a first reference example. In the manufacturing method according to the first reference example, the width of the first opening OP1 is the same as the width of the second opening OP2, as shown in Figures 11(a) and 11(b). As a result, the width of the first contact 31 can be the same as the width of the second contact 32, as shown in Figures 11(c) and 11(d).

[0049] In the manufacturing method according to the first reference example, the thickness of the insulating layer 15 formed above the first region 1a is different from the thickness of the insulating layer 15 formed above the second region 1b. Therefore, the focal position of photolithography used to form the first opening OP1 above the first region 1a is different from the focal position of photolithography used to form the second opening OP2 above the second region 1b. If the width of the second opening OP2 and the width of the first opening OP1 are made the same, it becomes difficult to ensure a focus margin. The focus margin is a margin that allows the pattern dimensions to be within an allowable range when the focus is shifted from the design position. As a result, the yield of semiconductor devices may decrease.

[0050] To address this issue, in the embodiment of the present invention, as shown in FIGS. 8(c) and 8(d), the width of the second opening OP2 is wider than the width of the first opening OP1. Therefore, the second opening OP2 is easier to form than in the first reference example. As a result, the yield of semiconductor devices can be improved. Furthermore, when the width of the second opening OP2 is wider than the width of the first opening OP1, the width of the second contact 32 can be wider than the width of the first contact 31, as shown in FIGS. 2, 3, 5, and 6. As a result, the contact resistance between the p-type guard ring region 4 and the second contact 32 can also be reduced. The p-type guard ring region 4 and the guard ring electrode 23 can be electrically connected more reliably. For example, the expansion of the depletion layer in the termination region of the semiconductor device 100 can be more stabilized.

[0051] 12(a) to 12(b), 13(a) and 13(b) are cross-sectional views showing a manufacturing method according to a second reference example. In the manufacturing method according to the second reference example, as shown in Figures 12(a) and 12(b), the width of the second opening OP2 is wider than the width of the first opening OP1. Figures 12(c) and 12(d) show a state in which the titanium-containing layer 30a, the titanium nitride-containing layer 30b, and the tungsten-containing layer 30c have been formed. The first opening OP1 is filled with the tungsten-containing layer 30c. On the other hand, the second opening OP2 is not completely filled with the tungsten-containing layer 30c.

[0052] When RIE is performed in this state, the tungsten-containing layer 30c formed at the bottom of the second opening OP2 is removed, and the titanium nitride-containing layer 30b is exposed at the bottom of the second opening OP2. A portion of the exposed titanium nitride-containing layer 30b is removed by RIE. As a result, the thickness of that portion of the titanium nitride-containing layer 30b is reduced.

[0053] 13(a) and 13(b) show a state in which the upper electrode 22 has been formed thereafter. The tungsten-containing layer 30c has been removed at the bottom of the second opening OP2. As a result, the tungsten-containing layer 30c is not present between the p-type guard ring region 4 and the upper electrode 22, and only the titanium-containing layer 30a and the titanium nitride-containing layer 30b are present. Furthermore, at the bottom of the second opening OP2, the thickness of the titanium nitride-containing layer 30b is smaller than the thickness of the other portions of the titanium nitride-containing layer 30b.

[0054] The titanium-containing layer 30a, titanium nitride-containing layer 30b, and tungsten-containing layer 30c function as barrier layers that suppress reactions between the semiconductor material and the metal material contained in the electrodes. When a semiconductor device manufactured by the manufacturing method according to the second reference example is used, the tungsten-containing layer 30c is absent between the p-type guard ring region 4 and the guard ring electrode 23, and the titanium nitride-containing layer 30b is also thin. This can lead to reactions between the semiconductor material of the p-type guard ring region 4 and the metal material of the guard ring electrode 23. For example, the metal material (especially aluminum) of the guard ring electrode 23 can diffuse into the p-type guard ring region 4, resulting in a phenomenon known as an alloy spike.

[0055] To address this issue, in an embodiment of the present invention, after etching the tungsten-containing layer 30c as shown in FIGS. 9(c) and 9(d), the tungsten-containing layer 30c is formed again as shown in FIGS. 10(a) and 10(b). This results in the tungsten-containing layer 30c being again disposed at the bottom of the second opening OP2. Furthermore, the thickness of the tungsten-containing layer 30c formed the second time is smaller than the thickness of the tungsten-containing layer 30c formed the first time. A layer containing tungsten has greater stress than other layers. By forming the second tungsten-containing layer 30c thin, stress generated in the semiconductor device 100 can be reduced, thereby reducing warpage of the semiconductor device 100.

[0056] According to the manufacturing method of the embodiment, a three-layer structure consisting of the second titanium-containing layer 32a, the second titanium nitride-containing layer 32b, and the second tungsten-containing layer 32c is formed in the second contact 32 between the p-type guard ring region 4 and the guard ring electrode 23. This makes it possible to suppress reaction between the semiconductor material of the p-type guard ring region 4 and the metal material of the guard ring electrode 23, compared to the semiconductor device according to the second reference example shown in FIG. 13(b). This makes it less likely that the semiconductor device 100 will be destroyed by alloy spikes, improving the reliability of the semiconductor device 100.

[0057] According to the embodiment, the contact resistance between the p-type guard ring region 4 and the guard ring electrode 23 can be reduced, while the reaction between the semiconductor material of the p-type guard ring region 4 and the metal material of the guard ring electrode 23 can be suppressed.

[0058] In the semiconductor device 100, a portion of the guard ring electrode 23 is formed inside the second opening OP2. That is, as shown in FIG. 6 , a portion of the guard ring electrode 23 is located between a portion of the second contact 32 and another portion of the second contact 32 in the X direction. As described above, the guard ring electrode 23 contains a metal such as aluminum or copper. The electrical resistivity of these metals is lower than that of tungsten. By positioning a portion of the guard ring electrode 23 between a portion of the second contact 32 and another portion of the second contact 32, the electrical resistance between the p-type guard ring region 4 and the guard ring electrode 23 can be reduced.

[0059] 6, the second contact 32 includes a first portion P1 and a second portion P2, and the thickness T1 of the first portion P1 is smaller than the thickness T2 of the second portion P2. With this structure, the lower end of the guard ring electrode 23 is positioned closer to the p-type guard ring region 4 than when the thickness T2 is larger than the thickness T1. This further reduces the electrical resistance between the p-type guard ring region 4 and the guard ring electrode 23.

[0060] FIG. 14 is a cross-sectional view showing another example of the second contact. As shown in Fig. 14, the width of the second contact 32v may be narrower than the example shown in Fig. 6. However, even in this case, the width W2 of the bottom of the second contact 32v is wider than the width W1 (shown in Fig. 5) of the bottom of the first contact 31. For example, the width W2 is 1.1 to 1.4 times the width W1.

[0061] 14, in second contact 32v, thickness T1 of first portion P1 in the Z direction can be greater than thickness T2 of second portion P2 in the X direction. Thickness T3 of second tungsten-containing layer 32c included in first portion P1 can be greater than thickness T4 of second tungsten-containing layer 32c included in second portion P2 in the X direction.

[0062] 14, a portion of guard ring electrode 23 is also located between a portion of second contact 32v and another portion of second contact 32v in the X direction, thereby reducing the electrical resistance between p-type guard ring region 4 and guard ring electrode 23.

[0063] 15(a) to 15(d), 16(a), and 16(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. To form the second contact 32v shown in FIG. 14, first, steps similar to those shown in FIGS. 8(a) to 8(d) are performed to form a first opening OP1 and a second opening OP2 as shown in FIGS. 15(a) and 15(b). The width of the second opening OP2 is formed narrower than the width of the second opening OP2 shown in FIG. 8(d). Next, a titanium-containing layer 30a, a titanium nitride-containing layer 30b, and a tungsten-containing layer 30c are formed. At this time, as shown in FIGS. 15(c) and 15(d), the second opening OP2 is filled with the tungsten-containing layer 30c except for the upper part thereof.

[0064] Then, the upper portion of the tungsten-containing layer 30c is etched so as to leave the tungsten-containing layer 30c formed at the bottom of the second opening OP2. As a result, as shown in FIGS. 16(a) and 16(b), the upper surface of the tungsten-containing layer 30c above the first region 1a is planarized while the tungsten-containing layer 30c remains at the bottom of the second opening OP2. After that, the upper electrode 22, the guard ring electrode 23, the gate pad 24, and the lower electrode 21 are formed, thereby manufacturing the semiconductor device 100 having the second contact 32v shown in FIG.

[0065] Even when the second contact 32v is used, as in the above-described embodiment, the contact resistance between the p-type guard ring region 4 and the guard ring electrode 23 can be reduced while suppressing the reaction between the semiconductor material of the p-type guard ring region 4 and the metal material of the guard ring electrode 23.

[0066] The width W3 of the third contact 33 may also be formed to be narrower than that of the example shown in Fig. 7. In this way, the third contact 33 can be formed so that it has a structure similar to that of the second contact 32v.

[0067] 17 and 18 are perspective cross-sectional views showing a part of a semiconductor device according to a modification of the embodiment. The embodiment of the present invention can also be applied to a MOSFET. The semiconductor device 110 according to the modification shown in FIGS. 17 and 18 is a MOSFET. + Instead of the n-type collector region 6 and the n-type buffer region 7, + The semiconductor device 100 differs from the semiconductor device 100 in that it includes a drain region 8 .

[0068] n + The drain region 8 is provided on the lower electrode 21 and is electrically connected to the lower electrode 21. - The semiconductor region 1 is n + The n-type drain region 8 is provided on the n-type drain region 8. - The n-type impurity concentration in the n-type semiconductor region 1 is + The n-type impurity concentration in the n-type drain region 8 is lower than that in the n-type drain region 8 .

[0069] In the semiconductor device 110, the second contact 32 including the second tungsten-containing layer 32c is provided, thereby reducing the contact resistance between the p-type guard ring region 4 and the guard ring electrode 23 while suppressing the reaction between the semiconductor material of the p-type guard ring region 4 and the metal material of the guard ring electrode 23.

[0070] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first region and a second region located around the first region along a first plane perpendicular to a first direction from the first electrode toward the first region; a second semiconductor region of a second conductivity type provided on the first region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second region and spaced apart from the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region via a first contact including: a first titanium-containing layer containing titanium; a first titanium nitride-containing layer containing titanium nitride and provided on the first titanium-containing layer; and a first tungsten-containing layer containing tungsten and provided on the first titanium nitride-containing layer; a third electrode provided on the fourth semiconductor region via a second contact including a second titanium-containing layer containing titanium, a second titanium nitride-containing layer containing titanium nitride and provided on the second titanium-containing layer, and a second tungsten-containing layer containing tungsten and provided on the second titanium nitride-containing layer; A semiconductor device comprising: (Feature 2) a plurality of second semiconductor regions are provided in the second direction; 2. The semiconductor device according to claim 1, wherein the fourth semiconductor region is located along the first surface around a plurality of the second semiconductor regions. (Feature 3) a plurality of the fourth semiconductor regions are provided spaced apart from each other in a direction from the first region toward the second region; 3. The semiconductor device according to claim 2, wherein a plurality of the third electrodes are provided on the plurality of the fourth semiconductor regions via a plurality of the second contacts, respectively. (Feature 4) 4. The semiconductor device according to claim 1, wherein the length in the second direction of the portion of the second contact that contacts the fourth semiconductor region is longer than the length in the second direction of the portion of the first contact that contacts the third semiconductor region. (Feature 5) an insulating layer aligned with the second contact in the second direction; The second contact is a first portion located between the fourth semiconductor region and the third electrode in the first direction; a second portion located between the insulating layer and the third electrode in the second direction; 5. The semiconductor device according to claim 1, comprising: (Feature 6) 6. The semiconductor device according to claim 5, wherein the thickness of the first portion in the first direction is smaller than the thickness of the second portion in the second direction. (Feature 7) 6. The semiconductor device according to claim 5, wherein the thickness of the first portion in the first direction is greater than the thickness of the second portion in the second direction. (Feature 8) 7. The semiconductor device of claim 6, wherein the second tungsten-containing layer included in the second portion has a thickness greater than a thickness of the second tungsten-containing layer included in the first portion. (Feature 9) 9. The semiconductor device according to claim 6, wherein the thickness of the second titanium nitride-containing layer included in the first portion is smaller than the thickness of the first titanium nitride-containing layer in the first direction. (Feature 10) a first semiconductor region of a first conductivity type including a first region and a second region located around the first region along a first surface; a second semiconductor region of a second conductivity type provided on the first region, the second semiconductor region having a first direction from the first region toward the second semiconductor region being perpendicular to the first surface; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second region and spaced apart from the second semiconductor region; an insulating layer having a first opening located above the third semiconductor region and a second opening located above the fourth semiconductor region; forming a titanium-containing layer along an inner surface of the first opening and an inner surface of the second opening for the structure; forming a titanium nitride-containing layer containing titanium nitride on the titanium-containing layer; forming a tungsten-containing layer containing tungsten on the titanium nitride-containing layer; and forming a tungsten-containing layer again after etching the upper surface of the tungsten-containing layer. (Feature 11) a first semiconductor region of a first conductivity type including a first region and a second region located around the first region along a first surface; a second semiconductor region of a second conductivity type provided on the first region, the second semiconductor region having a first direction from the first region toward the second semiconductor region being perpendicular to the first surface; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second region and spaced apart from the second semiconductor region; an insulating layer having a first opening located above the third semiconductor region and a second opening located above the fourth semiconductor region; forming a titanium-containing layer along an inner surface of the first opening and an inner surface of the second opening for the structure; forming a titanium nitride-containing layer containing titanium nitride on the titanium-containing layer; forming a tungsten-containing layer containing tungsten on the titanium nitride-containing layer; an upper portion of the tungsten-containing layer is etched so as to leave the tungsten-containing layer formed on the bottom of the second opening.

[0071] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0072] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0073] 1:n - p-type semiconductor region, 1a: first region, 1b: second region, 1c: third region, 2: p-type base region, 3: n + 4: p-type source region, 5: p-type guard ring region + Shape contact area, 6:p + collector region, 7:n buffer region, 8:n +drain region, 10: gate electrode, 11: gate insulating layer, 15: insulating layer, 21: lower electrode, 22: upper electrode, 23: guard ring electrode, 24: gate pad, 25: gate wiring, 30a: titanium-containing layer, 30b: titanium nitride-containing layer, 30c: tungsten-containing layer, 31: first contact, 31a: first titanium-containing layer, 31b: first titanium nitride-containing layer, 31c: first tungsten-containing layer, 32, 32v: second contact, 32a: second titanium-containing layer, 32b: second titanium nitride-containing layer, 32c: second tungsten-containing layer, 33: third contact, 33a: third titanium-containing layer, 33b: third titanium nitride-containing layer, 33c: third tungsten-containing layer, 100, 110: semiconductor device, OP1: 1st opening, OP2: 2nd opening, P1: 1st part, P2: 2nd part, ST: Structure, T1~T6: Thickness, W1~W4: Width

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode, the first semiconductor region including a first region and a second region positioned around the first region along a first plane perpendicular to a first direction from the first electrode toward the first region; a second semiconductor region of a second conductivity type provided on the first region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second region and spaced apart from the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region via a first contact including: a first titanium-containing layer containing titanium; a first titanium-nitride-containing layer containing titanium nitride and provided on the first titanium-containing layer; and a first tungsten-containing layer containing tungsten and provided on the first titanium-nitride-containing layer; a third electrode provided on the fourth semiconductor region via a second contact including: a second titanium-containing layer containing titanium; a second titanium-nitride-containing layer containing titanium nitride and provided on the second titanium-containing layer; and a second tungsten-containing layer containing tungsten and provided on the second titanium-nitride-containing layer; A semiconductor device comprising:

2. a plurality of second semiconductor regions are provided in the second direction; The semiconductor device according to claim 1 , wherein the fourth semiconductor region is located along the first surface around a plurality of the second semiconductor regions.

3. a plurality of the fourth semiconductor regions are provided spaced apart from each other in a direction from the first region toward the second region; 3. The semiconductor device according to claim 2, wherein a plurality of said third electrodes are provided on said plurality of fourth semiconductor regions via a plurality of said second contacts, respectively.

4. 2. The semiconductor device according to claim 1, wherein a length in the second direction of a portion of the second contact that contacts the fourth semiconductor region is longer than a length in the second direction of a portion of the first contact that contacts the third semiconductor region.

5. an insulating layer aligned with the second contact in the second direction; The second contact is a first portion located between the fourth semiconductor region and the third electrode in the first direction; a second portion located between the insulating layer and the third electrode in the second direction; The semiconductor device according to any one of claims 1 to 4, comprising:

6. The semiconductor device according to claim 5 , wherein the thickness of said first portion in said first direction is smaller than the thickness of said second portion in said second direction.

7. The semiconductor device according to claim 5 , wherein the thickness of said first portion in said first direction is greater than the thickness of said second portion in said second direction.

8. The semiconductor device according to claim 6 , wherein the thickness of the second tungsten-containing layer included in the second portion is greater than the thickness of the second tungsten-containing layer included in the first portion.

9. 7. The semiconductor device according to claim 6, wherein the thickness of said second titanium nitride-containing layer included in said first portion is smaller than the thickness of said first titanium nitride-containing layer in said first direction.

10. a first semiconductor region of a first conductivity type including a first region and a second region located around the first region along a first surface; a second semiconductor region of a second conductivity type provided on the first region, the second semiconductor region being perpendicular to the first surface in a first direction from the first region toward the second semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second region and spaced apart from the second semiconductor region; an insulating layer having a first opening located above the third semiconductor region and a second opening located above the fourth semiconductor region; forming a titanium-containing layer along an inner surface of the first opening and an inner surface of the second opening for the structure; forming a titanium nitride-containing layer containing titanium nitride on the titanium-containing layer; forming a tungsten-containing layer containing tungsten on the titanium nitride-containing layer; and forming a tungsten-containing layer again after etching the upper surface of the tungsten-containing layer.

11. a first semiconductor region of a first conductivity type including a first region and a second region located around the first region along a first surface; a second semiconductor region of a second conductivity type provided on the first region, the second semiconductor region being perpendicular to the first surface in a first direction from the first region toward the second semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type provided on the second region and spaced apart from the second semiconductor region; an insulating layer having a first opening located above the third semiconductor region and a second opening located above the fourth semiconductor region; forming a titanium-containing layer along an inner surface of the first opening and an inner surface of the second opening for the structure; forming a titanium nitride-containing layer containing titanium nitride on the titanium-containing layer; forming a tungsten-containing layer containing tungsten on the titanium nitride-containing layer; an upper portion of the tungsten-containing layer is etched so as to leave the tungsten-containing layer formed on the bottom of the second opening.

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