Storage device having a programmed cell storage density mode that is a function of capacity utilization of the storage device

Abstract

To speed up the performance of a storage device composed of memory chips having high-density but low-speed cells.SOLUTION: A solid state drive (SSD), which is a storage device, includes a controller and a plurality of flash memory chips. The plurality of flash memory chips includes a three dimensional stack of multi-bit storage cells, the multi-bit storage cells having a plurality of storage density modes. The controller programs the multi-bit storage cells in a low density storage mode up to a storage capacity threshold of the storage device of at least 25% and programs the multi-bit storage cells in a high density storage mode once the storage capacity threshold is reached.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention generally relates to storage devices having programmed cell storage density modes that are a function of capacity utilization of the storage device. [Background technology]

[0002] As computing systems become increasingly powerful, their memory storage needs continue to grow. In response to this trend, manufacturers of mass storage semiconductor chips are developing techniques for storing more than one bit per storage cell. Unfortunately, such cells may exhibit slower programming times compared to their binary storage cell predecessors. Therefore, manufacturers of mass storage devices are developing new techniques to speed up the performance of storage devices composed of memory chips with denser but slower cells. [Brief explanation of the drawings]

[0003] A better understanding of the present invention can be obtained from the following detailed description taken in conjunction with the following drawings.

[0004] [Figure 1a] 1 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. [Figure 1b] 1 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. [Figure 1c] 1 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. [Figure 1d] 1 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. [Figure 1e] 1 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. [Figure 1f] 1 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization. [Figure 1g] 1 shows patterns for programming multi-bit flash storage cells as a function of SSD storage capacity utilization.

[0005] [Figure 2] Charge transfer from MLC mode to QLC mode is shown.

[0006] [Figure 3] We show an SSD capable of implementing the write patterns of Figures 1a to 1g.

[0007] [Figure 4] The method performed by the SSD of FIG.

[0008] [Figure 5] 1 illustrates a computing system. DETAILED DESCRIPTION OF THE INVENTION

[0009] The structure of a flash memory device can be understood as a three-dimensional arrangement of storage cells consisting of an array of columns that extend vertically above a semiconductor substrate, each column containing a number of individual storage cells stacked on top of one another. A storage block corresponds to a number of such columns. To access specific ones of the storage cells within a storage cell block, word line wire structures ("word lines") are coupled to storage cells located in the same vertical direction in different columns of the storage cell block.

[0010] For example, if each column of a storage block is composed of a vertical stack of eight storage cells, eight different word lines may be used to access respective cells in the column of storage blocks at eight different storage levels (e.g., a first word line may be coupled to the lowest cell in each of the columns, a second word line may be coupled to the second-lowest cell in each of the columns, etc.). In the case of flash memory, where each storage cell can store more than one bit, multiple pages of information may be accessed through a single word line. However, mass storage devices have traditionally been accessed (read / written) in blocks of data, each consisting of multiple pages. Flash memory devices capable of storing more than one bit per storage cell typically allow access to different pages by activating a single word line within the storage block in which the pages are stored.

[0011] A memory block is generally the smallest unit in which storage cells can be erased (cells in the same block are erased together), and a page is generally the smallest unit in which cells can be written, or "programmed." Thus, for example, if a host commands an SSD to write multiple pages, multiple of those pages can be programmed within the same memory block by activating a single word line. The number of word lines activated to fully execute a write command depends on how many pages are involved in the write and how many pages are accessible per word line. A single flash memory chip is also typically made up of multiple planes, each containing a unique set of storage blocks within the chip.

[0012] As mentioned above, different flash memory technologies are generally characterized by how many bits can be stored per storage cell. Specifically, single-level cells (SLC) store one bit per cell, multi-level cells (MLC) store two bits per cell, ternary-level cells (TLC) store three bits per cell, and quad-level cells (QLC) store four bits per cell. While only SLC cells can store two logical states ("1" or "0") per cell, MLC, TLC, and QLC cell types, which can be characterized as different types of "multi-bit" storage cells, each significantly expand the storage capacity of a flash device because more than two digital states can be stored in a single cell (e.g., four digital states can be stored in an MLC cell, eight digital states can be stored in a TLC cell, and 16 logical states can be stored in a QLC cell).

[0013] However, there is a trade-off between storage density per cell and access time per cell. That is, generally, the more bits a storage cell stores, the longer the amount of time required to write information to the cell. Here, storage cells that store more bits can be understood to have tighter charge storage tolerances than storage cells that store fewer bits. That is, cells that store more bits have a smaller amount of charge that represents the difference between the different logic states that the cell can store, while cells that store fewer bits have a larger amount of charge that represents the difference between the logic states that the cell can store.

[0014] Flash cells are programmed or erased by pumping in charge. Cells that store fewer bits per invocation have a larger difference between their stored charge states than cells that store more bits per cell and use a more "coarse-grained" pumping process. This pumping process applies a larger charge increment in fewer pumping cycles than cells that store more bits per cell and use a more "fine-grained" pumping process. This pumping process applies a smaller charge increment (at least the maximum pumped charge amount) in more pumping cycles. The fewer pumping cycles associated with cells that store fewer bits means that such cells will exhibit, on average, shorter program access times compared to cells that store more bits.

[0015] Therefore, next generation flash manufacturing technologies will bring increased performance in terms of storage capacity per cell, but at the same time performance will decrease in terms of average program time per cell.

[0016] To address this trade-off, flash-based storage devices such as solid-state drives (SSDs) implement storage buffers composed of cells that store fewer bits per cell than their underlying manufacturing technology can store. For example, an SSD composed of QLC flash memory chips uses a percentage of the QLC cells to operate in either SLC or MLC mode. The cells operating in the lower-density mode are used by the SSD as a cache-like buffer into which newly input data is written. By writing new input data to a buffer composed of lower-density but faster cells, the SSD realizes faster raw program access times.

[0017] However, there are problems with implementing such a buffer. The first problem is that the buffer's contents must be constantly "cleared" by writing the contents back to the high-density cells as a background process. Now, typically, an SSD buffer occupies only more than 1 or 2 percent of the SSD's total storage capacity. If the buffer's contents are not regularly written back to the high-density cells, the buffer will fill up and become unavailable for subsequent writes to the SSD. Unfortunately, the background process itself can block the buffer for new write commands (if the buffer is being cleared when a new write command arrives, the write command must wait until the buffer is cleared or the background process can be interrupted). Additionally, the background process increases the overall complexity of the SSD's operation, increasing, for example, power consumption, cost, and / or failure mechanisms.

[0018] 1a through 1f show the improved SSD design operating in a low-density mode, using a much larger percentage of the device's high-density storage cells. In addition, these cells are more active than the device's standard storage cells, but less active than the device's buffer. As a result, the issues just discussed regarding the ongoing execution of highly managed background processes should be reduced.

[0019] As shown in FIG. 1a, an SSD can be viewed as being composed of multiple flash memory chips, each consisting of N storage blocks. For simplicity, the exemplary architecture of FIG. 1a assumes that there are only two flash memory chips (Die_0 and Die_1) in the SSD. However, one skilled in the art could easily apply the teachings of the exemplary device described herein to other devices containing more than two flash memory chips. Both of these memory devices are composed of four planes (Plane_0 through Plane_3). Each plane contains N storage blocks (thus, there are 4×N storage blocks per memory device). Each storage block contains M word lines, and each word line supports access to four different pages (lower (L), upper (U), spare (X), and top (T)) when operating in its highest-density QLC mode. FIG. 1a illustrates the initial state, for example, when the device is first used and no random customer data has yet been stored.

[0020] Figure 1b shows the state of the SSD after the first page number 101 has been programmed into the device. Here, the SSD includes a controller that manages a mapping table (also called an address translation table) that maps logical addresses to physical addresses. When a host sends a block of data to be written to the SSD, the host also attaches a block address to the data. This block address is called a logical block address (LBU). The SSD then writes the data block to the SSD and associates, in the mapping table, the LBU of the data with the physical locations within the SSD where the pages of data for that block are stored. These specific physical locations are specified by physical block addresses (PBAs), which uniquely identify one or more die, planes, blocks, word lines, and page resources within the SSD where the pages are stored.

[0021] As can be seen in Figure 1b, an exemplary SSD sequentially programs input pages into the same memory block and word line (WL) locations across different planes and different memory chips, thereby observing that the consumed storage capacity extends horizontally from left to right across the same block and word line locations in Figure 1b. Different SSD implementations may use different write patterns. For example, in another approach, the SSD may sequentially write input pages across the same die and plane resources across different block and word line resources (in this case, it will be observed that the consumed storage capacity extends vertically from top to bottom along the same plane within the same die).

[0022] As can be seen in Figure 1b, programming these first few pages involves writing to cells operating at a lower memory capacity per cell (MLC) than the highest density supported by the underlying manufacturing technology (QLC). Writing pages to cells operating in a lower-density MLC mode improves the program access time performance of the SSD compared to an approach in which pages are written only to cells operating in the highest-density QLC mode. That is, as noted above, lower-capacity cells have lower write access times than higher-density cells.

[0023] Additionally, due to the lower storage density, only half of the page capacity per word line is consumed. That is, for example, with cells operating in MLC mode, where only two bits are stored per cell, only two pages can be stored per word line. As explained in further more detail below, the unused half of the page storage capacity can be consumed when a threshold amount of the full capacity of the SSD's storage cells is consumed, which can therefore justify switching these cells from the low-density MLC mode to the high-density QLC mode.

[0024] The pattern of writing to only half of a word line's potential page storage is directly visible in FIG. 1b, in that only two pages (L and U) at block address 0 (BA=0) and word line address 0 (WL=0) are written across multiple planes and dies. Here, because 50% of the storage block's potential capacity is unused during the initial programming 101 of the pages into the SSD, two blocks are required to write four pages of information (even though four pages of information could be stored in a single word line in a single block in QLC mode). That is, because the cell is operating in low-density mode (two bits per cell mode), each block can only store two pages per word line. Therefore, the second block and word line combination is required to store the third and fourth pages. In contrast, if the cell were operating in high-density mode (four bits per cell mode), four pages could be programmed per block and word line combination.

[0025] Again, in an alternative implementation using a write pattern in which data is written sequentially across different blocks and word lines of the same plane and die, after pages L and U are written to BA=0 and WL=0 of plane 0 of die 1, the SSD may write pages L and U to BA=0 and WL=1 of plane 0 of die 1, for example. In this particular embodiment, again, only half of the potential storage capacity along a particular word line is programmed. Thus, there are an infinite number of different sequences of storage block and word line combinations that can be used to define a particular programming pattern as new pages being written to the SSD. For ease of discussion, the remainder of this description will primarily refer only to the embodiment in which the page write pattern is shown in Figures 1b through 1f.

[0026] FIG. 1c shows a further state of the SSD after an additional new page has been programmed into the SSD in low-density mode. Now, as can be seen from FIG. 1c, all of the L and U page locations at BA=0 and WL=0 have been written at a lower per-cell storage density across all sides of both dies in the SSD. Thus, because all cells at locations BA=0 and WL=0 across the SSD have been written in low-density mode, such cells are at their maximum capacity for their current mode (two pages per word line), but not at their maximum potential capacity (four pages per word line). That is, as can be seen from FIG. 1c, page locations X and T remain untouched across these same storage blocks, sides, and dies, resulting in a 50% reduction in utilization of the potential maximum storage capacity of these blocks. However, because the storage cells operated in a lower-density storage mode, programming of these pages can now be accomplished in less time.

[0027] 1d shows another further state of the SSD after an additional number of pages, whose combined data volume corresponds to 50% of the SSD's maximum capacity, have been programmed into the SSD according to the write pattern described above. Here, again, the written cells are operating in a low-density mode in which the SSD's write access time has been improved to 50% utilization of the SSD's storage capacity. Referring back to the discussion earlier in this description that traditional SSD buffers typically only utilize 1% or 2% of an SSD's storage cells, it should be noted that the improved approach described herein should exhibit SSD performance "as if" the SSD were composed of a buffer that consumed 50% of the SSD's storage cells.

[0028] Importantly, with such a large effective buffer, due to the buffer's small size, there is little or no need to implement costly and highly managed background processes that constantly read information from the buffer to create available space. Rather, the effective buffer of the improved approach has an initial capacity that is 50% of the storage capacity of the SSD. With such a large effective buffer, at least initially, there is no need to continuously read data from the effective buffer; rather, programmed data can simply remain in place according to standard cell storage usage models.

[0029] Figures 1e through 1f show the write pattern continuing from the state of Figure 1d onward after the SSD has programmed more pages into the SSD. Here, after the state of Figure 1d where 50% of the SSD's storage capacity has been consumed but 100% of the storage cells are being used at 50% of their maximum storage capacity, the cells need to be switched from MLC mode to their full QLC mode to accommodate the storage of more pages.

[0030] Therefore, as can be seen in FIG. 1e, the write pattern repeats for a second pass, but in QLC density mode rather than MLC density mode. Therefore, two additional pages of storage capacity are available along all BA=0 and WL=0 locations across different planes and dies of the SSD. Specifically, FIG. 1e shows the previously unused capacity of page locations X and T at BA=0 and WL=0 locations across different planes and dies of the SSD being consumed with data at these locations. Writing pages in maximum cell density mode may slow SSD performance compared to the initial 50% cell utilization due to the longer write times associated with QLC mode. In the alternative approach described above, the SSD exhibits a faster rate of utilization for the first 50% of capacity of an MLC-like SSD. (From FIG. 1d to FIG. 1e) After the first 50% of the SSD's storage capacity is utilized, the SSD's performance experiences some degradation due to the introduction of the slower QLC programming process.

[0031] According to one approach, to program cells that store MLC data along with QLC data, the charge distribution in the original MLC mode is converted to QLC mode according to the charge distribution transfer diagram provided in FIG. 2. As can be seen, the two bits stored per cell are converted to the two least significant bits in the four-bit QLC mode. Comparing FIG. 2 with FIGS. 1a through 1f, the L and U pages occupy the least significant bits of the four bits stored in the new QLC mode, while the X and T pages of the newly written pages occupy the two most significant bits of the four bits stored in QLC mode. In one embodiment, the four stored bits per cell are organized in terms of pages, which represent them from most significant bit to least significant bit as T, X, U, and L.

[0032] In various embodiments, to properly perform charge redistribution from MLC to QLC when writing the second pass of the write pattern at QLC density, a pair of bits originally stored in a cell during the first pass in MLC mode is read from the cell and then combined with the new data to be written to the cell. The combined four bits (the original two bits and the new two bits) are then programmed into the cell.

[0033] Figures 1f and 1g show the following states, which are equivalent to Figures 1c and 1d, respectively, in terms of the number of additional stored pages. As can be seen from Figures 1f and 1g, the cells in the SSD are continually overwritten during the second pass in the maximum storage density per cell mode, thereby expanding the storage capacity of each cell by an additional two bits from each of the two additional pages X and T. Thus, at the state of the SSD in Figure 1g, the full storage capacity of the SSD has been reached.

[0034] In various embodiments, information maintained by the wear leveling function of an SSD can be used to minimize the perceived performance hit to the SSD as a result of switching to higher density, slower cells, where, as is known in the art, storage cells that are written to more frequently will wear out faster than cells that are written to less frequently.

[0035] Thus, the SSD's controller performs wear leveling, remapping frequently accessed "hot" blocks of information to infrequently accessed "colder" blocks. Here, the controller monitors the access rate (and / or total number of accesses) of the SSD's physical addresses and maintains an internal map that maps these physical addresses to the original LBUs provided by the host. Based on the monitored rate and / or count, the controller determines when particular blocks are considered "hot" and require swapping of their associated data, and when particular blocks are considered "cold" and can receive hot blocks of data. In traditional wear leveling approaches, information from colder blocks can also be swapped into hot blocks.

[0036] To reduce the impact of programming performance degradation observed once high-density cell storage mode begins to be utilized, hot and cold block data maintained by the wear leveling function can also be used to maintain hot pages in cells operating in MLC mode and cold pages in storage cells operating in QLC mode. For example, FIG. 1e shows an SSD in which a significant percentage of the SSD's storage cells are operating in MLC mode and a significant percentage of the SSD's storage cells are operating in QLC mode. Therefore, there may be a sufficient number of hot blocks in slower QLC cells and a sufficient number of cold blocks in faster MLC cells. Wear leveling data maintained by the controller can be used to intelligently swap the locations of these pages so that hot blocks are moved to faster MLC cells and cold blocks are moved to slower QLC cells.

[0037] Note that once capacity utilization drops to 50% or lower, the SSD may revert to operating entirely in MLC mode.

[0038] 3 illustrates an embodiment of an SSD 301 that can operate in accordance with the teachings provided above. As can be seen in FIG. 3, the SSD includes many storage cells 302 that can store more than one bit. In addition, most or all of the storage cells of the SSD are capable of operating in both MLC mode and QLC mode. Which one of these modes a particular one of these cells operates in depends on the storage capacity utilization of the SSD (e.g., at 50% or less of full capacity utilization, all cells operate in MLC mode; between 50% and 100% capacity utilization, some cells operate in MLC mode while other cells operate in QLC mode; and at 100% capacity utilization, all cells operate in QLC mode).

[0039] The SSD includes a controller 306. The controller 306 is responsible for determining which cells operate in MLC mode and which cells operate in QLC mode. According to one embodiment described in detail above, a first programming pass is applied to all cells operating in MLC mode, and then a second pass is applied to all cells operating in QLC mode. Capacity utilization information and / or information identifying which cells are operating in which mode 311 is maintained, for example, in a combined and / or unified memory and / or register area 310 within the controller 306. In one embodiment, such information is represented in an MLC bit / QLC bit or similar digital record for each physical address or some level of granularity (e.g., block ID) at which a set of cells is treated the same as a common group with respect to their MLC mode / QLC mode of operation.

[0040] Thus, when such granularity is at the block level, each block is identified in information 311, which further specifies the time when each of these blocks was first programmed in terms of MLC. At capacity utilization rates above 50%, if the SSD begins converting MLC cells to QLC cells, information 311 is changed to indicate QLC mode with each newly overwritten MLC block in QLC mode. By the time 100% capacity utilization is reached, information 311 for all blocks should indicate QLC mode. Information 311 may also specify which blocks are actually written. This allows controller 306 to determine the capacity utilization percentage. Moreover, as described above, information 311 may be used to enhance the wear leveling algorithm executed by controller 306. Specifically, the wear leveling algorithm executed by controller 306 may swap hot blocks from QLC blocks to MLC blocks and cold blocks from MLC blocks to QLC blocks.

[0041] The controller 306 is also coupled to a charge pump circuit 307, which is designed to generate different charge pump signal sequences for QLC and MLC modes, where the controller 306 informs the charge pump circuit 307 which signals (MLC or QLC) to apply for any particular programming sequence according to the controller's determination based on the capacity utilization of the SSD of which operating mode is appropriate for the cell being written.

[0042] The controller may be implemented as dedicated hardwired logic circuitry (e.g., hardwired application-specific integrated circuit (ASIC) state machines and support circuitry), programmable logic circuitry (e.g., field programmable gate arrays (FPGAs)), programmable logic devices (PLDs), logic circuitry designed to execute program code (e.g., embedded processors, embedded controllers, etc.), or any combination thereof. In embodiments in which at least some portions of controller 306 are designed to execute program code, the program code is stored in local memory (e.g., the same memory in which information 311 is maintained) and executed by the controller from there. An I / O interface 312 is coupled to controller 306 and may be compatible with industry-standard peripheral or storage interfaces (e.g., Peripheral Component Interconnect (PCIe), Advanced Technology Attachment / Integrated Drive Electronics (ATA / IDE), Universal Serial Bus (USB), IEEE 1394 ("Firewire"), etc.).

[0043] It is pertinent to recognize that other embodiments may utilize the teachings provided herein even if they deviate somewhat from the specific embodiment described above. In particular, other embodiments may change the percentage of SSD capacity utilization at which SSD operation changes new programming from MLC mode to QLC mode. For example, in one embodiment, cell writing begins in QLC mode when capacity reaches 25% instead of 50% (or any capacity between 25% and 50%). In this case, programming in QLC mode begins before the state of FIG. 1d is reached, for example. Various embodiments may also allow the user / host to configure at what capacity utilization percentage the switch to QLC mode begins. For example, an SSD may support configurable options of 25%, 30%, 33%, 40%, and 50%, or any capacity utilization percentage between 25% and 50%. Conceivably, a capacity utilization percentage less than 25% could also be used to trigger a switch to QLC mode.

[0044] This also relates to recognizing that the low-density mode of MLC and the high-density mode of QLC are merely exemplary, and other embodiments may have different low-density and / or high-density modes. For example, in one embodiment, the low-density is TLC and the high-density is QLC. Note that in this embodiment, switching to the high-density mode may occur when, for example, capacity utilization reaches 75% (when all cells are programmed with 3 bits per cell) or less. In another embodiment, the low-density is SLC and the high-density is QLC. Note that in this embodiment, switching to the high-density mode may occur when capacity utilization reaches 25% (when all cells are programmed with 1 bit per cell). Previous TLC / QLC SSDs had larger but slower effective buffers than SLC / QLC SSDs, which have smaller but faster effective buffers. Thus, the exact rate at which switching to the high-density mode occurs may also be a function of the particular low-density and high-density modes utilized.

[0045] The teachings herein may be applied to systems other than the specific SSD described above in connection with Figure 3. For example, the functionality of the controller 306 described above may be partially or wholly integrated into a host system.

[0046] 4 illustrates the above-mentioned method. The method includes programming (401) multi-bit storage cells of a plurality of flash memory chips to a low-density storage mode. The method also includes programming (402) multi-bit storage cells of a plurality of flash memory chips to a high-density storage mode after at least 25% of the storage capacity of the plurality of flash memory chips has been programmed.

[0047] FIG. 5 provides an exemplary diagram of a computing system 500 (eg, a smartphone, a tablet computer, a laptop computer, a desktop computer, a server computer, etc.). As can be seen in FIG. 5 , basic computing system 500 may include a central processing unit 501 (which may include, for example, multiple general-purpose processing cores 515_1 to 515_X), a main memory controller 517 located on a multi-core processor or an application processor, system memory 502, a display 503 (e.g., touch screen, flat panel), a local wired point-to-point link (e.g., USB interface 504), various network I / O functions 505 (such as an Ethernet interface and / or a cellular modem subsystem), a wireless local area network (e.g., WiFi) interface 506, a wireless point-to-point link (e.g., Bluetooth®) interface 507, a global positioning system interface 508, various sensors 509_1 to 509_Y, one or more cameras 510, a battery 511, a power management control unit 512, a speaker and microphone 513, and an audio coder / decoder 514.

[0048] The application processor or multi-core processor 550 may include one or more general-purpose processing cores 515 within its CPU 501, one or more graphics processing units 516, memory management functions 517 (e.g., a memory controller), and I / O control functions 518. The general-purpose processing cores 515 typically perform the operations of the computing system's operating system and application software. The graphics processing unit 516 typically performs graphics-intensive functions, such as generating graphical information displayed on the display 503. The memory control functions 517 interface with the system memory 502 to write / read data to / from the system memory 502. The power management control unit 512 generally controls the power consumption of the system 500.

[0049] Each of the touchscreen display 503, communications interfaces 504-707, GPS interface 508, sensors 509, camera 510, and speaker / microphone codecs 513, 514 may be viewed as various forms of I / O (input and / or output) to the overall computing system, including integrated peripheral devices as needed (e.g., one or more cameras 510). Depending on the implementation, various of these I / O components may be integrated on the application processor / multicore processor 550 or may be located off-die or off-package of the application processor / multicore processor 550.

[0050] The computing system also includes non-volatile storage 520, which may be the mass storage component of the system, where, for example, the mass storage may consist of one or more SSDs comprised of flash memory chips whose multi-bit storage cells are programmed with different storage densities depending on the capacity utilization of the SSD, as described in detail above.

[0051] Embodiments of the present invention may include various processes described above. These processes may be embodied in machine-executable instructions. The instructions may be used to cause a general-purpose or application-specific processor to perform particular processes. Alternatively, these processes may be performed by specific / custom hardware components, including hardwired or programmable logic circuits (e.g., FPGAs, PLDs) for performing the processes, or by any combination of programmed computer components and custom hardware components.

[0052] Elements of the present invention may also be provided as a machine-readable medium for storing machine-executable instructions. Machine-readable media may include, but are not limited to, floppy diskettes, optical disks, CD-ROMs, magneto-optical disks, flash memory, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, propagation media, or other types of media / machine-readable media suitable for storing electronic instructions. For example, the present invention may be downloaded as a computer program product that may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) using a data signal embodied in a carrier wave or other propagation medium over a communications link (e.g., a modem or network connection).

[0053] In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

[0054] [Item 1] A storage device is provided. The storage device includes a controller and a plurality of flash memory chips; the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells; the multi-bit storage cell has a plurality of storage density modes; the controller programs the cells into a low-density storage mode up to a storage capacity threshold of the storage device of at least 25%, and programs the cells into a high-density mode once the capacity threshold is reached; Device. [Item 2] The low density memory mode is a multi-level cell (MLC); Item 1. The device according to item 1. [Item 3] The high-density memory mode is a quad-level cell (QLC); Item 2. The device according to item 2. [Item 4] The storage capacity threshold is 50%. Item 3. The device according to item 3. [Item 5] The storage capacity threshold is within the range of 25% to 75%. Item 1. The device according to item 1. [Item 6] The high-density storage mode is QLC; Item 1. The device according to item 1. [Item 7] The storage device is a solid state drive. Item 1. The device according to item 1. [Item 8] a controller for determining programming levels of a plurality of flash memory chips; the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells; the multi-bit storage cell has a plurality of storage density modes; the controller programs the cells into a low-density storage mode up to a storage capacity threshold of the flash memory chip of at least 25%, and programs the cells into a high-density storage mode once the capacity threshold is reached; Device. [Item 9] The low density memory mode is a multi-level cell (MLC); Item 9. The device according to item 8. [Item 10] The high-density memory mode is a quad-level cell (QLC); Item 9. The device according to item 9. [Item 11] The storage capacity threshold is 50%. Item 11. The device according to item 10. [Item 12] The storage capacity threshold is within the range of 25% to 75%. Item 9. The device according to item 8. [Item 13] The high-density storage mode is QLC; Item 9. The device according to item 8. [Item 14] The storage device is a solid state drive. Item 9. The device according to item 8. [Item 15] a plurality of processing cores; The main memory; a memory controller coupled between the plurality of processing cores and the main memory; a peripheral hub controller; a solid state drive coupled to the peripheral hub controller; Equipped with The solid state drive includes a controller and a plurality of flash memory chips; the plurality of flash memory chips including a three-dimensional stack of multi-bit storage cells; the multi-bit storage cell has a plurality of storage density modes; the controller programs the cells into a low-density storage mode up to a storage capacity threshold of the storage device of at least 25%, and programs the cells into a high-density storage mode once the capacity threshold is reached; Computing system. [Item 16] The low density memory mode is a multi-level cell (MLC); Item 16. The computing system of item 15. [Item 17] The high-density memory mode is a quad-level cell (QLC); Item 17. The computing system of item 16. [Item 18] The storage capacity threshold is 50%. Item 18. The computing system of item 17. [Item 19] The storage capacity threshold is within the range of 25% to 75%. Item 16. The computing system of item 15. [Item 20] When processed by a controller of a storage device having multiple flash memory chips, programming multi-bit storage cells of said plurality of flash memory chips into a low-density storage mode; programming the multi-bit storage cells of the plurality of flash memory chips to a high density storage mode after at least 25% of the storage capacity of the plurality of flash memory chips has been programmed; and stored program code causing the storage device to perform a method including: A manufactured product comprising:

Claims

[Claim 1] A storage device is provided. the storage device includes a controller and a plurality of flash memory chips; the plurality of flash memory chips include a three-dimensional stack of multi-bit storage cells; the multi-bit storage cell has a plurality of storage density modes; The controller includes at least writing first data to a first multi-bit storage cell in a low-density storage mode from the plurality of storage density modes; determining, in response to writing the first data, that a storage capacity of the storage device has reached a storage capacity threshold; determining that the second data stored in the low-density storage mode is accessed infrequently; In response to determining that the storage capacity of the storage device has reached the storage capacity threshold and in response to determining that the second data stored in the low-density storage mode is being accessed infrequently, write a bit combination comprising the first data and second data to the first multi-bit storage cell in a high-density storage mode from the plurality of storage density modes. It is configured as follows: Writing the bit combination to the first multi-bit storage cell in the high density storage mode includes: reading the second data stored in the low-density storage mode from a second multi-bit storage cell; generating the bit combinations including the first data and the second data; writing the bit combination to the first multi-bit storage cell in the high density storage mode; Device.

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