Display device

Abstract

An object is to provide an active matrix liquid crystal display device in which a plurality of kinds of circuits are formed over one substrate and a plurality of kinds of thin film transistor corresponding to characteristics of the plurality of kinds of circuits are provided.SOLUTION: An inverted-coplanar thin film transistor is used as a thin film transistor for a pixel, a channel-protective thin film transistor is used as a pixel electrode for a driver circuit, and a main portion of the pixel electrode is formed using a light-transmitting material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an active matrix liquid crystal display device and a method for manufacturing the same. The present invention relates to an electronic device that incorporates a Trick type liquid crystal display device as a component. [Background technology]

[0002] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. Metal oxides exist in a wide variety of forms and are used for a variety of purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0003] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. An element having terminals, and a channel region between a drain region and a source region, A current can flow through the drain region, the channel region, and the source region. So, if we do not distinguish between source and drain and call one the source, we will call the other the drain. I'll call him Rain.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using conductors have high field effect mobility. A driving circuit for a display device or the like can also be constructed using such a semiconductor device. Thin film transistors using metal oxides exhibiting high conductivity as the channel formation region are already known (particularly Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] When forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit are formed on the same substrate. In this case, the thin film transistor used in the pixel portion has excellent switching characteristics, e.g. For example, a large on-off ratio is required, and the thin film transistors used in the drive circuits have to have high operating speeds. In particular, the higher the resolution of the display device, the faster the display image Since the image writing time is shortened, the thin film transistors used in the driver circuit have a high operating speed. It is preferable to do so.

[0007] Multiple types of circuits are formed on the same substrate, and multiple types of thin films are used to match the characteristics of each of the multiple types of circuits. One of the objectives of the present invention is to provide an active matrix liquid crystal display device equipped with a thin film transistor. Let's say.

[0008] In addition, in the active matrix liquid crystal display device, a thin film using an oxide semiconductor film is Another object is to reduce variations in the electrical characteristics of transistors. [Means for solving the problem]

[0009] One embodiment of the present invention is a display device having a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit portion has a gate electrode layer, a source electrode layer, and a drain electrode layer formed of a metal conductive film. a thin film transistor for a driving circuit, the thin film transistor being configured such that the semiconductor layer is configured from an oxide semiconductor; and a wiring for a driving circuit formed of a metal conductive film, and the display section has a source electrode layer The drain electrode layer is made of an oxide conductor and the semiconductor layer is made of an oxide semiconductor. and a pixel thin film transistor configured as .

[0010] Thin film transistors with a bottom gate structure are used as thin film transistors for pixels and driving circuits. The pixel thin film transistor is formed on the source electrode layer and the drain electrode layer. Inverted coplanar (also called bottom-contact) thin-film transistors having an oxide semiconductor layer overlapping the It is a pedestrian.

[0011] In the present invention, a plurality of pixel electrodes are provided on the same substrate, and pixel electrodes electrically connected to the same It is possible to manufacture an active matrix liquid crystal display device in which a thin film transistor for use is formed. Cut.

[0012] In the active matrix liquid crystal display device, the formation of the active matrix circuit An optical film, specifically a color filter, is formed on a substrate (opposite substrate) facing the substrate. and a white light source, and a liquid crystal is sandwiched between the substrates to form a full-color liquid crystal display device. In this way, when displaying through a color filter, the thin film for the pixel The gate electrode layer, the source electrode layer, and the drain electrode layer of the film transistor are made of a light-transmitting material. By using a conductive film having a color filter, the aperture ratio can be improved. The filter is a three-color filter layer (red color) including a black matrix and an overcoat. The entire film is equipped with a color filter (e.g., white filter, blue color filter, green color filter, etc.). It does not refer to a single color, but rather a color filter.

[0013] On the other hand, the thin film transistor for the driver circuit has a different structure from the thin film transistor for the pixel. An oxide insulating layer is provided between the source electrode layer and the drain electrode layer and in contact with the exposed oxide semiconductor layer. It is a bottom-gate thin-film transistor.

[0014] The thin film transistor for the drive circuit has a drain electrode layer made of a metal conductive film such as Ti, A high-resistance drain electrode layer that is oxygen-deficient and in contact with a part of the top surface of the oxide semiconductor layer and overlaps with the drain electrode layer. The drain region (also called the HRD (High Resistance Drain) region) is Specifically, the carrier concentration of the high-resistance drain region is 1×10 18 / cm 3 Below top 1×10 21 / cm 3 or less (preferably 1 × 10 18 / cm 3 More than 1×10 20 / c m 3 The carrier concentration of the channel formation region is within the range of at least 1 × 10 14 / cm 3 More than 1×10 18 / cm 3 It should be noted that the range of the capacitance in this specification is higher than that of the capacitance in this specification. The carrier concentration refers to the value of the carrier concentration obtained by Hall effect measurement at room temperature.

[0015] The source electrode layer is in contact with a part of the top surface of the oxide semiconductor layer and overlaps with an oxygen-deficient portion. High Resistance Source (HRS) region, which is depleted ) area) is formed.

[0016] One embodiment of the present invention disclosed in this specification is a pixel having a first thin film transistor over the same substrate. a driving circuit having a second thin film transistor having a structure different from that of the first thin film transistor; The first thin film transistor has a gate electrode layer on the substrate and a gate electrode layer on the gate electrode layer. a gate insulating layer, a source electrode layer and a drain electrode layer on the gate insulating layer, and a semiconductor layer on the gate insulating layer. The oxide semiconductor layer overlapping the source electrode layer and the drain electrode layer and the oxide semiconductor layer in contact with the oxide semiconductor layer are a pixel electrode layer electrically connected to the drain electrode layer on the oxide insulating layer; , a gate electrode layer of the first thin film transistor, a gate insulating layer, an oxide semiconductor layer, and a source electrode At least one of the layer, the drain electrode layer, and the oxide insulating layer is a light-transmitting active matrix. It is a glass-type liquid crystal display device.

[0017] The above configuration solves at least one of the above problems.

[0018] In the above and in this specification, the ordinal numbers such as first and second are used for convenience. It does not indicate the order of steps or the order of layers. It does not indicate a specific name for the purpose of

[0019] In the above structure, a connection electrode layer may be provided between the pixel electrode layer and the drain electrode layer. The connection electrode layer is mainly made of an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Metallic films containing these components, or alloy films thereof, and laminated films combining these In addition, the source electrode layer and the drain electrode layer of the first thin film transistor may be formed of an oxide. Indium oxide, indium tin oxide, indium zinc oxide, or zinc oxide may be used. stomach.

[0020] Also, the source electrode layer and the drain electrode layer of the second thin film transistor, which is a thin film transistor for a driving circuit, The layer electrode is made of an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or Metallic materials such as alloys containing the above elements or alloys combining the above elements The source electrode layer and the drain electrode layer are not limited to a single layer containing the above-described element, and may be a layer containing two elements. A stack of more than one layer can be used.

[0021] The source electrode layer and the drain electrode layer of the second thin film transistor are formed of the oxide semiconductor layer. It does not overlap with the channel formation region. It also functions as a channel protection layer. The width of the oxide insulating layer between the side of the source electrode layer and the drain electrode facing the side is larger than the width of the oxide insulating layer between the source electrode layer and the drain electrode facing the side. The distance between the side of the layer is wider. Therefore, the width (length in the channel length direction) of the oxide insulating layer that functions as a channel protection layer is reduced. When a small design is attempted, the side of the source electrode layer and the drain electrode layer facing the side are The distance between the side surfaces also becomes smaller, and there is a risk of short-circuiting between the source electrode layer and the drain electrode layer. Therefore, it is useful to widen the gap distance. Its use improves the degree of circuit integration.

[0022] In the above structure, the second thin film transistor includes an oxide semiconductor layer. an oxide insulating layer over a semiconductor layer, The oxide semiconductor layer has a structure in which a peripheral portion of the oxide semiconductor layer is in contact with the oxide insulating layer. The oxide insulating layer in contact with the channel functions as a channel protection layer.

[0023] In the above structure, the insulating film functions as a channel protection layer for the thin film transistor for the driver circuit. The oxide insulating layer is an inorganic insulating film formed by a sputtering method, typically Silicon oxide film, silicon nitride oxide film, aluminum oxide film, aluminum oxynitride film, etc. is used.

[0024] The second thin film transistor has an oxide semiconductor layer between the oxide semiconductor layer and the source electrode layer. Alternatively, an oxide conductive layer may be provided between the gate electrode layer and the drain electrode layer. By adopting this structure, contact resistance can be reduced, and a thin film transistor capable of high-speed operation can be obtained. The oxide conductive layer preferably contains zinc oxide as a component. Preferably, the oxide conductive layer does not contain indium oxide. , zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, etc. Examples include:

[0025] In addition, the oxide semiconductor layer of the driver circuit thin film transistor has an upper surface a region that does not overlap with the oxide insulating layer, the drain electrode layer, and the source electrode layer, i.e., a third region; The length of the third region in the channel length direction is determined by the patterning position of the oxide semiconductor layer. and the patterning positions of the drain electrode layer and the source electrode layer. If the length of the region 3 in the channel length direction is widened, the off-state current of the thin film transistor for the driver circuit can be increased. In addition, the length of the third region in the channel length direction can be narrowed. This will enable the thin film transistors for the driver circuits to operate (switch) at higher speeds. .

[0026] The insulating layer in contact with the third region is also formed by a physical film formation method such as sputtering. The inorganic insulating film is typically a silicon nitride film, a silicon nitride oxide film, or an aluminum nitride film. In these film formation processes, the hydrogen concentration in the atmosphere and film formation material (both pure and non-pure) is important. to reduce as much as possible the amount of toxic substances (not only those contained in the substance itself but also those contained in the compound) It is desirable to sufficiently reduce the hydrogen concentration in the resulting film. The hydrogen concentration in the film is 1 cm 3 1 x 10 per 12 More than an atom, 1×10 18 Subatomic It is good.

[0027] The oxide semiconductor layer is InMO3(ZnO) m (m>0 and m must be an integer. A thin film represented by (b) is formed, and the thin film is used as an oxide semiconductor layer. M is a metal selected from Ga, Fe, Ni, Mn, and Co. It indicates a group element or multiple metal elements. For example, M can be Ga, or Ga In some cases, the above metal elements other than Ga may be contained, such as Ni and Ga or Fe and Ga. In the oxide semiconductor, in addition to the metal element contained as M, Fe, N are contained as impurity elements. Other transition metal elements or oxides of such transition metals may be included. In the document, for example, an oxide semiconductor containing In, Ga, and Zn is referred to as In-Ga-Zn-O These thin films are also called In-Ga-Zn-O films. The nO-based oxide semiconductor may contain other elements.

[0028] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-O, I n-Ga-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn -O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn- Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides are used. Silicon may also be contained in the oxide semiconductor layer made of the metal oxide. stomach.

[0029] In addition, one embodiment of the present invention for realizing the above structure is to form a first gate electrode on a substrate having an insulating surface. a gate electrode layer and a second gate electrode layer; forming a gate insulating layer on the layer; and forming a first source electrode layer on the gate insulating layer so as to overlap the first gate electrode layer. a first gate electrode layer and a second drain electrode layer are formed on the gate insulating layer; a first oxide semiconductor layer overlapping a portion of the first source electrode layer and a portion of the first drain electrode layer; a second oxide semiconductor layer overlapping the second gate electrode layer; and an oxide insulating layer in contact with a part of the conductor layer and in contact with the top surface and side surfaces of the second oxide semiconductor layer; a second source electrode layer and a second drain electrode layer over the second oxide semiconductor layer; An active layer is formed on the oxide insulating layer to form a pixel electrode layer electrically connected to the first drain electrode layer. This is a method for manufacturing a passive matrix display device.

[0030] In the above-described manufacturing method, The oxide insulating layer is formed by dehydrating or dehydrogenating the oxide semiconductor layer and then exposing it to the air. The oxide semiconductor layer is formed without any problem, and water or hydrogen is prevented from re-entering the oxide semiconductor layer.

[0031] In this specification, only the desorption of H2 by this heat treatment is referred to as dehydrogenation. It is not a simple process, but rather involves dehydration or dehydrogenation, including the elimination of H, OH, etc. I will call him that for convenience.

[0032] Although it depends on the deposition method, the oxide semiconductor layer contains some hydrogen or water. The part of the atom acts as a donor, providing electrons. When heat treatment is performed in an active gas atmosphere, hydrogen and water contained in the oxide semiconductor layer are removed. At the same time, the oxide semiconductor layer becomes oxygen-deficient by this heat treatment, and the resistance Anti-N type (N - (e.g., stylizing)

[0033] Then, an oxide insulating film is formed in contact with the oxide semiconductor layer. By creating an oxygen-excess state, it is possible to make the material highly resistive, i.e., I-type. To manufacture and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. This makes it possible to:

[0034] Dehydration or dehydrogenation is carried out using an inert gas such as nitrogen or a noble gas (argon, helium, etc.). Heat treatment is carried out in an atmosphere at 350°C or higher, preferably 425°C or higher and 700°C or lower, and This reduces impurities such as moisture contained in the oxide semiconductor layer.

[0035] The oxide semiconductor layer that has been appropriately dehydrated or dehydrogenated is subjected to a thermal desorption process. Analysis of the released gases (from room temperature to 450°C) using the Total Dispersion Analysis (TDS) method revealed that Of the two peaks arising from this, the peak appearing at around 300°C is not detected. .

[0036] Note that the heating temperature at which the oxide semiconductor layer is dehydrated or dehydrogenated may be changed depending on the temperature at which the oxide semiconductor layer is dehydrated or dehydrogenated. The dehydrogenation is carried out in the same furnace, without exposure to the atmosphere, and without recontamination with water or hydrogen. It is recommended to cool the temperature to room temperature. Also, if dehydration or dehydrogenation is performed, oxygen vacancies will occur ( The oxide semiconductor layer becomes oxygen-deficient and has low resistance (i.e., becomes N-type). When an oxide insulating film is formed in contact with the semiconductor layer, the oxide semiconductor layer becomes highly resistive again (i.e. When a thin film transistor is manufactured using such an oxide semiconductor layer, The threshold voltage (Vth) of the transistor can be made positive, so-called normally-off In the thin film transistor used in the display device, the gate voltage It is desirable for the channel to form at a positive voltage as close to 0V as possible.

[0037] If the threshold voltage of a thin film transistor is negative, the source will not turn on even if the gate voltage is 0V. Current flows between the source and drain electrodes, which is called a normally-on state. In a matrix display device, the electrical characteristics of the thin film transistors that make up the circuit are important. These electrical characteristics are crucial and determine the performance of the display device.

[0038] In particular, the threshold voltage is important among the electrical characteristics of thin film transistors. For example, thin film transistors have high field effect mobility but extremely high threshold voltages. Or, if the threshold voltage is negative, it is difficult to control the circuit. Thin film transistors with high low voltages do not function as thin film transistors when the driving voltage is low. It may not be able to perform its switching function and may become a load.

[0039] In the case of an n-channel thin film transistor, when a voltage of 0 V is applied to the gate, the channel A positive voltage of +1V to +5V is applied to form a channel, and the drain A transistor that allows current to flow is desirable. The driving voltage must be higher than +10V. There are transistors in which a channel is not formed, and transistors in which a channel is formed even under negative voltage conditions and a drain current is generated. A transistor through which current flows is unsuitable as a thin film transistor for use in a circuit.

[0040] The gas atmosphere when the temperature is lowered from the heating temperature for the dehydration or dehydrogenation to room temperature is The gas atmosphere may be changed to a gas atmosphere different from the gas atmosphere at the heating temperature. For example, Dehydration or dehydrogenation is carried out in a nitrogen atmosphere, and then the atmosphere in the furnace is changed to high-purity oxygen gas. or N2O gas, ultra-dry air (dew point below -40°C, preferably below -60°C) Cooling may also be performed.

[0041] After reducing the moisture content in the film by a heat treatment for dehydration or dehydrogenation, Slowly store in a dry, moisture-free atmosphere (dew point below -40°C, preferably below -60°C). The electrical characteristics of a thin film transistor are improved by using a cooled (or cooled) oxide semiconductor film. At the same time, we will realize thin-film transistors that are both mass-producible and high-performance.

[0042] An active matrix display device has a plurality of thin film transistors in its pixel portion, In the element part, the gate electrode of a thin film transistor and the source wiring of another thin film transistor, Alternatively, some have a location for connecting the drain wiring. If the drive circuit is formed by thin film transistors in the optical switch, The gate electrode of the thin film transistor is connected to the source wiring or drain wiring of the thin film transistor. Some have a place.

[0043] In addition, thin film transistors are easily damaged by static electricity, so the gate line or source A protection circuit for protecting the thin film transistors in the pixel area can be provided on the same substrate as the line. In this case, the protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer. This can be done.

[0044] A semiconductor device according to one embodiment of the present invention includes a driver circuit thin film transistor and a driver circuit thin film transistor. A driver circuit portion having a pixel portion and a pixel thin film transistor are manufactured. The manufacturing cost of the active matrix display device can be reduced. [Effects of the Invention]

[0045] By using an oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation, Thin film transistors with good electrical characteristics and high reliability are used as switching elements, It is possible to fabricate a high-performance active matrix display device. A thin film transistor for a driving circuit and a thin film transistor for a driving circuit are formed, and the thin film transistors are respectively An active matrix display device can be fabricated with a structure that matches these circuits. do. [Brief explanation of the drawings]

[0046] [Figure 1] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 3] FIG. 1 is a circuit diagram of one pixel of a general active matrix liquid crystal display device. [Figure 4] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 5] 1A and 1B are cross-sectional views and a plan view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 7] 1A and 1B are cross-sectional views and a plan view illustrating one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 9] FIG. 1 is a block diagram illustrating an active matrix liquid crystal display device. [Figure 10] 1A and 1B are diagrams illustrating the configuration of an active matrix signal line driver circuit and a timing chart illustrating the operation thereof; [Figure 11] FIG. 2 is a circuit diagram showing a configuration of a shift register. [Figure 12] 1 is a circuit diagram of a shift register and a timing chart illustrating the operation thereof; [Figure 13] FIG. 1 is a diagram illustrating an electronic device. [Figure 14] FIG. 1 is a diagram illustrating an active matrix liquid crystal display device. [Figure 15] FIG. 1 is a diagram illustrating an active matrix liquid crystal display device. [Figure 16] FIG. 1 is a diagram illustrating an active matrix liquid crystal display device. [Figure 17] FIG. 1 is a diagram illustrating an active matrix liquid crystal display device. DETAILED DESCRIPTION OF THE INVENTION

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In the drawings in this specification, parts having the same parts or similar functions are The same reference numerals are used to denote corresponding parts, and their explanations may be omitted.

[0048] (Embodiment 1) In this embodiment, an active matrix display device and an active matrix display device One embodiment of the manufacturing method of the device will be explained using FIG. 1. FIG. 1(E) shows a diagram of a device manufactured on the same substrate. 1 shows an example of the cross-sectional structure of two thin film transistors with different structures.

[0049] The thin film transistor 12 shown in FIG. 1(E) is one of bottom gate structures. The transistor 13 is a bottom gate type called a bottom contact type (also called an inverted coplanar type). It is one of the structures.

[0050] The thin film transistor 13 disposed in the pixel is formed by forming a gate electrode layer on a substrate 1 having an insulating surface. 3a, a gate insulating layer 4, an oxide semiconductor layer 8b including a channel formation region, and a source electrode layer 5a and the drain electrode layer 5b. Also, the thin film transistor 13 is covered with an oxide semiconductor layer An oxide insulating layer 7b is provided in contact with the top and side surfaces of 8b.

[0051] The thin film transistor 13 disposed in the pixel is a thin film transistor with a single gate structure. However, if necessary, a multi-gate structure having a plurality of channel forming regions may be used. Thin film transistors can also be formed.

[0052] The oxide semiconductor layer 8b is formed above the source electrode layer 5a and the drain electrode layer 5b. The oxide semiconductor layer 8b is connected to the gate electrode via the gate insulating layer 4. The channel forming region of the thin film transistor 13 arranged in the pixel is In the oxide semiconductor layer 8b, the side surface of the source electrode layer 5a and the drain electrode layer 5b facing the side surface are The region sandwiched between the side surface of the electrode layer 5b and the gate insulating layer 4, i.e., the region in contact with the gate electrode layer 3 This is the area that overlaps with a.

[0053] Furthermore, the thin film transistor 13 has a high aperture ratio as a light-transmitting thin film transistor. In order to realize a liquid crystal display device, the source electrode layer 5a and the drain electrode layer 5b are made of a material having a light-transmitting property. A conductive film having such a structure is used.

[0054] The gate electrode layer 3a of the thin film transistor 13 also uses a light-transmitting conductive film. In the specification, a film that is translucent to visible light is one that has a visible light transmittance of 75% or more and 100% or less. % or less, and if the film is conductive, it is also called a transparent conductive film. Alternatively, a conductive film that is semi-transparent to visible light may be used. This refers to a visual light transmittance of 50% or more but less than 75%.

[0055] The thin film transistor 12 disposed in the driving circuit is formed on the substrate 1 having an insulating surface. a gate electrode layer 2a, a gate insulating layer 4, an oxide semiconductor layer 6a, a source electrode layer 9a, and a drain electrode layer 10b. The oxide semiconductor layer 6a includes at least a channel formation region 8a, a high resistance semiconductor layer 9b, and a gate electrode layer 9b. The source region 11a and the high-resistance drain region 11b are formed in the channel forming region 8a. The oxide insulating layer 7a is provided in contact with the source electrode layer 9a and the drain electrode layer 9b. An insulating layer 10 is provided on b.

[0056] In addition, the first region 11c and the second region 11d of the oxide semiconductor layer 6a overlapping with the oxide insulating layer 7b are is in the same oxygen-excess state as the channel forming region 8a, and is effective in reducing leakage current and reducing parasitic capacitance. In addition, the third region of the oxide semiconductor layer 6a in contact with the insulating layer 10 also serves to reduce the The region 11e is provided between the channel forming region 8a and the high-resistance source region 11a. The fourth region 11f of the oxide semiconductor layer 6a in contact with the insulating layer 10 is high in relation to the channel formation region 8a. The first insulating layer 10 is provided between the resistive drain region 11b and the oxide semiconductor layer 6a. The third region 11e and the fourth region 11f can reduce the off current.

[0057] Generally, in a channel protection type thin film transistor, the source voltage is placed so as to overlap with the channel protection layer. In this structure, a channel layer and a drain electrode layer are formed in the channel forming region. To shorten the length L, it is necessary to narrow the width of the channel protection layer. When the source electrode layer and the drain electrode layer are provided on the channel protection layer, the source In this embodiment, the channel protection layer is formed of a thin film. The narrow oxide insulating layer 7a, which functions as a gate insulating layer, overlaps the source electrode layer 9a and the drain electrode layer 9b. The above problem can be overcome by adopting a configuration that does not require the use of a separate circuit.

[0058] In FIG. 1(E), the oxide insulating layer 7a and the gate electrode layer 2a are connected via the gate insulating layer. The overlapping region of the oxide semiconductor layer 6a is called a channel forming region. The channel length L of the transistor 12 is equal to the length of the oxide insulating layer 7a in the channel length direction. In the cross-sectional view shown in FIG. 1(E), the oxide insulating layer 7a is shown as a trapezoid. The channel length L of the transistor 12 is the length of the base of the trapezoid.

[0059] Hereinafter, using Figures 1(A), 1(B), 1(C), 1(D), and 1(E), The process of fabricating the thin film transistor 12 and the thin film transistor 13 on the substrate will be described.

[0060] First, a conductive film is formed on a substrate 1 having an insulating surface, and then a first photolithography process is performed. The gate electrode layers 2a and 2b are formed by the above steps. The resist mask may be formed by an ink jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0061] The conductive film forming the gate electrode layers 2a and 2b may be Al, Cr, Ta, Ti, Mo, W A metal whose main component is one of the elements selected from the above, or an alloy whose component is one of the elements listed above. or an alloy film made of a combination of the above elements.

[0062] When a glass substrate is used as the substrate 1, distortion may occur if the temperature of the subsequent heat treatment is high. It is recommended to use a substrate with a temperature of 730°C or higher. For example, aluminosilicate Glass materials such as glass, aluminoborosilicate glass, and barium borosilicate glass are used. Alternatively, crystallized glass or the like can be used.

[0063] Generally, the more barium oxide (BaO) is contained compared to boric acid, the more practical it becomes. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0064] The substrate 1 may be a substrate made of an insulating material such as a ceramic substrate, a quartz substrate, or a sapphire substrate. A board may also be used.

[0065] An insulating film serving as a base film may be provided between the substrate 1 and the gate electrode layers 2a and 2b. The film has a function of preventing the diffusion of impurity elements from the substrate 1, and is a silicon nitride film, a silicon oxide film, A laminated structure of one or more films selected from a silicon nitride oxide film or a silicon oxynitride film It can be formed.

[0066] Next, a light-transmitting conductive film is formed to cover the gate electrode layers 2a and 2b, and then a second film is formed. The gate electrode layers 3a and 3b are formed by a photolithography process. In order to reduce the line resistance, the gate wiring arranged in the pixel portion is made of the same metal conductor as the gate electrode layer 2b. The gate electrode is formed of a conductive film and overlaps with the oxide semiconductor layer to be formed later via the gate insulating layer 4. The material of the electrode layer 3a is formed from a conductive film having light-transmitting properties.

[0067] Next, a gate insulating layer 4 is formed on the gate electrode layers 2a, 2b, 3a, and 3b. The insulating layer 4 is formed by using a physical vapor deposition (PVD) method such as a plasma CVD method or a sputtering method. In this case, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer is used as a single layer or a stacked layer. For example, a film can be formed by using SiH4, oxygen, and nitrogen as the film forming gas. The silicon oxynitride layer may be formed by plasma CVD. In the case of a laminated layer, the thickness is, for example, 50 nm to 200 nm. a first gate insulating layer below the first gate insulating layer, and a second gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer; 2. A stack of gate insulating layers may be used.

[0068] In this embodiment, a silicon oxynitride (SiON) film having a thickness of 100 nm is formed by plasma CVD. The gate insulating layer 4 is formed using a material having a nitrogen concentration lower than that of oxygen.

[0069] In order to prevent hydrogen from diffusing into the oxide semiconductor layer formed thereon, it is necessary to form a gate electrode. It is preferable that the hydrogen concentration in the insulating layer 4 is sufficiently low. Sputtering can be performed with very little or no hydrogen in the physical methods such as laser ablation (also called laser sputtering), vacuum deposition, etc. It is preferable to use the vapor deposition (PVD) method.

[0070] Next, a light-transmitting conductive film is formed on the gate insulating layer 4, and then a third photolithography is performed. A source electrode layer 5a and a drain electrode layer 5b are formed by a polishing process (see FIG. 1(A)). The transparent conductive film is made of a conductive material that is transparent to visible light, such as In. -Sn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn- O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Z Applying metal oxides of nO, Al-Zn-O, In-O, Sn-O, and Zn-O The film thickness can be appropriately selected within the range of 50 nm to 300 nm. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The transparent conductive film is then coated with SiOx (X>0) which inhibits crystallization. In order to prevent crystallization during the heat treatment for dehydration or dehydrogenation in the process It is preferable that

[0071] Next, the gate insulating layer 4 is selectively etched by a fourth photolithography process. , a contact hole reaching the gate electrode layer 2b is formed as shown in FIG. 1(B). .

[0072] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm or more, is formed on the gate insulating layer 4. Form an oxide semiconductor film with a thickness of 20 nm or less. Then, the oxide semiconductor film can be easily dehydrated or dehydrogenated even after heat treatment. Maintains a crystalline state.

[0073] The oxide semiconductor film is made of In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Z nO system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system , In-Zn-O series, In-Ga-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based oxide semiconductor films are used. In a gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon ) and can be formed by sputtering in an oxygen atmosphere.

[0074] In addition, when using a sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. The oxide semiconductor film is formed using the above method, and contains SiOx (X>0), which inhibits crystallization. This prevents crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. This is preferable because it can be suppressed.

[0075] In this embodiment, an oxide semiconductor target containing In, Ga, and Zn (In:Ga: Zn=1:1:0.5[at%]) and the distance between the substrate and the target was 100m. m, pressure 0.6 Pa, direct current (DC) power supply 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere When a pulsed direct current (DC) power supply is used, the powdery material generated during film formation is This is preferable because it can reduce particles and make the film thickness distribution uniform. In this example, a 15 nm thick In-Ga-Zn-O non-single crystal film was formed under the above conditions. do.

[0076] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal conductive films. It is used in such cases.

[0077] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to form a film by discharging the same materials simultaneously. There is also a reactive sputtering method in which the deposited element reacts with the sputtering atmosphere.

[0078] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0079] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0080] One of these methods may be used to form an oxide semiconductor film. Before forming the film by sputtering, a reverse sputtering process is performed in which argon gas is introduced to generate plasma. Puttering is performed to remove moisture, organic matter, dust, etc. adhering to the surface of the gate insulating layer 4. Reverse sputtering is a method of applying an electric current to the substrate side, rather than the target side, using an RF power source. This method involves applying pressure to form plasma near the substrate to modify the surface. Instead of the atmosphere, nitrogen, helium, oxygen, etc. may be used. This step is not limited to being performed before the film formation, but may be performed before other film formation steps.

[0081] In this embodiment, the gate insulating layer is selectively formed by the fourth photolithography process. A contact hole reaching the gate electrode layer 2b is formed by etching. First, a resist mask is formed on the oxide semiconductor layer obtained by etching the oxide semiconductor film. Alternatively, a contact hole reaching the gate electrode layer 2b may be formed. In this case, a reverse sputtering The resist residues adhering to the surfaces of the oxide semiconductor layer and the gate insulating layer 4 are removed. It is preferable to remove it.

[0082] In addition, after an oxide semiconductor film is formed over the gate insulating layer, a resist mask is formed on the oxide semiconductor film. Then, a contact hole reaching the gate electrode layer 2b is formed. After that, a resist mask is formed again over the oxide semiconductor film, and the oxide semiconductor film is A step of processing the oxide semiconductor layer into an island shape by selective etching may be performed.

[0083] In this embodiment, the gate insulating layer 4 is selectively etched by the fourth photolithography process. In order to form a contact hole that reaches the gate electrode layer 2b by etching, After that, heat it under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) Treatment (400°C or higher) is performed to remove impurities such as hydrogen and water contained in the gate insulating layer 4. After that, an oxide semiconductor film is preferably formed.

[0084] Next, the oxide semiconductor film is formed into island-shaped oxide semiconductor layers by a fifth photolithography process. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no wet etching is used, the manufacturing cost can be reduced. Either etching or dry etching may be used.

[0085] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0086] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0087] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0088] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0089] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0090] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0091] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than 700°C, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. The treatment time should be longer than 1 hour.

[0092] Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment in a nitrogen atmosphere, the product is cooled without contact with the air to remove the oxygen. In this embodiment, the dehydration of the oxide semiconductor layer is performed to prevent water and hydrogen from re-entering the oxide semiconductor layer. Or, use the same furnace to heat from the dehydrogenation temperature to a temperature high enough to prevent water from entering again. Specifically, the material is slowly cooled in a nitrogen atmosphere until the temperature drops by 100°C or more below the heating temperature. It is not limited to a nitrogen atmosphere, but may be used under a rare gas atmosphere (e.g., helium, neon, argon, etc.). In this step, dehydration or dehydrogenation may be carried out.

[0093] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0094] In the first heat treatment, the atmosphere is nitrogen, helium, neon, argon, etc. It is preferable that the rare gas does not contain water, hydrogen, hydrocarbons, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the device should be 6N (99 0.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0095] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer In some cases, the crystals crystallize to form a microcrystalline or polycrystalline film. The proportion of the component in the whole is 80% or more (preferably 90% or more), and the adjacent fine grains It is preferable that the crystal grains are packed so as to be in contact with each other. Alternatively, depending on the material of the oxide semiconductor layer, the entire oxide semiconductor layer may be in an amorphous state. There are also.

[0096] After the first heat treatment, the oxide semiconductor layers 6a and 6b become oxygen-deficient and have low resistance (see FIG. 1(B). That is, after the first heat treatment, the oxide semiconductor film is more oxidized than the oxide semiconductor film immediately after the deposition. The carrier concentration is increased, preferably to 1×10 18 / cm 3 Oxide with carrier concentration above These become the compound semiconductor layers 6a and 6b.

[0097] Furthermore, depending on the conditions of the first heat treatment or the material of the gate electrode layers 3a and 3b, The electrode layers 3a and 3b may be crystallized to become microcrystalline or polycrystalline films. When an indium tin oxide film is used as the electrode layers 3a and 3b, the first heating is performed at 450° C. for 1 hour. The gate electrode layers 3a and 3b are formed of indium oxide containing silicon oxide. When a tin film is used, it does not crystallize.

[0098] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heat treatment device. The plate is removed and subjected to a fifth photolithography step. The etching rate of the conductor may decrease.

[0099] Next, an oxide insulating film is formed on the gate insulating layer 4 and the oxide semiconductor layers 6a and 6b by sputtering. After forming the film, a resist mask is formed by a sixth photolithography process. Then, the resist mask is removed. At this stage, the oxide semiconductor layers 6a and 6b are covered with an oxide insulating layer 7. In this region, the gate electrode layer 2a and the gate insulating layer 4b are formed. The region overlapping with the oxide insulating layer 7a via the oxide semiconductor becomes the channel formation region 8a. The first region 11c and the second region 11d overlap with the oxide insulating layer 7b that covers the periphery and side surfaces of the conductor layer. Also, a contact hole reaching the gate electrode layer 2b is formed by a sixth photolithography process. A contact hole and a contact hole reaching the drain electrode layer 5b are also formed.

[0100] The oxide insulating film should have a thickness of at least 1 nm. The film can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the film. In the embodiment, a silicon oxide film is formed as the oxide insulating film by sputtering. The substrate temperature during the heating process may be set to a temperature between room temperature and 300° C., and is set to 100° C. in this embodiment. The silicon oxide film is formed by sputtering under a rare gas (typically argon) atmosphere. The reaction can be carried out under an oxygen atmosphere or under an atmosphere of a rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target is used as the target. It is possible.

[0101] For example, a silicon target is used, and the silicon is deposited by sputtering in an oxygen and rare gas atmosphere. Silicon oxide can be formed in contact with the oxide semiconductor layers 6a and 6b with reduced resistance. The oxide insulating film is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film is used to block the penetration of oxygen from the inside of the material. A silicon film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0102] In this embodiment, the purity is 6N, and the columnar polycrystalline boron-doped silicon target (resistivity 0.01Ωcm), the distance between the substrate and the target (TS distance) was 89mm, Pressure: 0.4 Pa, DC power: 6 kW, oxygen (oxygen flow rate: 100%) atmosphere The film is formed by DC sputtering to a thickness of 300 nm.

[0103] Next, a second heat treatment (preferably 2) is carried out under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. The end of the oxide semiconductor layer 6a overlapping with the oxide insulating layer 7b and the end of the oxide semiconductor layer 6a overlapping with the oxide insulating layer 7a A part of 6a is heated in contact with the oxide insulating layer.

[0104] When the second heat treatment is performed, part of the oxide semiconductor layer that does not overlap with the oxide insulating layer is exposed. With the oxide semiconductor layer 6a exposed, the oxide semiconductor layer 6a is heated in a nitrogen or inert gas atmosphere. If heat treatment is performed under atmospheric conditions, the resistance of the oxide can be further reduced. The portions in contact with the insulating layers 7a and 7b are supplied with oxygen (excess oxygen) and become highly resistant (I-type). The oxide insulating layer 7a can be formed in the channel formation region of the oxide semiconductor layer 6a. The layer is provided on and in contact with the region where the channel is to be formed, and functions as a channel protection layer.

[0105] The timing for performing the second heat treatment is immediately after the end of the sixth photolithography process. There are no particular limitations on the process, as long as it is a process subsequent to the sixth photolithography process.

[0106] Next, a conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer 6a. After forming the film, a resist mask is formed by a seventh photolithography process. The source electrode layer 9a and the drain electrode layer 9b are formed by etching (FIG. 1(D)). )reference).

[0107] As shown in FIG. 1(D), a connection electrode layer 9c electrically connected to the gate electrode layer 2b is formed. A connection electrode layer 9d electrically connected to the drain electrode layer 5b is also formed. The methods include sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion plating. The coating method or spray method is used.

[0108] The conductive film may be made of an element selected from Ti, Mo, W, Al, Cr, Cu, and Ta, or An alloy containing the above elements or an alloy combining the above elements is used. The layer is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. In this embodiment, a titanium film (thickness 100 nm), an aluminum film (thickness 200 nm), and a titanium A three-layer conductive film is formed using a titanium nitride film (100 nm thick) instead of a titanium film. A polyimide film may also be used.

[0109] In the seventh photolithography step, only the conductive film in contact with the oxide semiconductor layer is Therefore, only the conductive film in contact with the oxide semiconductor layer is selectively removed. To remove the etchant, an alkaline etchant such as ammonia-hydrogen peroxide (e.g., hydrogen peroxide) is used. If a mixture of ammonia and water (5:2:2) is used, the metal conductive film can be selectively removed. In this case, an oxide semiconductor layer made of an In—Ga—Zn—O-based oxide semiconductor can be left. do.

[0110] The resist masks for forming the source electrode layer 9a and the drain electrode layer 9b are formed by ink. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0111] Through the above steps, the resistance of the oxide semiconductor layers 6a and 6b is reduced. As a result, a part of the insulating layer 7a in contact with the oxide insulating layer 7b is selectively made to have an oxygen excess state. The channel formation region 8a is I-type, and the region of the oxide semiconductor layer 6a that is in contact with the oxide insulating layer 7b is The first region 11c and the second region 11d are I-shaped, and the high-resistance solenoids overlapping the source electrode layer 9a are I-shaped. The source region 11a and the high-resistance drain region 11b overlapping the drain electrode layer 9b are self-aligned. is formed automatically.

[0112] The high-resistance source region 11a and the high-resistance drain region 11b are formed according to the thickness of the oxide semiconductor layer. When the thickness of the oxide semiconductor layer is, for example, 15 nm or less, the source The parts that overlap with the electrode layer, drain electrode layer, or conductive layer are all N-type (N - ) area, When the oxide semiconductor layer has a thickness of, for example, 30 nm to 50 nm, the source electrode layer and the drain electrode layer The portion overlapping with the source electrode layer, the drain electrode layer, or the conductive layer is adjacent to the source electrode layer, the drain electrode layer, or the conductive layer. An N-type region may be formed in the adjacent area, and an I-type region may be formed below the N-type region. do.

[0113] Furthermore, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), This improves the reliability of the drive circuit. By forming the drain electrode layer, the high-resistance drain region 11b and the channel region 11c are It is possible to provide a structure in which the conductivity can be changed stepwise over the panel formation region. Therefore, when the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD, Even if a high electric field is applied between the gate electrode layer and the drain electrode layer, a high resistance drain region (or The high-resistance source region (or high-resistance source region) acts as a buffer to prevent a local high electric field from being applied, A configuration with improved breakdown voltage can be achieved.

[0114] Furthermore, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), This makes it possible to reduce the leakage current in the channel forming region 8a when a drive circuit is formed. Cut.

[0115] Next, the oxide insulating layers 7a and 7b, the source electrode layer 9a, the drain electrode layer 9b, and the connection electrode layer An insulating layer 10 is formed on the insulating layer 10 and the connecting electrode layer 9c and the connecting electrode layer 9d (see FIG. 1(E)). For example, a silicon nitride film, a silicon nitride oxide film, or an aluminum nitride film is used. In this embodiment, the insulating layer 10 made of a silicon nitride film is formed by RF sputtering.

[0116] Through the above process, two types of thin film transistors, a channel protection type thin film transistor, and a A bottom-contact type thin film transistor 12 and a bottom-contact type thin film transistor 13 can be fabricated.

[0117] In the channel protection type thin film transistor 12, when the width of the oxide insulating layer 7a is narrowed, the channel The length L can be shortened to between 0.1 μm and 2 μm, realizing a thin-film transistor with high operating speed. The bottom contact type thin film transistor 13 can be a channel protection type thin film transistor. A thin-film transistor with a longer channel length than Transistor 12 and reduced off-current is realized. Furthermore, the bottom-contact thin film transistor 13 has the following structure except for the connection electrode layer 9d: It is made of a light-transmitting material.

[0118] When manufacturing an active matrix display device, multiple thin film transistors are used in one pixel. For example, it may be electrically connected to the pixel selection thin film transistor to select the pixel voltage. There may also be another thin film transistor connected to the electrode or storage capacitor. The transistor has a channel length L of 55 μm and a channel width W of 20 μm. The selected thin film transistor has a channel length L of 25 μm and a channel width W of 60 μm. The overlap width between the source electrode layer and the gate electrode layer in the channel length direction is 5 μm. The overlap width of the drain electrode layer and gate electrode layer in the channel length direction is 5 μm. The thin film transistor may also have a bottom contact type thin film transistor 13 structure.

[0119] When multiple thin film transistors are provided in one pixel as described above, the thin film transistors connected to the pixel A power supply line is provided which is electrically connected to the source electrode layer of the transistor. The wiring is made of the same material as the connection electrode layer 9c made of a metal conductive film and is formed in the same process. Alternatively, the power supply line may be formed so as to intersect with the source wiring and to be connected to the gate electrode layer 2b. They may be formed using the same material and the same process.

[0120] In addition, when forming a driving circuit on the same substrate, for example, a channel protection type thin film transistor The channel length L is set to 2 μm and the channel width W is set to 50 μm. The width of the third region 11e and the width of the fourth region 11f in the channel length direction are each preferably 2 μm. The overlap width between the source electrode layer and the gate electrode layer in the channel length direction is set to 2 μm. The overlap width between the drain electrode layer and the gate electrode layer in the longitudinal direction of the panel is preferably 2 μm.

[0121] A plurality of types of circuits, a driver circuit and a pixel portion in this embodiment mode, are formed on the same substrate. The channel protection type thin film transistor 12 or the bottom capacitor Optimization can be achieved by using a contact type thin film transistor 13.

[0122] This completes the active matrix circuit. The process will be explained with reference to FIGS. 2(A) and 2(B).

[0123] First, a planarizing insulating layer 14 is formed on the insulating layer 10 of the silicon nitride film of the substrate fabricated up to FIG. 1(E). The planarizing insulating layer 14 is formed to make the thickness of the liquid crystal layer uniform so that the liquid crystal display is uniform. It is not necessary to provide it in the drive circuit. ) the configuration is such that it is not provided in the drive circuit portion.

[0124] However, when forming a planarizing insulating layer, it is necessary to use a method such as spin coating to cover the entire substrate. When the insulating layer is formed on the surface, the planarization insulating layer of the driving circuit portion is then formed by photolithography. Therefore, in such cases, it is necessary to pattern and etch the In order to simplify the process, the planarization insulating layer in the drive circuit area is intentionally left. That's fine.

[0125] On the other hand, the patterning of the planarization insulating layer does not require high accuracy, so the process is If it is determined that this will not lead to a decrease in yield, the transparent conductive film formed thereafter may be The dielectric material can also be used as the back gate of the thin film transistor in the drive circuit section.

[0126] In one embodiment of the present invention, a part of a thin film transistor and a wiring in a pixel region also has a light-transmitting property. It is made of materials, but to get the most out of it, it is necessary to shape it afterwards. It is also preferable to make the area of ​​the pixel electrode layer as large as possible. The pixel electrode layer is provided on the resistors and wiring.

[0127] However, in such a structure, the thin film transistor and the pixel electrode layer or the wiring The parasitic capacitance between the line and the pixel electrode layer is a problem. Therefore, the selection of the material and thickness of the planarization insulating layer is important. Care must be taken in the selection of the planarizing insulating layer, i.e., the layer should be as thick as possible and its dielectric constant should be as low as possible. It is preferable that the rate be as small as possible.

[0128] The planarization insulating layer may be made of a material such as polyimide, acrylic resin, or benzocyclohexyl. Heat-resistant organic materials such as hydroxybutene resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, low-k materials and siloxane resins can also be used. , PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. By stacking multiple insulating films made of these materials, a planarized insulating layer can be formed. good.

[0129] The siloxane resin is a Si—O— compound formed using a siloxane material as a starting material. It corresponds to a resin containing Si bonds. Siloxane resins contain organic groups (e.g., alkane) as substituents. Alternatively, an alkyl group or an aryl group, or a fluoro group may be used. It's okay to be there.

[0130] The method for forming the planarization insulating layer 14 is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. method, spin coating method, dip method, spray coating method, droplet ejection method (inkjet method, Clean printing, offset printing, etc.), doctor knife, roll coater, A tool such as a curtain coater or a knife coater can be used.

[0131] The thickness is preferably 500 nm or more and 20 μm or less. The layer 14 is made of photosensitive acrylic and is formed to a thickness of 5 μm. A polishing process is performed to etch the planarization insulating layer 14, the oxide insulating layer 7b, and the insulating layer 10. A contact hole reaching the source electrode layer 5a is formed.

[0132] Next, a light-transmitting conductive film is formed, and a ninth photolithography step is performed. A mask is formed, and unnecessary portions are removed by etching to form the pixel electrode layer 15a and other pixel electrodes. The electrode layer 15b and the pixel electrode layer 15c of the pixel adjacent thereto are formed on the planarizing insulating layer 14, and A conductive layer 15d, which serves as a back gate of the thin film transistor of the driving circuit section, is attached to the insulating layer 10. As shown in FIG. 2(A), the pixel electrode layers 15b and 15c are formed by metal wiring. The gate electrode layer 2b is separated from the display area by this arrangement. The light can be used for display without blocking as much of it as possible.

[0133] By providing the conductive layer 15d at a position overlapping the channel formation region 8a of the oxide semiconductor layer, This can improve the reliability of thin film transistors. To check this, a bias-thermal stress test (hereinafter referred to as BT test) is performed. A thin-film transistor with a small change in threshold voltage before and after the test is a highly reliable thin-film transistor. The thin film transistor with the above structure has a difference in the resistance before and after the BT test compared to the one without the structure. The amount of change in the threshold voltage of the thin film transistor can be reduced. The layer 15d may have the same potential as the gate electrode layer 2a or may have a different potential. It can also function as a gate electrode layer.

[0134] For example, the potential of the conductive layer 15d may be GND, 0V, or may be in a floating state. Furthermore, if the threshold voltage of the thin film transistors differs between or within the substrate, The threshold voltage can be adjusted by adjusting the potential of this conductive layer 15d. .

[0135] Thereafter, a protective layer 16 is formed from polyimide to function as an alignment film. The substrate on the active matrix side of the device is completed. For convenience, this substrate is referred to as This is called an active matrix substrate.

[0136] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. The electrodes are provided on the active matrix substrate, and terminals are provided for electrical connection to the common electrode. The terminal is a terminal for setting the common electrode to a fixed potential, for example, GND or 0V.

[0137] A method for manufacturing the counter substrate 30 will be described below. The color filters are painted differently depending on the pixel, but in this case, The glass substrate 17 is a glass substrate used for the substrate 1 of the active matrix substrate. Furthermore, the transparent conductive material can be used to , a counter electrode 19, and a protective film 20 made of polyimide that functions as an alignment film.

[0138] In this way, the counter substrate 30 is obtained. After that, the protective layer 1 on the surface of the active matrix substrate is The surface of the protective film 20 of the opposing substrate 30 is subjected to rubbing treatment to orient the liquid crystal. Thereafter, a liquid crystal layer 21 made of a liquid crystal material is sandwiched between the substrates and bonded together.

[0139] When bonding the substrate 1 and the counter substrate 30 together, the cell gap of the liquid crystal display device is adjusted. The liquid crystal layer 21 is sandwiched between spacers (not shown) and a seal material (not shown) is used. The lamination step may be carried out under reduced pressure.

[0140] The sealing material typically uses visible light curing, ultraviolet curing or thermosetting resin. It is preferable to use an acrylic resin, an epoxy resin, an amine resin, or the like. In addition, photopolymerization initiators (typically ultraviolet light), heat curing agents, fillers, and coupling agents can be used. The composition may also contain a stimulating agent.

[0141] The liquid crystal layer 21 is formed by sealing a liquid crystal material in the gap. A dispenser method (dropping method) may be used to drop the adhesive agent before bonding the substrate 1 and the opposing substrate 30 together. Alternatively, the substrate 1 and the opposing substrate 30 are bonded together, and then liquid crystal is injected using capillary action. The entry method can be used.

[0142] There is no particular limitation on the liquid crystal material, and various materials can be used. If a material exhibiting a blue phase is used, the alignment treatment can be made unnecessary.

[0143] A polarizing plate 22a is provided on the outer side of the substrate 1, and a polarizing plate 22b is provided on the outer side of the counter substrate 30. A transmission type liquid crystal display device in this embodiment can be manufactured (see FIG. 2(B)).

[0144] Although not shown in the present embodiment, a black matrix (light-shielding layer), a polarizing member, a phase Optical members (optical substrates) such as a polarizing member and an anti-reflection member are provided as appropriate. A circularly polarized light source using a retardation substrate may be used. A thread or the like may also be used.

[0145] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixel electrodes, a display pattern is formed on the screen. By applying a voltage between the pixel electrode and the counter electrode corresponding to the pixel electrode, The liquid crystal layer placed between the electrodes is optically modulated, and this optical modulation is observed as a display pattern. be recognized by observers.

[0146] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0147] In addition, by increasing the normal vertical synchronization frequency by 1.5 times or more, preferably by 2 times or more, the response speed In addition, the gray scale to be written for each divided field in each frame is selected. There is also a driving technology called double speed driving, in which the speed is increased by 100 ps.

[0148] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that allows each light source to be independently lit intermittently within one frame. Three or more types of LEDs may be used, or white light emitting LEDs may be used. This allows the LEDs to be controlled in accordance with the switching timing of the optical modulation of the liquid crystal layer. The timing of light emission can also be synchronized. This driving technology allows LEDs to be partially turned off. This is especially true when the image display area is large and the black area occupies a large portion of the screen. This can reduce power consumption.

[0149] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0150] In addition, the thin film transistor described in this embodiment mode can also be applied to electronic paper. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. It is easy to read, consumes less power than other display devices, and can be made thinner and lighter. It has advantages.

[0151] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0152] Thus, electrophoretic displays utilize a technique in which materials with high dielectric constants move to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0153] The microcapsules dispersed in a solvent are called electronic ink. The ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0154] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cells, a display can be achieved. For example, an active matrix having the thin film transistor circuit described in this embodiment A substrate can be used.

[0155] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0156] FIG. 17 shows an active matrix type electronic page using the thin film transistor of this embodiment. The thin film transistor 13 used in the semiconductor device is the thin film transistor shown in this embodiment. It can be manufactured in the same way as a transistor and is a highly reliable thin film transistor containing an oxide semiconductor layer. In addition, a thin film transistor shown in any of the other embodiments can also be used. In FIG. 17, unless otherwise specified, the same parts as those in FIG. 1 or FIG. 2 are referred to as the same parts. Use the same symbol.

[0157] The electronic paper in Figure 17 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0158] The thin film transistor 13 is a thin film transistor with a bottom gate structure, and is in contact with the semiconductor layer. The source electrode layer or the drain electrode layer of the thin film transistor 13 is covered with the oxide insulating layer 7b. The polar layer is an active matrix pixel electrode layer 15g and an opening formed in the planarizing insulating layer 14. The pixel electrode layer 15g of the active matrix and the opposing substrate are in contact and electrically connected. Between the electrode layer 201 and the electrode layer 202, there are a black area 205a and a white area 205b. A spherical particle 204 is provided that includes a cavity 206 that is filled with a liquid, The area around the electrode 204 is filled with a filler 203 such as resin. 2 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 13. The common connection portion is used to connect the second electrode layer 20 to the substrate via conductive particles disposed between the pair of substrates. 2 can be electrically connected to a common potential line.

[0159] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. be.

[0160] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0161] In this way, various liquid crystal display devices can be formed using thin film transistors that use oxide semiconductors. In particular, the above method can reduce the manufacturing cost. By forming an oxide insulating film in contact with the conductor layer, a thin film transistor with stable electrical properties can be obtained. Therefore, it is possible to manufacture and provide a thin transistor with good electrical characteristics and high reliability. A semiconductor device having a film transistor can be provided.

[0162] In particular, the semiconductor layer in the channel forming region of the thin film transistor 13 is a high resistance region. The electrical characteristics of the film transistor are stabilized, and an increase in off-state current can be prevented. As a result, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be obtained. It becomes possible.

[0163] In addition, thin film transistors are easily damaged by static electricity, etc. The protection circuit is preferably provided over the same substrate as the gate insulating film. It is preferable to use a nonlinear element.

[0164] For example, the protection circuit is disposed between the pixel section and the scanning line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are provided to protect the scanning lines, signal lines, and capacitance bus lines from electrostatic discharge. It is designed to prevent damage to pixel transistors and other components when a surge voltage is applied due to wind or other factors. do.

[0165] Therefore, when a surge voltage is applied to the protection circuit, the charge is released to the common wiring. The protection circuit is composed of a nonlinear element arranged in parallel with the scanning line. The nonlinear element may be a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can be formed in the same process as the thin film transistor 13 in the pixel section. It is also possible to connect the gate terminal and drain terminal together to form a diode-like It can have characteristics.

[0166] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0167] (Embodiment 2) In this embodiment, the thin film transistor of the present invention is used in an active matrix liquid crystal display device. A case where a transparent storage capacitor is formed by utilizing a wiring layer used in a capacitor will be described.

[0168] FIG. 3 shows a circuit diagram of one pixel 31 of a typical active matrix liquid crystal display device. Here, the wiring 36 is a wiring called a gate line, a row line, or a scanning line, and The wiring 35 is used to switch the selection transistor 32 of the element. These lines are called base lines, row (column) lines, or data lines, and are used to send data to the pixels. Use it.

[0169] The transistor 32 of the pixel is turned on when a signal is sent to the wiring 36, and thereafter During the ON state, current flows between the source and drain of the transistor 32. However, when the transistor 32 is turned on, the current is cut off. When a signal is applied to the wiring 35 while in this state, the signal passes through the transistor 32. The liquid crystal element 33 is a kind of capacitor, and the opposing substrate 38 The transparency changes depending on the voltage generated by the charge held between the When the transistor 32 is turned off, the voltage of the liquid crystal element 33 is kept relatively constant.

[0170] The charge held in the liquid crystal element is kept constant when transistor 32 is in the off state. However, in reality, there is leakage current from the liquid crystal material and transistors, so This can cause flickering of the display. In the active matrix liquid crystal display device, a storage capacitor 34 is provided to reduce the electric charge. The impact of this has been reduced as much as possible.

[0171] The storage capacitor 34 is a capacitor, one terminal of which is connected to a constant potential via a capacitance line 37. In FIG. 3, the capacitance line 37 is arranged in parallel with the wiring 35. However, it may be arranged parallel to the wiring 36 or in the gate of the pixels in other rows. It is also acceptable to use a toe line.

[0172] Conventionally, the storage capacitor 34 has generally been made of a metal material, which is one of the reasons for the decrease in aperture ratio. There have also been attempts to form the storage capacitor using a transparent conductive material, but this has not been possible with conventional active materials. In a liquid crystal display device of a passive matrix type, in order to form two or more transparent conductive layers, separate However, the process requires lamination, photolithography, and etching, which reduces productivity. was.

[0173] In contrast, in one embodiment of the present invention, a transparent conductive material other than the pixel electrode layer is used for at least two layers. Therefore, if a storage capacitor is formed using this, no additional process is required. A transparent storage capacitor is obtained. The manufacturing process will be explained below with reference to FIG. The general fabrication method is the same as that of the first embodiment except for the formation of the storage capacitor, so the materials and processing methods are the same as those of the first embodiment. Further details such as the above will be omitted. Also, when referring to the same parts as in FIG. 1, the same reference numerals as in FIG. 1 are used. For details, please refer to the first embodiment. Although not shown in FIG. 4, the processing of the contact hole and the formation of the contact hole are the same as those in the first embodiment and FIG. It should be understood that this is done in the same way.

[0174] First, as in the first embodiment, a metallic conductive film is formed on a substrate 1 having an insulating surface. The first photolithography process forms thin film transistors for the active matrix driver circuit. The gate electrode layer 2a of the gate electrode 2 is formed.

[0175] Next, a light-transmitting conductive film is formed to cover the gate electrode layer 2a, and then a second photolithography The gate electrode layer 3 of the thin film transistor of the active matrix pixel is formed by a lithography process. d, and an electrode layer 3c which will be one electrode of the storage capacitor.

[0176] Next, a gate insulating layer 4 is formed on the gate electrode layers 2a, 3d and the electrode layer 3c. After forming a light-transmitting conductive film on the insulating layer 4, a third photolithography process is performed. The source electrode layer 5d and the drain electrode layer 5e of the thin film transistor of the pixel are formed by the An electrode layer 5c that will become the other electrode of the capacitor is formed (see FIG. 4(A)).

[0177] Thus, a capacitor is formed by the electrode layer 3c and the electrode layer 5c. The dielectric is a gate insulating layer 4 used as a gate insulator for a thin film transistor. Generally, it is desirable that the gate insulator of a film transistor has a high dielectric constant and is thin. However, the purpose of the storage capacitor is generally the same as that of the storage capacitor. This is desirable, so a thickness and material suitable for this is required.

[0178] Next, the gate insulating layer 4 is selectively etched by a fourth photolithography process. , a contact hole reaching the gate electrode layer 2b is formed as shown in FIG. 1(B). However, this step is not shown in FIG.

[0179] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm or more, is formed on the gate insulating layer 4. An oxide semiconductor film having a thickness of 20 nm or less is formed. The oxide semiconductor film has a thickness of 50 nm or less. Even if heat treatment for dehydration or dehydrogenation is subsequently performed, the oxide semiconductor film remains amorphous. It can maintain a good condition.

[0180] Next, as shown in FIG. 4B, the oxide semiconductor film is subjected to a fifth photolithography step. The oxide semiconductor film is etched into island-shaped oxide semiconductor layers 6a and 6c. Next, the oxidizing step as shown in the first embodiment may be performed. The compound semiconductor layer is dehydrated or dehydrogenated.

[0181] Next, the gate insulating layer 4, the oxide semiconductor layers 6a and 6c, the source electrode layer 5d, and the drain electrode layer 5d are formed. The electrode layer 5c, which will be the other electrode of the storage capacitor, is formed by sputtering. After forming the oxide insulating film, a resist mask is formed by a sixth photolithography process. Then, selective etching is performed to form oxide insulating layers 7a and 7b, and then a resist mask is applied. Remove the crust (see Figure 4(C)).

[0182] Next, a metallic film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. After the conductive film is formed, a resist mask is formed by a seventh photolithography process. Selective etching is performed to form the source electrode layer 9a and the drain electrode layer 9b (FIG. 4 4(D)). Also, as shown in FIG. 4(D), a connecting electrode electrically connected to the electrode layer 5c is The connection electrode layer 9g is electrically connected to the source electrode layer 5d of the thin film transistor of the pixel. A connection electrode layer 9e is also formed to electrically connect the drain electrode layer 5e to the first electrode layer 5f.

[0183] Next, the oxide insulating layers 7a and 7b, the source electrode layer 9a, the drain electrode layer 9b, and the connection electrode layer An insulating layer 10 is formed on the layers 9e, 9f, and 9g (see FIG. 4(E)).

[0184] By the above steps, a channel protection type thin film transistor 1 to be used in a driving circuit is formed on the same substrate. 2. A bottom-contact thin-film transistor 42 used in a pixel, and a storage capacitor of the pixel 41 can be produced.

[0185] In the above steps, the connection electrode layer 9e connected to the drain electrode layer of the thin film transistor of the pixel is formed. The structure differs from that of the thin film transistor shown in FIG. 1 in that a The reason for providing the connection electrode layer 9e is that it is necessary to connect the storage capacitor of this embodiment. More details will be given later.

[0186] In addition, in FIG. 4(E), the connection electrode layer 9g is arranged so as to occupy most of the storage capacitor 41. Although it is written in large letters, the area where this is necessary is very limited, so most of the storage capacity is transparent. It can be made of a non-woven material.

[0187] In the storage capacitor fabricated in this embodiment, one electrode layer 3c is connected to the thin film transistor of the pixel. A connection electrode layer 9g is formed in the same layer as the gate electrode layer 3d of the transistor and is connected to the other electrode layer 5c. is formed in the same layer as the connection electrode layer 9e on the drain side of the thin film transistor of the pixel. As is apparent, the gate electrode layer 3b (same as the gate electrode layer 3d in FIG. 4) is made of a metal material. The gate electrode layer 2b (gate wiring layer) is made of a material. The gate electrode layer 3d is connected to the wiring layer in the same layer as the gate electrode layer 2b (gate wiring layer) in FIG. , this may be the capacitance line 37 in FIG. 3. In this case, unlike the case shown in FIG. The capacitance line may be configured to be parallel to the wiring 36. In this case, the thin film of the pixel The connection electrode layer 9e connected to the drain electrode layer of the transistor may not be provided.

[0188] The connection electrode layer 9g connected to the electrode layer 5c is a connection electrode layer on the source side of the thin film transistor of the pixel. The connection electrode layer 9f is the same layer as the electrode layer 9f, and the connection electrode layer 9f becomes the wiring 35 in FIG. As with the capacitance line 37 of the third embodiment, the capacitance line 37 can be arranged in parallel with the wiring 35. In this case, the capacitance line 37 of the third embodiment can be arranged in parallel with the wiring 35. The electrode layer 5c must be connected to the drain electrode layer 5e of the thin film transistor. , the same layer as the connection electrode layer 9e, and the wiring shown as the connection electrode layer 9c in FIG. The electrode layer 3c is connected to the gate electrode layer 3b in the same layer via the gate electrode layer 2b. It is clear from this that this can be easily achieved.

[0189] Regarding the active matrix type liquid crystal display device having the above-described storage capacitor, 6 also illustrates the wiring intersections and capacitance portions (storage capacitances) in the first embodiment. 1 and 2. The same reference numerals will be used when referring to the following.

[0190] In FIG. 6, the thin film transistor of the pixel is a bottom-contact thin film transistor 13 In the pixel portion, as shown in FIG. 6, a storage capacitor made up of an electrode layer 3c and an electrode layer 5c The storage capacitor shown in FIG. 6 uses the gate insulating layer 4 as a dielectric.

[0191] In addition, at the wiring intersections, in order to reduce parasitic capacitance as shown in Figure 6, Between the gate insulating layer 2c and the source wiring layer 9h, the gate insulating layer 4 and the oxide insulating layer 7b are laminated. Although FIG. 6 shows an example in which the gate wiring layer 2c is made of a metal conductive film, If resistance is not an issue, or if the material has a sufficiently low sheet resistance (e.g., silver nanowires), In this case, the conductive layer 12 has the same light-transmitting property as the gate electrode layer 3a of the thin film transistor 13. It can also be formed using an electrically conductive film.

[0192] Next, using the above thin film transistor, a VA type (Verti 14 to 16 show liquid crystal display devices of the vertical alignment type. 16 will be used to explain.

[0193] Figure 14 shows the pixel structure of a VA type liquid crystal display panel. Figure 15 shows the configuration of the counter electrode. FIG. 16 is a circuit diagram of one pixel. In the following explanation, these drawings will be used. This will be explained with reference to the following.

[0194] This pixel structure has multiple pixel electrodes in one pixel, and each pixel electrode is connected to a thin-film transistor. Each thin film transistor is connected to a different gate signal. In other words, in a pixel with a multi-domain design, each pixel electrode The applied signals are independently controlled.

[0195] The thin film transistor 628 and the thin film transistor 629 are both connected to the wiring 690 and the wiring 616. The pixel electrode 624 is connected to the thin film transistor 618 through the contact hole 623. The pixel electrode 626 is connected to a transistor 628. The gate of the thin film transistor 628 is connected to the thin film transistor 629 by a wiring 619. The gate wiring 602 of the thin film transistor 629 and the gate wiring 603 of the thin film transistor 629 are connected to different gate signals. On the other hand, the wiring 616 which functions as a data line is separated so that is commonly used in the thin film transistor 628 and the thin film transistor 629. A wiring for the storage capacitor shown in this embodiment mode may be provided in parallel with the pixel electrode. The transistor 628 and the thin film transistor 629 are different from the thin film transistors shown in this embodiment mode. A thin film transistor described in any of the other embodiments may be used as appropriate.

[0196] The pixel electrodes 624 and 626 have different shapes and are separated by a slit. A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. The timing of applying voltages to the pixel electrodes 624 and 626 is controlled by the thin film transistor 6 The alignment of the liquid crystal is controlled by varying the polarity of the polarizer 28 and the polarity of the thin film transistor 629 . An equivalent circuit of this pixel structure is shown in Figure 16. The thin film transistor 628 is connected to the gate wiring 602. The thin film transistor 629 is connected to the gate wiring 603. and the gate wiring 603 are supplied with different gate signals, thereby The operation timing of the transistor 629 can be made different.

[0197] The structure of the opposing substrate side is shown in FIG. 15. The opposing substrate is As shown in the figure, a color filter layer and a counter electrode are formed. Therefore, it is desirable to provide a planarizing film between the color filter layer and the counter electrode. The counter electrode 640 is an electrode that is shared between different pixels, but has a slit 641 formed therein. The slit 641 and the slits on the pixel electrode 624 and pixel electrode 626 sides are By arranging the layers so that they interdigitate with each other, a diagonal electric field is effectively generated, and the orientation of the liquid crystal is controlled. This allows the liquid crystal to be oriented in different directions depending on the location. This allows for a wider viewing angle.

[0198] The pixel electrode 624, the liquid crystal layer, and the counter electrode 640 are overlapped to form a first liquid crystal element 651. In addition, the pixel electrode 626, the liquid crystal layer, and the counter electrode 640 are overlapped with each other, In other words, the first liquid crystal element 651 and the second liquid crystal element 652 are formed in one pixel. The liquid crystal display device 650 has a multi-domain structure in which two liquid crystal elements 652 are provided.

[0199] (Embodiment 3) In this embodiment, the appearance and cross section of an active matrix liquid crystal display panel are shown in FIG. 7. FIG. 7(A) shows an active matrix circuit made up of thin film transistors. A liquid crystal is sealed between a first substrate having a path and a second substrate (opposite substrate) by a sealant. 7(B) is a plan view of the panel, and corresponds to a cross-sectional view taken along line HI in FIG. 7(A). , including the structure shown in FIG. 2(B).

[0200] A pixel section 72, signal line driving circuits 73a and 73b, and scanning lines are provided on a first substrate 71. A sealing material 75 is provided so as to surround the driving circuits 74a and 74b. 72, a second signal line driving circuit 73a, 73b, and a second scanning line driving circuit 74a, 74b are provided on the signal line driving circuit 73a, 73b, and the scanning line driving circuit 74a, 74b. A substrate 76 is provided. Therefore, the pixel section 72, the signal line driving circuits 73a and 73b, and the driving circuits 73a and 73b are The scanning line driving circuits 74a and 74b are formed by a first substrate 71, a sealing material 75, and a second substrate 76. Thus, the liquid crystal 78 is sealed together with the liquid crystal 78. In this way, the airtightness is high so that the liquid crystal 78 is not exposed to the outside air. Protective films with little degassing (lamination films, UV-curable resin films, etc.) It is preferable to package (enclose) it in a bar material.

[0201] A pixel section 72, signal line driving circuits 73a and 73b, and a scanning line driving circuit 73a are provided on the first substrate 71. The scan line driving circuits 74a and 74b have a plurality of thin film transistors. In FIG. 7B, The thin film transistor 80 included in the pixel section 72 and the thin film transistor included in the signal line driving circuit 73a The pixel section 72 also includes a storage capacitor 81. These may be the same as those described in the first or second embodiment. You can refer to these descriptions for the configuration of the servers, etc.

[0202] The signal line driving circuits 73a and 73b, the scanning line driving circuits 74a and 74b, or the pixel section 72 The various signals and potentials are supplied from FPCs 77a and 77b.

[0203] The connection terminal electrode 82 is formed from the same conductive film as the pixel electrode layer 83, and the terminal electrode 84 is formed from a thin film. The source electrode layer and the drain electrode layer of the transistor 79 are formed using the same conductive film.

[0204] The connection terminal electrode 82 is electrically connected to the terminal of the FPC 77a via the anisotropic conductive film 85. is connected.

[0205] The signal line driving circuits 73a and 73b and the scanning line driving circuits 74a and 74b are separately prepared. It is mounted on a substrate with a driving circuit formed by a single crystal semiconductor film or a polycrystalline semiconductor film. Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or only the scanning line driver circuit, or a part of the scanning line driver circuit may be used. The portion may be separately formed and mounted, and the configuration is not limited to that shown in FIG.

[0206] An example of the configuration of the terminal section of the above-mentioned active matrix liquid crystal device is shown in FIG. 5, the same parts as those in FIGS. 1, 2 and 6 are denoted by the same reference numerals.

[0207] 5(A1) and 5(A2) are a cross-sectional view and a top view, respectively, of the gate line terminal portion. FIG. 5(A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 5(A2). In (A1), the conductive layer 15e formed on the laminate of the insulating layer 10 and the protective layer 16 is It is a terminal electrode for connection that functions as a terminal. Also, in FIG. 5(A1), , a first terminal 2d formed of the same material as the gate wiring layer 2c, and a second terminal 2c formed of the same material as the source wiring layer 9h. The gate insulating layer 4 is interposed between the connection electrode layer 9i and the conductive layer 15e. The conductive layer 15e is made of the same material as the pixel electrode layer 15a, and the same material as the pixel electrode layer 15a. It can be formed in the same process.

[0208] 5B1 and 5B2 are a cross-sectional view and a top view of the source wiring terminal portion, respectively. FIG. 5(B1) is a cross-sectional view taken along the line C3-C4 in FIG. 5(B2). In FIG. 5(B1), a conductive layer formed on the lamination of the insulating layer 10 and the protective layer 16 is The layer 15f is a terminal electrode for connection that functions as an input terminal. In the terminal portion, the electrode layer 2e formed of the same material as the gate wiring layer 2c is connected to the source wiring layer 2c. The electrode layer 2 overlaps the second terminal 9j, which is electrically connected to the gate insulating layer 4, via the gate insulating layer 4. The electrode layer 2e is not electrically connected to the second terminal 9j, and the electrode layer 2e is different from the second terminal 9j. If you set the potential, for example, floating, GND, 0V, etc., the capacitance for noise suppression Alternatively, a capacitance for anti-static measures can be formed. The conductive layer 15 is electrically connected to the conductive layer 15f via the layer 10 and the protective layer 16. The pixel electrode layer 15f can be formed using the same material having the same light-transmitting properties as the pixel electrode layer 15a in the same process.

[0209] A plurality of gate lines, source lines, common potential lines, and power supply lines are provided according to the pixel density. In addition, in the terminal section, a first terminal having the same potential as the gate wiring, a source wiring, a second terminal at the same potential as the line, a third terminal at the same potential as the power supply line, and a fourth terminal at the same potential as the common potential line. The number of each terminal can be set to any number. It is sufficient if the implementer decides accordingly.

[0210] Next, an example of a block diagram of an active matrix display device in which such connections are made is shown below. 9A. A pixel portion 91, a first scanning line driver circuit 9, and a second scanning line driver circuit 9 are provided on a substrate 90 of the display device. 2, a second scanning line driver circuit 93, and a signal line driver circuit 94. The pixel portion 91 has a plurality of The signal lines are arranged extending from the signal line driving circuit 94, and a plurality of scanning lines are arranged in the first scanning line driving circuit. The wiring 92 and the second scanning line driving circuit 93 are arranged to extend therefrom.

[0211] In the intersecting regions of the scanning lines and the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 90 is mounted on a flexible printed circuit board (FPC). A timing control circuit 95 (controller, control circuit) is connected to the timing control circuit 95 via a connection part such as a timing control circuit. It is connected to an IC.

[0212] In FIG. 9A, a first scanning line driving circuit 92, a second scanning line driving circuit 93, a signal line driving circuit The wiring 94 is formed on the same substrate 90 as the pixel section 91. Since the number of components such as the above is reduced, costs can be reduced. When a circuit is provided, the number of connections at the connection part can be reduced by extending the wiring, This can improve reliability or yield.

[0213] The timing control circuit 95 controls the first scanning line driving circuit 92 to, for example, The start signal for the scanning line driver circuit (GSP1), the clock signal for the scanning line driver circuit (GCK 1) is supplied to the second scanning line driving circuit 93. As an example, the start signal (GSP2) for the second scanning line driving circuit (also called the start pulse) A clock signal (GCK2) for the scanning line driving circuit is supplied to the signal line driving circuit 94. Start signal for signal line driver circuit (SSP), clock signal for signal line driver circuit (SCK), Video signal data (DATA) (also simply called video signal) and latch signal (LAT) Each clock signal may be a plurality of clock signals with different periods. Alternatively, it may be supplied together with an inverted clock signal (CKB). It is possible to omit either the first scanning line driving circuit 92 or the second scanning line driving circuit 93. It is possible.

[0214] In FIG. 9B, circuits with low driving frequencies (for example, the first scanning line driving circuit 92, the second scanning The scanning line driving circuit 93 is formed on the same substrate 90 as the pixel section 91, and the signal line driving circuit 94 is formed on the pixel section 91. With this configuration, the display device It is possible to increase the size of the display and speed up the display.

[0215] The thin film transistor of the driver circuit shown in Embodiment 1 is an n-channel thin film transistor. In Figure 10(A) and Figure 10(B), a signal transistor configured with an n-channel thin film transistor is shown. An example of the configuration and operation of the line driver circuit will be described below.

[0216] The signal line driver circuit includes a shift register 101 and a switching circuit portion 102. The switching circuit 102 is made up of switching circuits 102_1 to 102_N (N is a natural number). The switching circuits 102_1 to 102_N each include a thin film transistor. The thin film transistors are designated as 103_1 to 103_k (k is a natural number). The transistors 103_1 to 103_k are N-channel thin film transistors. do.

[0217] The connection relationship of the signal line driver circuit will be described using the switching circuit 102_1 as an example. The drains of the thin film transistors 103_1 to 103_k are connected to the wirings 104_1 to 104_k, respectively. The sources of the thin film transistors 103_1 to 103_k are connected to the signal lines The gates of the thin film transistors 103_1 to 103_k are connected to the wiring 1. Connected to 05_1.

[0218] The shift register 101 sequentially outputs H level (H signal, high voltage) to the wirings 105_1 to 105_N. The switching circuits 102_1 to 102_N are connected to the power supply potential level. It has the function of selecting in order.

[0219] The switching circuit 102_1 is a conductor between the wirings 104_1 to 104_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the source and drain), that is, the wiring 104_1 to 104_1 ._k is supplied to the signal lines S1 to Sk. The switching circuit 102_1 has a function as a selector.

[0220] The wirings 104_1 to 104_k are each supplied with video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. It is often the number.

[0221] Next, the operation of the signal line driver circuit of FIG. 10(A) will be explained with reference to the timing chart of FIG. 10(B). 10B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 101, and signals Vdata_1 to Vdata_ k are examples of signals input to the wirings 104_1 to 104_k. One operation period of the drive circuit corresponds to one gate selection period in the display device. For example, the period is divided into periods T1 to TN. This is a period for writing video signal data (DATA) to pixels belonging to the selected row.

[0222] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0223] During the period T1 to the period TN, the shift register 101 outputs a high-level signal to the wiring 105. For example, in the period T1, the shift register 101 outputs Then, the thin film transistor 103_1 outputs a high-level signal to the wiring 105_1. 103_k are turned on, so that the wirings 104_1 to 104_k and the signal lines S1 to Sk are At this time, the wirings 104_1 to 104_k are connected to Data(S1) to Da ta(Sk) is input. Data(S1) to Data(Sk) are the thin film transistors. The pixels in the first to kth columns of the selected row are output via registers 103_1 to 103_k. In this way, during the periods T1 to TN, the pixel in the selected row is written. Video signal data (DATA) is written to the pixels in order, k columns at a time.

[0224] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be extended, and the video signal can be written This can prevent under-crowding.

[0225] The shift register 101 and the switching circuit unit 102 are the same as those in the first embodiment. Alternatively, a circuit configured with thin film transistors as shown in 2 can be used. The polarity of all the transistors in the shift register 101 is set to N-channel or P-channel. The polarity of the casing can be either one of the polarities.

[0226] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register. In some cases, a level shifter, a buffer, etc. may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S) are input to the shift register. P) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line, and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on all at once, so the buffer must be able to pass a large current. is used.

[0227] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, 11 and 12, the shift register is a first pulse output circuit 11. 0_1 to N-th pulse output circuits 110_N (N is a natural number of 3 or more) (FIG. 1 1(A)).

[0228] The first pulse output circuits 110_1 to N-th pulses of the shift register shown in FIG. The output circuit 110_N receives a first clock signal CK1 from a first wiring 111 and a second wiring A second clock signal CK2 is output from 112, and a third clock signal CK3 is output from a third wiring 113. A fourth clock signal CK4 is supplied from a fourth wiring 114.

[0229] In the first pulse output circuit 110_1, a start pulse SP 1 (first start pulse) is input. 0_n (n is a natural number between 2 and N), the pulse output circuit 110_(n-1 ) (called the previous stage signal OUT(n-1)) is input.

[0230] In addition, in the first pulse output circuit 110_1, the third pulse output circuit 110_3, which is two stages later, Similarly, in the pulse output circuit 110_n of each stage from the second stage onwards, a signal from The signal from the (n+2)-th pulse output circuit 110_(n+2) in the subsequent stage (subsequent stage signal OUT Therefore, the nth pulse output circuit outputs the following / or the first output signal OUT(1) (SR ) to OUT(N)SR, a second output signal OUT(1) that is electrically input to another circuit, etc. OUT(N) are output.

[0231] As shown in FIG. 11(A), the last two stages of the shift register are connected to the next stage signal O. Since UT(n+2) is not input, for example, a second start pulse SP2, The third start pulse SP3 may be input to each of the input terminals.

[0232] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The four clock signals (CK4) are delayed by a quarter period in sequence (i.e., 90° from each other). In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are The clock signal (CK4) is used to control the driving of the pulse output circuit. The signal may be called GCK or SCK depending on the input drive circuit, but here it is called C I will explain as K.

[0233] Each of the first pulse output circuit 110_1 to the N-th pulse output circuit 110_N has a first input input terminal 121, a second input terminal 122, a third input terminal 123, a fourth input terminal 124, It is assumed that the fifth input terminal 125, the first output terminal 126, and the second output terminal 127 are included. (See FIG. 11(B)). The first input terminal 121, the second input terminal 122 and the third input terminal The terminal 123 is electrically connected to any one of the first wiring 111 to the fourth wiring 114. do.

[0234] For example, in FIG. 11A, the first pulse output circuit 110_1 has a first input terminal 1 21 is electrically connected to the first wiring 111, and the second input terminal 122 is electrically connected to the second wiring 112. and the third input terminal 123 is electrically connected to the third wiring 113. In addition, the second pulse output circuit 110_2 has a first input terminal 121 connected to the second wiring 11. 2, the second input terminal 122 is electrically connected to the third wiring 113, The third input terminal 123 is electrically connected to the fourth wiring 114 .

[0235] In the first pulse output circuit 110_1, a first clock signal is input to a first input terminal 121. CK1 is input to the first input terminal 122, a second clock signal CK2 is input to the second input terminal 123, and a third clock signal CK3 is input to the third input terminal 124. A third clock signal CK3 is input to the input terminal 123, and a start signal CK4 is input to the fourth input terminal 124. A second signal OUT(3) is input to the fifth input terminal 125, and a second signal OUT(4) is input to the first input terminal 126. The first output signal OUT(1)(SR) is output from the output terminal 126, and the second output terminal The second output signal OUT(1) is output from 127.

[0236] The first pulse output circuit 110_1 to the N-th pulse output circuit 110_N are each a thin film transistor with three terminals. In addition to the thin film transistor, the thin film transistor having the back gate described in the first embodiment can also be used. FIG. 11C shows a semiconductor device having a back gate as described in the above embodiment. The symbol of the thin film transistor 128 shown in FIG. The symbol for the transistor 128 is a thin-film transistor having a back gate as described in the first embodiment. In this specification, the term "thin film transistor" is used in the drawings. When a transistor has two gate electrodes through a semiconductor layer, the gate electrode below the semiconductor layer The electrode is also called the lower gate electrode, and the gate electrode above the semiconductor layer is also called the upper gate electrode. The thin film transistor 128 receives a first control signal G1 input to the lower gate electrode and a second control signal G2 input to the upper gate electrode. The voltage between the In terminal and the Out terminal is controlled by a second control signal G2 input to the gate electrode of the other terminal. It is an element that can be electrically controlled.

[0237] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, A structure that can control the threshold voltage is preferable. The threshold voltage of the thin film transistor 128 is determined by the presence of a gate electrode above and below the channel forming region of the thin film transistor 128. A gate electrode is provided via a gate insulating film, and the potential of the upper and / or lower gate electrodes is controlled. By controlling the voltage, it is possible to control the voltage to a desired value.

[0238] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0239] The first pulse output circuit 110_1 includes a first transistor 131 to a thirteenth transistor 11(D)). Also, the first input terminal 121 to the fifth input terminal 143 are In addition to the input terminal 125, the first output terminal 126, and the second output terminal 127, a power supply line 151 to which a power supply potential VDD is supplied, and a power supply line 152 to which a second high power supply potential VCC is supplied; 152, a power supply line 153 to which a low power supply potential VSS is supplied, and A signal or a power supply potential is supplied to the thirteenth transistor 143. The magnitude relationship of the power supply potentials of the power supply lines is as follows: the first power supply potential VDD is higher than the second power supply potential VCC. The second power supply potential VCC is set to a potential higher than the third power supply potential VSS. The first clock signal (CK1) to the fourth clock signal (CK4) go high at regular intervals. It is a signal that alternates between high and low levels, but when it is high it is VDD and when it is low it is VSS. As shown in FIG. 11(D), the first transistor 131 to the thirteenth transistor The first transistor 131, the sixth transistor 136 to the ninth transistor 137, and the sixth transistor 138 are connected to the first transistor 131 and the sixth transistor 138 to the ninth transistor 139. The transistor 139 is a thin film transistor having a back gate as shown in FIG. It is preferable to use the first transistor 131 and the sixth transistor 132. The sixth to ninth transistors 139 operate when one of the source and drain electrodes is connected to a The potential of the node connected to the gate electrode is required to be switched by the control signal of the gate electrode. It is a transistor that responds quickly to the control signal input to the gate electrode (the rise of the on-current A transistor that can reduce malfunctions in the pulse output circuit by having a steep rise time. Therefore, the thin film transistor 12 having a back gate shown in FIG. By using 8, the threshold voltage can be controlled, and malfunctions can be further reduced. In FIG. 11(D), the first control signal G1 and the second control signal G2 are Although the circuit configuration is such that the control signal G2 is the same, a configuration in which different control signals are input may also be used. stomach.

[0240] In FIG. 11D, the drain of the first transistor 131 is electrically connected to the power supply line 151. the source is electrically connected to the drain of the ninth transistor 139, and the gate voltage The electrodes (lower gate electrode and upper gate electrode) are electrically connected to the fourth input terminal 124. It is being done.

[0241] The drain of the second transistor 132 is electrically connected to the power supply line 153, and the source of the second transistor 132 is electrically connected to the power supply line 153. The gate electrode of the fourth transistor 139 is electrically connected to the drain of the fourth transistor 139. The gate electrode of the capacitor 134 is electrically connected to the gate electrode of the capacitor 134 .

[0242] The third transistor 133 has a drain electrically connected to the first input terminal 121 and a The source is electrically connected to the first output terminal 126. The fourth transistor 134 The drain is electrically connected to the power supply line 153 and the source is electrically connected to the first output terminal 126. is connected.

[0243] The fifth transistor 135 has a drain electrically connected to the power supply line 153 and a source The gate electrode of the second transistor 132 and the gate electrode of the fourth transistor 134 are electrically connected to each other. The gate electrode is electrically connected to the fourth input terminal 124 .

[0244] The sixth transistor 136 has a drain electrically connected to the power supply line 152 and a source The gate electrode of the second transistor 132 and the gate electrode of the fourth transistor 134 are electrically connected to each other. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the fifth input terminal 125 is electrically connected to the

[0245] The seventh transistor 137 has its drain electrically connected to the power line 152, its source electrically connected to the source of the eighth transistor 138, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the third input terminal 123.

[0246] The eighth transistor 138 has its drain electrically connected to the gate electrode of the second transistor 132 and the gate electrode of the fourth transistor 134, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the second input terminal 122.

[0247] The ninth transistor 139 has its drain electrically connected to the source of the first transistor 131 and the second transistor 132, its source electrically connected to the gate electrode of the third transistor 133 and the gate electrode of the tenth transistor 140, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the power line 152. .

[0248] The tenth transistor 140 has its drain electrically connected to the first input terminal 121, its source electrically connected to the second output terminal 127, and its gate electrode electrically connected to the source of the ninth transistor 1 39.

[0249] The eleventh transistor 141 has its drain electrically connected to the power line 153, its source electrically connected to the second output terminal 127, and its gate electrode electrically connected to the gate electrode of the second transistor 132 and the gate electrode of the fourth transistor 134.

[0250] The twelfth transistor 142 has a drain electrically connected to the power supply line 153 and a source The gate electrode of the seventh transistor 137 is electrically connected to the second output terminal 127. The gate electrodes are electrically connected to the gate electrodes (lower gate electrode and upper gate electrode).

[0251] The thirteenth transistor 143 has a drain electrically connected to the power supply line 153 and a source The seventh transistor 137 has a gate electrode electrically connected to the first output terminal 126 and a gate electrode electrically connected to the gate of the seventh transistor 137. The gate electrodes are electrically connected to the gate electrodes (lower gate electrode and upper gate electrode).

[0252] In FIG. 11D, the gate electrode of the third transistor 133, the gate electrode of the tenth transistor The connection point of the gate electrode of the ninth transistor 140 and the source of the ninth transistor 139 is referred to as node A. The gate electrode of the second transistor 132 and the gate electrode of the fourth transistor 134 are connected to each other. electrode, the source of the fifth transistor 135, the source of the sixth transistor 136, the eighth The drain of the transistor 138 and the connection point of the eleventh transistor 141 are connected to a node B (See FIG. 12(A)).

[0253] In FIG. 11(D) and FIG. 12(A), the node A is set to the floating state. A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0254] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 12(B). In this case, the period 161 in FIG. 12(B) is a vertical blanking period, and the period 62 corresponds to a gate selection period. Correct.

[0255] As shown in FIG. 12A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 139, the following occurs before and after the bootstrap operation: There are advantages such as:

[0256] If the ninth transistor 139, whose gate electrode is applied with the second potential VCC, is not present, the boost When the potential of the node A rises due to the trap operation, the source of the first transistor 131 The potential of the first transistor rises and becomes higher than the first power supply potential VDD. In the transistor 131, there are large gate-source and drain-drain The bias voltage applied causes a large stress, which can cause the transistor to deteriorate. It is possible.

[0257] Therefore, a ninth transistor 139 is provided to the gate electrode of which the second power supply potential VCC is applied. By keeping the voltage at node A low, the voltage at node A rises due to the bootstrap operation. This can prevent the rise in the potential of the source of the first transistor 131. By providing the ninth transistor 139, the gate of the first transistor 131 Therefore, the voltage between the source and the output of the first transistor 131 can be reduced. Deterioration can be suppressed.

[0258] The ninth transistor 139 is provided in a location where the first transistor 131 A third transistor 133 is connected between its source and the gate through its drain and source. In this embodiment, a plurality of pulse output circuits are provided. In the case of a shift register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 139 may be omitted.

[0259] Note that the semiconductor layers of the first to thirteenth transistors 131 to 143 are made of oxide. By using a compound semiconductor, the off-current of the thin film transistor is reduced and the on-current is also reduced. and the field effect mobility can be increased, and the degree of degradation can be reduced. Therefore, malfunctions within the circuit can be reduced.

[0260] Furthermore, transistors using oxide semiconductors have The degree of deterioration of the transistor due to the application of a high potential to the gate electrode is small. Therefore, the same effect occurs when the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC. This allows for a reduction in the number of power supply lines between circuits, It is also possible to make it smaller.

[0261] In FIG. 11(D) (and FIG. 12(A)), the gate voltage of the seventh transistor 137 is The electrodes (lower gate electrode and upper gate electrode) are supplied by a third input terminal 123. A clock signal is input to the gate electrode of the eighth transistor 138 (the lower gate electrode and A clock signal supplied by a second input terminal 122 is input to the gate electrodes (the upper and lower gate electrodes). Each of them receives a clock signal supplied by the second input terminal 122. The wiring relationship is input so that the clock signal is supplied by the third input terminal 123. The same effect can be achieved even if the two are replaced.

[0262] If the wiring relationships are rearranged as described above, the shift register shown in FIG. Then, the seventh transistor 137 and the eighth transistor 138 are both turned on, and the third transistor 138 is turned off. The seventh transistor 137 is turned off and the eighth transistor 138 is turned on. The seventh transistor 137 is turned off, and the eighth transistor 138 is turned off. Accordingly, the potentials of the second input terminal 122 and the third input terminal 123 decrease. As a result, the potential at node B drops twice.

[0263] In the shift register shown in FIG. 12A, the seventh transistor 137 and the eighth transistor The seventh transistor 137 is turned on, and the eighth transistor 138 is turned on. The seventh transistor 137 is turned off, and the eighth transistor 138 is turned off. By turning off the transistor 138, the potential at the node B is reduced by the eighth transistor. This can be reduced by a drop in the potential of the gate electrode of the transistor 138.

[0264] Therefore, the gate electrode of the seventh transistor 137 (the lower gate electrode and the upper gate electrode) a clock signal provided by the third input terminal to the eighth transistor 138; The gate electrodes (lower gate electrode and upper gate electrode) are supplied with a voltage from the second input terminal. By using a clock signal that is generated by the clock, the fluctuation of the potential of node B is reduced, and noise can be reduced. This is preferable because it can reduce noise.

[0265] In this way, the potentials of the first output terminal 126 and the second output terminal 127 are kept at the L level. By configuring the node B to periodically receive a high-level signal during this period, This can suppress malfunction of the output circuit.

[0266] The active matrix liquid crystal display device disclosed in this specification, including the present embodiment, The present invention can be applied to various electronic devices (including gaming machines). For example, television equipment (also called television or television receiver), computer Monitors, digital cameras, digital video cameras, digital photo frames, mobile phones, etc. Telephones (also called mobile phones or mobile phone devices), portable game consoles, personal digital assistants, and sound reproduction Examples include large gaming machines such as pachinko machines.

[0267] 13A shows an example of a mobile phone. The mobile phone 1100 has a housing 1101. In addition to the display unit 1102 incorporated in the device, the device also includes operation buttons 1103, an external connection port 1104, It is equipped with a speaker 1105, a microphone 1106, etc.

[0268] The mobile phone 1100 shown in FIG. 13A displays information by touching the display portion 1102 with a finger or the like. In addition, operations such as making a phone call or sending an email can be performed using the display. This can be done by touching 1102 with a finger or the like.

[0269] The screen of the display unit 1102 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0270] For example, when making a call or creating an email, the display unit 1102 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1102. I wish.

[0271] In addition, the mobile phone 1100 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1100 (portrait or landscape) can be determined and the display The screen display of the display unit 1102 can be automatically switched.

[0272] The screen mode can be switched by touching the display unit 1102 or by operating the housing 1101. This is done by operating the button 1103. Also, depending on the type of image displayed on the display unit 1102, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0273] In the input mode, the optical sensor of the display unit 1102 detects a signal and displays it. If there is no input by touch operation of the part 1102 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0274] The display unit 1102 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0275] The display portion 1102 includes a plurality of thin film transistors 13 shown in Embodiment 1. Since the transistor 13 has a light-transmitting property, when a light sensor is provided in the display portion 1102, This is effective because the thin film transistor 13 does not block the incident light. When using a backlight that emits light or a sensing light source that emits near-infrared light This is also preferable because the thin film transistor 13 does not block light.

[0276] FIG. 13(B) is also an example of a mobile phone. The portable information terminal shown in FIG. 13(B) is It can have multiple functions. For example, in addition to the telephone function, it can also have a built-in computer and perform various functions. It can also have various data processing functions.

[0277] The portable information terminal shown in FIG. 13B is configured with two housings, a housing 1800 and a housing 1801. The housing 1800 includes a display panel 1802, a speaker 1803, a microphone Phone 1804, pointing device 1806, camera lens 1807, external connection The housing 1801 is provided with a keyboard 1810, an external memory slot, etc. 1811, etc. The antenna is built into the housing 1801.

[0278] The display panel 1802 is equipped with a touch panel, and the image displayed on the display panel 1802 is shown in FIG. A plurality of operation keys 1805 are indicated by dotted lines.

[0279] In addition to the above configuration, a contactless IC chip, a small recording device, etc. may be built in.

[0280] An active matrix liquid crystal display device can be used for the display panel 1802. The display direction changes appropriately depending on the display mode. The camera is equipped with a lens 1807, which allows video calls. The microphone 1804 is not limited to voice calls, but is also capable of video calls, recording, playback, etc. Furthermore, the housing 1800 and the housing 1801 slide and unfold as shown in FIG. 13(B). The device can be folded from a flat state to an overlapping state, making it possible to miniaturize it for portability.

[0281] The external connection terminal 1808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 1811, it is possible to store and transfer a larger amount of data. do.

[0282] In addition to the above functions, it also has infrared communication functions, TV reception functions, etc. Good too.

[0283] As described above, the active matrix display devices shown in the first and second embodiments have the following features: The thin film transistor 12 can be disposed on the display panel of various electronic devices such as the The thin film transistor 13 is used as a switching element of the display panel. This allows the active matrix display device to have a high aperture ratio, especially when it is a bottom emission type. It is possible to provide a highly reliable electronic device having a display unit having the above-mentioned display element.

[0284] (Fourth embodiment) In this embodiment, an example in which a part of the manufacturing process of a thin film transistor is different from that in Embodiment 1 is shown in FIG. Figure 8 is the same as Figure 1 except for some differences in the process, so the same parts are designated with the same symbols. The same reference numerals will be used and detailed explanations of the same parts will be omitted.

[0285] First, according to the first embodiment, two types of gate electrode layers 2a, 2b, 3a, and 3b are formed on a substrate 1. Then, a gate insulating layer 4 is formed, and a solenoid is formed that partially overlaps the gate electrode layer 3a via the gate insulating layer 4. Then, a gate insulating layer 4, a source electrode layer 5a, and a drain electrode layer 5b are formed. An oxide semiconductor film 6 is formed on the electrode layer 5a and the drain electrode layer 5b.

[0286] Next, the oxide semiconductor film 6 is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or higher, preferably 425° C. or higher. If the temperature is above 425°C, the heat treatment time can be 1 hour or less. , and for a period longer than one hour.

[0287] Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor film 6 is After the heat treatment under a nitrogen atmosphere, the oxide semiconductor film 6 was While preventing the re-incorporation of water or hydrogen, high-purity oxygen gas, high-purity N2O gas, or Cooling is carried out by introducing ultra-dry air (dew point below -40°C, preferably below -60°C). It is preferable that the nitrogen gas or N2O gas does not contain water, hydrogen, etc. The purity of oxygen gas or N2O gas introduced into the treatment equipment must be 6N (99.9999%) or higher. Preferably, 7N (99.99999%) or more (i.e., impurities in oxygen gas or N2O gas) It is preferable to keep the concentration of the substance at 1 ppm or less, preferably 0.1 ppm or less.

[0288] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor, the oxide semiconductor film 6 In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. The proportion of the component in the whole is 80% or more (preferably 90% or more), and the adjacent fine grains It is preferable that the crystal grains are packed so as to be in contact with each other. may be in an amorphous state.

[0289] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0290] By going through the above steps, the entire oxide semiconductor film 6 is made into an oxygen-excess state, and thus high In this embodiment, the oxide semiconductor film 6 is deionized immediately after being formed. Although the first heat treatment for hydration or dehydrogenation is described as an example, it is not particularly limited. Any process may be performed after the semiconductor film 6 is formed.

[0291] Next, the oxide semiconductor film 6 and the gate insulating layer 4 are selectively etched by a photolithography process. The oxide semiconductor film 6 is then etched to form a contact hole that reaches the gate electrode layer 2b. By forming a resist on the gate insulating layer 4, contamination of the interface between the gate insulating layer 4 and the oxide semiconductor film 6 can be prevented. The state after removing the resist mask is shown in FIG.

[0292] Next, the oxide semiconductor film 6 is selectively etched to form island-shaped oxide semiconductor layers 6c and 6d. (See FIG. 8(B)).

[0293] Next, an oxide insulating film is formed on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d by sputtering. After forming the film, a resist mask is formed by a photolithography process, and selective etching is performed. Then, oxide insulating layers 7a and 7b are formed by etching, and the resist mask is then removed. At this stage, a region of the oxide semiconductor layer that is in contact with the oxide insulating layer is formed, and in this region, The region where the gate electrode layer 2a and the oxide insulating layer 7a overlap with each other via the gate insulating layer 4 is a channel-shaped region. In addition, the region overlapping with the oxide insulating layer 7b that covers the periphery and side surfaces of the oxide semiconductor layer is Also, a contact region reaching the gate electrode layer 2b is formed by this photolithography process. A contact hole is formed, and a contact hole reaching the drain electrode layer 5b is also formed ( See Figure 8(C).

[0294] The oxide insulating film is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film is used to block the penetration of oxygen from the atmosphere. A film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0295] Next, an oxide conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. By using the sputtering method, a laminate of an oxide conductive film and a metal conductive film is formed. The above stacked layers can be continuously formed without being exposed to the air.

[0296] The oxide conductive film preferably contains zinc oxide as a component and does not contain indium. As such an oxide conductive film, zinc oxide, zinc aluminum oxide, etc. Examples of the zinc oxide include aluminum, zinc aluminum oxynitride, and zinc gallium oxide. In this case, a zinc oxide film is used.

[0297] The metal conductive film may be made of an element selected from Ti, Mo, W, Al, Cr, Cu, and Ta. The alloys used are those containing the above elements or those combining the above elements. In addition, the layer is not limited to a single layer containing the above-mentioned elements, and a laminate of two or more layers can be used. In this embodiment, a three-layer laminate of a molybdenum film, an aluminum film, and a molybdenum film is used. A membrane is used.

[0298] Next, a resist mask is formed, and the metal conductive film is selectively etched to form the source electrode layer 2. 3a, the drain electrode layer 23b, the connection electrode layers 23c and 23d are formed, and then a resist mask is formed. The resist remover used to remove the resist mask is aluminum. When a resist stripping solution is used, the source electrode layer 23a and the drain electrode The oxide conductive film is also selectively etched using the layer 23b and the connection electrode layers 23c and 23d as a mask. It will be googled.

[0299] An oxide conductive layer 24a is formed under and in contact with the source electrode layer 23a, and a drain electrode layer 23b The oxide conductive layer 24b is formed below and in contact with the source electrode layer 23a and the oxide semiconductor layer. By providing the oxide conductive layer 24a between the electrodes, the contact resistance can be reduced, and the resistance can be reduced. The source electrode layer 23a and the oxide semiconductor layer 23b can be formed on the thin film transistor 100b. The oxide conductive layer 24a provided between the conductor layer functions as a source region, and the drain electrode The oxide conductive layer 24b provided between the layer 23b and the oxide semiconductor layer serves as a drain region. This function is effective in improving the frequency characteristics of peripheral circuits (drive circuits).

[0300] Furthermore, when the molybdenum film and the oxide semiconductor layer are in direct contact with each other, there is a problem that the contact resistance becomes high. This is because Mo is less likely to oxidize than Ti, and therefore has the effect of extracting oxygen from the oxide semiconductor layer. This is because the contact interface between Mo and the oxide semiconductor layer is weak and does not become N-type.

[0301] However, even in such a case, the oxide conductive layer 24a is provided between the oxide semiconductor layer and the source electrode layer. The oxide conductive layer 24b is interposed between the oxide semiconductor layer and the drain electrode layer. This reduces contact resistance and improves the frequency characteristics of the peripheral circuits (drive circuits). .

[0302] In the same process, an oxide conductive layer 24c is formed below and in contact with the connection electrode layer 23c. An oxide conductive layer 24d is formed below and in contact with the electrode layer 23d (see FIG. 8(D)). By forming an oxide conductive layer 24c between the electrode layer 23c and the gate electrode layer 2b, The resistance becomes thin, and the series resistance is only that of the thickness, which is preferable. Furthermore, it does not form an insulating oxide with the metal. This is preferable because it does not

[0303] Since the oxide semiconductor layer and the oxide conductive layer have different etching rates, The overlying oxide conductive layer can be removed by time control.

[0304] After selectively etching the metal conductive film, the resist mask is removed by oxygen ashing. After removing the oxide conductive film, the source electrode layer 23a, the drain electrode layer 23b, The oxide conductive film may be selectively etched using the connection electrode layers 23c and 23d as a mask. .

[0305] In addition, when the first heat treatment is performed after selectively etching the metal conductive film, the oxide conductive film is The layers 24a, 24b, 24c, and 24d do not contain crystallization inhibitors such as silicon oxide. As long as the first heat treatment is performed, the oxide conductive layers 24a, 24b, 24c, and 24d are crystallized. Due to this mechanism, the oxide semiconductor layer does not crystallize and remains amorphous. As a result, the source and drain electrodes are formed. In addition, when etching the metal film above the oxide conductive layer, the underlayer oxide conductive layer is This can prevent cuts from forming.

[0306] Next, in order to reduce the variation in the electrical characteristics of the thin film transistors, Alternatively, a second heat treatment (preferably at 150° C. or higher and lower than 350° C.) is performed in a nitrogen gas atmosphere. For example, heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere. By the heat treatment, oxygen is introduced from the oxide insulating film or the like in contact with the oxide semiconductor layer into the oxide semiconductor layer. The impregnation and diffusion of oxygen into the oxide semiconductor layer creates a channel formation region. This allows the resistance of the thin film transistor to be increased (i-type). The second heat treatment can be performed to form the oxide conductive layers 24a and 24b. The conductivity of 4b, 24c, and 24d can also be improved by crystallizing them.

[0307] Next, insulating layers are formed on the oxide insulating layers 7a and 7b, the source electrode layer 23a, and the drain electrode layer 23b. A layer 10 is formed (see FIG. 8(E)).

[0308] By the above steps, the thin film transistor 25 and the thin film transistor 13 are fabricated on the same substrate. It is possible.

[0309] The thin film transistor 25 disposed in the driving circuit is provided on the substrate 1 having an insulating surface, and has a gate electrode Layer 2a, gate insulating layer 4, oxide semiconductor layer, oxide conductive layers 24a and 24b, source electrode layer The oxide semiconductor layer includes at least a channel formation region, a drain electrode layer, and a drain electrode layer. An oxide insulating layer 7a is provided in contact with the channel forming region 26. An insulating layer 10 is provided on the source electrode layer 23a and the drain electrode layer 23b. do.

[0310] In addition, the first region 27c and the second region 27d of the oxide semiconductor layer 6c in contact with the oxide insulating layer 7b is in the same oxygen-excess state as the channel forming region 26, and is effective in reducing leakage current and reducing parasitic capacitance. In addition, the third region of the oxide semiconductor layer 6c in contact with the insulating layer 10 also serves to reduce the The region 27e is provided between the channel formation region 26 and the high-resistance source region 27a. The fourth region 27f of the oxide semiconductor layer 6c in contact with the insulating layer 10 is high in relation to the channel formation region 26. The first insulating layer 10 is provided between the resistive drain regions 27b and the oxide semiconductor layer 6c. The third region 27e and the fourth region 27f can reduce the off current.

[0311] The active matrix substrate thus obtained is the same as that described with reference to FIG. 2 in the first embodiment. As shown in the figure, it can be combined with an opposing substrate to form an active matrix liquid crystal display device. This can be done.

[0312] This embodiment mode can be freely combined with either embodiment mode 2 or 3. [Explanation of symbols]

[0313] 1 board 2a Gate electrode layer 2b Gate electrode layer 2e electrode layer 3a Gate electrode layer 3b Gate electrode layer 3c electrode layer 3d gate electrode layer 4 Gate insulating layer 5a Source electrode layer 5b Drain electrode layer 5c electrode layer 5d Source electrode layer 5e Drain electrode layer 6. Oxide semiconductor film 6a Oxide semiconductor layer 6b Oxide semiconductor layer 6c Oxide semiconductor layer 7a Oxide insulating layer 7b Oxide insulating layer 8a Channel formation region 8b Oxide semiconductor layer 9a Source electrode layer 9b Drain electrode layer 9c Connection electrode layer 9d Connection electrode layer 9e Connection electrode layer 9f Connection electrode layer 9g Connection electrode layer 9i connection electrode layer 10 Insulating layer 11a High-resistance source region 11b High-resistivity drain region 11c 1st area 11d 2nd area 11e 3rd area 11f 4th area 12 Thin-film transistor 13 Thin-film transistor 14 Planarizing insulating layer 15a Pixel electrode layer 15b Pixel electrode layer 15c Pixel electrode layer 15d Conductive layer (back gate) 15e Conductive layer 15f conductive layer 15g Pixel electrode layer 16 Protective layer 17 Glass substrate 18 Color filter layer 19 Counter electrode 20 Protective film 21 Liquid crystal layer 22a Polarizing plate 22b Polarizing plate 23a Source electrode layer 23b Drain electrode layer 23c Connection electrode layer 23d Connection electrode layer 24a conductive layer 24b Conductive layer 24c conductive layer 24d conductive layer 25 Thin-film transistor 26 Channel formation region 27c 1st area 27d 2nd area 27e Third area 27f 4th area 30 Opposing substrate 38 Opposing substrate 42 Thin-film transistor 71 PCB 76 Circuit Board 79 Thin-film transistor 80 Thin-film transistor 83 Pixel electrode layer 90 PCB 103 Thin-film transistor 128 Thin Film Transistor 201 Opposing substrate 202 Electrode layer 628 Thin Film Transistor 629 Thin-film transistor 640 Counter electrode

Claims

1. A pixel portion and a driver circuit portion are included. the pixel portion has a first transistor, the drive circuit unit has a second transistor, the first transistor has a single gate structure, a channel formation region of the first transistor is provided in a first oxide semiconductor layer; the second transistor has a first gate electrode layer and a second gate electrode layer; a channel formation region of the second transistor is provided in a second oxide semiconductor layer; the second gate electrode layer has a region facing the first gate electrode layer with the second oxide semiconductor layer interposed therebetween; the second gate electrode layer is supplied with the same potential as the first gate electrode layer; a conductive layer functioning as a source electrode layer or a drain electrode layer of the first transistor is provided to have a region in contact with a bottom surface of the first oxide semiconductor layer; a display device, wherein an oxide insulating layer containing silicon oxide is provided to have a region in contact with a top surface of the first oxide semiconductor layer, a region in contact with a side surface of the first oxide semiconductor layer, and a region in contact with a side surface of the second oxide semiconductor layer.

2. A pixel portion and a driver circuit portion are included. the pixel portion has a first transistor, the drive circuit unit has a second transistor, the first transistor has a single gate structure, a channel formation region of the first transistor is provided in a first oxide semiconductor layer; the second transistor has a first gate electrode layer and a second gate electrode layer; a channel formation region of the second transistor is provided in a second oxide semiconductor layer; the second gate electrode layer has a region facing the first gate electrode layer with the second oxide semiconductor layer interposed therebetween; the second gate electrode layer is supplied with the same potential as the first gate electrode layer; a conductive layer functioning as a source electrode layer or a drain electrode layer of the first transistor is provided to have a region in contact with a bottom surface of the first oxide semiconductor layer; a display device, wherein an oxide insulating layer containing silicon oxide is provided to have a region in contact with a top surface of the first oxide semiconductor layer, a region in contact with a side surface of the first oxide semiconductor layer, a region in contact with a top surface of the second oxide semiconductor layer, and a region in contact with a side surface of the second oxide semiconductor layer.

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