Deposition mask and method for manufacturing electronic device

Abstract

To provide a vapor deposition mask capable of forming a vapor deposition film having an excellent pattern dimension and suppressing mutual influence between adjacent pixels, and to provide a method for manufacturing an electronic device using the vapor deposition mask.SOLUTION: The vapor deposition mask 1 is arranged between a substrate to be vapor-deposited and a vapor deposition source to vapor-deposit a vapor deposition material from the vapor deposition source through an opening 5, and has a first face 2 a facing the substrate to be vapor-deposited and a second face 2b positioned on the opposite side of the first face and facing the vapor deposition source. A plurality of openings penetrating between the first surface and the second surface are formed, the sidewall surfaces 6 of the openings are inclined so that the opening widths become narrower from the second surface side toward the first surface side, the opening widths W1 defined on the first surface side are larger than 3 μm and smaller than 15 μ m, the deposition mask has a configuration in which a membrane having openings is supported on the support substrate 4, the support substrate includes a Si layer and a side SiO2 layer, and the membrane has SiN.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a deposition mask and a method for manufacturing an electronic device. [Background technology]

[0002] For example, a deposition mask is known that is used to paint three RGB colors when manufacturing organic EL displays.

[0003] As shown in Patent Documents 1 and 2, the deposition mask has a plurality of openings, and the deposition material passes through the openings to form a film on the deposition substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-184708 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-189990 Summary of the Invention [Problem to be solved by the invention]

[0005] Variations in the opening width of a deposition mask can cause mutual influence between adjacent pixels in the deposited film formed on the deposition substrate, which can increase the risk of color mixing, for example. For this reason, a deposition mask that can improve the pattern dimensions of the deposited film and suppress mutual influence between adjacent pixels was needed.

[0006] An object of the present invention is to provide a deposition mask that can form a deposited film having excellent pattern dimensions and can suppress mutual influence between adjacent pixels, and a method for manufacturing an electronic device using the deposition mask. [Means for solving the problem]

[0007] The deposition mask of the present embodiment is a deposition mask that is placed between a substrate to be deposited and a deposition source, and that deposits a deposition material from the deposition source onto a surface of the substrate to be deposited through openings. The deposition mask has a first surface facing the substrate to be deposited and a second surface located opposite the first surface and facing the deposition source. A plurality of openings are formed between the first surface and the second surface, and sidewall surfaces of the openings are inclined so that the opening widths narrow from the second surface side toward the first surface. The opening width defined on the first surface side is greater than 3 μm and smaller than 15 μm. The deposition mask has a configuration in which a membrane having the openings is supported on a supporting substrate, the supporting substrate includes a Si layer and a SiO2 layer, and the membrane contains SiN. [Effects of the Invention]

[0008] According to the present invention, by controlling the opening width and the variation σ, it is possible to stably form a vapor-deposited film that has excellent pattern dimensions and reduces the risk of color mixing between adjacent pixels. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a cross-sectional view showing an example of a deposition mask according to the present embodiment. [Figure 2] 2 is an enlarged cross-sectional view of a part of the deposition mask shown in FIG. 1. FIG. [Figure 3] FIG. 2 is a partially enlarged cross-sectional view showing a part of an opening of the deposition mask of the present embodiment. [Figure 4] 1A to 1C are cross-sectional views showing a method for manufacturing an electronic device using the vapor deposition mask of the present embodiment. [Figure 5] FIG. 1 is an image diagram of adjacent pixels formed on a substrate to be vapor-deposited. [Figure 6] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a vapor deposition mask according to an embodiment of the present invention. [Figure 7] 1A to 1C are process diagrams illustrating an example of a method for manufacturing a vapor deposition mask according to an embodiment of the present invention. [Figure 8] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing an example of a deposition mask according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. Furthermore, even when the same parts are shown between the drawings, the dimensional relationships and ratios between them may be different. In particular, the embodiments shown below are merely examples of structures for embodying the technical idea of ​​the present invention, and do not specify the technical idea of ​​the present invention. In the following description, elements having the same function and configuration are designated by the same reference numerals, and redundant description will be omitted. Furthermore, the lower and upper limits of numerical ranges include error ranges.

[0011] <Background to the Invention> Virtual reality / augmented reality (VR / AR) technology and the VR / AR-related market are growing rapidly. As this growth continues, display panels suitable for the VR / AR field are becoming smaller, with higher pixel counts (PPI), faster response times, and wider color gamuts. Silicon-based organic light-emitting diode (OLED) microdisplay panels are becoming increasingly popular as a driving force behind these technological advances.

[0012] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and higher PPI. To effectively prepare for AR and VR as high-value-added industries, it is expected to realize ultra-high resolution displays, for example, over 1000 ppi. As a result, there is a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.

[0013] The deposition mask has a plurality of openings corresponding to the deposited film, and the accuracy of the openings in the deposition mask is important for improving the pattern dimensions of the deposited film.

[0014] The deposition mask is disposed between the substrate to be deposited and the deposition source, and the deposition material passes from the deposition source through the openings in the deposition mask and reaches the surface of the substrate to be deposited. The width of the openings in the deposition mask in this embodiment has been narrowed to meet the needs of the OLED microdisplays described above. However, if the opening width is too small, the deposition material will accumulate on the sidewalls of the openings, making the opening width narrower than the actual width, and making it difficult to form a deposition film with excellent pattern dimensions.

[0015] On the other hand, as the aperture width becomes wider, the variation in aperture width tends to increase. The effect of variation on the deposited film formed on the substrate is small if the light-emitting area is large, but the risk of color mixing with adjacent pixels increases. Since the risk of color mixing is determined by the absolute value of the variation σ in the aperture width, it was necessary to reduce the variation σ.

[0016] Therefore, as a result of intensive research, the inventors have focused on the opening width and the variation σ and have developed a deposition mask that has excellent pattern dimensions while suppressing mutual influence between adjacent pixels (for example, the risk of color mixing).

[0017] <Outline of the deposition mask 1 according to the present embodiment> Fig. 1 is a cross-sectional view of a deposition mask 1 according to the present embodiment. Fig. 2 is a cross-sectional view showing an enlarged portion of the deposition mask shown in Fig. 1. Fig. 3 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask according to the present embodiment. Fig. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask according to the present embodiment.

[0018] The deposition mask 1 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably made of an SOI (Silicon on Insulator) substrate 9.

[0019] The semiconductor layer 2 is preferably a silicon single crystal layer, and is also called an active layer or a membrane. There are no limitations on the thickness of the semiconductor layer 2, but it is about 1 μm to 300 μm.

[0020] 1, the deposition mask 1 has a plurality of opening regions 15 and a surrounding region 16 located around the opening regions 15. The surrounding region 16 has a structure in which a semiconductor layer 2, an insulating layer 3, and a support substrate 4 are stacked. On the other hand, only the semiconductor layer 2 is disposed in the opening regions 15, that is, the insulating layer 3 and the support substrate 4 are removed, and each opening region 15 has a plurality of minute openings 5 ​​formed therein.

[0021] FIG. 2 is an enlarged view of the vicinity of one of the opening regions 15 shown in FIG. 2, the semiconductor layer 2 has a first surface 2a and a second surface 2b that face each other in the thickness direction. An insulating layer 3 and a support substrate 4 are provided on the second surface 2b side. As shown in FIG. 4, the first surface 2a is the surface facing the deposition target substrate 10, and the second surface 2b is the back surface facing the deposition source 11.

[0022] As shown in FIG. 2, a plurality of openings 5 ​​are formed in the semiconductor layer 2, penetrating between the first surface 2a and the second surface 2b. As shown in FIG. 2, the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a. Therefore, the sidewall surface 6 of the opening 5 is inclined. Also, in FIG. 2, the opening width W1 is defined by the width dimension in the planar direction along the first surface 2a. Thus, in FIG. 2, the opening width W1 is illustrated at the point where the width dimension is narrowest. Note that in FIG. 2, the reference symbols for the opening width W1 and the sidewall surface 6 are illustrated for only one opening 5, but they also apply to the other openings 5 ​​in the same way. Note that the shape of the sidewall surface 6 of the opening 5 will be described in detail later.

[0023] The planar pattern of the openings 5 ​​(the shape when viewed from directly above the semiconductor layer 2 toward the first surface 2a) is not limited to any particular shape, and examples include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. All the openings 5 ​​may have the same planar pattern, or some of them may have different patterns. The openings 5 ​​may be arranged regularly, irregularly, or a mixture of regular and irregular patterns. Although there are no limitations on the interval between adjacent openings 5, the interval is about 1 μm to 20 μm when viewed from the first surface 2a side.

[0024] The outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer, and the diameter (the length of one side in the case of a rectangle) is not limited, but is preferably about 100 mm to 500 mm. In this way, even if the diameter of the semiconductor layer 2 is large, the openings 5 ​​can be formed uniformly.

[0025] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, a silicon oxide (SiO2) layer. The insulating layer 3 is also called a BOX layer (Buried Oxide Layer). The thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 μm.

[0026] 2 is removed from the opening region facing the opening 5 of the semiconductor layer 2, and remains only in the surrounding region of the opening region on the second surface 2b of the semiconductor layer 2. The insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and the presence of the insulating layer 3 enables stable processing.

[0027] 2 is a semiconductor substrate, for example, a silicon substrate. The thickness of the support substrate 4 is not limited, but is, for example, about 100 μm to 1000 μm.

[0028] As shown in FIG. 1, the support substrate 4 can function as the columnar portions 16a and the peripheral frame 16b that surround the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be kept in a taut state by the support substrate 4, eliminating the need for a tensioning process. The deposition mask 1 of this embodiment can also be closely attached to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force. As shown in FIG. 1, the columnar portions 16a are located inside the peripheral frame 16b, and all of them have the same length (height). However, for example, the height of the columnar portions 16a may be lower than that of the peripheral frame. However, by making the heights uniform, greater strength can be maintained.

[0029] 1 and 2, an alignment mark for positioning can be formed in the peripheral region on the first surface 2a side of the semiconductor layer 2. The alignment mark can be formed, for example, in a recessed shape on the first surface 2a, and can be formed to a depth that reaches the insulating layer 3.

[0030] <Detailed Description of Openings 5 ​​in Vapor Deposition Mask 1 in the Present Embodiment> [How to calculate opening width W1] As shown in Fig. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. For this reason, as shown in Fig. 2, the opening width W1 was determined as the dimension in the planar direction along the first surface 2a, where it is narrowest. For example, the opening width W1 can be determined from an SEM image obtained using an eCD-2 manufactured by KLA-Tencor.

[0031] [Calculation method for variation σ of opening width W1] In this embodiment, the variation σ of the opening width W1 of the deposition mask 1 is defined. A predetermined range is defined within the plane of the deposition mask 1 shown in Fig. 1, and the opening widths W1 of the multiple openings 5 ​​located within the predetermined range are measured to determine the standard deviation σ. Then, this standard deviation σ is defined as the variation σ of the opening width W1.

[0032] Although not limited thereto, the "predetermined range" can be defined as the central region of the deposition mask 1. In this case, the central region preferably has a size that includes at least 100 openings 5 ​​or more.

[0033] A predetermined number of adjacent openings 5 ​​included in the central region were selected, and the opening widths W1 of these openings 5 ​​were measured to determine the variation σ. The "predetermined number" is not limited to a specific number, but may be approximately several tens to several hundreds, and more specifically, may be approximately 50 to 150. In this embodiment, 100 adjacent openings 5 ​​were selected to determine the variation σ.

[0034] Furthermore, "adjacent openings" can be defined as openings contained within a rectangular, square, circular, elliptical, or polygonal outline, or openings lined up in a row. Preferably, a plurality of openings existing within a square or rectangular outline are picked up, and when selecting 100 openings 5, for example, 100 openings arranged in a 10 x 10 matrix in the vertical and horizontal directions can be selected.

[0035] 3 is a partially enlarged cross-sectional view showing one opening 5 formed in the deposition mask 1, and shows the middle part of the opening 5 in the height direction (thickness direction of the semiconductor layer 2). Note that although reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side in the figure, the cross-sectional shape is symmetrical, and the side wall surface 6 on the right side in the figure has the same configuration.

[0036] 3, the side wall surface 6 of the opening 5 is formed with an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding inward of the opening 5 and concave portions 8 located between the convex portions 7 are formed continuously and repeatedly along the height direction of the opening 5. In this embodiment, the height difference between the protrusions and recesses of the opening 5 is calculated as follows.

[0037] [Calculation method for unevenness height difference] First, an SEM (scanning electron microscope) image was obtained of the cross section of the opening 5. Although the SEM is not limited to this, for example, a Regulus 8220 manufactured by Hitachi High-Technologies was used.

[0038] At a midpoint between the first surface 2a and the second surface 2b of the opening 5, exactly in the center of the thickness, five pitches of the uneven shape were measured using an SEM. Note that the number of pitches is not limited to five, but if the number of pitches is too small, parameter noise will increase, and if the number of pitches is too large, depending on the thickness, it may not be possible to ensure that number of pitches, and parameter calculation will be time-consuming and complicated. Therefore, it is preferable to use a number of pitches ranging from several to 10 pitches. In this embodiment, measurements are basically performed at five pitches, but if this is difficult, the number of pitches can be appropriately set or changed.

[0039] Furthermore, instead of the concept of pitch described above, it is also possible to measure the height at, for example, five points at the center of the thickness in an SEM image. In this case, the points with height can be regarded as convex portions, and the areas between them can be regarded as concave portions.

[0040] In FIG. 3, only two pitches are shown and explained. In FIG. 3, the two convex portions 7 are denoted by the reference numerals 7a and 7b to distinguish them from each other. When viewed from each convex portion 7a, 7b, a half pitch is formed with the concave portion 8 located on the first surface 2a side (upper side in the figure). The two concave portions 8 are also denoted by the reference numerals 8a and 8b to distinguish them from each other. The convex portion 7a and the concave portion 8a form a first half pitch P1, and the convex portion 7b and the concave portion 8b form a second half pitch P2. Note that the pitch refers to the distance between convex portions or the distance between concave portions, and half that distance is defined as the half pitch.

[0041] As shown in Figure 3, an approximate line T1 was drawn connecting the lowest positions (bottoms A) of the recesses 8a and 8b within the measurement range. The bottom A is, for example, the farthest position as seen from the center line O in the width direction of the opening 5. The approximate line T1 can be determined by the least squares method. Note that if an irregular recess 8 is formed within the measurement range (for example, if the bottom A is located at an extremely low position), the approximate line T1 can be drawn excluding that recess 8.

[0042] Next, as shown in FIG. 3, the highest position (apex) B of the convex portion 7a was determined at the first half pitch P1. The apex B was the closest position when viewed from the center line O of the opening 5 in the width direction. Then, as shown in FIG. 3, a straight line S1 was drawn perpendicular to the approximated line T1 so as to intersect with the apex B. The length of the straight line S1 from the approximated line T1 to the apex B was determined. The length of this straight line S1 was defined as the uneven height difference D1 at the first half pitch P1.

[0043] The unevenness height difference for the second half pitch P2 and other half pitches can be calculated in the same way as for the first half pitch P1. That is, the length of a straight line perpendicular to the approximate line T1 to the apex B of each convex portion is calculated, and this straight line length is used as the unevenness height difference for each pitch. Incidentally, Figure 3 shows the unevenness height difference D2 for the second half pitch P2.

[0044] In this way, multiple irregularity height differences can be determined. When five pitches are measured, five irregularity height differences Dn (n = 1 to 5) are calculated. Then, the average value Ave of these irregularity height differences Dn is calculated.

[0045] Although minute irregularities may be formed on the surfaces of the recesses 8a and 8b (or on the bottoms of the protrusions 7a and 7b), these minute irregularities can be ignored. For example, minute irregularities on the order of several nanometers in wavelength or smaller can be cut off, and a waviness curve can be created to determine the difference in irregularity height.

[0046] [Calculation method for taper angle θ1] In this embodiment, the taper angle θ1 of the opening 5 is determined as follows. That is, as shown in Fig. 3, a straight line is drawn between the end of the opening width W1 in the surface direction along the first surface 2a and the end of the opening width W2 in the surface direction along the second surface 2b, and the inclination angle between this line and the first surface 2a can be set as the taper angle θ1 of the opening 5. The taper angle θ1 was determined by measuring the length of an SEM image taken using a Hitachi High-Tech Regulus 8220.

[0047] [Calculation method for unevenness angles θ2 and θ3] As shown in Fig. 3, the unevenness angle θ2 can be determined as the angle between a straight line L1 connecting the apex B of the convex portion 7a and the lowest bottom A (farthest from the center line O in the width direction of the opening 5) of the concave portion 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximate line T1. Also, as shown in Fig. 3, the unevenness angle θ3 can be determined as the angle between a straight line L2 connecting the apex B of the convex portion 7a and the lowest bottom A (farthest from the center line O in the width direction of the opening 5) of the concave portion 8b located on the deposition source 11 side (lower side in the figure, see Fig. 4) as viewed from the convex portion 7a, and the approximate line T1.

[0048] Small concave-convex angles θ2 and θ3 mean that the height of the convex ridge portion 7 is low (the depth of the concave portion 8 is shallow) and the waviness of the side wall surface 6 is small.

[0049] <Characteristic Configuration of Aperture Parameters in the Present Embodiment> The deposition mask 1 in this embodiment is (1) The side wall surface 6 of the opening 5 is inclined so as to become narrower from the second surface 2b side to the first surface 2a side. (2) The opening width W1 is greater than 3 μm and smaller than 15 μm.

[0050] Thus, in this embodiment, the opening width W1 is set to a range of more than 3 μm and less than 15 μm. This satisfies the needs of the deposition mask 1 having the semiconductor layer 2, and in particular, it is necessary to further reduce the opening width W1 as a deposition mask for separate RGB coloring used in the manufacturing process of an OLED microdisplay. In this embodiment, the opening width W1 is preferably 4 μm or more and 10 μm or less.

[0051] The opening width W1 is preferably set as a width dimension in the planar direction along the first surface 2a facing the deposition target substrate 10.

[0052] FIG. 4 is a cross-sectional view of the deposition mask 1 of this embodiment arranged between a substrate 10 to be deposited and a deposition source 11, illustrating one step of a method for manufacturing an electronic device.

[0053] 4, deposition material (deposition particles) 12 from a deposition source 11 passes through the openings 5 ​​in the deposition mask 1 and reaches the surface 10a of the deposition target substrate 10, forming a deposition film 13. When the pattern width W3 of the deposition film 13 is measured and the ratio to the opening width W1 is calculated, an opening width W1 where the pattern width ratio ((pattern width W3 / opening width W1)×100(%)) is 80% or more is defined as the present example, and an opening width W1 where the pattern width ratio is less than 80% is defined as a comparative example.

[0054] In this embodiment, the opening width W1 is set to a range of greater than 3 μm and less than 15 μm, preferably 4 μm to 10 μm, thereby achieving a pattern width ratio of 80% or greater and reducing the variation σ in the opening width W1. The reason for setting the pattern width ratio at 80% or greater is that a ratio below 80% results in a large deviation from the desired pattern width W3 of the deposited film 13, leading to a decrease in yield, a decrease in the area that should emit light at the designed position, such as coordinate position accuracy, leading to a decrease in the brightness of the light-emitting element itself, or a numerical value required for product quality assurance. To improve production efficiency, the pattern width ratio is set to 85% or greater, preferably 90% or greater, and more preferably 95% or greater.

[0055] When the opening width W1 is 3 μm or less, the pattern width ratio tends to fall below 80%. This is because the narrower the opening width W1, the greater the influence of the deposition material 12 deposited on the sidewall surface 6. As shown in FIG. 3, the sidewall surface 6 is formed with an uneven shape. Therefore, the deposition material 12 tends to adhere to the side surface of the convex portion 7 located on the deposition substrate side (upper side in FIG. 3) as viewed from the recess 8. Therefore, in this embodiment, it is preferable to control the average value Ave of the unevenness height difference Dn in addition to setting the opening width W1. That is, in this embodiment, the average value Ave of the unevenness height difference Dn is preferably 0.200 μm or less, more preferably 0.195 μm or less, even more preferably 0.190 μm or less, even more preferably 0.180 μm or less, and most preferably 0.175 μm or less. Furthermore, although the lower limit of the average value Ave of the unevenness height difference Dn is not limited, the average value Ave of the unevenness height difference Dn can be specified to be 0.003 μm or more, or 0.005 μm or more, or 0.008 μm or more. In the present embodiment, adjusting the average value Ave of the unevenness height difference Dn as described above reduces the deposition of the deposition material 12 on the side wall surface 6 of the opening 5, which also has the effect of reducing the number of times the deposition mask 1 needs to be cleaned.

[0056] In this embodiment, the variation σ of the opening width W1 is preferably smaller than 0.09 μm. As described above, the variation σ can be determined, for example, as the standard deviation σ of the opening widths W1 of 100 adjacent openings 5.

[0057] When the opening width W1 is 15 μm or more, the variation σ tends to be 0.09 μm or more, and even 0.10 μm or more. FIG. 5 is an image diagram showing RGB pixels 23 arranged in a matrix on a vapor deposition film 13 formed on the surface of a substrate using a vapor deposition mask 1. When the opening width W1 of the vapor deposition mask 1 is increased, the light-emitting area of ​​each pixel 23 is less susceptible to the influence of the variation σ, but the risk of color mixing with adjacent pixels 23 shown in FIG. 5 increases. The risk of color mixing is determined by the absolute value of the variation σ, and the greater the variation σ, the higher the risk of color mixing. Therefore, in this embodiment, the variation σ is set to a range smaller than 0.09 μm, and preferably set to a range of 0.01 μm to 0.08 μm.

[0058] In this embodiment, openings 5 ​​are formed in semiconductor layer 2 by dry etching. At this time, if the etching is slightly over-etched compared to the width dimension W4 of through-hole 14a shown in FIG. 6, for example, the opening width W1 will not be uniform and variations are likely to occur. In this case, it is thought that if opening width W1 is made larger, it is likely to be formed by over-etching, resulting in larger variations σ. For this reason, in this embodiment, it has been discovered that the variations σ can be further reduced by setting opening width W1 in the range of greater than 3 μm and less than 15 μm.

[0059] The concave-convex angles θ2 and θ3 described in FIG. 3 are within a range of approximately 0.5° to 50°, preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less. By reducing the concave-convex angles θ2 and θ3, the protrusion height of the convex ridge portions 7 can be reduced, or the interval between adjacent convex ridge portions 7 can be increased (the range of the concave portions 8 can be increased), thereby suppressing the deposition of the deposition material 12 on the side surfaces of the convex ridge portions 7. The most preferable range of the concave-convex angles θ2 and θ3 is approximately 0.5° to 2°. The concave-convex angle θ3 shown in FIG. 3 is preferably smaller than the concave-convex angle θ2. This suppresses the deposition of the deposition material 12 on the side wall surfaces 6.

[0060] In this embodiment, the opening width of the opening 5 gradually narrows from the second surface 2b side toward the first surface 2a side. That is, as shown in FIG. 4 , the opening width W1 of the deposition mask 1 on the side facing the deposition substrate 10 is narrowed, and the side wall surface 6 of the opening 5 is formed as an inclined surface. This facilitates stable formation of a deposition film 13 having a desired pattern width W3. Furthermore, when the deposition material 12 deposited on the side wall surface 6 peels off from the side wall surface 6, it is less likely to fly toward the deposition substrate 10. From the viewpoint of manufacturing, inclining the side wall surface 6 of the opening 5 facilitates the formation of the side wall surface 6. While not limited to this, the taper angle θ1 of the side wall surface 6 is preferably 60° or more, more preferably 70° or more, and even more preferably 80° or more. Furthermore, the taper angle θ1 is preferably less than 90° and more preferably 88° or less. If the taper angle θ1 is less than 60°, the amount of deposition material 12 deposited on the sidewall surface 6 increases, and the pattern width ratio of the deposited film tends to be smaller than 80%. Furthermore, the taper angle θ1 can be set to approximately 90°, i.e., the sidewall surface 6 can be formed almost vertically. However, in this case, the influence of the unevenness height difference Dn on the sidewall surface 6 during deposition is considered to be greater. In particular, the narrower the opening width W1, the smaller the average value Ave of the unevenness height difference Dn needs to be. The taper angle θ1 is also related to the thickness of the semiconductor layer 2. That is, as the thickness of the semiconductor layer 2 increases, it becomes more difficult to form the sidewall surface 6 as a vertical surface. Therefore, in this embodiment, the taper angle θ1 of the sidewall surface 6 is controlled to be smaller than 90°, preferably 88° or less.

[0061] <Method of manufacturing the deposition mask 1 according to the present embodiment> 6A and 6B are process diagrams showing a first manufacturing method of the deposition mask 1 of the present embodiment. Here, the deposition mask 1 in the manufacturing process shown in FIG. 6 and FIG. 7 described later shows only the vicinity of one opening region 15, as in FIG. 2, but in reality, the multiple opening regions 15 shown in FIG. 1 are formed simultaneously. In FIG. 6A, an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in FIG. 1, so please refer to that.

[0062] In the case of the SOI substrate 9, the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.

[0063] In FIG. 6(b), a mask layer 14 is patterned on the surface of the semiconductor layer 2. The mask layer 14 is preferably a resist, and can be patterned by exposure and development. A plurality of through holes 14a are formed in the mask layer 14. These through holes 14a are an opening pattern for forming openings 5 ​​in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed to be greater than 3 μm and less than 15 μm.

[0064] Next, in FIG. 6(c), the semiconductor layer 2 exposed through the through-hole 14a of the mask layer 14 is dry-etched. In this embodiment, the semiconductor layer 2 is deep-etched. It is preferable to use a so-called Bosch process, for example, by repeatedly etching Si with SF6 and forming a polymer film with C4F8 to deeply etch the silicon, alternately protecting the sidewall and etching the bottom. The Bosch process results in an uneven sidewall surface 6 of the opening 5 formed in the semiconductor layer 2.

[0065] At this time, the composition and flow rate of the etching gas, the internal pressure of the etching chamber, the power of the high frequency power source, etc. are appropriately adjusted so as to form an inversely tapered surface as shown in Figure 6(c). Furthermore, by adjusting these factors, the taper angle θ1 of the inversely tapered surface and the height difference Dn between the protrusions and recesses can be controlled.

[0066] For example, a Bosch process was performed using a dry etching system, alternating between SF6 gas and C4F8 gas. Using the same gas as in the mode used for isotropic dry etching using fluorine radicals with SF6 gas, anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate being etched. For example, the processing conditions were adjusted as follows: SF6 gas at 0-500 sccm, C4F8 gas at 0-300 sccm, platen LF at 0-1500 W, coil RF at 300-1500 W, and chamber pressure at 1-10 Pa.

[0067] By the Bosch process described above, a plurality of openings 5 ​​can be formed by deep digging in the semiconductor layer 2, and at this time, the taper angle θ1 of the sidewall surface 6 of the openings 5 ​​and the height difference between the protrusions and recesses can be adjusted appropriately.

[0068] In this embodiment, in addition to adjusting the conditions in the etching process described above, reducing the unevenness height difference Dn can also be achieved by, for example, performing deep etching of silicon and then smoothing the unevenness height difference Dn by laser hydrogen annealing.

[0069] 6(d), the mask layer 14 is removed, thereby completing the SOI substrate 9 in which a plurality of openings 5 ​​are formed in the semiconductor layer 2.

[0070] 6(e), a protective layer 20 is formed on the surface of the semiconductor layer 2. This makes it possible to appropriately protect the entire surface of the semiconductor layer 2. The protective layer 20 is, for example, a resist film, but is not limited thereto.

[0071] Next, in the step shown in FIG. 6(f), a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9. Although not limited thereto, the mask layer 21 is a resist pattern. As shown in FIG. 6(f), the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the semiconductor layer 2 in the thickness direction, but is provided only in the surrounding region 16 (see also FIG. 1). The mask layer 21 may be formed together with the mask layer 14 in the step shown in FIG. 6(b).

[0072] 6(g), the support substrate 4 that is not covered with the mask layer 21 is removed by dry etching, and in the step shown in Fig. 6(h), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains the shape having the multiple openings 5. 6(i), the protective layer 20 and the mask layer 21 are removed, thereby completing the deposition mask 1.

[0073] 7A to 7C are process diagrams showing a second manufacturing method of the deposition mask 1 of the present embodiment. In FIG. 7A, an SOI substrate 9 is prepared. The SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in FIG. 1, so please refer to that explanation.

[0074] Although there is no limitation on the diameter of the SOI substrate 9, in this embodiment, it can accommodate a diameter up to about 500 mm.

[0075] 7(b), a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9. The mask layer 21 is, but is not limited to, a resist pattern. As in FIG. 6(f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0076] Next, in the process shown in Figure 7(c), the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching, and in the process shown in Figure 7(d), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching.

[0077] 7(e), a mask layer 22 is formed on the back surface of the semiconductor layer 2. Although not limited to this, the mask layer 22 can be formed using a resist pattern. As shown in FIG. 7(e), a plurality of openings 22a are patterned in the mask layer 22 by exposure and development.

[0078] 7(f), the semiconductor layer 2 exposed from the opening 22a is etched. This etching is dry etching, and preferably, an etching gas containing a fluorine compound and oxygen, and optionally a rare gas, is used, although this is not limited thereto.

[0079] The fluorine compound may be, for example, one or more selected from CF4, SF6, NF3, BF3, PF5, and F2, and the rare gas may be one or more selected from helium and argon.

[0080] For example, etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus. The processing conditions were adjusted as follows: CF4 gas 10-100 sccm, O2 gas 0-100 sccm, Ar gas 0-200 sccm, IPC power 200-1000 W, RIE power 0-1000 W, and chamber pressure 1-10 Pa.

[0081] In the step of FIG. 7(f), openings 5 ​​are formed in the semiconductor layer 2 such that the width gradually decreases with increasing distance from the mask layer 22 (toward the first surface 2a of the semiconductor layer 2). This allows the sidewall surfaces 6 of the openings 5 ​​to be formed as inclined surfaces. Then, in the step of FIG. 7(g), the mask layer 22 is removed. This completes the deposition mask 1.

[0082] In both the manufacturing method shown in Figure 6 and the manufacturing method shown in Figure 7, multiple openings 5 ​​can be formed in the semiconductor layer 2, and the side wall surfaces 6 of the openings 5 ​​can be formed as inclined surfaces so that the opening width gradually narrows from the back surface (second surface 2b) of the semiconductor layer 2 facing the deposition source 11 side toward the front surface (first surface 2a) facing the deposition substrate 10 side.

[0083] In this embodiment, although not limited thereto, the opening width W1, the opening variation σ, and the taper angle θ1 can be adjusted by various gas flow rates, chamber pressure, power of the plasma generation source, and the like.

[0084] <Method of Manufacturing Electronic Device According to the Present Embodiment> 4, the deposition mask 1 is placed between the deposition substrate 10 and the deposition source 11. At this time, the first surface 2a of the semiconductor layer 2 of the deposition mask 1 faces the deposition substrate 10, and the second surface 2b of the semiconductor layer 2 faces the deposition source 11. A plurality of openings 5 ​​are formed in the semiconductor layer 2, and the opening width is narrower on the first surface side than on the second surface side.

[0085] The deposition mask 1 is placed on a holder (not shown) of a deposition device, and an electrostatic chuck can be used to fix the deposition mask 1 and the deposition substrate 10. The deposition mask 1 and the deposition substrate 10 are rotated around the axis of the holder.

[0086] The deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 ​​of the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, whereby a deposition film 13 is formed.

[0087] In this embodiment, examples of the electronic device include an OLED microdisplay panel, a liquid crystal panel, and a solar cell, and the present invention is particularly suitable for a method of manufacturing an OLED microdisplay panel as an organic electronic device.

[0088] By using the deposition mask 1 of this embodiment, the pattern width W3 of the deposited film 13 can be ensured to be 80% or more, preferably 85% or more, and more preferably 90% or more of the opening width W1. In this way, the deposited film 13 with excellent pattern dimensions can be formed.

[0089] <Effects of using the deposition mask 1 of this embodiment> In this embodiment, the opening width W1 of the opening 5 of the deposition mask 1 is set to be greater than 3 μm and smaller than 15 μm, thereby making it possible to stably form a deposition film that has excellent pattern dimensions and suppresses mutual influence between adjacent pixels.

[0090] Conventionally, the opening width W1 has not been set in consideration of the pattern dimensions and the mutual influence between adjacent pixels (e.g., the risk of color mixing). In particular, the variation σ of the opening width W1 has not been taken into consideration. Therefore, conventional control methods have not been able to stably form a vapor-deposited film 13 that has a high pattern dimension and a low risk of color mixing.

[0091] In contrast, in this embodiment, by adjusting the opening width W1 to a range greater than 3 μm and less than 15 μm, it is possible to stably form a deposited film 13 having a pattern width W3 with a pattern width ratio of 80% or more and reducing the mutual influence between adjacent pixels.

[0092] In this embodiment, the variation σ in the aperture width W1 can be made smaller than 0.09 μm, preferably 0.01 μm to 0.08 μm, thereby effectively reducing the mutual influence between adjacent pixels.

[0093] In this embodiment, by adjusting the average value Ave of the unevenness height differences Dn, deposition of the deposition material 12 can be suppressed, the frequency of cleaning the deposition mask can be reduced, and quality control of the deposition mask can be easily performed. In addition, clogging of the openings can be reduced, and the life of the deposition mask can be extended. Although the embodiments and modifications have been described, other embodiments may be combinations of the above embodiments and modifications in whole or in part.

[0094] Furthermore, the present invention is not limited to the above-described embodiments and modifications, and may be variously changed, substituted, or modified within the scope of the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.

[0095] An embodiment of a layer structure different from that of the deposition mask 1 shown in FIG. 1 will be described. 8, the structure may be such that a membrane 31 made of SiN, SiO2, or the like is formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 are formed in the membrane 31 in the central region where the silicon substrate 30 has been removed, or a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (preferably a silicon substrate). The membrane is formed by CVD, and it is preferable to use SiN from the viewpoint of ease of stress control.

[0096] 9 to 11, an SOI substrate 9 is used as in Fig. 1, but in Fig. 9, a SiN layer 33 is formed on the back side (support substrate 4 side, side facing deposition source 11) of the SOI substrate 9, in Fig. 10, a SiN layer 33 is formed on the front side (semiconductor layer 2 side, side facing deposition target substrate 10) of the SOI substrate 9, and in Fig. 11, a SiN layer 33 is formed on both the back side and front side of the SOI substrate 9. In the configuration in which the SiN layer 33 is formed on the front side (semiconductor layer 2 side) of the SOI substrate 9, an opening 5 is formed continuous with the semiconductor layer 2, as shown in Figs. 10 and 11.

[0097] By providing the SiN layer 33, it is easy to control the stress of the deposition mask, and distortion and the like can be suppressed. Also, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is preferably thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9. Although not limited, the film thickness of the SiN layer 33 formed on the front surface side of the SOI substrate 9 is about 0.05 μm to 0.5 μm, and the film thickness of the SiN layer 33 formed on the back surface side of the SOI substrate 9 is about 0.05 μm to 3 μm. Since the semiconductor layer 2 is thinner than the support substrate 4 and a large number of openings 5 are also formed in the semiconductor layer 2, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9 in order to control stress well in a balanced manner between the front surface side and the back surface side.

Example

[0098] Hereinafter, the effects of the present invention will be described with reference to the examples and comparative examples of the present invention. Note that the present invention is not limited in any way by the following examples.

[0099] <SOI substrate> For the SOI substrate, a support substrate (625 μm) / insulating layer (0.5 μm) / semiconductor layer (15 μm or 5 μm) was used. The parentheses indicate the thickness. The support substrate was a Si substrate, the semiconductor layer was a Si layer, and the insulating layer was a SiO2 layer. The outer diameter of the SOI substrate was 200 mm. In the experiment, two types of SOI substrates with semiconductor layer thicknesses of 15 μm and 5 μm were prepared.

[0100] <Original master used> In the process of (b) shown in FIG. 6, an opening pattern was formed in the mask layer (resist layer) by i-line exposure, and the opening width of the original master used when forming this opening pattern was adjusted within the range of 2.0 μm to 30 μm.

[0101] <Method for manufacturing deposition mask> A deposition mask 1 was fabricated using the manufacturing method shown in Figure 6. In the experiment, the opening width W1 was varied using the master described above. The opening width W1 and taper angle formed in the semiconductor layer 2 were adjusted by adjusting the gas flow rates, chamber pressure, and power of the plasma generation source. For example, in the dry etching shown in Figure 6(c), anisotropic dry etching using fluorine ions was performed using SF6 gas, the same gas as used in isotropic dry etching using fluorine radicals, by applying a bias to the substrate to be etched. The processing conditions were adjusted as follows: SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm, platen LF at 0 to 1500 W, coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa.

[0102] <Dimensions of the opening 5 formed in the deposition mask 1> In the experiment, the opening width W1, the variation σ, the average value Ave of the unevenness height difference Dn, and the taper angle were determined. As shown in Figure 1, the opening width W1 was the width dimension in the surface direction along the first surface 2a of the semiconductor layer 2.

[0103] The variation σ of the opening width W1 was calculated by calculating the standard deviation σ from the opening width W1 of each of 10 × 10 (100) adjacent openings in the vertical and horizontal directions in the central region of the deposition mask 1. The opening width W1 was calculated from an SEM image obtained using an eCD-2 manufactured by KLA-Tencor.

[0104] The average value Ave of the unevenness height difference Dn and the taper angle were determined from SEM images taken using a Hitachi High-Tech Regulus 8220.

[0105] <About determining deposition pattern dimensions> Using the multiple deposition masks formed above, a pattern of a deposition film of a green light emitting material Alq3 (tris(8-hydroxyquinoline)aluminum) was formed on the glass surface through the deposition masks by vacuum resistance heating deposition.

[0106] The pattern width W3 of the vapor-deposited film was then measured, and the pattern width ratio of the vapor-deposited film to the opening width W1 of the vapor-deposition mask ((W3 / W1) × 100(%)) was calculated. Experimental examples in which the pattern width ratio was less than 80% were marked with an ×, experimental examples in which the pattern width ratio was 80% to 90% with an ◯, and experimental examples in which the pattern width ratio was more than 90% with an ⊚.

[0107] <About opening variation judgment> In determining the aperture variation, experimental examples in which the variation (standard deviation) σ of the aperture width W1 was 0.08 μm or less were marked ○, experimental examples in the range of 0.09 μm to 0.10 μm were marked △, and experimental examples in which the variation was over 0.10 μm were marked ×.

[0108] The "taper angles" shown in Tables 1 to 6 are representative values, and it was confirmed that all experimental examples fell within a range of ±3° from each representative value. Tables 1 to 3 show the experimental results when the semiconductor layer thickness is 15 μm, and Tables 4 to 6 show the experimental results when the semiconductor layer thickness is 5 μm.

[0109] [Table 1]

[0110] [Table 2]

[0111] [Table 3]

[0112] [Table 4]

[0113] [Table 5]

[0114] [Table 6]

[0115] As shown in Tables 1 to 6, there were experimental examples No. 1 to No. 36, and the opening width W1 was in the range of 3 μm to 20 μm. Experimental examples No. 1, 7, 13, 19, 25, and 31 were judged as × or △ in the deposition pattern dimensions, and all of these are comparative examples. Experimental examples No. 5, 6, 11, 12, 18, 23, 24, 29, 30, 35, and 36 were judged as △ or × in the opening variation, and all of these are comparative examples. The remaining experimental examples were judged as ○ or ◎ in the deposition pattern dimensions, and as ○ in the opening variation, and all of these correspond to examples.

[0116] This experiment revealed that by setting the opening width W1 to be greater than 3 μm and smaller than 15 μm, deposition of the deposition material 12 on the sidewall surface 6 of the opening 5 can be suppressed, and a deposition film can be stably formed in which the pattern width W3 relative to the opening width W1 is 80% or more, preferably greater than 90%. In addition, it was found that the variation σ of the opening width W1 can be reduced, specifically, the variation σ can be set to 0.09 μm or less. In this example, the variation σ is preferably 0.01 μm or more and 0.08 μm or less. Furthermore, this example satisfies the needs of a deposition mask 1 having a semiconductor layer 2, and is particularly suitable for use as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays.

[0117] Furthermore, the average value Ave of the unevenness height difference Dn is preferably 0.200 μm or less, more preferably 0.180 μm or less, and even more preferably 0.170 μm or less.

[0118] Furthermore, experimental results showed that the taper angle is preferably 60° or more, and more preferably 70° or more. The lower limit of the taper angle (tilt angle) can be less than 90° or 88° or less. An error of about ±3° is permitted for the taper angle.

[0119] It was also found that the unevenness angles θ2 and θ3 described in Fig. 3 can be set within a range of approximately 0.5° to 50°. They are preferably set to 10° or less, and a more preferable range is approximately 0.5° to 2°. It was also found that the unevenness angle θ3 is smaller than the unevenness angle θ2, which makes it possible to suppress deposition of the evaporation material. [Explanation of symbols]

[0120] 1: Deposition mask 2: Semiconductor layer 2a: 1st page 2b: 2nd side 3: Insulating layer 4: Support substrate 5:Aperture 6: Side wall 7: Convex part 8: Recess 9: SOI substrate 10: Deposition substrate 11: Vapor deposition source 12: Vapor deposition material 13: Vapor deposition film 14: Mask layer 15:Aperture area 16: Surrounding area 16a: Columnar part 16b: Peripheral frame 20 :Protective layer 21, 22: Mask layer 23: Pixels 30: Silicon substrate 31:Membrane T1: Approximate straight line W1: Opening width W3: Pattern width θ1: Taper angle

Claims

1. a deposition mask disposed between a substrate to be deposited and a deposition source, for depositing a deposition material from the deposition source onto a surface of the substrate to be deposited through an opening, the deposition mask comprising: a first surface facing the deposition substrate and a second surface located on the opposite side of the first surface facing a deposition source, and a plurality of openings are formed through the first surface and the second surface; a side wall surface of the opening is inclined so that the opening width narrows from the second surface side toward the first surface side, the opening width defined on the first surface side is greater than 3 μm and smaller than 15 μm, the deposition mask has a configuration in which a membrane having the openings is supported on a support substrate, The support substrate is made of a Si layer and a SiO ２ layer, The membrane comprises SiN. A deposition mask characterized by:

2. The opening width is 4 μm or more and 10 μm or less.

2. The deposition mask according to claim 1.

3. The variation σ of the opening width is less than 0.09 μm.

2. The deposition mask according to claim 1.

4. The variation σ of the opening width is 0.01 μm or more and 0.08 μm or less.

4. The deposition mask according to claim 3.

5. The support substrate further includes a SiN layer.

2. The deposition mask according to claim 1.

6. The membrane is disposed on the surface of the support substrate, which is the first surface side, the SiN layer forms the back surface of the support substrate, and the SiO ２ the outer peripheral surface between the top surface and the back surface of the Si layer is exposed; 6. The deposition mask according to claim 5.

7. The membrane has a plurality of opening regions each having a plurality of the openings, and a surrounding region located around each opening region; the support substrate includes a peripheral frame that supports the membrane in the peripheral region, and a columnar portion located inside the peripheral frame; The outer peripheral frame and the columnar portion are formed to have the same height.

2. The deposition mask according to claim 1.

8. the deposition mask according to claim 1 is disposed between a substrate to be deposited and a deposition source, with the first surface facing the substrate to be deposited and the second surface facing the deposition source; A deposition material is deposited on the surface of the deposition substrate through the opening.

1. A method for manufacturing an electronic device comprising the steps of:

Images