Conformal and smooth titanium nitride layer and method of forming the same

Abstract

To provide formation of a thin film containing TiN by a cyclic vapor deposition process, and a semiconductor structure having the thin film.SOLUTION: In one aspect, a method of forming a thin film comprising TiN comprises exposing a semiconductor substrate to one or more first cyclical vapor deposition cycles each comprising an exposure to a first Ti precursor and an exposure to a first N precursor to form a first portion of the thin film, and exposing the semiconductor substrate to one or more second cyclical vapor deposition cycles each comprising an exposure to a second Ti precursor and an exposure to a second N precursor to form a second portion of the thin film. The exposure to one or both of the first Ti precursor and the first N precursor during the one or more first cyclical vapor deposition cycles is performed under a different pressure compared to the exposure to one or both of the second Ti precursor and the second N precursor during the corresponding one or more second cyclical vapor deposition cycles. Semiconductor structures incorporating the thin films and methods of forming the same are also aspects.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The disclosed techniques relate generally to forming titanium nitride layers, and more particularly to forming conformal and smooth titanium nitride layers. [Background technology]

[0002] Titanium nitride (TiN) is widely used in the fabrication of various structures within integrated circuits (ICs). For example, TiN has been used in diffusion barriers, various electrodes, and metallization structures. This widespread use of TiN in IC manufacturing can be attributed to its structural, thermal, and electrical properties. As the size of various IC structures shrinks, TiN is formed on features with increasingly smaller sizes and complex topologies. For example, as technology nodes scale beyond the 10-nm node, thin films, such as diffusion barriers, that can conformally line trenches and vias with high aspect ratios and dimensions as small as a few nanometers are required. While techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have been used in the IC industry for decades to form TiN diffusion barriers, the increasing need for conformal TiN films deposited in smaller trenches and vias may ultimately limit their use. While atomic layer deposition (ALD) has been demonstrated for conformal deposition of TiN films, some electrical (e.g., conductivity) and physical (e.g., surface roughness) properties of the films may be inferior to those of TiN films formed using other methods, such as physical vapor deposition (PVD). Thus, there is a need for atomic layer deposition methods to form TiN-based films with superior surface smoothness and step coverage relative to TiN films formed by PVD and CVD, while also possessing comparable or superior electrical and physical properties, for use in IC manufacturing. Summary of the Invention [Means for solving the problem]

[0003] In one aspect, a method for forming titanium nitride (TiN) by a cyclic deposition process includes forming a first portion of a thin film on a semiconductor substrate by exposing the semiconductor substrate to one or more first cyclic deposition cycles, each cycle including exposure to a first Ti precursor and a first N precursor. The method further includes forming a second portion of a thin film on the first portion of the thin film by exposing the semiconductor substrate to one or more second cyclic deposition cycles, each cycle including exposure to a second Ti precursor and a second N precursor. The exposure to one or both of the Ti precursor and the N precursor during the one or more second ALD cycles is conducted at a higher pressure than the corresponding exposure to one or both of the Ti precursor and the N precursor during the one or more first ALD cycles.

[0004] In another aspect, a method for forming a thin film comprising titanium nitride (TiN) by a cyclic deposition process includes providing a semiconductor substrate having a trench or via with an aspect ratio greater than 1. The method further includes forming a thin film in the trench or via by exposing the semiconductor substrate to one or more first cyclic deposition cycles, each including exposure to a first Ti precursor and exposure to a first N precursor, to form a first portion of the thin film in the trench or via. The method further includes exposing the semiconductor substrate to one or more second cyclic deposition cycles, each including exposure to a second Ti precursor and exposure to a second N precursor, to form a second portion of the thin film on the first portion of the thin film. The exposure to one or both of the first Ti precursor and the first N precursor during the one or more first cyclic deposition cycles is performed under a different pressure than the corresponding exposure to one or both during the one or more second cyclic deposition cycles.

[0005] In another aspect, a semiconductor structure includes a semiconductor substrate having a non-metallic sidewall surface with a trench or via having an aspect ratio greater than 5. The semiconductor structure further includes a thin film comprising TiN conformally coating the non-metallic sidewall surface, wherein the ratio of the thickness of the thin film formed on the lower 25% of the height of the trench or via to the thickness of the thin film formed on the upper 25% of the height of the trench or via is greater than 0.9. [Brief explanation of the drawings]

[0006] [Figure 1] 1A-1D show schematic diagrams of the nucleation and growth mechanisms of thin films under different growth modes. [Figure 2] Figure 2 is a cross-sectional transmission electron micrograph of a TiN layer grown on an oxide-coated silicon substrate by thermal atomic layer deposition. [Figure 3A] FIG. 3A is a flow diagram that schematically illustrates, in an embodiment, an atomic layer deposition method for forming a TiN layer by exposing a substrate to multiple cycles under different corresponding precursor exposure pressures. [Figure 3B] FIG. 3B is a schematic cross-sectional view of a semiconductor structure including a TiN layer formed by atomic layer deposition by exposing a substrate to multiple cycles under different corresponding precursor exposure pressures, according to an embodiment. [Figure 4] FIG. 4 shows, in an embodiment, a schematic pressure trace of different cycles of an atomic layer deposition process in which a substrate is exposed to multiple cycles under different corresponding precursor exposure pressures. [Figure 5] FIG. 5 shows a schematic cross-section of a via lined with TiN layers of different thicknesses in different parts of the via. [Figure 6] FIG. 6 is a graph showing experimentally measured surface roughness and step coverage trends as a function of thickness of TiN layers formed by atomic layer deposition, in accordance with an embodiment, where the substrate was exposed to multiple cycles under different corresponding precursor exposure pressures. [Figure 7A] FIG. 7A is a cross-sectional transmission electron micrograph of a high aspect ratio via lined with a TiN layer formed by atomic layer deposition, where the substrate was exposed to ALD cycles performed under the same precursor exposure pressure. [Figure 7B] FIG. 7B is a cross-sectional transmission electron micrograph of the top region of the high aspect ratio via shown in FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional transmission electron micrograph of the lower region of the high aspect ratio via shown in FIG. 7A. [Figure 8A] FIG. 8A is a cross-sectional transmission electron micrograph of a TiN layer formed in the top region of a high aspect ratio via similar to that shown in FIG. 7A by atomic layer deposition, where the substrate was exposed to multiple cycles under different corresponding precursor exposure pressures, in an embodiment. [Figure 8B] FIG. 8B is a cross-sectional transmission electron microscope photograph of the TiN layer formed in the lower region of the high aspect ratio via trench shown in FIG. [Figure 9] FIG. 9 is a graph illustrating a statistical comparison of measured step coverage between TiN layers formed by atomic layer deposition under a single exposure pressure and TiN layers formed by atomic layer deposition under multiple exposure pressures, according to an embodiment. [Figure 10] FIG. 10 shows a schematic cross-section of a via lined with a TiN layer, where the substrate was exposed to multiple cycles under different corresponding precursor exposure pressures, in an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] As noted above, there is a need in the integrated circuit (IC) industry for smooth, conformal TiN films with excellent electrical and physical properties, and methods for forming such films. To address these and other needs, smooth, conformal TiN-containing thin films, and cyclic vapor deposition methods for forming such films, are disclosed herein that exhibit the conformal properties of films deposited by cyclic vapor deposition processes, while also possessing electrical and physical properties comparable to or superior to TiN films formed by existing physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes. In particular, a method for forming a titanium nitride (TiN)-containing thin film includes forming a first portion of the thin film on the semiconductor substrate by exposing the semiconductor substrate to one or more first cyclic deposition cycles, each cycle including exposure to a first Ti precursor and a first N precursor. The method further includes forming a second portion of the thin film on the first portion of the thin film by exposing the semiconductor substrate to one or more second cyclic deposition cycles, each cycle including exposure to a second Ti precursor and a second N precursor. The exposure to one or both of the second Ti precursor and the second N precursor during one or more second cyclical deposition cycles is different from the corresponding exposure to one or both of the first Ti precursor and the first N precursor during one or more first cyclical deposition cycles. The cyclical deposition process disclosed herein is sometimes referred to as atomic layer deposition (ALD). However, the cyclical deposition process is not limited to atomic layer deposition processes. For example, in various embodiments described herein, the precursors can partially or nearly completely saturate the reaction surface.

[0008] By exposing the substrate to Ti and / or N precursors at relatively low pressures, e.g., less than 3 Torr, during deposition of the first portion of the thin film, the initial film growth can be substantially in a layer-by-layer growth mode. This advantageously results in smaller average grain sizes and less surface roughness than comparable TiN films deposited by exposing the substrate to Ti and / or N precursors at pressures greater than, e.g., 3 Torr or 5 Torr. On the other hand, by exposing the substrate to Ti and / or N precursors at relatively high pressures, e.g., greater than 3 Torr, during deposition of the second portion of the thin film, the second portion of the film growth can advantageously result in a higher level of conformality or step coverage than comparable TiN films deposited by exposing the substrate to Ti and / or N precursors at relatively low pressures, e.g., less than 3 Torr or less than 1 Torr.

[0009] Furthermore, because the first portion of the TiN film is grown in a layer-by-layer mode, a second portion of the thin film can continue to grow in a layer-by-layer mode using the first portion as a template, compared to comparable thin film growth that begins with exposure to Ti and / or N precursors at relatively high pressures.

[0010] The net result is that when deposited on a given surface, e.g., a surface including a non-metallic surface, a thin film including first and second portions deposited by the methods described herein by vapor deposition of one or both of the Ti and N precursors under two different corresponding exposure pressures advantageously has a superior combination of surface roughness and conformality compared to a thin film layer formed on the same surface using a single pressure. Alternatively or additionally, due in part to the improved smoothness and conformality, the thin film has a relatively lower electrical resistivity compared to a TiN layer formed by a given existing method.

[0011] As described herein, compounds referred to by their constituent elements without their specific stoichiometric ratios should be understood to include all possible non-zero concentrations of each element unless expressly limited. For example, titanium nitride (TiN) has the general formula Tix This is understood to encompass all possible stoichiometric and non-stoichiometric compositions of titanium nitride that can be expressed as N, x>0, including TiN, Ti3N4, Ti4N3, Ti6N5, Ti2N, and TiN2, as well as other non-stoichiometric compositions of Ti and N.

[0012] As mentioned above, titanium nitride-based thin films play an important role in integrated circuit (IC) manufacturing. While techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have been used to deposit TiN films in the IC industry, there is a growing need for deposition methods that can produce TiN-based films with high conformality without significantly compromising their electrical and / or physical properties.

[0013] Additionally, while plasma-enhanced processes such as plasma-enhanced atomic layer deposition (PE-ALD) can be effective at forming conformal films on surfaces with relatively low aspect ratios, these processes may not be effective at depositing films inside vias or cavities with high aspect ratios. Without being bound by any theory, one possible reason for this is that, under certain circumstances, the plasma may not reach the deep portions of a high-aspect-ratio via. Under such circumstances, different portions of the via may be exposed to different amounts of plasma, potentially resulting in undesirable structural effects resulting from non-uniform film deposition. For example, a thicker film may be deposited near the opening of the via compared to deeper portions (often referred to as cush or keyhole formation). For these reasons, thermal ALD may be more advantageous because these thermal processes do not rely on the plasma's ability to reach every portion of the surface being deposited.

[0014] However, while thermal ALD techniques can be suitable for forming relatively conformal TiN films over topography, particularly over topography with relatively high aspect ratios (e.g., greater than 1:1), the inventors have recognized that TiN films formed by thermal ALD may be inferior in some respects to TiN-based thin films formed by PVD or CVD, for example, in terms of film roughness and electrical resistivity. In this regard, the inventors have found that some electrical and / or physical properties of ALD-grown TiN-based films can be affected by the mode of growth. In particular, the inventors have found that while it may be desirable to grow TiN-based films in a two-dimensional layer-by-layer growth mode in ALD, such a layer-by-layer growth mode may not be readily achievable in some circumstances. The inventors have further discovered that growing TiN-based thin films by ALD in a layer-by-layer growth mode presents particular challenges in IC manufacturing when forming TiN-based thin films on non-metallic surfaces, particularly insulating surfaces such as oxide and nitride surfaces or doped and undoped silicon surfaces. Without being bound by any theory, the inventors have recognized that the degree to which TiN-based thin films can be grown in a layer-by-layer growth mode may depend on the initial growth mode, which in turn depends on the type and crystallinity of the surface, as disclosed herein with reference to Figures 1A-1D.

[0015] FIG. 1A schematically illustrates the nucleation of a TiN layer, and FIGS. 1B-1D illustrate different growth modes of a TiN layer on different surfaces. Referring to FIG. 1A, once precursor molecules 104 arrive at a substrate 100, they are physically adsorbed onto the substrate. Some of the adsorbed molecules 104 can diffuse along the surface of the substrate 100 until they reach energetically favorable positions for chemisorption. Surface diffusion is governed by, among other factors, the substrate temperature, the substrate material, and the kinetic energy of the adsorbed molecules. Once the size of the nuclei formed by the chemisorbed molecules exceeds a certain size (sometimes referred to as the "critical size") determined by the tradeoff between volume free energy and surface energy, the nuclei become energetically stable and can begin to grow in size. The layer 108 of stable nuclei thus formed continues to grow by incorporating additional precursor molecules 104. The subsequent film growth can be classified according to different growth modes, as shown schematically in FIGS. 1B-1D.

[0016] 1B schematically illustrates a three-dimensional island growth mode, sometimes referred to as the Volmer-Weber growth mode, in which a layer 112 of three-dimensional islands is formed. Without being bound by any theory, the island growth mode may dominate when the net surface free energy associated with the three-dimensional islands is positive, indicating that the deposited atoms are more strongly bound to each other than to the substrate. For example, when a metallic TiN layer is deposited on a given semiconductor and / or insulating material surface, it will be understood that the energetics of the ALD growth of the TiN layer favors the island growth mode.

[0017] 1C illustrates the layer-by-layer growth mode, sometimes referred to as the Frank-van der Merwe growth mode, which results in the formation of a relatively smooth two-dimensional layer 116. Without being bound by any theory, the layer-by-layer growth mode may dominate when the deposited atoms bond more strongly to the substrate than to each other, making a stable two-dimensional layer 116 energetically favorable. The layer-by-layer growth mode may be sustained when the value of the interlayer bonding energy decreases continuously from the initial monolayer of TiN to the bulk crystal.

[0018] Figures 1B and 1C show two different possible growth modes for TiN-based thin films. However, under certain circumstances, growth modes intermediate between the layer-by-layer and three-dimensional growth modes are possible. Figure 1D shows an example of an intermediate growth mode known as the Stranski-Krastanov (SK) growth mode. Without being bound by any theory, the SK growth mode can occur in thin film growth that begins in the layer-by-layer growth mode. If the layer-by-layer growth mode becomes unfavorable after the formation of one or more monolayers, the island growth mode begins and becomes dominant over the layer-by-layer growth mode, resulting in a thin film structure 120 in which three-dimensional islands form on top of two-dimensional initial layers. The SK growth mode can occur as a strain relaxation mechanism (strain-induced surface roughening).

[0019] In addition to the interaction between the deposit and the substrate, other factors such as substrate temperature, reaction pressure, and deposition rate can significantly affect the nucleation and initial growth process, which in turn affects the final nanostructure or microstructure of the resulting thin film. For example, deposition conditions that promote surface diffusion, such as a relatively high substrate temperature, a relatively low pressure, and / or a low deposition rate, can promote growth in a layer-by-layer mode. Thus, as disclosed herein, by promoting surface diffusion during deposition of the initial portion of the TiN film, such as by low pressure and deposition rate, initial film growth according to embodiments can proceed substantially in a layer-by-layer growth mode.

[0020] In IC manufacturing, when TiN is grown by ALD on a variety of intended surfaces, such as dielectric and semiconductor surfaces, the ALD growth has been found to initiate in a three-dimensional island or SK growth mode. For example, under given circumstances, ALD growth of TiN on substrate surfaces including doped or undoped Si, SiO, SiN, and other high- or low-K materials may proceed in either the island or SK growth mode. The inventors have found that, in part due to the initial growth mode, either the island or SK growth mode, subsequent growth of TiN by ALD often results in film morphology that is undesirable in many applications of ultrathin conformal TiN in high-aspect-ratio structures, such as that shown in FIG. 2.

[0021] Figure 2 shows a cross-sectional transmission electron micrograph of a TiN layer grown by thermal ALD on a native oxide-covered Si substrate. After initial film growth in either the 3D island or SK growth modes, ALD growth of TiN is often characterized by competitive growth of neighboring crystals with different orientations, which, under certain circumstances, can result in V-shaped grains close to the nucleation layer and, as the film thickness increases, in the form of a columnar morphology. As shown in Figure 2, the resulting film morphology includes faceted columnar structures that result in significant surface roughness and a low density of columnar boundaries relative to the grains. It will be appreciated that the columnar boundaries can have significantly poorer diffusion barrier properties than the grains themselves and can act as paths of least resistance for the transport of undesired contaminants through the TiN layer.

[0022] The inventors have found that when an initial portion of a TiN layer is formed on a non-metallic surface by exposing the substrate to Ti and / or N precursors at a relatively low pressure, e.g., less than 1 Torr, the initial three-dimensional or SK growth mode can be suppressed and the layer-by-layer growth mode can be promoted in the initial stages, e.g., the nucleation stage of TiN deposition. Among other reasons, this can be attributed to the fact that it takes longer for adsorbed Ti and N precursor molecules to diffuse locally and wet the substrate surface, particularly the non-metallic surface, with a relatively small contact angle. TiN layers grown under relatively low exposure pressures result in layers that uniformly cover large areas of the non-metallic surface without forming substantial islands, thereby making the layer-by-layer growth mode more dominant on the substrate during the initial stages of ALD TiN growth, where the three-dimensional island or SK growth mode typically dominates, as discussed above. Therefore, by initiating ALD of TiN by exposing the substrate to Ti and / or N precursors at a relatively low precursor exposure pressure, e.g., less than 3 Torr, the resulting initial layer can grow in the layer-by-layer mode, e.g., during the nucleation stage. The subsequent bulk stage of growth can proceed by exposing the substrate to Ti and N precursors at relatively high precursor exposure pressures, e.g., above 3 Torr, and can continue to proceed in a layer-by-layer mode. By employing methods according to embodiments, some of the drawbacks of conventional ALD of TiN can be avoided, particularly when TiN layers are formed by ALD directly on certain semiconductor and / or insulator materials, particularly on inorganic layers containing Si, SiO, and / or SiN, which, as discussed above, can lead to initial growth characterized by island or SK growth modes followed by columnar growth.

[0023] FIG. 3A is a flow diagram illustrating an embodiment of an atomic layer deposition method 300 for forming a TiN layer by exposing a substrate to multiple cycles with different corresponding precursor exposure pressures. The resulting film has at least two regions formed under different corresponding exposure pressures. FIG. 3B illustrates a schematic cross-sectional view of a semiconductor structure 350 including a TiN layer formed by atomic layer deposition, in which the substrate is exposed to multiple cycles with different corresponding precursor exposure pressures, according to the method illustrated in FIG. 3A. Referring to FIG. 3A, the method 300 includes providing a substrate including a non-metallic surface in a reaction chamber configured for ALD, e.g., thermal ALD, 310. The method 300 further includes an initial stage, e.g., a nucleation stage, that includes forming a first portion of a thin film on the substrate 320 by exposing the semiconductor substrate to one or more first ALD cycles, each cycle including exposure to a first Ti precursor and a first N precursor under a first respective exposure pressure. The method 300 further includes a subsequent step, e.g., a bulk deposition step, that includes forming a second portion of the thin film on the first portion of the thin film by exposing the semiconductor substrate to one or more second ALD cycles, each including exposure to a second Ti precursor and an exposure to a second N precursor under a second respective exposure pressure 330. The exposure to one or both of the Ti precursor and the N precursor in the one or more second ALD cycles is conducted at a higher pressure than the corresponding exposure to one or both of the Ti precursor and the N precursor in the one or more first ALD cycles.

[0024] Referring to FIG. 3B, a cross-sectional view of a semiconductor thin film structure 350 includes a substrate 360 ​​having a non-metallic surface, e.g., a dielectric surface and / or a semiconductor surface. A first portion 370 of a thin film including TiN is formed on the substrate 360, and a second portion 380 of the thin film is formed on the first portion 370. The first and second portions 370, 380 are formed by atomic layer deposition, as shown in FIG. 3A, where the substrate 360 ​​is exposed to first and second cycles using different corresponding precursor exposure pressures. The first portion 370 can be grown in a layer-by-layer growth mode, e.g., during the initial nucleation stage, as described above, such that at least the first portion 370 or both the first and second portions 370, 380 can be substantially free of adjacent crystals with different orientations and relatively high (e.g., 10% of the thickness) surface roughness characteristic of columnar growth of V-shaped grains. The resulting TiN layer has one or more of the following superior properties compared to comparable thin film layers formed under a single pressure during the nucleation and bulk deposition stages: relatively high conformality or step coverage, lower surface roughness, smaller average grain size, higher electrical conductivity, and / or barrier properties.

[0025] As described herein and throughout the specification, it will be understood that semiconductor substrates on which TiN thin films according to embodiments are formed can be implemented on a variety of substrates, including, but not limited to, doped semiconductor substrates, which can be formed from Group IV elemental materials (e.g., Si, Ge, C, or Sn, etc.) or alloys formed from Group IV materials (e.g., SiGe, SiGeC, SiC, SiSn, SiSnC, GeSn, etc.), III-V compound semiconductor materials (e.g., GaAs, GaN, InAs, etc.) or alloys formed from III-V materials, and II-VI semiconductor materials (e.g., CdSe, CdS, ZnSe, etc.) or alloys formed from II-VI materials.

[0026] In certain embodiments, the substrate may also be implemented as a semiconductor-on-insulator substrate, such as, for example, a silicon-on-insulator (SOI) substrate. SOI substrates typically include a silicon-insulator-silicon structure, where the various structures described above are insulated from a supporting substrate using an insulator layer, such as a buried SiO layer. Furthermore, it will be understood that the various structures described herein may be formed, at least in part, at or near the surface region of an epitaxial layer.

[0027] Additionally, substrates can include a variety of structures formed thereon, such as diffusion regions, insulating regions, electrodes, vias, and lines, etc. Any structure including a TiN layer according to embodiments can be formed thereon, including topological features such as vias, cavities, holes, or trenches with one or more semiconductor or dielectric surfaces. Thus, non-metallic surfaces on which TiN layers according to embodiments can be formed include semiconductor surfaces, such as doped or undoped Si surfaces, and / or dielectric surfaces, such as interlayer dielectric (ILD) surfaces, mask or hard mask surfaces, or gate dielectric surfaces, which can include dielectric materials such as inorganic insulators, oxides, nitrides, high-K dielectrics, low-K dielectrics, or carbon.

[0028] As used herein and throughout the specification, a reaction chamber refers to any reaction chamber, including a single-wafer or batch-wafer processing reaction chamber, suitably configured for thermal atomic layer deposition (ALD). In a thermal ALD reactor, a substrate can be placed on a suitable substrate holder, such as a susceptor or carrier boat. The substrate can be heated directly by thermal conduction through a heated susceptor, or indirectly by radiation from an irradiation source, such as a lamp, or by convection through heated chamber walls.

[0029] Generally, in an ALD process, reactants or precursors, such as an oxidation reactant and a reduction reactant, are alternately introduced into a reaction chamber having a substrate disposed therein. The introduction of one or more reactants or precursors can be sequentially alternated with purging and / or pumping steps to remove excess reactants or precursors from the reaction chamber. The reactants can be introduced into the reaction chamber under conditions for a suitable time interval so that the surface of the substrate becomes at least partially saturated with the precursors or reactants and / or their reaction products. Excess or residual precursors or reactants can then be removed from the substrate, such as by purging and / or pumping the reaction chamber. The pumping step can be performed by a suitable vacuum pumping step, and the purging step can be performed by introducing a non-reactive or inert gas, such as nitrogen or a noble gas, into the reaction chamber. In the context of layers formed by thermal ALD in the embodiments described below, there are generally two categories of precursors or reactants: nitrogen (N) precursors and titanium (Ti) precursors.

[0030] Referring now to FIG. 4 , an example method 300 ( FIG. 3A ) for forming a thin film comprising TiN by ALD, such as thermal ALD, having at least two regions formed by exposing a substrate to multiple cycles under different corresponding precursor exposure pressures is described below, according to an embodiment.

[0031] Atomic layer deposition of TiN by exposing substrates to multiple cycles under different corresponding precursor exposure pressures. 3A , after providing 310 a substrate including a non-metallic surface (substrate 360 ​​in FIG. 3B ) in a reaction chamber, the method 300 proceeds to form a first portion of a thin film on the non-metallic surface by atomic layer deposition (ALD), such as thermal ALD, by exposing the semiconductor substrate to one or more first ALD cycles, and then forming a second portion of the thin film by exposing the semiconductor substrate to one or more second ALD cycles 320. The exposure pressures used during the first and second ALD cycles are diagrammed below.

[0032] 4 schematically illustrates pressure traces corresponding to exposure of a substrate to Ti and N precursors during a first cycle 400A, e.g., a nucleation stage, to form a first portion 370 ( FIG. 3B ) of a thin film, and during a second cycle 400B, e.g., a bulk formation stage, to form a second portion 380 ( FIG. 3B ) of the thin film, according to an embodiment. Referring to FIG. 4 , the first portion of the thin film is formed by exposing the semiconductor substrate to one or more first ALD cycles 400A, each including one or more exposures 404 or pulses to a partial pressure of a first Ti precursor or one or more exposures 408 or pulses to a partial pressure of a first N precursor. The second portion of the thin film is formed by exposing the semiconductor substrate to one or more second ALD cycles 400B, each including one or more exposures 412 or pulses to a partial pressure of a second Ti precursor or one or more exposures 416 or pulses to a partial pressure of a second N precursor.

[0033] As shown schematically, each of the first Ti precursor exposure 404, first N precursor exposure 408, second Ti precursor exposure 412, and second N precursor exposure 416 can have a different partial pressure range, including corresponding partial pressure rise periods 404A, 408A, 412A, and 416A, main exposure periods 404B, 408B, 412B, and 416B, and partial pressure drop periods 404C, 408C, 412C, and 416C. Each of the partial pressure rise periods 404A, 408A, 412A, and 416A can correspond to, for example, a particular precursor being introduced into the reaction chamber. Each of the main exposure periods 404B, 408B, 412B, and 416B can correspond to a period during which the amount of each particular precursor in the reaction chamber is relatively constant. The relatively constant amount of each particular precursor can be maintained using, for example, a pressure transducer or a throttle valve. Each of the partial pressure drop zones 404C, 408C, 412C, and 416C can correspond to, for example, a zone when a respective precursor is being purged or pumped out of the reaction chamber.

[0034] 4, it will be understood that in a given embodiment, the precursors may be pumped out and / or purged after each exposure. In a given embodiment where the precursors are pumped out without being purged, the reaction chamber pressure may be substantially represented by the partial pressure of the individual precursors, and the pressure traces for exposures 404, 408, 412, and 416 may substantially represent the reaction chamber pressure or precursor partial pressure during the individual exposures. In a given embodiment where the precursors are purged with an inert gas without being pumped out, the reaction chamber pressure may be represented by the reaction chamber total pressures 404P, 408P, 412P, and 416P corresponding to exposures 404, 408, 412, and 416, where the reaction chamber total pressure is derived from the mixture of the individual precursors and the inert gas.

[0035] In practice, a combination of pumping and purging can be used for higher throughput and better film quality. In these examples, the substrate can be exposed to partial pressures of a first Ti precursor, a first N precursor, a second Ti precursor, and a second N precursor while measuring the total pressures 404P, 408P, 412P, and 416P, including during purging and pumping. In a given embodiment, the total chamber pressure can be maintained relatively constant throughout a given precursor exposure or exposure pulse, while the pump power is adjusted using a pressure transducer or by replacing removed precursors with an inert gas. In these examples, each of the one or more first ALD 400A cycles to form the first portion (370 in FIG. 3B) can include one or more exposures 404 to a partial pressure of a first Ti precursor (the measured parameter can be the reaction chamber total pressure 404P) and one or more exposures 408 to a partial pressure of a first N precursor (the measured parameter can be the reaction chamber total pressure 408P). Similarly, each of the one or more second ALD 400B cycles to form the second portion (380 in FIG. 3B) can include one or more exposures 412 to a partial pressure of a second Ti precursor (the parameter measured can be the reaction chamber total pressure 412P) and one or more exposures 416 to a partial pressure of a second N precursor (the parameter measured can be the reaction chamber total pressure 416P).

[0036] According to various embodiments, during precursor exposure, the measured reaction chamber total pressure can be proportional to the precursor partial pressure. Thus, higher total pressures 412P and 416P compared to total pressures 404P and 408P correspond to higher partial pressures of the second Ti precursor and the second N precursor compared to the partial pressures of the first Ti precursor and the first N precursor, respectively. However, embodiments are not so limited, and in other embodiments, higher total pressures 412P and 416P compared to total pressures 404P and 408P can correspond to partial pressures of the second Ti precursor and the second N precursor that are the same or lower compared to the partial pressures of the first Ti precursor and the first N precursor, respectively.

[0037] Referring back to method 300 shown in FIG. 3A , the exposure pressure of one or both of the second Ti precursor and the second N precursor during one or more subsequent second ALD cycles, e.g., bulk deposition phases, is higher than the exposure pressure of one or both of the first Ti precursor and the first N precursor during one or more prior first ALD cycles, e.g., nucleation phases. In a given embodiment, the exposure pressure can be the partial pressure of the precursor or the total pressure of the reaction chamber. Thus, in various embodiments, referring to FIG. 4 , one or both of the exposure to the second Ti precursor 412 and the exposure to the second N precursor 416 can be conducted at a higher partial pressure and / or a higher total reaction chamber pressure than the corresponding one or both of the exposure to the first Ti precursor 404 and the exposure to the first N precursor 408, respectively.

[0038] 4 , in various embodiments, the corresponding partial or total pressures during corresponding exposures to the Ti and N precursors in the first and second cycles 400A and 400B can be the corresponding partial or total pressures during any one of the partial pressure increase zones 404A, 408A, 412A, and 416A, the main exposure zones 404B, 408B, 412B, and 416B, and the partial pressure decrease zones 404C, 408C, 412C, and 416C. For example, the exposures 412, 416 to one or both of the second Ti precursor and the second N precursor during the main exposure zones 412B and 416B, respectively, in the second ALD cycle 400B can be conducted at higher total or partial pressures than the exposures 404, 408 to one or both of the first Ti precursor and the first N precursor during the main exposure zones 404B and 408B, respectively, in the first ALD cycle 400A. In various embodiments, the corresponding partial or total pressures between corresponding exposures to the Ti and N precursors during the first and second cycles 400A and 400B can be the corresponding average, mean, or peak partial or total pressures during exposures 404, 408, 412, and 416.

[0039] 4, in the illustrated embodiment, the total and / or partial pressures during exposure to the first Ti precursor 404 and exposure to the first N precursor 408 are different, and the total and / or partial pressures during exposure to the second Ti precursor 412 and exposure to the second N precursor 416 are different. However, embodiments are not so limited, and in a given embodiment, the total and / or partial pressures can be maintained constant during exposure to the first Ti precursor 404 and exposure to the first N precursor 408 and / or the total and / or partial pressures can be maintained constant during exposure to the second Ti precursor 412 and exposure to the second N precursor 416.

[0040] Still referring to FIG. 4 , the total pressure during each of the first Ti precursor exposure 404 and the first N precursor exposure 408 can be the same or different, but can be between 0.01 and 0.2 Torr, 0.2 and 0.4 Torr, 0.4 and 0.6 Torr, 0.6 and 0.8 Torr, 0.8 and 1.0 Torr, 1.0 and 1.5 Torr, 1.5 and 2.0 Torr, 2.0 and 2.5 Torr, 2.5 and 3.0 Torr, or a pressure within a range defined by any of these values. The total pressure during the second Ti precursor exposure 412 and the second N precursor exposure 416 can be the same or different, but can be 3.0-4.0 Torr, 4.0-5.0 Torr, 5.0-6.0 Torr, 6.0-7.0 Torr, 7.0-8.0 Torr, 8.0-9.0 Torr, 9.0-10.0 Torr, 10.0-11.0 Torr, 11.0-12.0 Torr, or a pressure within a range defined by any of these values. The ratio of the total pressure (measured in Torr) of the reaction chamber during the second Ti precursor exposure 412 to that during the first Ti precursor exposure 404 can be 2-5, 5-10, 10-20, 20-50, 50-100, or a range defined by any of these values. Similarly, the ratio of the total pressure (measured in Torr) of the reaction chamber during exposure 416 to the second N precursor to that during exposure 408 to the first N precursor can be 2-5, 5-10, 10-20, 20-50, 50-100, or within a range defined by any of these values. In each of exposures 404, 408, 412, and 416, the individual Ti or N precursor can be 1-2%, 2-5%, 5-10%, 10-20%, 20-50%, 50-100%, or within a range defined by any of these values ​​of the total amount of gas molecules in the reaction chamber.

[0041] Still referring to FIG. 4 , according to various embodiments, the total or partial pressures during the first Ti precursor exposure 404 and the first N precursor exposure 408 are controlled in relation to the flow rates of the individual precursors and inert gases and the pumping power of the reaction chamber so that the deposition rate during the first cycle 400A or phase is between 0.10-0.20 Å / cycle, 0.20-0.30 Å / cycle, 0.30-0.40 Å / cycle, 0.40-0.50 Å / cycle, 0.50-0.60 Å / cycle, or a value within a range defined by any of these values ​​per cycle including the first Ti precursor exposure 404 and the first N precursor exposure 408. The total or partial pressures during the exposure to the second Ti precursor 412 and the exposure to the second N precursor 416, in relation to the flow rates of the individual precursors and inert gases and the pumping power of the reaction chamber, are controlled so that the deposition rate during the second cycle 400B or stage is between 0.20-0.30 Å / cycle, 0.30-0.40 Å / cycle, 0.40-0.50 Å / cycle, 0.50-0.60 Å / cycle, 0.60-0.70 Å / cycle, 0.70-0.80 Å / cycle, or a value within a range defined by any of these values ​​per cycle including the exposure to the second Ti precursor 412 and the exposure to the second N precursor 416. The ratio of the deposition rate per cycle during the second cycle 400B to that during the first cycle 400A can be 1-1.5, 1.5-2.0, 2.5-3.0, or a ratio within a range defined by any of these values.

[0042] The inventors have discovered that various technical advantages of the TiN thin films disclosed herein may be realized when forming 320 (FIG. 3A) a first portion 370 (FIG. 3B) and forming 330 a second portion 380 (FIG. 3B) of the thin film comprising TiN includes exposing the semiconductor substrate to first cycles 400A (FIG. 4) and second cycles 400B (FIG. 4), respectively, for a number of cycles between 1 and 25 cycles, between 26 and 50 cycles, between 50 and 100 cycles, between 100 and 200 cycles, between 200 and 300 cycles, between 300 and 400 cycles, between 400 and 500 cycles, between 500 and 600 cycles, or within a range defined by any of these values. In various embodiments, the ratio of the number of second cycles to the number of first cycles can be greater than 1, 2, 5, or 10, or a ratio within a range defined by any of these values, or can be less than 1, 0.5, 0.1, or 0.1, or a ratio within a range defined by any of these values. The total thickness of the thin film comprising TiN, including first portion 370 (FIG. 3B) and second portion 380 (FIG. 3B), can have a combined stack thickness that does not exceed about 25 nm, 20 nm, 15 nm, 10 nm, 7 nm, 4 nm, 2 nm, or a value within a range defined by any of these values. The thickness ratio of first portion 370 (FIG. 3B) to second portion 380 (FIG. 3B) can be about 1:20 to 1:10, 1:10 to 1:5, 1:5 to 1:2, 1:2 to 1:1, 1:1 to 2:1, 2:1 to 5:1, 5:1 to 10:1, 10:1 to 20:1, or a ratio within a range defined by any of these values. It will be understood that in a given embodiment, first portion 370 (FIG. 3B) can be relatively thin, for example, when high conformality is more important than low film roughness, while second portion 380 (FIG. 3B) can be relatively thin when low film roughness is more important than high conformality.

[0043] 4, the exposure of the substrate to the first Ti precursor 404 and the exposure of the substrate to the second Ti precursor 412 are each conducted such that the surface of the substrate is substantially wholly or partially saturated with the first Ti precursor or the second Ti precursor, respectively. After the exposure of the substrate to the first Ti precursor 404 and the exposure of the substrate to the second Ti precursor 412, respectively, excess or remaining first and / or second Ti precursors or their reaction products that do not remain physisorbed or chemisorbed on the substrate surface can be pumped out and / or purged.

[0044] Similarly, the substrate exposure 408 to the first N precursor and the substrate exposure 416 to the second N precursor are each conducted so that the surface of the substrate is substantially fully or partially saturated with the first N precursor or the second N precursor, respectively. After each of the substrate exposures 408 to the first N precursor and the second N precursor 416, excess or residual first and / or second N precursors or their reaction products that do not remain physisorbed or chemisorbed on the substrate surface can be pumped out and / or purged. By exposing the substrate to one or more exposures to the first Ti precursor and one or more exposures to the first N precursor, approximately less than a monolayer of TiN can be formed per cycle. Similarly, by exposing the substrate to one or more exposures to the second Ti precursor and one or more exposures to the second N precursor, approximately less than a monolayer of TiN can be formed per cycle.

[0045] In a given embodiment, the exposure to the first Ti precursor 404, the exposure to the first N precursor 408, the exposure to the second Ti precursor 412, and / or the exposure to the second N precursor 416 can be performed multiple times in succession before the introduction of other precursors. For example, under certain circumstances, exposing the substrate to the Ti precursor and / or the N precursor more than once can be advantageous in achieving a higher level of surface saturation, for example, when significant steric hindrance effects are present.

[0046] With further reference to FIG. 4 , it will be understood that the relative order of exposure to the first Ti precursor and the first N precursor may be selected depending on competing circumstances. In certain embodiments, it may be advantageous to have the first Ti precursor be the first precursor to which the substrate surface is exposed. For example, direct exposure of the Si surface to the first Ti precursor one or more times can result in the formation of one or more monolayers of TiSi and prevent the formation of SiN, which may be advantageous in reducing the contact resistance between the underlying Si and the TiN layer formed thereon. However, in certain other embodiments, it may be advantageous to have the first N precursor be the first precursor to which the substrate surface is exposed. For example, direct exposure of the Si surface to the first N precursor can intentionally form one or more monolayers of SiN, which may be advantageous in improving the barrier properties of the stack.

[0047] It will be appreciated that in various embodiments, the frequency and repetition of exposure of the substrate to the first Ti reactant and / or first N precursor in each first cycle 400A and the second Ti reactant and / or second N precursor in each second cycle 400B can be varied to obtain a desired thickness and stoichiometry based on various considerations, including the susceptibility of the precursors to steric hindrance effects.

[0048] In various embodiments, non-limiting examples of first and second Ti precursors, which may be the same or different, for forming the first and second portions of the TiN layer according to embodiments include titanium tetrachloride (TiCl), tetrakis(dimethylamino)titanium (TDMAT), or tetrakis(diethylamino)titanium (TDEAT). Having the same precursor for the first and second portions of TiN may be advantageous, for example, in terms of cost reduction and / or ease of process design. However, having different precursors for the first and second portions of TiN may be advantageous, for example, in terms of different deposition characteristics or film quality.

[0049] In various embodiments, non-limiting examples of first and second N precursors, which can be the same or different, to form the first and second portions of the TiN layer according to embodiments include ammonia (NH), hydrazine (NH), and monomethylhydrazine (CH(NH)NH, "MMH"). Having the same precursor in the first and second portions can be advantageous, for example, in terms of cost reduction and / or ease of process design. However, having different precursors in the first and second portions of the TiN can be advantageous, for example, in terms of different deposition characteristics or film quality.

[0050] In various embodiments, non-limiting examples of inert gases for purging include nitrogen N2 or noble gases such as Ar or He.

[0051] The various technical advantages and benefits described herein can be realized, according to embodiments, when one or both of the first and second portions 370, 380 (FIG. 3B) of the TiN-containing thin film are formed at a substrate temperature of 350° C. to 800° C., 450° C. to 750° C., 500° C. to 700° C., 550° C. to 650° C., or within a range defined by any of these values, such as about 600° C. Because temperature adjustment during the process can take a long time, maintaining the same temperature during the growth of the first and second portions 370, 380 can be advantageous for throughput and ease of process control.

[0052] In various embodiments, the exposure or pulse time for each of the first and second Ti precursors and the first and second N precursors can be about 0.1-1 seconds, 1-10 seconds, 10-30 seconds, 30-60 seconds, or a duration within a range defined by any of these values.

[0053] Advantageously, in various embodiments, when a TiN layer is formed using atomic layer deposition techniques in which a substrate is exposed to multiple cycles under different corresponding precursor exposure pressures, one or both of the surface roughness and electrical resistivity can be significantly reduced relative to conventional TiN films, including TiN films formed using other ALD processes with a single pressure setting. Thin films comprising TiN formed by the methods described herein and having the above-described thicknesses and thickness ratios of the first and second portions 370, 380 (FIG. 3B) can have root-mean-square (RMS) surface roughness values ​​of 3%, 4%, 5%, 6%, 7%, 8%, and 9%, or values ​​within a range defined by any of these values, based on the average thickness of the thin film. Alternatively, thin films comprising TiN deposited with the above-described thicknesses and thickness ratios of the first and second portions 370, 380 (FIG. 3B) can have RMS surface roughness values ​​of 2.5 nm, 2 nm, 1.5 nm, 1.0 nm, 0.5 nm, or values ​​within a range defined by any of these values.

[0054] When deposited, a thin film comprising TiN formed by the methods described herein and having the above-described thicknesses and thickness ratios of first and second portions 370, 380 (FIG. 3B) can have an electrical resistivity of <70 μΩ-cm, 70-100 μΩ-cm, 100-130 μΩ-cm, 130-160 μΩ-cm, 160-190 μΩ-cm, 190-220 μΩ-cm, 220-250 μΩ-cm, 250-280 μΩ-cm, 280-310 μΩ-cm, or 310 μΩ-cm or greater, or a value within a range defined by any of these values, for example, less than about 200 μΩ-cm.

[0055] In addition to reduced surface roughness and electrical resistivity, thin films including TiN formed by the methods described herein have high conformality when deposited on high-aspect-ratio structures. One measure of conformality in the context of high-aspect-ratio structures is referred to herein as step coverage. The high-aspect-ratio structure may be, for example, a via, a hole, a trench, a cavity, or a similar structure. As an illustrative example, FIG. 5 schematically shows a semiconductor structure 500 having an exemplary high-aspect-ratio structure 516 formed therein to explain some exemplary metrics for defining and / or measuring the conformality of thin films formed on the high-aspect-ratio structure. The illustrated high-aspect-ratio structure 516 is lined with a TiN layer 512 having different thicknesses at different portions thereof. As described herein, the high-aspect-ratio structure has an aspect ratio greater than 1, e.g., the ratio of the depth or height (H) of the high-aspect-ratio structure 516 divided by the width (W) of the open region. In the illustrated example, the high aspect ratio structure 516 is a via formed through a dielectric layer 508, e.g., an interlayer dielectric (ILD) layer, formed on a semiconductor substrate 504, with the bottom surface of the high aspect ratio structure 516 exposing the underlying semiconductor 504. The TiN layer 512 can cover different surfaces of the high aspect ratio structure 516 to different thicknesses. As described herein, one measure of the conformality of a thin film formed with a high aspect ratio is referred to as step coverage. Step coverage can be defined as the ratio of the thickness of the thin film at the lower or bottom region of the high aspect ratio structure to the thickness of the thin film at the upper or top region of the high aspect ratio structure. The upper or top region can be a region of the high aspect ratio structure with a relatively small depth, e.g., 0-10% or 0-25% of H, measured from the top of the opening. The lower or bottom region can be a region of the high aspect ratio structure of a relatively large depth, for example, at 90-100% or 75-100% of H measured from the top of the opening. For a given high aspect ratio structure, step coverage can be defined or measured by the ratio of the thickness of the thin film 512A formed on the bottom surface to the thickness of the thin film 512C formed on the sidewall surface of the top or top of the high aspect ratio structure.However, it will be appreciated that a given high aspect ratio structure may have a bottom surface that is not well-defined or has a bottom surface with a small radius of curvature, and in such structures, step coverage may be more consistently defined or measured by the ratio of the thickness of the thin film 512B formed on the lower or bottom sidewall surface to the thickness of the thin film 512C formed on the upper or top sidewall surface of the high aspect ratio structure.

[0056] As discussed above, thin films comprising TiN formed by the methods disclosed herein exhibit reduced surface roughness and electrical resistivity while also providing high conformality in high aspect ratio structures. In various embodiments, high aspect ratio structures having aspect ratios greater than 1, 2, 5, 10, 20, 50, 100, 200, or a value within a range defined by any of these values, can be conformally coated with TiN films according to embodiments with step coverages defined herein of greater than 70%, 80%, 90%, 95%, or a value within a range defined by any of these values.

[0057] Physical properties of TiN formed by exposing substrates to multiple cycles at different corresponding precursor exposure pressures. Figure 6 shows experimentally measured root-mean-square (RMS) surface roughness trends 604 and step coverage trends 608 as a function of the number of first cycles of Ti and N precursor exposure at a relatively low chamber pressure of 0.5 Torr, out of a total of 600 combinations of first cycles (e.g., nucleation stage) and second cycles (bulk deposition stage). The second cycle of Ti and N precursor exposure was performed at a relatively high chamber pressure of 5 Torr. The experimental data points in Figure 6 were obtained from TiN films grown on native SiO-coated Si for surface roughness measurements and from TiN films grown in vias formed in SiO with an aspect ratio of approximately 40:1. The measured deposition rates for the first and second cycles were 0.28 Å / cycle and 0.38 Å / cycle, respectively. Experimental data were measured on four different TiN films: 0 1st cycle (0 Å) / 600 2nd cycle (228 Å), 50 1st cycle (14 Å) / 550 2nd cycle (209 Å), 200 1st cycle (56 Å) / 400 2nd cycle (152 Å), and 600 1st cycle (168 Å) / 0 2nd cycle (0 Å). The four TiN films had total thicknesses of approximately 228 Å, 223 Å, 208 Å, and 168 Å, respectively. As noted above, the measured surface roughness of TiN films decreases with increasing relative number of first cycles, which include exposure to relatively low pressures. Without being bound by any theory, this is believed to be because slower growth rates tend to increase surface diffusion, which tends to reduce surface roughness and promote layer-by-layer growth. The measured surface roughness values ​​for the 0 first cycle / 600 second cycle, 50 first cycle / 550 second cycle, and 200 first cycle / 400 second cycle thin films were 21 Å, 17.5 Å, and 12.5 Å, respectively, corresponding to approximately 9%, 8%, and 6% of the total thickness of the TiN films, respectively. Furthermore, as noted above, the measured step coverage values ​​for the TiN films grown with 0 first cycles / 600 second cycles were higher than those grown with 600 first cycles / 0 second cycles. Without being bound by any theory, this is believed to be because higher pressures tend to allow more precursor to reach the bottom of high aspect ratios, which tends to improve step coverage. However, the inventors surprisingly found that step coverage actually improves with increasing the number of first cycles, up to about 50 first cycles (8% of the total number of cycles). Thus, according to given embodiments, forming a first portion of a TiN film includes alternatingly exposing the semiconductor substrate to 1 to 50 cycles, each cycle including exposure to a first Ti precursor and exposure to a first N precursor under a relatively low exposure pressure of less than about 3 Torr.

[0058] Figures 7A-7C show further experimental comparisons between TiN films grown by exposing substrates to cycles using the same precursor exposure pressure and TiN films grown by exposing substrates to multiple cycles using different corresponding precursor pressures. Figure 7A is a transmission electron micrograph of a high-aspect-ratio via lined with a TiN layer formed by atomic layer deposition (ALD) in which the substrate was exposed to an ALD cycle under the same precursor exposure pressure corresponding to the second cycle. Figures 7B and 7C are transmission electron micrographs (TEM) of TiN films grown using only the second cycle of exposure to Ti and N precursors at a relatively high chamber pressure of 5 Torr. These TEM images were taken of the top (Figure 7B) and bottom (Figure 7C) regions of a via formed in SiO2 with an aspect ratio of approximately 40:1. 8A and 8B are transmission electron micrographs (TEMs) of TiN films grown using a combination of first and second cycles of exposure to Ti and N precursors at relatively low (0.5 Torr) and high (5 Torr) chamber pressures, according to an embodiment. The TEMs were taken of the top (FIG. 8A) and bottom (FIG. 8B) regions of a via formed in SiO2 with an aspect ratio of approximately 40:1. FIG. 9 is a graph showing an experimental statistical comparison between the measured step coverage 904 measured from the TEM micrographs shown in FIGS. 7A-7C and the measured step coverage 908 measured from the TEM micrographs shown in FIGS. 8A-8B. The data points in FIG. 9 represent ratios taken from different locations within the lower region of the via and different locations within the upper region of the via. While not readily apparent from the TEM images, the statistical comparison in FIG. 9 clearly shows a higher median step coverage of 93% for TiN films deposited in accordance with embodiments compared to 87% for TiN films deposited using a single exposure pressure. In addition, one measure of step coverage for TiN films deposited in accordance with embodiments is that the statistical spread of step coverage is significantly smaller than that for TiN films deposited using a single exposure pressure, indicating significantly higher film roughness for the latter.

[0059] [Application] Thin films comprising TiN formed using different exposure pressures according to various embodiments disclosed herein can be used in a variety of applications that can benefit from the various advantageous properties of the TiN layers disclosed herein, particularly when the substrate includes relatively high aspect ratio structures and / or non-metallic surfaces. Exemplary applications include depositing vias, holes, trenches, cavities, or similar structures having aspect ratios (e.g., defined as the depth divided by the width at the top) greater than 1, 2, 5, 10, 20, 50, 100, 200, or a value within a range defined by any of these values.

[0060] By way of example, FIG. 10 schematically illustrates the application of a diffusion barrier concept for a contact structure, e.g., a source or drain contact, formed on an active semiconductor substrate region, which may be heavily doped. A portion of a semiconductor device 1000 is shown having formed thereon a dielectric layer 1008, e.g., an interlayer or metal-insulated dielectric (ILD) layer, comprising a dielectric material such as an oxide or nitride. Vias or trenches can be formed through the dielectric layer 1008 to form contacts to various regions of the substrate 1004, including various doped regions, e.g., source and drain regions. The vias or trenches may expose various non-metallic surfaces, such as an exposed bottom surface, including a substrate surface, e.g., a silicon substrate surface, as well as dielectric sidewalls of the via. The bottom and side surfaces of the via can be conformally coated with a first portion (corresponding to first portion 370 in FIG. 3B ) and then coated with a second portion (corresponding to second portion 380 in FIG. 3B ) of a TiN layer formed according to various embodiments described herein. According to various embodiments disclosed herein, a conformal first portion can be first formed directly on the interior surface of the via, followed by a conformal second TiN layer. The lined via can then be filled with a metal such as W, Al, or Cu to form the contact plug 1016. For example, the via can be filled with tungsten by CVD using, for example, WF.

[0061] The barrier layer 1012 formed in accordance with embodiments may be advantageous for a variety of reasons. In particular, due to the conformal nature of the barrier layer 1012 formed by ALD, the tendency for pinch-off during a subsequent metal fill process may be substantially reduced. Furthermore, as discussed above, the barrier layer 1012 can provide effective blocking of material transport across it, such as out-diffusion of dopants (B, P) from the substrate 1004 and in-diffusion of reactants, etchants, and metals (e.g., F, Cl, W, or Cu) from the contact plug formation process. The barrier effect may be enhanced by reduced surface roughness and increased step coverage. Furthermore, as discussed above, the layer-by-layer growth mode can reduce the overall contact resistance of the barrier layer 1012. Furthermore, reduced film roughness allows for the formation of a relatively thin barrier layer 1012 while still achieving the desired barrier function, resulting in further reduction of contact resistance.

[0062] Other applications of thin films comprising TiSiN and / or TiAlN formed according to various embodiments disclosed herein include a variety of conductive structures such as recessed substrates (such as buried electrodes or lines), electrodes (such as DRAM capacitor electrodes or gate electrodes), higher metal level metallization barriers (such as barriers in vias / trenches for Cu contacts / lines), high aspect ratio vertical rod electrodes or vias for 3D memory, and through silicon vias (TSVs), to name a few.

[0063] While the present invention has been described herein with reference to particular embodiments, these embodiments do not serve to limit the invention but are set forth for purposes of illustration. It will be apparent to those skilled in the art that changes and modifications can be made without departing from the spirit and scope of the invention.

[0064] Such simple modifications and improvements of the various embodiments disclosed herein are within the scope of the disclosed technology, the specific scope of which will be further defined by the appended claims.

[0065] In the foregoing, it will be understood that the features of any one of the embodiments can be combined with or substituted for the features of any other one of the embodiments.

[0066] Unless the context clearly requires otherwise, throughout this specification and the claims, words such as "comprise," "consisting," "include," "including," and the like are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to an exclusive or exhaustive sense. The word "coupled," as generally used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Similarly, the word "connected," as generally used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Furthermore, as used herein, words such as "herein," "above," "below," and similar terms refer to this specification as a whole, rather than to a particular portion of this specification. Furthermore, in the above description of the detailed description of the invention, words using the singular or plural number may also include the plural or singular number, respectively, where the context allows. The word "or" referring to a list of two or more items includes all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0067] Furthermore, as used herein, particularly conditional terms such as "can," "could," "might," "may," "e.g.," "for example," and "such as," are generally intended to convey that certain embodiments include certain features, elements, and / or conditions, and that other embodiments do not, unless otherwise specified or understood within the context in which they are used. Thus, such conditional terms are generally not intended to imply that features, elements, and / or conditions are in any way required by one or more embodiments, or that these features, elements, and / or conditions may or may not be included in or practiced in any particular embodiment.

[0068] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while functions are shown in a given arrangement, in alternative embodiments, similar functions may be performed with different components and / or sensor topologies, and some functions may be deleted, moved, added, subdivided, combined, and / or modified. Each of these functions may be implemented in a variety of different ways. Any appropriate combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The various functions and processes described above may be implemented independently of each other or may be combined in various ways. All possible combinations and subcombinations of features of the present disclosure are intended to be within the scope of the present disclosure.

Claims

1. a semiconductor substrate including a non-metallic sidewall surface within a trench or via having an aspect ratio greater than 5; a thin film comprising TiN conformally lining the non-metallic sidewall surface; A semiconductor structure, wherein the ratio of the thickness of a thin film formed on the lower 25% of the height of the trench or via to the thickness of a thin film formed on the upper 25% of the height of the trench or via is greater than 0.

9.

2. The semiconductor structure of claim 1 , wherein the trench or via has an aspect ratio greater than 10.

3. 10. The semiconductor structure of claim 1, wherein the thin film formed on the non-metallic sidewall surface has a root mean square surface roughness of less than about 8% relative to the average thickness of the thin film.

4. The semiconductor structure of claim 1 , wherein the trench or via has dielectric sidewalls.

5. The semiconductor structure of claim 1 , wherein the trench or via has a bottom surface that exposes semiconductor material of the semiconductor substrate.

6. 10. The semiconductor structure of claim 1, wherein the TiN layer has an electrical resistivity of less than about 200 μΩ-cm.

7. 10. The semiconductor structure of claim 1, wherein the thin film-lined trench or via is filled with a metal comprising tungsten.

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