Light emitting device and image forming apparatus including the same

Abstract

To provide an image forming apparatus equipped with a light emitting device in which structures of a light emitting chip and a driving circuit are improved.SOLUTION: The image forming apparatus has a light emitting device provided with a silicon wafer on the surface of which an electrode layer and a light emitting layer are formed and a driving circuit for driving the light emitting layer is provided. A drive circuit that drives the light emitting device includes a voltage generation circuit that generates a drive voltage, and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on the image data, and the drive circuit applies the drive voltage generated by the voltage generation circuit to each of the plurality of electrodes according to the pulse signal.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a light-emitting device and an image forming apparatus, and more particularly to an electrophotographic printer. [Background technology]

[0002] Printers, which are electrophotographic image forming devices, commonly use an exposure head to expose a photosensitive drum to light to form a latent image. The exposure head is typically made of LEDs (light-emitting diodes) or organic electroluminescence (OLED). The exposure head consists of a row of light-emitting elements aligned along the length of the photosensitive drum and a rod lens array that focuses light from the row of light-emitting elements onto the photosensitive drum. LEDs and organic EL elements are known to have a surface-emitting configuration in which the light emitted from the light-emitting surface is directed in the same direction as the rod lens array. The length of the row of light-emitting elements is determined by the width of the image area on the photosensitive drum, and the spacing between the light-emitting elements is determined by the printer's resolution. For example, in a 1200 dpi printer, the pixel spacing is 21.16 μm, and therefore the spacing between the light-emitting elements also corresponds to 21.16 μm. Printers using such exposure heads use fewer parts than laser scanning printers, which scan a photosensitive drum with a laser beam deflected by a rotating polygon mirror, making it easier to make the device smaller and less expensive.

[0003] Patent Document 1 discloses an exposure head in which a light-emitting chip and a signal generating circuit serving as a drive circuit for driving the light-emitting chip are individually mounted on a circuit board. The signal generating circuit transmits a light-emitting signal to the light-emitting chip via wiring on the printed circuit board, causing the light-emitting element of the light-emitting chip to emit light. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-183436 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention aims to improve the structure of the light emitting chip and the driving circuit disclosed in Patent Document 1. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, the present invention has the following configuration. (1) An image forming apparatus comprising: a photosensitive member that is driven to rotate about a rotation axis; a light-emitting device; a circuit board on which the light-emitting device is mounted; an exposure head including a lens array that guides light emitted from the light-emitting device to the surface of the photosensitive member; and a controller that outputs image data for driving the light-emitting device to the circuit board; wherein the light-emitting device includes a silicon wafer including a drive circuit that drives the light-emitting device; a first electrode layer that is arranged in a direction approximately parallel to the rotation axis of the photosensitive member and includes a plurality of electrodes; a second electrode layer that is light-transmitting and has a layered structure; and a light-emitting layer that is formed in a layered structure between the first electrode layer and the second electrode layer and emits light when a voltage is applied thereto; and wherein the drive circuit includes a voltage generation circuit that generates a drive voltage; and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on the image data; and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the plurality of electrodes. (2) A light-emitting device comprising: a silicon wafer including a circuit; a first electrode layer including a plurality of electrodes; a layered second electrode layer that is light-transmitting; and a light-emitting layer formed in a layered state between the first electrode layer and the second electrode layer and that emits light when a voltage is applied thereto; and a layered body formed on the surface of the silicon wafer; wherein the drive circuit includes a voltage generation circuit that generates a drive voltage; and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on drive data; and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the plurality of electrodes. [Effects of the Invention]

[0007] It is possible to provide a light emitting device that causes a layered body including a light emitting layer formed on the surface of a silicon wafer to emit light by a drive circuit provided on the silicon wafer, and an image forming apparatus using the same. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of an image forming apparatus; [Figure 2] A diagram showing the configuration of an exposure head [Figure 3] Diagram showing the structure of a printed circuit board [Figure 4] Diagram showing the structure of a silicon substrate [Figure 5] Cross-sectional view of a light-emitting region and a configuration diagram of a light-emitting device [Figure 6] Image controller and printed circuit board block diagram [Figure 7] Circuit diagram inside the light-emitting device [Figure 8] 10A and 10B are diagrams showing waveforms of each signal and shifts in image data; [Figure 9] An explanatory diagram of a pulse signal generating unit and a diagram showing the waveforms of each signal. [Figure 10] Circuit diagram inside the light-emitting device [Figure 11] Analog block diagram, drive circuit diagram [Figure 12] An explanatory diagram of a pulse signal generating unit and a diagram showing the waveforms of each signal. [Figure 13] A diagram showing a printed circuit board and an explanatory diagram of the correction amount p [Figure 14] A diagram showing the position of the lower electrode in the short-side direction and a diagram showing the waveforms of each signal [Figure 15] FIG. 10 is a diagram showing a modified example of a printed circuit board. [Figure 16] 1 is a cross-sectional view of a light-emitting region as a modified example, and a configuration diagram of a light-emitting device; [Figure 17] Conceptual diagram of multiple exposure [Figure 18] FIG. 10 is a diagram showing a modified example of a circuit in a light-emitting device. [Figure 19] 1 is a diagram showing waveforms of signals and image data in multiple exposure; [Figure 20] FIG. 10 is a diagram showing a modified example of a circuit in a light-emitting device for switching the light-emitting order. [Figure 21] Timing chart for explaining chip select signals [Figure 22] Block diagram showing a modified example of the image controller unit and the printed circuit board [Figure 23] Timing chart for explaining a modified chip select signal DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. [Example]

[0010] [Configuration of image forming device] Fig. 1 is a schematic cross-sectional view showing the configuration of an electrophotographic image forming apparatus in Example 1. The image forming apparatus shown in Fig. 1 is a multifunction peripheral (MFP) equipped with a scanner function and a printer function, and is composed of a scanner unit 100, an image creating unit 103, a fixing unit 104, a paper feed / transport unit 105, and a printer control unit (not shown) that controls these. The scanner unit 100 illuminates a document placed on a document table to optically read the document image, and converts the read image into an electrical signal to create image data.

[0011] The imaging unit 103 includes four image forming stations arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K) along the rotational direction (counterclockwise) of an endless conveyor belt 111. The four image forming stations have the same configuration, and each image forming station includes a photosensitive drum 102, which is a photosensitive member that rotates in the direction of the arrow (clockwise), an exposure head 106, a charger 107, and a developing unit 108. The suffixes a, b, c, and d of the photosensitive drum 102, exposure head 106, charger 107, and developing unit 108 indicate that the configuration corresponds to the image forming station (black (K), yellow (Y), magenta (M), and cyan (C), respectively. In the following, the suffixes of the reference numerals will be omitted except when referring to a specific photosensitive drum, etc.

[0012] In the image forming unit 103, the photosensitive drum 102 is rotated and charged by a charger 107. An exposure head 106, which serves as an exposure means, causes a light-emitting device to emit light in accordance with image data, and the light generated by the light-emitting device is focused onto the photosensitive drum 102 (on the photosensitive member) by a rod lens array, forming an electrostatic latent image. A developing device 108, which serves as a development means, develops the electrostatic latent image formed on the photosensitive drum 102 with toner. The developed toner image is then transferred to a recording sheet on a conveyor belt 111 that conveys the recording sheet. This series of electrophotographic processes is performed at each image forming station. During image formation, after a predetermined time has elapsed since the start of image formation at the cyan (C) image forming station, image forming operations are performed sequentially at the magenta (M), yellow (Y), and black (K) image forming stations. This results in a full-color image being formed.

[0013] The image forming apparatus shown in FIG. 1 includes a paper feed / transport unit 105 having internal paper feed units 109a and 109b, a large-capacity external paper feed unit 109c, and a manual paper feed unit 109d as units for feeding recording paper. During image formation, recording paper is fed from a predetermined paper feed unit and transported to registration rollers 110. Registration rollers 110 transport the recording paper to a transport belt 111 at the timing when the toner image formed in the image forming unit 103 is transferred to the recording paper. Toner images formed on the photosensitive drums 102 of each image forming station are sequentially transferred onto the recording paper transported by the transport belt 111. The recording paper with the unfixed toner image transferred is transported to a fixing unit 104. Fixing unit 104 has a built-in heat source such as a halogen heater, and fixes the toner image on the recording paper to the recording paper by applying heat and pressure with two rollers. The recording paper on which the toner image has been fixed by the fixing unit 104 is discharged by a discharge roller 112 to the outside of the image forming apparatus.

[0014] An optical sensor 113, which serves as a detection unit, is disposed downstream of the black (K) image forming station in the recording paper transport direction, facing the transport belt 111. The optical sensor 113 detects the position of a test image formed on the transport belt 111 to derive the amount of color shift of the toner images between the image forming stations. The amount of color shift derived by the optical sensor 113 is notified to an image controller unit 700 (see FIG. 6), which will be described later, and the image position of each color is corrected so that a full-color toner image without color shift is transferred onto the recording paper. In addition, a printer control unit (not shown) executes image formation operations while controlling the scanner unit 100, image creation unit 103, fixing unit 104, paper feed / transport unit 105, etc., in accordance with instructions from an MFP control unit (not shown), which controls the entire multifunction peripheral (MFP).

[0015] Here, as an example of an electrophotographic image forming apparatus, an image forming apparatus that directly transfers a toner image formed on the photosensitive drum 102 of each image forming station onto recording paper on a conveyor belt 111 has been described. The present invention is not limited to printers that directly transfer a toner image on the photosensitive drum 102 onto recording paper. For example, the present invention can also be applied to an image forming apparatus that includes a primary transfer unit that transfers the toner image on the photosensitive drum 102 onto an intermediate transfer belt, and a secondary transfer unit that transfers the toner image on the intermediate transfer belt onto recording paper.

[0016] [Exposure head configuration] Next, the exposure head 106 that exposes the photosensitive drum 102 will be described with reference to Fig. 2. Fig. 2(a) is a perspective view showing the positional relationship between the exposure head 106 and the photosensitive drum 102, and Fig. 2(b) is a diagram illustrating the internal configuration of the exposure head 106 and how a light beam from the exposure head 106 is focused onto the photosensitive drum 102 by a rod lens array 203. As shown in Fig. 2(a), the exposure head 106 is attached to the image forming apparatus by an attachment member (not shown) at a position above the photosensitive drum 102, which rotates in the direction of the arrow, facing the photosensitive drum 102 (Fig. 1).

[0017] As shown in FIG. 2(b), the exposure head 106 is composed of a printed circuit board 202, a light-emitting device group 400 mounted on the printed circuit board 202, a rod lens array 203, and a housing 204. The rod lens array 203 and printed circuit board 202 are attached to the housing 204. As shown in FIG. 2, the rod lens array 203 is disposed between the light-emitting device group 400 and the photosensitive drum 102. The rod lens array 203 is disposed along the longitudinal direction of the printed circuit board 202 and focuses the light beams emitted by the light-emitting device group 400 onto the photosensitive drum 102. In the factory, the exposure head 106 is assembled and adjusted individually, and focus and light intensity adjustments are performed. Here, assembly adjustments are performed so that the distance between the photosensitive drum 102 and the rod lens array 203, and the distance between the rod lens array 203 and the light-emitting device group 400 are predetermined intervals. As a result, light from the light-emitting device group 400 is imaged on the photosensitive drum 102. Therefore, when adjusting the focus at the factory, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting device group 400 is a predetermined value. Also, when adjusting the light intensity at the factory, the lower electrode of the light emitting device 401 (described later) is driven, and a voltage (described later) applied to the light emitting device 401 is adjusted so that the light condensed on the photosensitive drum 102 via the rod lens array 203 has a predetermined light intensity.

[0018] [Configuration of light-emitting devices] 3A and 3B are diagrams illustrating a printed circuit board 202 and a light emitting device group 400 mounted on the printed circuit board 202. Fig. 3A is a schematic diagram showing the configuration of the surface of the printed circuit board 202 on which the light emitting device group 400 is mounted, and Fig. 3B is a schematic diagram showing the configuration of the surface (second surface) opposite to the surface (first surface) on which the light emitting device group 400 of the printed circuit board 202 is mounted.

[0019] As shown in FIG. 3A, the light-emitting device group 400 mounted on the printed circuit board 202, which is the second substrate, has a configuration in which 20 light-emitting devices 401-1 to 401-20, which are independent chips, are arranged in two staggered rows along the longitudinal direction of the printed circuit board 202. That is, on the printed circuit board 202 (second substrate), odd-numbered light-emitting devices 401-1... (401-2n+1: n ≥ 0) and even-numbered light-emitting devices 401-2... (401-2n: n ≥ 1) are arranged at different positions in the rotation direction of the photosensitive drum 102. The light-emitting devices 401-1 to 401-20 are sometimes collectively referred to as light-emitting devices 401. Note that in FIG. 3A, the up-down direction indicates the rotation direction of the photosensitive drum 102, which is a first direction, and the horizontal direction indicates the longitudinal direction, which is a second direction perpendicular to the first direction. The longitudinal direction is also a cross direction that intersects with the rotation direction of the photosensitive drum 102. Each light-emitting device 401 has a total of 748 lower electrodes (described later). In this embodiment, the lower electrodes are arranged at intervals of 21.16 μm (≒ 2.54 cm / 1200 dots). As a result, the arrangement distance from end to end of the 748 lower electrodes in one light-emitting device 401 is approximately 15.8 mm (≒ 21.16 μm × 748). The light-emitting device group 400 is composed of 20 light-emitting devices 401. The number of lower electrodes that can be exposed in the light-emitting device group 400 is 14,960 (= 748 electrodes × 20 chips), and the light-emitting device group 400 can expose an image width in the longitudinal direction of approximately 316 mm (≒ approximately 15.8 mm × 20 chips).

[0020] 3(b), a connector 305 is mounted on the surface of the printed circuit board 202 opposite to the surface on which the light emitting device group 400 is mounted. The connector 305 is a connector for connecting a control signal and a power supply line that controls the light emitting device group 400 from an image controller unit 700 (see FIG. 6), which will be described later, and the light emitting devices 401-1 to 401-20 are driven via the connector 305.

[0021] 3(c) is a diagram showing the boundary between chips of light emitting devices 401 arranged in two rows in the longitudinal direction, with the horizontal direction being the longitudinal direction of the light emitting device group 400 in FIG. 3(a), and multiple light emitting devices 401 arranged. FIG. 3(c) shows the boundary between chips of light emitting device 401 (the portion where the ends of chips overlap in the longitudinal direction (overlapping portion)). Even at the boundary between light emitting device 401-n and light emitting device 401-n+1, ​​the pitch of the lower electrodes at the ends between different light emitting devices 401 (the distance (L) between the center points of two lower electrodes) is approximately 21.16 μm, which is the pitch for a resolution of 1200 dpi.

[0022] The light emitting devices 401 are arranged in two rows, one above the other, in the short direction, and are arranged as follows: That is, the distance between the lower electrodes (shown by arrow S in the figure) of the upper and lower light emitting devices 401, which will be described later, is approximately 105 μm (a distance corresponding to five pixels at 1200 dpi, or an integer multiple of the resolution of 10 pixels at 2400 dpi). The distance between the light emitting points of the exposure head 106 in the longitudinal direction (shown by arrow L in the figure) is approximately 21.16 μm (a distance corresponding to one pixel at 1200 dpi). Note that, in the present invention, the distances S and L between the light emitting devices 401 do not have to be limited to the values ​​described above.

[0023] [Configuration of light-emitting device] FIG. 4 is a schematic diagram showing the internal configuration of a light-emitting device 401. As shown in FIG. 4, the longitudinal direction of the light-emitting device 401 is the X direction, and the lateral direction is the Y direction. The Y direction is the rotation direction of the photosensitive drum 102, or in other words, the movement direction of the photosensitive surface (photoconductor surface) of the rotating photosensitive drum 102. The X direction is a direction substantially perpendicular to the Y direction, i.e., the rotation direction of the photosensitive drum 102. It is also a direction substantially parallel to the rotation direction of the photosensitive drum 102. Note that substantially perpendicular allows a tilt of approximately ±1° relative to an angle of 90°, and substantially parallel allows a tilt of approximately ±1° relative to an angle of 0°. The light-emitting device 401 has wire bonding pads (hereinafter referred to as WB pads) 601-1, 601-2, 601-3, and 601-4 formed on a silicon substrate 402, which is a first substrate. A circuit unit 602 (indicated by a broken line), which serves as a drive unit, is built into the silicon substrate 402. An analog driving circuit, a digital control circuit, or both can be used as the circuit portion 602. Power supply to the circuit portion 602 and input / output of signals from outside the light emitting device 401 are performed via a WB pad 601.

[0024] The light-emitting device 401 of this embodiment includes a linear light-emitting region 604 extending along the rotation axis direction of the photosensitive drum 102. The light-emitting region 604 includes an anode, a cathode, and a light-emitting layer 450 (see FIG. 5 ), which will be described later, and is a region that emits light when a potential difference occurs between the anode and the cathode.

[0025] A silicon wafer is used as the silicon substrate 402. This has the following advantages. Specifically, silicon substrates have well-developed process technologies for forming integrated circuits, and are already used as substrates for various integrated circuits, so they have the advantage of being able to form high-speed, highly functional circuits at high density. In addition, large-diameter silicon substrates are commercially available, so they have the advantage of being inexpensive.

[0026] In this embodiment, the circuit unit 602 is provided with a drive circuit for driving the light-emitting region 604, including a data transfer unit for generating a signal for causing the light-emitting region 604 to emit light (hereinafter referred to as a light-emitting signal), a light-emitting signal generation unit, and a drive voltage generation circuit for generating a drive voltage to be applied to the lower electrode. The circuit unit 602 is then formed as an integrated circuit on the silicon substrate 402. The lower electrode is evaporated onto the silicon substrate 402 so as to be electrically connected. This makes it possible to increase the light-emitting cycle and reduce the number of wire bonds to the lower electrode.

[0027] [Light-emitting area configuration] The light-emitting device 401 will be described in more detail using FIG. 5. The X direction in FIG. 5 indicates the longitudinal direction of the exposure head 106. The Z direction is the direction in which each layer of the layer structure described below overlaps (stacking direction). FIG. 5(a) is an enlarged view of a main part of the schematic diagram of the AA cross section in FIG. 4. FIG. 5(a) is a schematic diagram of lower electrodes 410-1 to 410-748 described below as viewed from the Y direction. As shown in FIGS. 5(a) and 5(c), the light-emitting device 401 includes a silicon substrate 402, lower electrodes 410-1 to 410-748, a light-emitting layer 450, and an upper electrode 460. The silicon substrate 402 is a drive substrate on which drive circuits including drive units corresponding to the lower electrodes 410-1 to 410-748 described below are formed during the manufacturing process.

[0028] As shown in Figures 5(a) and 5(c), lower electrodes 410-1 to 410-748 (cathodes) are multiple electrodes formed in layers (first electrode layers) on silicon substrate 402. Each of lower electrodes 410-1 to 410-748 is formed on multiple drive units built into silicon substrate 402 using Si integrated circuit processing technology in addition to the manufacturing process for silicon substrate 402. Lower electrodes 410-1 to 410-748 are preferably made of a metal with high reflectivity at the emission wavelength of light-emitting layer 450, which will be described later. Therefore, lower electrodes 410-1 to 410-748 preferably contain silver (Ag), aluminum (Al), or an alloy thereof, a silver-magnesium alloy, or the like.

[0029] 5, lower electrodes 410-1 to 410-748 are electrodes provided corresponding to each pixel in the X direction. That is, lower electrodes 410-1 to 410-748 are electrodes provided to form one pixel each. Lower electrodes 410-1 to 410-748 form a first electrode row.

[0030] In this embodiment, the width W of the lower electrodes 410-1 to 410-748 in the X direction corresponds to the width of one pixel. The interval d is the distance between the lower electrodes in the X direction (arrangement interval). Because the lower electrodes 410-1 to 410-748 are formed on the silicon substrate 402 with the interval d between them, the multiple driving units formed on the silicon substrate 402 can individually control the voltages of the lower electrodes 410-1 to 410-748. The interval d is filled with an organic material of the light-emitting layer 450, and the lower electrodes are partitioned by the organic material.

[0031] In the light-emitting device 401 of this embodiment, the width W of the lower electrodes 410-1 to 410-748 is set to a nominal dimension of 20.90 μm, and the spacing d is set to a nominal dimension of 0.26 μm. In other words, the light-emitting device 401 of this embodiment has one lower electrode 410 every 21.16 μm in the X direction. Since 21.16 μm is the size of one pixel at 1200 dpi, the width of each lower electrode 410 in the X direction corresponds to one pixel, which corresponds to the output resolution of the image forming apparatus of this embodiment. The process rule for the light-emitting device 401 of this embodiment is highly accurate, at approximately 0.2 μm, and it is possible to form the width d with a resolution of 0.26 μm.

[0032] 5B, the width of the lower electrodes 410-1 to 410-748 in the Y direction, which is the rotation direction of the photosensitive drum 102, is also W. That is, the lower electrodes 410-1 to 410-748 in this embodiment are 20.90 μm square, and the area of ​​the lower electrode 410 is 436.81 μm 2 This means that the area of ​​one pixel is 447.7456 μm 2The organic light-emitting material emits less light than an LED. By forming the lower electrodes 410 on the silicon substrate 402 in a square shape with a small distance between adjacent lower electrodes as described above, it is possible to ensure a light-emitting area sufficient to obtain a light intensity sufficient to change the potential of the photosensitive drum 102. It is desirable to ensure a lower electrode area of ​​at least 90% of the area occupied by one pixel. Therefore, for an image forming apparatus with an output resolution of 1200 dpi, it is desirable to form the lower electrode 410 with a side width of at least approximately 20.07 μm, and for an image forming apparatus with an output resolution of 2400 dpi, it is desirable to form the lower electrode 410 with a side width of at least approximately 10.04 μm.

[0033] On the other hand, the upper limit of the area occupied by the lower electrode 410 should be set based on the transmittance of the rod lens array 203 and the upper electrode 460 (described later). In this embodiment, however, the upper limit is set to 110% of the area occupied by one pixel. If the area is designed to be larger than 110% of the area occupied by one pixel, the size of the pixel formed when the highly sensitive photosensitive drum 102 is exposed may significantly exceed the resolution. Therefore, the upper limit of the area occupied by the lower electrode 410 is set to 110%. Therefore, for an image forming apparatus with an output resolution of 1200 dpi, it is desirable to form the lower electrode 410 with a side width of approximately 22.19 μm or less. For an image forming apparatus with an output resolution of 2400 dpi, it is desirable to form the lower electrode 410 with a side width of approximately 11.10 μm or less. In other words, the range of the area occupied by the lower electrode 410 with respect to the area occupied by one pixel is preferably 90% or more and 110% or less.

[0034] The shape of the lower electrode 410 is not limited to a square, and may be a polygon with more sides than a square, a circle, an ellipse, or the like, as long as it emits light of an exposure area size corresponding to the output resolution of the image forming device and the image quality of the output image produced by that light is at a level that satisfies the design specifications of the image forming device.

[0035] Next, the light-emitting layer 450 will be described. The light-emitting layer 450 is formed by being laminated on the silicon substrate 402 on which the lower electrodes 410-1 to 410-748 are formed. That is, the light-emitting layer 450 is laminated on the lower electrodes 410-1 to 410-748 in the portions where the lower electrodes 410-1 to 410-748 are formed. The light-emitting layer 450 is laminated on the silicon substrate 402 in the portions where the lower electrodes 410-1 to 410-748 are not formed. In this example, the light-emitting layer 450 in the light-emitting device 401 is formed so as to span all of the lower electrodes 410-1 to 410-748, but the embodiment is not limited to this. For example, the light-emitting layer 450 may be formed so as to be separately laminated on each lower electrode, similar to the lower electrodes 410-1 to 410-748, or the lower electrodes 410-1 to 410-748 may be divided into a plurality of groups, and one light-emitting layer may be laminated on each lower electrode belonging to each divided group.

[0036] For example, an organic material can be used for the light-emitting layer 450. The light-emitting layer 450, which is an organic EL film, is a laminated structure including functional layers such as an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and a hole blocking layer. In addition to organic materials, an inorganic material having light-emitting properties may also be used for the light-emitting layer 450.

[0037] An upper electrode 460 (anode) is laminated (second electrode layer) on the light-emitting layer 450. The lower electrode 410, light-emitting layer 450, and upper electrode 460 form a layered body. The upper electrode 460 is an electrode that can transmit (is transmissive to) light of the wavelength emitted by the light-emitting layer 450. For this reason, a material containing indium tin oxide (ITO) is used as a transparent electrode for the upper electrode 460 in this embodiment. An indium tin oxide electrode has a transmittance of 80% or more for light in the visible light range, making it suitable as an electrode for organic EL.

[0038] The upper electrode 460 is formed on the opposite side of the lower electrodes 410-1 to 410-748, with at least the light-emitting layer 450 sandwiched between them. That is, in the Z direction, the light-emitting layer 450 is disposed between the upper electrode 460 and the lower electrodes 410-1 to 410-748, and when the lower electrodes 410-1 to 410-748 are projected onto the upper electrode 460 in the Z direction, the area where the lower electrodes 410-1 to 410-748 are formed falls within the area where the upper electrode 460 is formed. Note that the transparent electrode does not need to be stacked over the entire light-emitting layer 450. However, in order to efficiently emit light generated in the light-emitting layer 450 to the outside of the light-emitting device 401, it is preferable that the area occupied by the upper electrode 460 is 100% or more, and more preferably 120% or more, of the area occupied by one pixel. The upper limit of the area occupied by the upper electrode 460 can be arbitrarily designed depending on the areas of the silicon substrate 402 and the light-emitting layer 450. Wiring may be provided in the upper electrode 460 except for the portion through which light is transmitted.

[0039] The upper electrode 460 in this embodiment is an anode provided in common to the lower electrodes 410-1 to 410-748, but it may be provided individually for each of the lower electrodes 410-1 to 410-748, or one upper electrode may be provided for each of the lower electrodes.

[0040] The drive circuit controls the potential of each of the lower electrodes 410-1 to 410-748 based on image data to generate a potential difference between the upper electrode 460 and any one of the lower electrodes 410-1 to 410-748.

[0041] The light-emitting device 401 in this embodiment is a so-called top-emission type emission device. When a voltage is applied to the upper electrode 460, which is an anode, and the lower electrode 410, which is a cathode, a potential difference is generated between them. Electrons flow from the cathode into the light-emitting layer 450, and holes flow from the anode into the light-emitting layer 450. The electrons and holes then recombine in the light-emitting layer 450, causing the light-emitting layer 450 to emit light. When the light-emitting layer 450 emits light, light directed toward the upper electrode 460 passes through the upper electrode 460 and is emitted from the light-emitting device 401 in the direction of arrow A shown in FIG. 5 . Light directed from the light-emitting layer 450 toward the lower electrode 410 is reflected by the lower electrode 410 toward the upper electrode 460, and the reflected light also passes through the upper electrode 460 and is emitted from the light-emitting device 401. Although there is a time difference in the emission timing from the upper electrode 460 between the light emitted from the light-emitting layer 450 directly toward the upper electrode 460 and the light reflected by each lower electrode 410 and emitted from the upper electrode 460, the light can be regarded as being emitted almost simultaneously because the thickness of the layers of the light-emitting device 401 is extremely small. Note that the light-emitting device of this embodiment may be a bottom-emission type emission system.

[0042] By using a transparent electrode such as indium tin oxide as the upper electrode 460, the aperture ratio, which indicates the light transmittance of the electrode, can be made substantially equal to the transmittance of the upper electrode 460. In other words, since there is substantially no portion other than the upper electrode 460 that attenuates or blocks light, the light emitted from the light-emitting layer 450 is attenuated as little as possible or becomes emitted light without being blocked.

[0043] Furthermore, as described above, by forming the lower electrodes 410-1 to 410-748 using high-precision Si integrated circuit processing technology, the lower electrodes 410-1 to 410-748 can be arranged at high density. As a result, most of the area of ​​the light-emitting region 604 (here, the total area of ​​the lower electrodes 410-1 to 410-748 and the area of ​​the region between adjacent lower electrodes) can be allocated to the lower electrodes 410-1 to 410-748. In other words, the exposure head has a high utilization efficiency of the light-emitting region per unit area.

[0044] When light-emitting layer 450 is made of a moisture-sensitive light-emitting material such as an organic EL layer or an inorganic EL layer, it is desirable to seal light-emitting region 604 to prevent moisture from entering. For example, a sealing film is formed by forming a thin film, such as a single film or a laminated film, of silicon oxide, silicon nitride, or aluminum oxide. A method that excels in covering structures such as steps is preferred as a method for forming the sealing film, and for example, atomic layer deposition (ALD) can be used. The materials, configurations, and formation methods of the sealing film are merely examples, and are not limited to the above examples, and any suitable method may be selected as appropriate.

[0045] [Control Block] 6 shows a block diagram of the image controller unit 700 and the printed circuit board 202. Hereinafter, the chip select signal is referred to as cs_x, the line synchronization signal as lsync_x, the clock signal as clk, and the image data signal as data. In the first embodiment, to simplify the explanation, processing of a single color will be described, but it is assumed that similar processing is performed in parallel for four colors.

[0046] (Image controller) Image data generated by the scanner unit 100 is input to an image controller unit 700, which is a processor that is at least one integrated circuit (IC). The image controller unit 700 transmits control signals for controlling the printed circuit board 202 to the printed circuit board 202 via a cable such as a flexible flat cable. The image data input to the image controller unit 700 may be data generated by the scanner unit 100 as described above, or data transferred from a personal computer via a network device (not shown). The control signals include a chip select signal cs_x indicating the valid range of the image data, a clock signal clk, an image data signal data, a line synchronization signal lsync_x indicating the division of each line of image data, and a communication signal with the CPU 703. Each signal is transmitted to the light-emitting device 401 in the printed circuit board 202 via a chip select signal line 705, a clock signal line 706, an image data signal line 707, a line synchronization signal line 708, and a communication signal line 709. The image controller unit 700 processes the image data and print timing. The image data generation unit 701 performs dithering processing on image data received from the scanner unit 100 or from outside the image forming apparatus at a resolution instructed by the CPU 703 to generate image data for print output. In the first embodiment, the dithering processing is performed at a resolution of, for example, 1200 dpi.

[0047] The synchronization signal generation unit 704 generates a line synchronization signal lsync_x, which is a second signal. The CPU 703 instructs the synchronization signal generation unit 704 on the time interval of the signal period, assuming one line period for a predetermined rotation speed of the photosensitive drum 102. Here, one line period is the period during which the surface of the photosensitive drum 102 moves in the rotation direction by a pixel size of 1200 dpi (approximately 21.16 μm). For example, if printing is performed at a speed of 200 mm / s in the conveyance direction of the recording paper, the CPU 703 instructs the synchronization signal generation unit 704 on the time interval, assuming one line period of 105.8 μs (decimals to two decimal places omitted). The speed in the conveyance direction is calculated by the CPU 703 using a set value (fixed value) of the printing speed (image formation speed) set in a control unit (not shown) that controls the speed of the photosensitive drum 102. The printing speed is set, for example, depending on the type of recording paper.

[0048] The chip data conversion unit 702 divides one line of image data for each light emitting device 401 in synchronization with a line synchronization signal lsync_x generated by a synchronization signal generation unit 704. The chip data conversion unit 702 transmits the image data divided for each light emitting device 401 to the printed circuit board 202 together with a clock signal clk and a chip select signal cs_x. The clock signal clk is a signal that serves as a reference for control.

[0049] (printed circuit board) Next, the configuration of the printed circuit board 202 will be described. The head information storage unit 710 is a storage device that stores head information such as the light emission amount and mounting position information of each light-emitting device 401, and is connected to the CPU 703 via a communication signal line 709. A clock signal line 706, an image data signal line 707, a line synchronization signal line 708, and a communication signal line 709 extending from the image controller 700 branch off and are connected to each of the light-emitting devices 401. A chip select signal line 705 extending from the image controller 700 for transmitting a chip select signal is connected to the light-emitting device 401-1. The output of the light-emitting device 401-1 is connected to the input of the light-emitting device 401-2 via a signal line 711-1, and the output of the light-emitting device 401-2 is connected to the input of the light-emitting device 401-3 via a signal line 711-2. In this way, the chip select signal line 705 (or signal line 711) is connected in a so-called daisy chain (cascade connection) via each light-emitting device 401. Each light emitting device 401 controls the voltage of its lower electrode based on the set values ​​set by a chip select signal line 705, a clock signal line 706, a line synchronization signal line 708, an image data signal line 707, and a communication signal line 709. Each light emitting device 401-n also generates a chip select signal for the next (subsequent) light emitting device 401-n+1.

[0050] [Circuit configuration inside the light-emitting device] FIG. 7(a) shows a circuit block diagram within the light-emitting device 401. The circuit section 602 within the light-emitting device 401 has a digital section 800 and an analog section 806. The digital section 800 has the function of generating pulse signals for driving the lower electrodes 410-n in synchronization with a clock signal clk based on preset settings and various signals set by communication signals, and transmitting the generated pulse signals to the analog section 806 via a pulse signal line 907. Here, the various signals refer to a chip select signal cs_x, an image data signal data, and a line synchronization signal lsync_x. The digital section 800 also has the function of generating a chip select signal for the next light-emitting device 401 from the input chip select signal cs_x.

[0051] [Digital Department] The communication IF unit 801 controls the writing and reading of setting values ​​to and from the register unit 802 based on communication signals from the CPU 703. The register unit 802 stores setting values ​​(preset setting values) required for operation. These setting values ​​include exposure timing information used in the data storage unit 804, width and phase information of the pulse signal generated by the pulse signal generation unit 805, and setting information for the drive voltage set by the analog unit 806. Note that since the drive voltage can be derived from the resistance value between the lower electrode and the upper electrode and the range of this resistance value is known in advance, information on the drive current may be stored instead of setting information for the drive voltage. The register unit 802 stores at least one of these pieces of information. The chip select signal generation unit 803, which is a first generation unit, delays the input first signal, the chip select signal cs_x, generates the next chip select signal for the light-emitting device 401, and transmits it via the signal line 711. The chip select signal is an enable signal that allows the light-emitting device 401 to sample image data. The data storage unit 804 receives and stores image data output by the image controller 700 via a data signal line 707 while the input chip select signal cs_x is valid, and outputs the image data to a pulse signal generation unit 805 in synchronization with a line synchronization signal lsync_x. Details will be described later.

[0052] The pulse signal generating unit 805 generates a pulse signal based on the width information and phase information of the pulse signal set in the register unit 802 in accordance with the image data input from the data storage unit 804, and outputs the generated pulse signal to the analog unit 806. Details will be described later. The analog unit 806 generates a signal required to drive the lower electrode based on the pulse signal generated in the digital unit 800. Details will be described later.

[0053] (Image data storage section) Next, the operation of the data storage unit 804 will be described. The data storage unit 804 of the first embodiment is built into the light emitting device 401. An example will be described in which the chip select signal cs_x and the line synchronization signal lsync_x are negative logic signals, but they may also be positive logic. FIG. 7(b) is a circuit configuration diagram of the data storage unit 804. The clock gate circuit 810 outputs the logical product of the inverted signal of the chip select signal cs_x and the clock signal clk. The clock gate circuit 810 outputs the clock signal s_clk to the flip-flop circuit 811 only when the chip select signal cs_x is valid.

[0054] The flip-flop circuit 811 receives the image data signal data input to the data storage unit 804 as its original input. The flip-flop circuits 811 are connected in series in the same number as the number of lower electrodes 410 arranged in the longitudinal direction of the light-emitting device 401 (748 in the first embodiment), forming a shift register. The flip-flop circuits 811 operate in response to a clock signal s_clk sent from the clock gate circuit 810. Specifically, the highest flip-flop circuit 811 in the shift register samples the image data output by the image controller 700 in response to the clock signal s_clk, and each flip-flop circuit 811 shifts the sampled image data to the subsequent flip-flop circuit. The flip-flop circuits 811 and flip-flop circuits 812 are provided in the longitudinal direction of the lower electrodes 410 in the same number as the number of lower electrodes 410 (748 in the first embodiment).

[0055] A flip-flop circuit 812 serving as a register operates in response to the line synchronization signal lsync_x, with the output of the flip-flop circuit 811 as its input. The output of the flip-flop circuit 812 is output to the pulse signal generating unit 805 as image data buf_data_0_000 to buf_data_0_747.

[0056] FIG. 8 is a timing chart showing the operation of the data storage unit 804 in the longitudinal direction of the light emitting device 401. In FIG. 8, (i) shows the waveform of the clock signal clk, (ii) shows the waveform of the line synchronization signal lsync_x, (iii) shows the waveform of the chip select signal cs_x, and (iv) shows the image data signal data indicated by 000 to 747. Here, "000" indicates image data corresponding to, for example, the lower electrode 410-1, and "747" indicates image data corresponding to the lower electrodes 410-748. The shaded portions of the image data signal data indicate invalid data. (v) indicates image data dly_data_000 and the like that is the output of the flip-flop circuit 811, and (vi) indicates image data buf_data_0_000 and the like that is the output of the flip-flop circuit 812.

[0057] During the period from time T0 to time T1 when the chip select signal cs_x is 0 (cs_x=0 (low level)), the image data is shifted through the serially connected flip-flop circuits 811 as follows: Time T1 is the time when cs_x=0 is captured by the rising edge of the clock signal clk. That is, the image data is shifted in the following order: data → dly_data_000 → dly_data_001 → ... → dly_data_747. During the period when the chip select signal cs_x is low level (cs_x=0), the clock signal clk is input in the same number as the number of bottom electrodes 410 in the longitudinal direction of the light emitting device 401, i.e., 748. In this way, one line's worth of image data is held in dly_data_000 to dly_data_747.

[0058] After time T1, the chip select signal cs_x is 1 (cs_x=1 (high level)), so no shift operation is performed and the image data at time T1 is held. For example, the image data dly_data_000 held in the first flip-flop circuit 811 after time T1 is 747. When the line synchronization signal lsync_x becomes 0 (lsync_x=0 (low level)) at time T2, one line's worth of image data is simultaneously output to the pulse signal generation unit 805 as buf_data_0_000 to buf_data_0_747. Time T2 is the time when lsync_x=0 is captured by the rising edge of the clock signal clk. In other words, the image data dly_data_000 etc. held in the flip-flop circuit 811 is output to the pulse signal generation unit 805 via the flip-flop circuit 812 as image data buf_data_0_000 etc.

[0059] (Pulse signal generation unit) The pulse signal generating unit 805 will now be described. When the number of lower electrodes 410 is n, there are also n pulse signal generating units 805, the same number as the number of lower electrodes 410. In the first embodiment, pulse signal generating units 805-1 to 805-748 are provided for lower electrodes 410-1 to 410-748. The pulse signal generating units 805 provided for each lower electrode 410 have the same structure. Therefore, pulse signal generating unit 805-1 will be described here as an example.

[0060] 9(a) shows a block diagram of pulse signal generation unit 805-1. Pulse signal generation unit 805-1 has a pulse width selection unit 901, an output determination unit 903, and a counter unit 904. Pulse width selection unit 901 converts image data input from data storage unit 804 into a pulse width b in accordance with a pulse width table of pulse signals set by register unit 802. Table 1 shows the pulse width table, which is a conversion table used when converting image data into pulse width b.

[0061] [Table 1] Table 1 shows image data in the first column and pulse width b of the pulse signal corresponding to the image data in the second column. For example, the image data is 4 bits ([3:0]) (0 to 15).

[0062] For example, when the input of image data is 2, the pulse width selection unit 901 (pulse width determination unit) sets pulse width b to 8 based on the pulse width Table of Table 1 set by the register unit 802 and outputs it to the output determination unit 903. However, the pulse width Table shown in Table 1 is only an example, and the bit width of the image data and pulse width may be different from the example of Table 1, and the value of pulse width b may also be set arbitrarily. The pulse width Table stored in the register unit 802 may be set individually for each lower electrode 410, or may be shared.

[0063] Due to process variations and the like, the light-emitting layers 450 corresponding to the lower electrodes 410 may have different light intensities even when the pulse signal has the same pulse width. The variations in the light intensities of the light-emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748 cause unevenness in the electrostatic latent image formed on the photosensitive drum 102, resulting in unevenness in the printed image. To eliminate this unevenness in the electrostatic latent image, a pulse width table is set for each of the lower electrodes 410-1 to 410-748 according to the measured light intensities, thereby changing the pulse width of the output pulse signal so that an image with a dot width suited to the input image data is formed. By setting the pulse width table for each of the lower electrodes 410-1 to 410-748 through the above control, it is possible to correct unevenness in the printed image caused by the variations in the light intensities of the light-emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748. The light intensity of the light emitting layers 450 corresponding to the lower electrodes 410-1 to 410-748 is measured in a factory or by installing a light intensity measuring device (not shown) at a position opposite the exposure head 106.

[0064] The counter unit 904 counts the clock signal clk input from the image controller 700 via the clock signal line 706, and resets the count to 1 every period c of the line synchronization signal lsync_x (hereinafter referred to as the line synchronization signal period) (timings C-1 and C-2 in FIG. 9B). The line synchronization signal period is shown as timings C-1 and C-2 in FIG. 9B, which will be described later. The output of the counter unit 904 is represented as count, and count is input to the output determination unit 903. In the first embodiment, count is set to 1 by resetting, but it does not have to be 1. Furthermore, in the first embodiment, the counting method of the clock signal clk is up-counting, but down-counting may also be used. The counter unit 904 may be provided for each pulse signal generation unit 805 corresponding to each lower electrode 410, or may be shared.

[0065] The operation of the output determination unit 903 will be described with reference to Fig. 9(b). In Fig. 9(b), (i) shows the waveform of the clock signal clk, (ii) shows the waveform of the line synchronization signal lsync_x, (iii) shows the value of count, which is the output of the counter unit 904, and (iv) shows the waveform of the pulse signal generated by the pulse signal generation unit 805.

[0066] The output determination unit 903 generates a pulse signal according to the count input from the counter unit 904 and the pulse width b output from the pulse width selection unit 901. The output determination unit 903 sets the output pulse signal to high level when the line synchronization signal lsync_x is at low level at the rising edge of the clock signal clk (timings C-1 and C-2). The output determination unit 903 then sets the output pulse signal to low level at the rising edge of the clock signal clk when the count matches the pulse width b (timing B). This causes the output determination unit 903 to generate a pulse signal.

[0067] [Digital section modification] The clock signal clk and line synchronization signal lsync_x used in the pulse signal generation unit 805 may also be as follows. For example, they may be generated separately by the image controller unit 700 and input to the pulse signal generation unit 805 via a pulse generation clock signal line 910 and a pulse generation line synchronization signal line 912 as shown in Fig. 10. However, as shown in Fig. 7(a), by using a clock signal line 706 and a line synchronization signal line 708 to input the clock signal clk and line synchronization signal lsync_s used in the pulse signal generation unit 805, it is possible to reduce the amount of wiring on the printed circuit board 202.

[0068] [Analog section] 11(a) shows a block diagram of the analog unit 806. In the first embodiment, for the sake of simplicity, the explanation will be given by illustrating only the driver units 1001-1 and 1001-2 that drive the two lower electrodes 410-1 and 410-2 in the lower electrodes 410-1 to 410-748. However, it is assumed that similar driver units 1001-3 to 1001-748 are formed corresponding to the lower electrodes 410-3 to 410-748. Furthermore, as described above, it is the light-emitting layer 450 in the regions corresponding to the lower electrodes 410-1 and 410-2 that actually emits light when the lower electrodes 410-1 and 410-2 are driven.

[0069] Pulse signal generating units 805-1 and 805-2 generate pulse signals that control the light emission (ON) timing of lower electrodes 410-1 and 410-2. Pulse signal generating units 805-1 and 805-2 input pulse signals to driving units 1001-1 and 1001-2 via pulse signal lines 907-1 and 907-2.

[0070] A digital-to-analog converter (hereinafter referred to as DAC) 1002 supplies an analog voltage that determines the drive current to drivers 1001-1 and 1001-2 via signal line 1003 based on the data set in register unit 802. That is, digital-to-analog converter 1002 functions as a voltage generator that generates drive voltages to be applied to lower electrodes 410-3 to 410-748. A driver selector 1007 supplies a driver select signal that selects drivers 1001-1 and 1001-2 to drivers 1001-1 and 1001-2 via signal lines 1004 and 1005 based on the data set in register unit 802. The driver select signal is generated so that only the signal connected to the selected driver 1001 is at a high level. For example, when driver 1001-1 is selected, a high-level driver select signal is supplied only to signal line 1004, and a low-level driver select signal is supplied to signal lines 1005 and the like connected to other driver units 1001-2 and the like. In the first embodiment, the driver select signal is positive logic, but it may also be negative logic.

[0071] An analog voltage input via signal line 1003 is set for driver units 1001-1 and 1001-2 at the timing selected by driver unit selection unit 1007 (the timing when the driver unit select signal goes high). CPU 703 sequentially selects driver units 1001-1 and 1001-2 via register unit 802 and sets a voltage corresponding to the selected driver units 1001-1 and 1001-2. In this way, CPU 703 sets analog voltages (drive voltages) for all driver units 1001 using one DAC 1002. By the above-described operation, analog voltages and pulse signals that determine the drive current are input to driver units 1001-1 and 1001-2, and voltages are applied independently to each of lower electrodes 410-1 and 410-2 by the drive circuits described below.

[0072] (Drive unit) 11(b) shows the circuit of the driver 1001-1 that drives the lower electrode 410-1. Note that the driver 1001 for the other lower electrodes is also driven by a similar circuit. A MOS field effect transistor (hereinafter referred to as MOSFET) 1102 supplies a drive current to the lower electrode 410-1 according to the gate voltage value, and controls the current so that the drive current is turned off (light is turned off) when the gate voltage is at a low level.

[0073] A pulse signal line 907-1 is connected to the gate terminal of the MOSFET 1104, and when the pulse signal is at a high level, the voltage charged in the capacitor 1106 is transferred to the MOSFET 1102. A driver unit select signal (transmitted via a signal line 1004) sent from the driver unit selection unit 1007 is connected to the gate terminal of the MOSFET 1107. When the received driver unit select signal is at a high level, the MOSFET 1107 turns on and charges the analog voltage (transmitted via a signal line 1003) output from the DAC 1002 to the capacitor 1106. In the first embodiment, the DAC 1002 sets an analog voltage in the capacitor 1106 before image formation, and keeps the MOSFET 1107 in an off state during the image formation period, thereby maintaining the voltage level.

[0074] Through this operation, MOSFET 1102 supplies a drive current to lower electrode 410 in accordance with the set analog voltage and pulse signal. If the input capacitance of lower electrode 410-1 is large and the response speed when turned off is slow, it is possible to speed up the turn-off speed by using MOSFET 1103. A signal obtained by logically inverting a pulse signal by inverter 1105 is input to the gate terminal of MOSFET 1103. When the pulse signal is at low level, the gate terminal of MOSFET 1103 becomes high level, and the charge stored in the input capacitance of lower electrode 410-1 is forcibly discharged.

[0075] As described above, in Example 1, the light emitting region 604 and the circuit unit 602 are provided within the same silicon substrate 402. This reduces the costs associated with wire bonding and the area of ​​the wiring substrate, while providing a drive signal generation circuit for each lower electrode and enabling the pulse width of the pulse signal and the light emission timing to be controlled in minute time units.

[0076] As described above, according to the first embodiment, it is possible to reduce the cost of wire bonding and the area of ​​the wiring board. [Example]

[0077] [Pulse signal generation section] In the second embodiment, the overall configuration of the image forming apparatus, the configuration of the exposure head 106, and the configuration of the silicon substrate 402 are the same as those in the first embodiment. What differs from the first embodiment is the configuration of the pulse signal generating unit 805, so the differences in the pulse signal generating unit 805 from the first embodiment will be described below. When the number of lower electrodes 410 is n, there are also n pulse signal generating units 805, the same number as the number of lower electrodes 410, but the pulse signal generating units 805 for each lower electrode 410 have the same structure. Therefore, pulse signal generating unit 805-1 will be described here as an example.

[0078] FIG. 12(a) shows a block diagram of a pulse signal generating unit 805-1 of the second embodiment. This differs from the pulse signal generating unit 805-1 of the first embodiment shown in FIG. 9(a) in that a pulse delay time a, which is a first time transmitted from the register unit 802, is provided as an input. The counter unit 904 of the second embodiment includes a pulse delay time counter 1201 and a pulse width counter 1203. The output of the pulse delay time counter 1201 is count_a, and the output of the pulse width counter 1203 is count_b. The operations of the counter unit 904 and the output determining unit 903 will be described with reference to FIG. 12(b). Here, graphs (i), (ii), and (v) in FIG. 12(b) are similar to graphs (i), (ii), and (iv) in FIG. 9(b), and therefore will not be described here. (iii) in FIG. 12(b) shows the value of count_a, which is the output of the pulse delay time counter 1201, and (iv) shows the value of count_b, which is the output of the pulse width counter 1203.

[0079] The pulse delay time counter 1201 receives the clock signal clk and the line synchronization signal lsync_x as inputs. The pulse delay time counter 1201 counts the clock signal clk and resets the count to 1 at the timings when the line synchronization signal lsync_x is at a low level at the rising edge of the clock signal clk (timings C-1 and C-2).

[0080] The pulse width counter 1203 receives the clock signal clk, count_a, and pulse delay time a as inputs. The pulse width counter 1203 counts the clock signal clk and resets the count to 1 at the timing (timing A) when count_a coincides with the pulse delay time a at the rising edge of the clock signal clk. The counter unit 904 outputs count_a and count_b to the output determination unit 903.

[0081] The output determining unit 903 sets the pulse signal to high level at the timing (timing A) when count_a coincides with pulse delay time a at the rising edge of the clock signal clk. On the other hand, the output determining unit 903 sets the pulse signal to low level at the timing (timing B) when count_b coincides with pulse width b at the rising edge of the clock signal clk. As a result, the output determining unit 903 generates a pulse signal delayed according to the pulse delay time a.

[0082] The pulse delay time a can be changed in units of the cycle of the clock signal clk (hereinafter referred to as the clock signal cycle) by rewriting the memory of the register unit 802. In the second embodiment, the values ​​of count_a and count_b are set to 1 by resetting, but they do not have to be 1. In the second embodiment, the counting method of the clock signal clk is up-counting, but down-counting may also be used. Furthermore, although the counter unit 904 has two counters, the number of counters does not have to be two; for example, one counter may perform the operations of the pulse delay time counter 1201 and the pulse width counter 1203.

[0083] [Light emission timing control according to the position of the light emitting device] Using the configuration of Example 2, a method for controlling light emission timing according to the position of light emitting device 401 on printed circuit board 202 will be described. When light emitting devices 401-1 to 401-20 are arranged in a staggered pattern on printed circuit board 202, deviation from the original mounting position may occur due to the influence of mounting accuracy. As a result, the positions of lower electrodes 410 may differ from each other in the short direction of light emitting device 401. If the position of lower electrode 410 is misaligned, deviation occurs on the printed image, so light emission timing needs to be corrected according to the position of lower electrode 410. A method for correcting light emission timing according to the position of lower electrode 410 will be described below. Since the light emission timing correction performed for each of light emitting devices 401-1 to 401-20 is the same, light emitting device 401-1 will be used as an example for the description.

[0084] FIG. 13A shows an enlarged view of a portion of the lower electrode mounting surface of the printed circuit board 202. After the light-emitting device 401-1 is mounted on the printed circuit board 202, the following values ​​are measured. Specifically, a position y1, which is a first distance, and a position y748, which is a second distance, are measured relative to a reference position (hereinafter referred to as the reference position) of the lower electrode 410-1 at one end of the light-emitting device 401-1 and the lower electrode 410-748 at the other end. The measured positions y1 and y748 are stored as position data in the head information storage unit 710. The reference position (hereinafter referred to as the reference position) for the positions y1 and y748 is, for example, the most upstream position in the rotation direction of the photosensitive drum 102 where the lower electrode 410 is disposed when the light-emitting devices 401-1 to 401-20 are mounted. In the second embodiment, the position of the lower electrode 410-748 at the right end of the light-emitting device 401-5 in FIG. 13A is set as the reference position indicated by the dashed line.

[0085] The CPU 703 reads information on the positions y1 and y748 of the lower electrodes 410-1 and 410-748 at both ends of the light-emitting device 401-1 from the head information storage unit 710, and calculates the correction amount for each lower electrode 410. For example, the position ym, which is the third distance of the m-th lower electrode 410-m from the left end of the light-emitting device 401-1 in FIG. 13(a), can be calculated by the following formula (1). ym=y1+(m-1)(y748-y1) / 747 Formula (1)

[0086] Note that the positions y1 to y748 of all the lower electrodes 410 in the light-emitting device 401-1 relative to the reference position may be measured and stored in the head information storage unit 710 as correction amounts for each lower electrode 410. Furthermore, the measurement of the positions of both ends or all of the lower electrodes 410 of the light-emitting device 401 may be performed at a factory, or may be performed after the exposure head 106 is attached to the image forming apparatus.

[0087] The CPU 703 divides the correction amount for each lower electrode 410 into an amount for one line in the short-side direction of the light-emitting device 401 and an amount less than one line. Here, the amount for one line among the calculated correction amounts is defined as the correction amount p to be corrected by the image controller unit 700, and the amount less than one line is defined as the correction amount q to be corrected by the pulse signal generator 805. For example, a case will be described in which the CPU 703 calculates the correction amount for a certain lower electrode 410 as 110.8 μm. Here, if the resolution of the light-emitting device 401 in the short-side direction is 1200 dpi, 105.8 μm, which corresponds to five lines of the correction amount 110.8 μm, is defined as the correction amount p to be corrected by the image controller unit 700 (p=105.8 μm). In other words, the correction amount p is an integer (= 1, 2, . . . ) times (e.g., 5 times) the amount (e.g., 21.16 μm) corresponding to the first resolution (e.g., 1200 dpi). Further, 5 μm, which is an amount less than one line (an amount less than the amount corresponding to the first resolution) of the correction amount 110.8 μm, is set as the correction amount q to be corrected in the pulse signal generating unit 805 (q=5 μm).

[0088] The image controller unit 700 generates a read timing signal for image data in accordance with the correction amount p of each lower electrode 410 in the CPU 703, and outputs the signal to the chip data converter 702 via a signal line 709. The chip data converter 702 delays the image data by one line in accordance with the read timing signal and outputs the delayed image data.

[0089] The output timing control of image data according to the correction amount p performed by the image controller unit 700 will be described with reference to FIG. 13(b). The image controller unit 700 stores multiple lines of image data generated by the image data generation unit 701 in a memory unit (not shown). FIG. 13(b) is a diagram schematically showing the image data held in the memory unit. The left and right sides of FIG. 13(b) indicate the longitudinal direction of the light-emitting device 401. In FIG. 13(b), each rectangular block represents image data for each pixel stored in the memory unit, and colored blocks represent image data to be output. For example, for the second electrode from the left (lower electrode 410-2), the correction amount p is 1, one line is corrected by the image controller unit 700, and image data is output for the first colored line.

[0090] When the correction amount p of a certain lower electrode 410 in the longitudinal direction of the light emitting device 401 is n lines, the CPU 703 generates a read timing signal such that image data for the nth line in FIG. 13(b) is output delayed by n lines. The chip data conversion unit 702 reads and outputs image data (colored blocks in FIG. 13(b)) according to the read timing signal. This makes it possible to output image data for each lower electrode 410 for lines according to the correction amount p, as shown in FIG. 13(b). Note that, although the image data stored in the storage unit (not shown) is five lines (lines 0 to 4) as an example in FIG. 13(b), it is not limited to five lines. As described above, the image controller unit 700 functions as a correction unit.

[0091] The pulse signal generating unit 805 performs the correction by delaying the light emission timing according to the correction amount q of each lower electrode 410. When converting the correction amount q in the pulse signal generating unit 805 into a delay time of the light emission timing, the CPU 703 calculates the delay time using equation (2). Delay time = (correction amount q / photosensitive drum surface speed) / clock signal period Equation (2) The CPU 703 obtains the delay time for each lower electrode 410 and stores it as a pulse delay time a in the register unit 802. The pulse signal generation unit 805 generates a pulse signal with a light emission timing according to the pulse delay time a stored in the register unit 802, thereby correcting the difference (positional deviation during mounting) from the reference position for each lower electrode 410 with an accuracy of the clock signal period x the photosensitive drum surface speed.

[0092] As an example, a method for correcting the positions of lower electrodes 410-i and 410-j in a light-emitting device 401 shown in Figure 14(a) will be described. Note that the number of lower electrodes in the light-emitting device 401 is omitted in Figure 14(a). The resolution in the short direction of the light-emitting device 401 is 1200 dpi (approximately 21.16 μm), and the surface speed of the photosensitive drum 102 is 200 mm / s. Furthermore, the line synchronization signal period is c, the clock signal frequency is 40 MHz, and the pulse width of the pulse signal corresponding to any of the lower electrodes 410 is b.

[0093] (Lower electrode 410-i) The position yi of the lower electrode 410-i relative to the reference position is assumed to be 4 μm. In this case, the correction amount q in the pulse signal generating unit 805-i is 4 μm, and the pulse delay time a is calculated to be 800 clk from equation (2). The pulse signal generating unit 805-i generates a pulse signal represented by the timing chart in FIG. 14(b). Here, (i) to (v) in FIG. 14(b) are the same as (i) to (v) in FIG. 12(b), and therefore their explanation will be omitted.

[0094] (Lower electrode 410-j) Similarly, the position yj of the lower electrode 410-j relative to the reference position is assumed to be 23.16 μm. The correction amount 23.16 μm is divided into a correction amount p (one line) and a correction amount q (= 2 μm = 23.16 μm - 21.16 μm). If the pulse signal generation unit 805 were to perform a light emission timing correction equivalent to 23.16 μm, the pulse delay time a would be greater than the line synchronization signal period, and the correct pulse signal would not be output. Therefore, the correction amount p for one line in the short direction of the light-emitting device 401, which is 21.16 μm for one line, is corrected by the image controller unit 700. As a result, the correction amount q in the pulse signal generation unit 805 becomes 2 μm, and the pulse delay time a is calculated to be 400 clk using equation (2). The pulse signal generation unit 805-j generates a pulse signal represented by the timing chart in FIG. 14(c). Here, (i) to (v) in FIG. 14(c) are the same as (i) to (v) in FIG. 12(b), and the description thereof will be omitted.

[0095] Note that measurements, calculations, and corrections may be performed not only on the mounting positions of the light-emitting devices 401-1 to 401-20 but also on the mounting position of the exposure head 106. Furthermore, the measurements and calculations may be performed at a factory or within the image forming apparatus. The control of the corrections for each lower electrode 410 may be performed for each lower electrode 410, or may be performed for a group of several lower electrodes 410. Furthermore, variations in the amount of light emitted by the light-emitting layers 450 corresponding to each lower electrode 410 may be corrected using a pulse signal (light-emitting timing signal) generated by the pulse signal generation unit 805. As described above, the image controller unit 700 performs corrections in line units according to the position of each lower electrode 410, and the pulse signal generation unit 805 performs corrections in units of less than one line. This allows for correction of misalignment of the printed image due to the position of each lower electrode 410 with an accuracy of the clock signal period x the photosensitive drum surface speed.

[0096] As described above, according to the second embodiment, it is possible to reduce the cost for wire bonding and the area of ​​the wiring board. [Example]

[0097] Example 3 differs from Example 1 in the configuration of the exposure head 106 and the configuration of the silicon substrate 1502. In particular, Example 3 differs from Example 1 in the arrangement of the lower electrodes, and the configuration of the drive circuit provided on the silicon substrate of the lower electrodes is partially different from Examples 1 and 2. Below, the example will be described focusing on the differences from Examples 1 and 2.

[0098] [Configuration of light-emitting devices] 15 is a diagram showing the boundary between chips of light-emitting devices 1501 arranged in two rows in the longitudinal direction, and the arrangement of electrodes. Each light-emitting device 1501 of this example has two rows of lower electrodes arranged along the longitudinal direction. The distance between adjacent lower electrodes is the same as in Example 1.

[0099] [Light-emitting area configuration] The light-emitting device 1501 will be described in more detail using FIG. 16. The X direction in FIG. 16 indicates the longitudinal direction of the exposure head 106. The Z direction is the direction in which each layer of the layer structure described below overlaps (the stacking direction). FIG. 16(a) is an enlarged view of a main part of the schematic diagram of the AA cross section in FIG. 4. FIG. 16(a) is a schematic diagram of lower electrodes 410-1 to 410-748 described below as viewed from the Y direction. As shown in FIGS. 16(a) and 16(c), the light-emitting device 1501 includes a silicon substrate 1502, lower electrodes 410-1 to 410-748, lower electrodes 420-1 to 420-748, a light-emitting layer 450, and an upper electrode 460. The silicon substrate 1502 is a drive substrate on which drive circuits including drive units corresponding to the lower electrodes 410-1 to 410-748 described below are formed during the manufacturing process.

[0100] The lower electrodes 410-1 to 410-748 (cathodes) shown in FIGS. 16(a) and 16(c) correspond to the lower electrodes shown in FIG. 5, and therefore a description thereof will be omitted.

[0101] 16, light emitting device 1501 of this embodiment includes lower electrodes 420-1 to 420-748 in addition to lower electrodes 410-1 to 410-748. Like lower electrodes 410-1 to 410-748, lower electrodes 420-1 to 420-748 are multiple electrodes formed in layers (first electrode layers) on silicon substrate 1502. Lower electrodes 420-1 to 420-748 form a second electrode row. In other words, light emitting device 1501 includes lower electrodes that are two-dimensionally arranged. The size, shape, and arrangement in the X direction of lower electrodes 420-1 to 420-748 are the same as those of lower electrodes 410-1 to 410-748, so a description thereof will be omitted.

[0102] Lower electrodes 420-1 to 420-748 (second electrode row) are arranged at a distance d from lower electrodes 410-1 to 410-748 (first electrode row) in the Y direction. Lower electrode 420-1 is arranged adjacent to lower electrode 410-1 in the Y direction, and similarly, lower electrodes 420-2 to 420-748 are arranged adjacent to lower electrodes 410-2 to 410-748, respectively. Note that, as in this embodiment, it is not necessary to design the distance between lower electrodes in the X direction and the distance between lower electrodes in the Y direction to be equal, but it is desirable to design the distance between lower electrodes in both directions to be equal in order to efficiently arrange the lower electrodes within a specified area. Furthermore, in this embodiment, a light-emitting device including two electrode rows is illustrated as an example for ease of explanation, but as shown in FIG. 16(d), the number of electrode rows may be any number of rows, such as three or more. For example, similarly to the above, lower electrodes 430-1 to 430-748 may be arranged adjacent to lower electrodes 420-1 to 420-748, respectively, and further lower electrodes 440-1 to 440-748 may be arranged adjacent to lower electrodes 430-1 to 430-748. For ease of explanation, the following description will be given taking light emitting device 1501 having lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 as an example.

[0103] When the lower electrode 410-1 and the lower electrode 420-1 are driven simultaneously, the distance between the central positions exposed by driving the two electrodes on the photosensitive drum 102 is shifted by W+d in the rotation direction of the photosensitive drum 102. The image forming apparatus of this embodiment exposes an area corresponding to one pixel in the output resolution of the image forming apparatus by driving multiple lower electrodes (for example, the lower electrode 410-1 and the lower electrode 420-1) that are adjacent in the rotation direction of the photosensitive drum 102. Therefore, by providing a time difference between the timing of applying a voltage to the lower electrode 410-1 and the timing of applying a voltage to the lower electrode 420-1 in accordance with the rotation speed of the photosensitive drum 102, it is possible to expose an area corresponding to one pixel multiple times (multiple exposure).

[0104] Next, light-emitting layer 450 in this example will be described. Light-emitting layer 450 is formed by being laminated on silicon substrate 1502 on which lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 have been formed. That is, light-emitting layer 450 is laminated on lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 in the portions where lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 have been formed. Light-emitting layer 450 is laminated on silicon substrate 1502 in the portions where lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 have not been formed. In this example, light-emitting layer 450 is formed across all of lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 in light-emitting device 1501, but the embodiment is not limited to this. For example, light-emitting layer 450 may be formed so as to be separately laminated on each lower electrode, similar to lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748, or lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 may be divided into a plurality of groups, and one light-emitting layer may be laminated on each lower electrode belonging to that group.

[0105] [Exposure area shape for multiple exposures] FIG. 17 shows the positional relationship of exposure areas (spots) during multiple exposure. FIG. 17 shows the exposure areas on the exposure head 106 that are exposed by driving a lower electrode 410-n (n is a natural number satisfying 1≦n≦748) and a lower electrode 420-n adjacent to it in the Y direction. That is, FIG. 17 shows the exposure areas of two lower electrodes 410-n and 420-n aligned in the Y direction for the nth lower electrode among the 748 lower electrodes arranged in the X direction. When voltages are applied to the lower electrodes 410-n and 420-n in the Y direction of the silicon substrate 1502 substantially simultaneously to cause the light-emitting layer 450 to emit light, the exposure areas corresponding to the lower electrodes 410-n and 420-n are positioned at different positions in the Y direction, as shown in FIG. 17(a). The positions of the exposure areas are similar to the positional relationship between the lower electrodes 410-n and 420-n in the Y direction. That is, the center-to-center distance between the exposure areas in the Y direction is W (μm)+d (μm).

[0106] 17(b) shows the state of the exposure area when the timing of applying electric charge to the lower electrode 420-n arranged so as to expose the downstream side of the lower electrode 410-n in the rotation direction of the photosensitive drum 102 (hereinafter referred to as lighting timing) is delayed according to equation (3) in accordance with the rotation direction and rotation speed Vdr (mm / s) of the photosensitive drum 102. The timing T at which the positions of the exposure areas formed on the photosensitive drum 102 coincide is controlled based on the delay time Tdelay calculated by equation (3). Tdelay = ((W + d) ÷ 1000) ÷ Vdr Equation (3) In this embodiment, the light emission signal is generated so that the maximum value Tw of the light emission time of each lower electrode corresponding to each pixel is equal to the time corresponding to the interval of one line in the Y direction, and is expressed by equation (4) using the resolution (e.g., 1200 dpi) and the rotation speed Vdr. Tw=(25.4÷1200)÷Vdr Formula (4) Multiple exposure enables exposure at approximately the same position on the photosensitive drum 102 using the lower electrode 410-n and the lower electrode 420-n, and the amount of light received by the photosensitive drum 102 can be increased in proportion to the number of lower electrodes arranged in the Y direction. Note that, in order to maintain this effect, it is preferable that the positional deviation of the exposure areas on the photosensitive drum 102 of the lower electrodes that are multiple exposed is small.

[0107] FIG. 17(c) shows an example in which the positions of the exposure areas on the photosensitive drum 102 are misaligned in multiple exposure. In this example, the two exposure areas resulting from multiple exposure do not completely overlap, but do partially overlap. Ideally, it is preferable for the two exposure areas to approximately coincide (completely overlap) as in FIG. 17(b), as this results in sharply formed dots. However, even when the exposure areas partially overlap as in FIG. 17(c), the required density can be obtained, although the sharpness of the dots is degraded compared to FIG. 17(b).

[0108] Therefore, even if there are variations in control, the time Tdelay is controlled so that the light emission timing is within the allowable error ΔT of the light emission timing so that it falls within the range of equation (5) for the size Ws (μm) of the exposure area. ΔT=(Ws÷1000)÷Vdr Formula (5)

[0109] [Control Block] The image controller unit 700 and the printed circuit board 202 will now be described. Hereinafter, the chip select signal will be referred to as cs_x, the line synchronization signal as lsync_x, the clock signal as clk, and the image data signal as data. In this embodiment, to simplify the explanation, monochromatic processing will be described, but similar processing will be performed in parallel for four colors.

[0110] [Circuit configuration inside the light-emitting device] The circuit block diagram within the light-emitting device 1501 is similar to that shown in FIG. 7(a), and therefore FIG. 7(a) is used for the purpose. The circuit unit 602 within the light-emitting device 1501 includes a digital unit 800 and an analog unit 806. The digital unit 800 synchronizes with a clock signal clk to generate pulse signals for driving the lower electrodes 410-n and 420-n based on preset values ​​and various signals transmitted via communication signals, and transmits the generated pulse signals to the analog unit 806 via a pulse signal line 907. The various signals referred to here include a chip select signal cs_x, an image data signal data, and a line synchronization signal lsync_x. The digital unit 800 also generates a chip select signal for the next light-emitting device 1501 from the input chip select signal cs_x.

[0111] [Digital Department] The communication IF unit 801 controls the writing and reading of setting values ​​to and from the register unit 802 based on communication signals from the CPU 703. The register unit 802 stores setting values ​​(preset setting values) required for operation. These setting values ​​include exposure timing information used in the data storage unit 804, width and phase information of the pulse signal generated by the pulse signal generation unit 805, and setting information of the drive voltage set by the analog unit 806. Note that since the drive voltage can be derived from the resistance value between the lower electrode and the upper electrode and the range of this resistance value is known in advance, information on the drive current may be stored instead of setting information of the drive voltage. The register unit 802 stores at least one of these pieces of information. The chip select signal generation unit 803, which is a second generation unit, delays the input chip select signal cs_x, which is the first signal, and generates a chip select signal for the next light-emitting device 1501 and transmits it via the signal line 711. The data storage unit 804 receives and stores image data output by the image controller 700 via a data signal line 707 while the input chip select signal cs_x is valid, and outputs the image data to a pulse signal generation unit 805 in synchronization with a line synchronization signal lsync_x. Details will be described later.

[0112] The pulse signal generating unit 805 generates a pulse signal based on the width information and phase information of the pulse signal set in the register unit 802 in accordance with the image data input from the data storage unit 804, and outputs the generated pulse signal to the analog unit 806. Details will be described later. The analog unit 806 generates a signal required to drive the lower electrode based on the pulse signal generated in the digital unit 800. Details will be described later.

[0113] (Data storage unit) Next, the operation of the data storage unit 804 will be described. The data storage unit 804 of the third embodiment is built into the light emitting device 1501. An example will be described in which the chip select signal cs_x and the line synchronization signal lsync_x are negative logic signals, but they may also be positive logic. FIG. 18 is a circuit configuration diagram of the data storage unit 804. The clock gate circuit 810 outputs the logical product of the inverted signal of the chip select signal cs_x and the clock signal clk. The clock gate circuit 810 outputs the clock signal s_clk to the flip-flop circuit 811 only when the chip select signal cs_x is valid.

[0114] The flip-flop circuit 811 receives as its original input the image data signal DATA input to the data storage unit 804. The flip-flop circuits 811 are connected in series in the same number (748 in this embodiment) as the number of bottom electrodes 410, 420 provided in the longitudinal direction of the light emitting device 1501. The flip-flop circuits 811 operate in response to the clock signal s_clk sent from the clock gate circuit 810. The output of the flip-flop circuit 811 is output as image data dly_data_000 to dly_data_747 to the next flip-flop circuit 811 and flip-flop circuit 812 connected adjacently. The flip-flop circuits 811 and flip-flop circuits 812 are provided in the longitudinal direction of the bottom electrodes 410, 420 in the same number as the number of bottom electrodes (748 in this embodiment).

[0115] The flip-flop circuit 812 receives the output of the flip-flop circuit 811 as input and operates in response to the line synchronization signal lsync_x. The output of the flip-flop circuit 812 is output as image data buf_data_0_000 to buf_data_0_747 to the pulse signal generating units 805 (805-1, 805-3, 805-5, etc.) and the flip-flop circuit 813. Each flip-flop circuit 812 functions as a memory circuit, and the flip-flop circuit 812 provided for one lower electrode column (lower electrodes 410-1 to 410-748) functions as a memory circuit group (or a first memory circuit group). The pulse signal generating units 805-1, 805-3, 805-5, etc. function as a first pulse signal generating unit group that generates a first pulse signal. Pulse signal generating unit 805-1 generates a pulse signal for driving lower electrode 410-1, pulse signal generating unit 805-3 generates a pulse signal for driving lower electrode 410-2, and pulse signal generating unit 805-5 generates a pulse signal for driving lower electrode 410-3.

[0116] The flip-flop circuit 813 receives the output of the flip-flop circuit 812 as input and operates in response to the multiple exposure timing signal lshift_0. The output of the flip-flop circuit 813 is output as image data buf_data_1_000 to buf_data_1_747 to the pulse signal generating units 805 (805-2, 805-4, 805-6, etc.). Each flip-flop circuit 813 functions as a memory circuit, and the flip-flop circuit 813 provided for one lower electrode row (420-1 to 420-748) functions as a memory circuit group (or a second memory circuit group). The pulse signal generating units 805-2, 805-4, 805-6, etc. function as a second pulse signal generating unit group that generates a second pulse signal. Pulse signal generating unit 805-2 generates a pulse signal for driving lower electrode 420-1, pulse signal generating unit 805-4 generates a pulse signal for driving lower electrode 420-2, and pulse signal generating unit 805-6 generates a pulse signal for driving lower electrode 420-3.

[0117] That is, the flip-flop circuit 811, the flip-flop circuit 812, and the flip-flop circuit 813 function as a memory that temporarily stores drive data for controlling the voltage applied to the lower electrode.

[0118] The multiplex timing signal generator 814, which is a first generator, generates a multiple exposure timing signal lshift_0, which is a timing signal, based on the line synchronization signal lsync_x, the clock signal clk, and the multiplex timing setting signal lshift_start. That is, the multiplex timing signal generator 814 generates the multiple exposure timing signal lshif_0 to generate pulse signals for the pulse signal generators 805-2, 805-4, ... at timings different from those of the pulse signal generators 805-1, 805-3, .... In this embodiment, the multiplex timing signal generator 814 delays the line synchronization signal lsync_x by a setting value set in the multiplex timing setting signal lshift_start to generate the multiple exposure timing signal lshift_0. For example, when the multiplex timing setting signal lshift_start is set to 1 (lshift_start=1), the multiple exposure timing signal lshift_0 is a signal obtained by delaying the line synchronization signal lsync_x by one cycle of the clock signal clk. The multiple timing signal generation unit 814 generates the multiple exposure timing signal lshift_0 based on the rotation speed of the photosensitive drum 102. That is, the multiple timing setting signal lshift_start is set based on the delay time Tdelay calculated by the above-mentioned equation (3).

[0119] Fig. 19 is a timing chart showing the operation of the data storage unit 804 in the Y direction. Fig. 19 shows, in (i), the waveform of the line synchronization signal lsync_x, and in (ii) the image data buf_data_0_000 and the like that are output from the flip-flop circuit 812. Fig. 19 shows, in (iii) the waveform of the multiple exposure timing signal lshift_0, and in (iv) the image data buf_data_1_000 and the like that are output from the flip-flop circuit 813. Fig. 19 will representatively explain the image data buf_data_0_000 that are output from the flip-flop circuit 812 and the image data buf_data_1_000 that are output from the flip-flop circuit 813, which are located at the leftmost end of Fig. 18. The same applies to all of the image data buf_data_0_001 to buf_data_0_747 and buf_data_1_001 to buf_data_1_747.

[0120] As described in FIG. 8, image data dly_data_000 is input to the flip-flop circuit 812 at time T10 in FIG. 19, which is the timing when the line synchronization signal lsync_x becomes 0 at time T0 in FIG. 8. Then, the value of the image data dly_data_000 is output from the flip-flop circuit 812 as image data buf_data_0_000. At time T11, the multiple exposure timing signal lshift_0 is input as a low level (lshift_0=0) to the flip-flop circuit 813. Then, the value of the image data buf_data_0_000 output from the flip-flop circuit 812 is output from the flip-flop circuit 813 to the pulse signal generation unit 805 as image data buf_data_1_000. In this way, the data output to the pulse signal generation unit 805 as buf_data_0_000 when lsync_x=0 is output again to the pulse signal generation unit 805 as buf_data_1_000 at the next timing when lshift_0=0. Here, time T11 when the multiple exposure timing signal lshift_0 becomes low level is delayed by the multiple timing setting signal lshift_start from time T10 when the line synchronization signal lsync_x becomes low level. The image data buf_data_0_000 is output to the pulse signal generation unit 805 corresponding to the lower electrode used for the earlier exposure in the Y direction on the photosensitive drum 102. Also, the image data buf_data_1_000 is output to the pulse signal generation unit 805 corresponding to the lower electrode used for the later exposure in the Y direction on the photosensitive drum 102. In this way, multiple exposure is realized.

[0121] In this embodiment, multiple exposure is performed using two lower electrodes 410-n and 420-n arranged in the Y direction. However, the number of lower electrodes used for multiple exposure is not limited to two. To increase the number of lower electrodes used for multiple exposure (for multiple exposure of m=3 or more columns), the flip-flop circuits 812 (748) and 813 (748) shown in FIG. 18 can be increased to m columns (m×748). This allows image data corresponding to m columns (m×748) of lower electrodes to be held. Furthermore, by increasing the number of pulse signal generators 805 connected to the m columns of flip-flop circuits to m columns (m×748), the light emission timing of each of the m columns (m×748) of lower electrodes can be controlled, enabling multiple exposure of m columns.

[0122] In this embodiment, a flip-flop circuit has been used as an example of a means for retaining image data for each lower electrode. In this configuration, flip-flop circuits are arranged parallel to lower electrodes 410-1 to 410-748, resulting in a simpler circuit with a smaller wiring area. On the other hand, even if flip-flop circuits are not used, the following configuration can be adopted. That is, as long as there is a memory circuit (e.g., RAM) corresponding to the lower electrode and a control unit that controls the read timing and write timing to the memory circuit, it is not necessary to use a flip-flop circuit.

[0123] Increasing the number of lower electrodes used for multiple exposure and making the number of lower electrode rows selectable for multiple exposure enables more dynamic control of light intensity. For example, in a configuration where the number of lower electrode rows, m, is 10 and the lower electrodes are arranged in the Y direction, it is possible to select from 2 to 10 lower electrode rows for multiple exposure depending on the image formation speed of the image forming apparatus. This allows for nine levels of light output change. Therefore, the control range of the drive current for each lower electrode can be narrowed, making it possible to always drive the lower electrodes under approximately the same drive current conditions. For example, when driving the lower electrodes with a low current (i.e., low light intensity), the response of the lower electrodes may be slow, making it impossible to obtain the desired light intensity. In such cases, the multiple exposure of this embodiment enables stable drive of the lower electrodes. In this way, when selecting which of multiple rows of lower electrodes to use, a reset terminal may be added to flip-flop circuits 812, 813, etc., to selectively stop the output of image data. In addition to this method, a means for stopping the output of the pulse signal may be added to the pulse signal generating section 805.

[0124] As for the analog section 806 shown in FIG. 7(a), the configuration of the analog section for each lower electrode is the same as that shown in FIG. 11(b) of the first embodiment, and therefore the description thereof will be omitted.

[0125] [Switching the drive direction of the bottom electrode (for staggered arrangement)] As described above, this embodiment illustrates a configuration in which the light-emitting devices 1501 are arranged in a staggered pattern (hereinafter referred to as a staggered arrangement) on the printed circuit board 202. When the light-emitting devices 1501 are arranged in a staggered pattern, good imaging characteristics can be obtained by arranging the lower electrodes close to the center of the lenses in the short-side direction of the rod lens array 203. When an inexpensive rod lens array is used, there is a limit to the aperture of the rod lens. Therefore, if the lower electrodes are arranged too far from the center of the rod lens, light may not reach the aperture of the rod lens, and light may not be able to be emitted onto the photosensitive drum 102. For this reason, it is effective to arrange the lower electrode rows closer to one side of the center of the light-emitting device 1501 in the short-side direction, and to arrange each lower electrode row as close as possible to the center of the rod lens.

[0126] In FIG. 15, the center of the rod lens array 203 in the lateral direction is indicated by a dashed line as L_center. The rod lens array 203 and the light emitting devices 1501 are mounted so that the center line (hereinafter referred to as the center line) L_center of the rod lens array 203 in the lateral direction coincides with the center of the two light emitting devices 1501 arranged in a staggered pattern. The lower electrodes of each light emitting device 1501 are arranged closer to the center line L_center than the center of the light emitting device 1501. Here, in the light emitting device 1501A (one of the first substrates), the surface farther from the light emitting device 1501B is referred to as end face 311, and the surface closer to the light emitting device 1501B is referred to as end face 310. In addition, in the light emitting device 1501B (the other first substrate), the surface farther from the light emitting device 1501A is referred to as end face 311, and the surface closer to the light emitting device 1501B is referred to as end face 310. In each of the light emitting devices 1501, the lower electrodes 410 and 420 are disposed closer to the end face 310 side.

[0127] By arranging the lower electrodes 410 and 420 in this manner, light from each of the lower electrodes is incident on the opening of the rod lens array 203. In this embodiment, the lower electrodes in the light emitting device 1501 are arranged at a position shifted to one side from the center in the lateral direction of the light emitting device 1501. The mounting direction of each of the light emitting devices 1501 is determined so that the end face 310 of each of the light emitting devices 1501 is on the center line L_center side. That is, on the silicon substrate 1502, the plurality of lower electrodes 410 and 420 are arranged on the side closer to the center (center line L_center) in the lateral direction of the rod lens array 203. When the light emitting devices 1501 are arranged in a two-row staggered arrangement, the light emitting devices 1501A and 1501B are arranged 180° inverted from each other and so that their light emitting points are closer to the center line L_center.

[0128] In this way, the mounting direction of light emitting device 1501 is determined so that the positions of the lower electrodes within light emitting device 1501 are shifted to one side and the lower electrodes are closer to center line L_center. This makes it possible to obtain good imaging characteristics. Meanwhile, as described above, since light emitting devices 1501 are arranged in different mounting directions, it is necessary to control the order in which the lower electrodes are driven in the Y direction according to the direction of light emitting device 1501. For example, in light emitting device 1501A, the lower electrode on the side closer to end face 311 (upper side in the figure) is driven first, and in light emitting device 1501B, the lower electrode on the side closer to end face 310 (upper side in the figure) is driven first. A control method for such a case will be described below.

[0129] (Circuit with selector) FIG. 20 is a circuit block diagram inside light emitting device 1501 that switches the light emission order of lower electrodes 410-1 to 410-748 in the short-side direction of printed circuit board 202. As with FIG. 18, a case will be described in which two rows of lower electrodes 410-1 to 410-748 and lower electrodes 420-1 to 420-748 are arranged in the Y direction. In addition to the circuit configuration described in FIG. 18, data storage unit 804 has selectors 2200-12, 2200-34, 2200-56, .... Selector 2200-12 switches the connection combination between flip-flop circuit 812 and flip-flop circuit 813 and pulse signal generation unit 805-1 and pulse signal generation unit 805-2. Selector 2200-34 switches the connection combination between flip-flop circuit 812 and flip-flop circuit 813 and pulse signal generation unit 805-3 and pulse signal generation unit 805-4. The selector 2200-56 switches the connection combination between the flip-flop circuit 812 and the flip-flop circuit 813 and the pulse signal generating unit 805-5 and the pulse signal generating unit 805-6.

[0130] The selectors 2200-12, 2200-34, 2200-56, ... are collectively referred to as selector 2200. The selector 2200 is capable of switching the connection relationship with the pulse signal generation unit 805, which is the destination of image data from the flip-flop circuits 812 and 813. In other words, the selector 2200 functions as a selection unit that selects a combination of connections between the first memory circuit group and the second memory circuit group and the first pulse signal generation unit group and the second pulse signal generation unit group.

[0131] For example, in one light emitting device 1501 in the longitudinal direction of the staggered arrangement, flip-flop circuit 812 is connected to pulse signal generating unit 805-1, and flip-flop circuit 813 is connected to pulse signal generating unit 805-2. In the other light emitting device 1501 in the longitudinal direction of the staggered arrangement, flip-flop circuit 812 is connected to pulse signal generating unit 805-2, and flip-flop circuit 813 is connected to pulse signal generating unit 805-1. Connection information of selector 2200 is set in a predetermined register of register unit 802 based on a communication signal from CPU 703. It is assumed that selector 2200 controls the connection based on the connection information (register value) set in register unit 802.

[0132] As described above, by providing a means for switching the drive order of the lower electrodes, multiple exposure can be performed regardless of the arrangement direction of the light-emitting device 1501 on the printed circuit board 202. In this embodiment, the usefulness of the staggered arrangement has been explained, but it is also useful when using the same exposure head in multiple different image forming apparatuses. The drive order is selected depending on the rotation direction of the photosensitive drum 102 and the installation direction of the exposure head. This makes it possible to use the same exposure head even in image forming apparatuses in which the rotation direction of the photosensitive drum 102 is different.

[0133] As explained above, in this embodiment, by arranging the lower electrodes in the Y direction and performing multiple exposure, it is possible to increase the optical output of the exposure head, which makes it possible to increase the speed of the image forming device and to accommodate photosensitive materials that require a larger amount of light. Furthermore, by configuring the lower electrode array and circuit unit 602 on a silicon substrate, it is possible to increase the resolution of the output and improve the performance of the control by making it possible to incorporate a large-scale logic circuit for the light-emitting device.

[0134] The silicon substrate 1502 also has a means for generating image data for multiple exposure. This makes it possible to generate the necessary image data without increasing the wiring (wire bonding) of the light emitting device 1501 interface. Optimal placement of memory circuits (flip-flop circuits) makes it possible to optimize the wiring area. Furthermore, the light emission timing can be controlled according to the printing speed and resolution of the image forming apparatus and the spacing between the lower electrodes of the light emitting device 1501. This makes it possible to sharpen the exposure area on the photosensitive drum 102 by multiple exposure.

[0135] As described above, according to this embodiment, it is possible to propose an exposure head that can be driven at high speed with a higher optical output. [Example]

[0136] In the fourth embodiment, a method of transferring image data from the image controller unit 700 to each light emitting device 401 using the above-mentioned chip select signal will be described using the configuration of the first embodiment as an example. Note that the image data transfer method of this embodiment can also be applied to the second and third embodiments.

[0137] FIG. 21 is a timing chart showing the relationship between (i) the clock signal clk, (ii) the line synchronization signal lsync_x, (iii) the chip select signals cs_x, cs_x_1 to cs_x_19, and (iv) the image data signal data.

[0138] In FIG. 21, cs_x represents the chip select signal line 705 in FIG. 6, cs_x_1 represents the chip select signal input to light-emitting device 401-2 via signal line 711-1 in FIG. 6, cs_x_2 represents the chip select signal input to light-emitting device 401-3 via signal line 711-2 in FIG. 6, and cs_x_19 represents the chip select signal input to light-emitting device 401-20. Furthermore, image data for driving one line of the bottom electrodes in the nth light-emitting device 401-n is represented as data(n-1). For example, image data for driving one line of the bottom electrodes in the first light-emitting device 401-1 is represented as data0. The image controller 700 keeps the chip select signal cs_x low for the number of clock cycles ΔT0 required to transfer image data for driving one line of the bottom electrodes in light-emitting device 401-1. In this embodiment, image data for one bottom electrode is transferred per clock cycle, and ΔT0 is 748 cycles. It is also possible to use a configuration in which image data for a plurality of lower electrodes is transferred in one cycle, or a configuration in which one piece of image data is transferred in multiple cycles.

[0139] The chip select signal generator 803 built into the light-emitting device 401-1 delays the chip select signal cs_x_1 input to the light-emitting device 401-1 by ΔT1 cycles, resulting in a chip select signal cs_x_1. Here, ΔT1 is defined as ΔT0 plus the delay required to generate the chip select signal. In this embodiment, signal generation takes two cycles, so ΔT1 = 750 cycles. This allows the chip select signal generator 803 to generate the chip select signal cs_x_1 so that it does not go low simultaneously with cs_x. The chip select signal generators 803 built into the other light-emitting devices 401-2 and onward similarly generate new chip select signals so that the chip select signal input from the previous light-emitting device does not go low simultaneously with the input chip select signal, and transfer these signals sequentially to the subsequent light-emitting device. That is, each light-emitting device samples image data using the input chip select signal, delays the input chip select signal by a predetermined amount, and passes it to the subsequent light-emitting device. As a result, each chip select signal goes low in the order of cs_x → cs_x_1 → cs_x_2 → ... → cs_x_19. In addition, the period ΔT2 of the line synchronization signal lsync_x is set to a value greater than the time it takes for cs_x_19 to be input to light-emitting device 401-20, in order to send image data to all light-emitting devices 401. This can be expressed as the following equation: ΔT2≧ΔT1×20

[0140] The image controller unit 700 controls the period when cs_x_19 is Low so that the period when cs_x is Low next does not overlap, and sends image data data0 to data19 to the image data signal line 707 in accordance with each chip select signal, with an interval of (ΔT1-ΔT0) cycles. A chip select signal is also input to a data storage unit 804 built into each light-emitting device 401. When a low-level chip select signal is input, the data storage unit 804 can receive image data from the image data signal 707. In other words, during one cycle of Lsync_x, only one light-emitting device out of light-emitting devices 401-1 to 401-20 can receive image data from the image controller 700 via the image data signal line 707. By passing the chip select signal sequentially from light-emitting device 401-1 to light-emitting device 401-20, the image controller unit 700 can allocate and send each image data to each light-emitting device 401 via the common image data signal line 707 and one chip select signal line.

[0141] As described above, by cascading the light emitting devices with chip select signals, it is possible to suppress an increase in the number of signal lines even if the bit width of the image data signal lines is increased.

[0142] (Variation) A modified example of the fourth embodiment will be shown using Figures 22 and 23. Figure 22 shows a block diagram of the image controller unit 700 and the printed circuit board 202 in the modified example. What differs from Figure 6 of the first embodiment is that a second image data signal line 1307 (second signal line) is additionally output from the chip data conversion unit 702 in addition to the image data signal line 707 (hereinafter referred to as the first image data signal line or the first signal line for distinction), and in the signal line connection to the light emitting device 401 within the printed circuit board 202.

[0143] In the chip data conversion unit 702 of this embodiment, image data for one line is divided into first image data intended for the light emitting devices 401-2, 401-4, ... arranged on the lower side of the printed circuit board 202 in FIG. 22 in synchronization with the line synchronization signal generated by the synchronization signal generation unit 704, and second image data intended for the light emitting devices 401-1, 401-3, ... arranged on the upper side of the printed circuit board 202 in FIG. 22, and sent to the printed circuit board 202 together with a clock signal and a chip select signal. The first image data and second image data are sent separately. The other configurations of the image controller unit 700 are the same as those of the first embodiment.

[0144] Next, the configuration of the printed circuit board 202 will be described. The head information storage unit 710 is the same as in the first embodiment. The clock signal line 706, the line synchronization signal line 708, and the communication signal line 709 are connected to all of the light-emitting devices 401. The first image data signal line 707 is connected to the light-emitting devices 401-2, 401-4, ... arranged on the lower side of the printed circuit board 202 in the figure. That is, the first image data signal line 707 is used in common for the light-emitting devices 401-2, 401-4, ... for transmitting image data. The second image data signal line 1307 is connected to the light-emitting devices 401-1, 401-3, ... arranged on the upper side of the printed circuit board 202 in the figure. That is, the second image data signal line 1307 is used in common for the light-emitting devices 401-1, 401-3, ... for transmitting image data. The light emitting devices 401-2, 401-4, . . . are defined as a first group of light emitting elements, and the light emitting devices 401-1, 401-3, . . . are defined as a second group of light emitting elements.

[0145] Chip select signal line 705 is connected to the input of light emitting device 401-1, the output of light emitting device 401-1 is connected to the input of light emitting device 401-3 via signal line 711-1, and so on, forming a cascade connection of upper light emitting devices. Chip select signal line 705 is also connected to the input of light emitting device 401-2, the output of light emitting device 401-2 is connected to the input of light emitting device 401-4 via signal line 711-2, and so on, forming a cascade connection of lower light emitting devices. The operation of each light emitting device 401 is the same as in Example 1.

[0146] Next, we will explain the transfer of image data from the image controller unit 700 to the light emitting device 401 in this embodiment. Fig. 23 is a timing chart showing the relationship between (i) the clock signal clk, (ii) the line synchronization signal lsync_x, (iii) the chip select signals cs_x, cs_x_1 to cs_x_19, and (iv) the first image data signal data_1 and the second image data signal data_2. In Fig. 23, cs_x represents the chip select signal input to light emitting device 401-1 and light emitting device 401-2 via chip select signal line 705 in Fig. 22, cs_x_1 represents the chip select signal input to light emitting device 401-3 via signal line 711-1 in Fig. 22, cs_x_2 represents the chip select signal input to light emitting device 401-4 via signal line 711-2 in Fig. 22, cs_x_3 represents the chip select signal input to light emitting device 401-5 via signal line 711-3 in Fig. 23, cs_x_4 represents the chip select signal input to light emitting device 401-6 via signal line 711-4 in Fig. 23, cs_x_18 represents the chip select signal input to light emitting device 401-19, and cs_x_19 represents the chip select signal input to light emitting device 401-20. Image data is represented in the same way as in Fig. 21.

[0147] The low width ΔT0 of the chip select signal cs_x and the generation of the chip select signal within the light emitting device 401 are the same as in Example 1. In this example, the chip select signal cs_x is input to light emitting devices 401-1 and 401-2, which are cascade-connected above and below each other. As a result, two identical chip select signals are generated in parallel: one system in which the chip select signals go low in the order of cs_x → cs_x_1 → cs_x_3 → ... → cs_x_19, and the other system in which the chip select signals go low in the order of cs_x → cs_x_2 → cs_x_4 → ... → cs_x_18.

[0148] The cycle ΔT2 of the line synchronization signal lsync_x is constrained by the following equation because the number of stages in the cascade connection is half that of the first embodiment. ΔT2 ≥ ΔT1 × 10

[0149] The image controller unit 700 controls the chip select signals cs_x_18 and cs_x_19 so that the intervals when they are Low do not overlap with the intervals when the chip select signal cs_x next becomes Low, and sends image data data1, data3..., data19 to the first image data signal line 707 and data0, data2..., data18 to the second image data signal line 1307 in accordance with each chip select signal, with an interval of (ΔT1-ΔT0) cycles between each.

[0150] As described above, by providing multiple systems for cascading the light emitting devices 401 using chip select signals and running the image data signal lines in parallel, it is possible to relax the lower limit constraint on the period of the line synchronization signal lsync_x and improve productivity. Note that although this embodiment is divided into two systems, it may also be divided into three or four systems.

[0151] As described above, according to this embodiment, it is possible to propose an exposure head that can be driven at high speed with a higher optical output. [Explanation of symbols]

[0152] 202 Printed Circuit Board 401 Light-emitting device 402 Silicon substrate 410 Lower electrode 602 Circuit section 604 Light-emitting area

Claims

1. An image forming apparatus, a photosensitive member that is driven to rotate around a rotation axis; an exposure head including a light emitting device, a circuit board on which the light emitting device is mounted, and a lens array that guides light emitted from the light emitting device to a photosensitive member surface; a controller that outputs image data for driving the light emitting device to the circuit board; The light emitting device comprises: a silicon wafer including a drive circuit for driving the light emitting device; a layered body formed on a surface of the silicon wafer, the layered body including a first electrode layer including a plurality of electrodes arranged in a direction substantially parallel to the rotation axis of the photosensitive member, a layered second electrode layer through which light can pass, and a light-emitting layer formed in a layered state between the first electrode layer and the second electrode layer and emitting light when a voltage is applied thereto; The image forming apparatus is characterized in that the drive circuit includes a voltage generation circuit that generates a drive voltage and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on the image data, and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the plurality of electrodes.

2. 2. The image forming apparatus according to claim 1, wherein the first electrode layer is formed separately on the surface of the silicon wafer, the light-emitting layer is formed in a layer on the first electrode layer, and the second electrode layer is formed on the opposite side of the silicon wafer with the light-emitting layer sandwiched therebetween.

3. the drive circuit includes a shift register including a plurality of flip-flop circuits corresponding to the plurality of electrodes, respectively, for storing the image data, and a register including a plurality of flip-flop circuits corresponding to the plurality of electrodes, respectively, and individually connected to the plurality of flip-flop circuits of the shift register, 2. The image forming apparatus according to claim 1, wherein the pulse signal generating section generates the pulse signal based on image data stored in a flip-flop circuit of the register.

4. the controller generates a clock signal and a line synchronization signal; the shift register samples the image data output by the controller in synchronization with the clock signal and shifts the image data in the plurality of flip-flop circuits; 4. The image forming apparatus according to claim 3, wherein image data stored in each flip-flop circuit corresponding to the lower electrode of the shift register is transferred to the flip-flop circuit of the register in response to the line synchronization signal.

5. 5. The image forming apparatus according to claim 1, wherein a plurality of the light emitting devices are arranged on the circuit board along a direction substantially parallel to the axis of rotation.

6. the controller and the plurality of light-emitting devices are connected by a common signal line in order to transmit the image data from the controller to the plurality of light-emitting devices; The image forming apparatus according to claim 5, wherein the controller outputs an enable signal to one of the plurality of light-emitting devices to enable sampling of the image data, and each of the plurality of light-emitting devices sequentially passes the enable signal with a delay, starting from the one light-emitting device.

7. the plurality of light-emitting devices are divided into a first group of light-emitting devices connected to the controller by a common signal line for transmitting the image data, and a second group of light-emitting devices connected to the controller by a common second signal line for transmitting the image data; The image forming apparatus of claim 5, wherein the controller outputs an enabling signal to one of the plurality of light-emitting devices included in the first group of light-emitting devices and one of the plurality of light-emitting devices included in the second group of light-emitting devices to enable sampling of the image data, and each of the plurality of light-emitting devices included in each group of light-emitting devices delays and sequentially passes the enabling signal starting from each of the one light-emitting devices.

8. a silicon wafer containing circuitry; a layered body formed on a surface of the silicon wafer, the layered body including a first electrode layer including a plurality of electrodes, a layered second electrode layer that is light-transmitting, and a light-emitting layer that is layered between the first electrode layer and the second electrode layer and emits light when a voltage is applied thereto; The light-emitting device is characterized in that the drive circuit includes a voltage generation circuit that generates a drive voltage and a pulse signal generation circuit that generates a pulse signal for each of the plurality of electrodes based on drive data, and the drive circuit applies the drive voltage generated by the voltage generation circuit in response to the pulse signal to each of the plurality of electrodes.

9. 9. The light-emitting device according to claim 8, wherein the first electrode layer is formed separately on the surface of the silicon wafer, the light-emitting layer is formed in a layer on the first electrode layer, and the second electrode layer is formed on the opposite side of the silicon wafer with the light-emitting layer sandwiched therebetween.

10. the drive circuit includes a shift register corresponding to each of the plurality of electrodes and including a plurality of flip-flop circuits for storing the drive data, and a register corresponding to each of the plurality of electrodes and including a plurality of flip-flop circuits individually connected to each of the plurality of flip-flop circuits of the shift register, 10. The light emitting device according to claim 8, wherein the pulse signal generating section generates the pulse signal based on image data stored in a flip-flop circuit of the register.

Images