Gaming machine

Abstract

To promote the efficiency of a substrate configuration.SOLUTION: The game machine includes a first board. The first substrate includes heat dissipation means disposed at a position away from a component mounting surface of the substrate by a predetermined distance in a height direction, a first electronic component disposed at a position below the heat dissipation means when the component mounting surface is viewed from an upper surface side of the substrate, and a first component information notation portion in which a character or a symbol as information on the first electronic component is denoted on the component mounting surface. The first component information display part is provided at a position where it can be visually recognized while the heat radiation means is mounted.SELECTED DRAWING: Figure 62

Description

[Technical Field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] In pinball and rotary gaming machines, various devices such as LCD screens, speakers, LEDs, gadgets, vibrators, and blowers are used to enhance the gaming experience. The following patent documents disclose techniques for controlling various performance actions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-64693 Summary of the Invention [Problem to be solved by the invention]

[0004] In these gaming machines, the configuration and layout of the circuit boards used to drive the various performance devices are becoming increasingly complex in response to the diverse and complex performances that are being performed. This requires more efficient circuit board configurations, including miniaturization, easier inspection during manufacturing and maintenance, and proper protection of the circuit boards. In accordance with such circumstances, the present invention proposes a suitable board configuration for gaming machines. [Means for solving the problem]

[0005] The gaming machine of the present invention comprises a first board, the first board having a heat dissipation means arranged at a position a predetermined distance in the vertical direction from the component mounting surface of the board, a first electronic component arranged at a position below the heat dissipation means when the component mounting surface is viewed from the top side of the board, and a first component information notation section on the component mounting surface on which letters or symbols are written as information about the first electronic component, the first component information notation section being arranged in a position that can be seen while the heat dissipation means is attached. [Effects of the Invention]

[0006] According to the present invention, it is possible to improve the efficiency of the board configuration in gaming machines and thereby reduce costs. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a front perspective view showing the appearance of a gaming machine according to an embodiment of the present invention; [Figure 2] 1 is a diagram showing the configuration of a gaming board of a gaming machine according to an embodiment; [Figure 3] 2 is a block diagram showing the control configuration of the gaming machine according to the embodiment; [Figure 4] An explanatory diagram of an example of a preview performance in an embodiment. [Figure 5] 1 is a perspective view of a gaming machine according to an embodiment with the door open. [Figure 6] 1 is an oblique view of an embodiment of the gaming machine with the inner frame open. FIG. [Figure 7] FIG. 2 is an explanatory diagram of the board arrangement on the back side of the game board according to the embodiment. [Figure 8] An explanatory diagram of the board arrangement of the door and inner frame of the gaming machine of the embodiment. [Figure 9] 10 is an explanatory diagram of the board arrangement of the inner frame of the gaming machine of the embodiment. FIG. [Figure 10] FIG. 2 is an explanatory diagram of the arrangement of various devices. [Figure 11] FIG. 2 is a block diagram of the connection configuration of the board. [Figure 12] FIG. [Figure 13] FIG. 4 is an explanatory diagram of components mounted on a power supply board. [Figure 14] This is an explanatory diagram of an example of single-system transmission in which signals are transmitted between the performance control board and the LED connection board via a single transmission path using a pair of connectors. [Figure 15] This is an explanatory diagram of an example of dual-system transmission in which signals are transmitted between the performance control board and the LED connection board via two transmission paths using two pairs of connectors. [Figure 16]FIG. 10 is an explanatory diagram of the assignment of two-row connector pins in an example of multiple-system transmission. [Figure 17] FIG. 10 is a block diagram of the configuration around the input connector of the LED connection board. [Figure 18] FIG. 2 is a block diagram of the peripheral configuration of the LED drive unit of the LED connection board. [Figure 19] FIG. 10 is a block diagram of the configuration around the motor drive unit of the LED connection board. [Figure 20] FIG. 10 is a circuit diagram of the periphery of the input connector of the LED connection board in a single-system transmission example. [Figure 21] This is a circuit diagram of the periphery of the input connector of the LED connection board in an example of multiple system transmission. [Figure 22] This is a circuit diagram of the LED driver and its periphery on the LED connection board. [Figure 23] This is a circuit diagram of the LED driver and its periphery on the LED connection board. [Figure 24] This is a circuit diagram of the area surrounding the output connector on the LED connection board. [Figure 25] This is a circuit diagram of the area surrounding the output connector on the LED connection board. [Figure 26] FIG. 10 is a circuit diagram of a portion of the power supply system of the LED connection board. [Figure 27] FIG. 10 is an explanatory diagram of a connector in the case of a single-system transmission example. [Figure 28] FIG. 10 is an explanatory diagram of a connector in the case of a multiple system transmission example. [Figure 29] FIG. 10 is an explanatory diagram of a connector in the case of a multiple system transmission example. [Figure 30] FIG. 10 is an explanatory diagram of an example of connector arrangement in a duplicated transmission example. [Figure 31] FIG. 10 is an explanatory diagram of an example of connector arrangement in a duplicated transmission example. [Figure 32] FIG. 10 is an explanatory diagram of an example of connector arrangement in a duplicated transmission example. [Figure 33] FIG. 10 is an explanatory diagram of an example of connector arrangement in a duplicated transmission example. [Figure 34] FIG. 10 is an explanatory diagram of the assignment of two-row connector pins in an example of multiple-system transmission. [Figure 35]FIG. 4 is an explanatory diagram of the pattern of the surface layer of the LED connection board. [Figure 36] FIG. 2 is an explanatory diagram of the pattern of the back surface layer of the LED connection board. [Figure 37] FIG. 2 is an explanatory diagram of the pattern of the first inner layer of the LED connection board. [Figure 38] FIG. 10 is an explanatory diagram of the pattern of the second inner layer of the LED connection board. [Figure 39] 3 is an explanatory diagram showing a partially enlarged pattern of the surface layer of the LED connection board. FIG. [Figure 40] FIG. 10 is an explanatory diagram of an example of a test point. [Figure 41] 3 is an explanatory diagram showing a partially enlarged pattern of the surface layer of the LED connection board. FIG. [Figure 42] 10 is an explanatory diagram showing an enlarged view of a part of the pattern on the back surface layer of the LED connection board. FIG. [Figure 43] FIG. 1 is an explanatory diagram of a chip-type fuse. [Figure 44] FIG. 2 is an explanatory diagram of a fuse arrangement in a series supply path of a power supply voltage. [Figure 45] FIG. 2 is an explanatory diagram of a fuse arrangement in a series supply path of a power supply voltage. [Figure 46] FIG. 10 is an explanatory diagram of terminal assignment in a two-row connector. [Figure 47] An explanatory diagram of the connection between the performance control board and the LED connection board and the assignment of connector terminals. [Figure 48] This is an explanatory diagram of the wiring between the connector and the CPU on the performance control board. [Figure 49] FIG. 10 is an explanatory diagram of the arrangement of connectors and bypass capacitors. [Figure 50] FIG. 10 is an explanatory diagram of an example of the board configuration after the performance control board. [Figure 51] FIG. 10 is an explanatory diagram of a case enclosing a performance control board and a performance interface board. [Figure 52] FIG. 10 is a circuit diagram relating to a performance control signal in the performance interface board. [Figure 53] FIG. 10 is an explanatory diagram of an example configuration in which a performance interface board outputs to multiple boards. [Figure 54] FIG. 10 is an explanatory diagram of the wiring of the pull-up resistors on the performance interface board. [Figure 55] An explanatory diagram of a performance control board equipped with a heat sink. [Figure 56] An explanatory diagram of a performance control board equipped with a fan. [Figure 57] An explanatory diagram of the performance control board with the heat dissipation means removed. [Figure 58] This is an explanatory diagram of a performance control board with outer edge lines indicated. [Figure 59] An explanatory diagram of the lower range and center point on the performance control board. [Figure 60] FIG. 10 is an explanatory diagram showing that the component information notation portion in the lower area of ​​the heat sink is visible. [Figure 61] FIG. 10 is an explanatory diagram of the visible range below the heat sink. [Figure 62] FIG. 10 is an explanatory diagram of a state in which the component information notation section is located on the outer edge side of the electronic component. [Figure 63] FIG. 10 is an explanatory diagram of an example in which the correspondence between an electronic component and a component information notation portion is indicated by a lead line. [Figure 64] FIG. 10 is an explanatory diagram of an example in which the correspondence between an electronic component and a component information notation portion is indicated by a lead line. [Figure 65] FIG. 10 is an explanatory diagram of an example in which a part information notation portion is located outside the outer edge line. [Figure 66] FIG. 10 is an explanatory diagram of an example in which a part information notation section is positioned across an outer edge line. [Figure 67] FIG. 10 is an explanatory diagram of an example in which an electronic component is positioned across the outer edge line. [Figure 68] FIG. 10 is an explanatory diagram of an example in which an electronic component is positioned across an outer edge line and the correspondence is indicated by a leader line. [Figure 69] 10 is an explanatory diagram of an example in which a plurality of electronic components are associated with component information notation units; FIG. [Figure 70] 10 is an explanatory diagram of an example in which a plurality of electronic components are associated with component information notation units; FIG. [Figure 71] 10 is an explanatory diagram of an example in which a plurality of electronic components are associated with component information notation units; FIG. [Figure 72] 10 is an explanatory diagram of an example in which a plurality of electronic components are associated with component information notation units; FIG. [Figure 73] 10 is an explanatory diagram illustrating a state in which an electronic component and a component information notation portion outside the lower range are adjacent to each other. FIG. [Figure 74] FIG. 10 is an explanatory diagram of the distance relationship between an electronic component, a component information notation section, an outer edge, and a CPU. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in the following order with reference to the accompanying drawings. <1. Structure of the gaming machine> <2. Control configuration of gaming machine> [2.1 Main control board] [2.2 Performance control board] <3. Overview of operation> [3.1 Game Status] [3.2 Game with changing symbols] [3.3 About winning] [3.4 Production] <4. Opening and closing structure and board layout> <5. Circuit board configuration> [5.1 Connection status of each board] [5.2 Transmission path between the performance control board and the LED connection board] [5.3 LED connection board] 6. Characteristic Configuration and Effects of the Embodiments <7.Other>

[0009] <1. Structure of the gaming machine> The structure of a pachinko gaming machine 1 as an embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a perspective view of the front side showing the appearance of the pachinko gaming machine 1, and Figure 2 is a view showing the front side of a game board 3 that the pachinko gaming machine 1 has. The pachinko gaming machine 1 has a frame member, a door member that is provided so as to be able to open and close relative to the frame member, and an exchangeable member that is attached so as to be able to be exchanged relative to the frame member. The pachinko gaming machine 1 described below has an inner frame 2 as a component equivalent to a frame member, a door 6 as a component equivalent to a door member, and a gaming board 3 as a component equivalent to a replaceable member.

[0010] The pachinko gaming machine 1 shown in Figure 1 (hereinafter sometimes abbreviated as "gaming machine 1") has a picture-frame-shaped inner frame 2 attached to the front of a wooden outer frame 4 so that it can be opened and closed, a gaming board 3 (see Figure 2) mounted in a gaming board storage frame (not shown) attached to the back of the inner frame 2, and a gaming area 3a formed on the surface of this gaming board 3 faces the opening of the inner frame 2. The gaming board 3 can be called an exchangeable member because it can be attached and detached to the inner frame 2 in an exchangeable manner. A door 6 supporting transparent glass is provided at the front of the game area 3a. Also, various control boards (see FIG. 3) for controlling game operations are provided at the rear side of the game board 3.

[0011] On the front side (player side) of the door 6, a side unit 10 is formed as a decorative unit that surrounds the entire periphery of the game board 3 or a part of it, for example. The side unit 10 itself is given a decorative shape that matches the theme of the gaming machine 1, and may be equipped with LEDs, accessories, and other presentation elements inside, thereby achieving a presentation effect that conveys the atmosphere of the game to the player. This side unit 10 is a unit that is attached to the door 6 in an interchangeable manner.

[0012] A key cylinder (not shown) for unlocking the door is provided on the front side of the door 6; by inserting a key into this key cylinder and operating it to one side, the locked state of the door 6 relative to the inner frame 2 can be released, allowing the door 6 to be opened to the front; and by operating it to the other side, the locked state of the inner frame 2 relative to the outer frame 4 can be released, allowing the inner frame 2 to be opened to the front.

[0013] A front operation panel 7 is disposed below the door 6 and is pivotally supported on the inner frame 2 by a hinge (not shown) so as to be able to be opened and closed freely. An upper tray unit 8 is provided on the front operation panel 7, and this upper tray unit 8 is formed with an upper tray 9 for storing the discharged gaming balls.

[0014] The upper tray unit 8 is also provided with a ball removal button 14 for removing game balls stored in the upper tray 9 downward from the gaming machine 1, a ball lending button 11 for requesting the game ball lending device (not shown) to dispense game balls, and a card return button 12 for requesting the return of any valuable medium inserted into the game ball lending device. Additionally, an effect button 13 (operation means) that can be operated by a player is provided on the upper tray unit 8. This effect button 13 becomes operable (input acceptable) when a built-in lamp (button LED 75) lights up during a predetermined input acceptance period, and it is possible to bring about a change in the effect by performing a predetermined operation (pressing, repeatedly pressing, long pressing, etc.) while the built-in lamp is lit. The upper tray unit 8 is also provided with controls such as a cross key 15a that allows users such as players and hall staff to select various items and give direction instructions, and a decision button 15b that allows users to decide on a selected item.

[0015] Further, on the right end side of the front operation panel 7, a firing operation handle 15 for operating the firing device 32 (see FIG. 3) is provided.

[0016] In addition, speakers 46 that produce sound effects (sound effects) through acoustics are provided on both sides of the upper part of the inner frame 2 and on the upper side of the firing operation handle 15. In Fig. 1, only the two speakers 46 on the upper part of the inner frame 2 are shown. The plurality of speakers 46 allows so-called stereophonic sound reproduction or multi-channel sound reproduction for sounds related to the performance.

[0017] Furthermore, a plurality of decorative lamps 45 (for example, full-color LEDs for light effects: see FIG. 3) that create a light effect through light decoration are provided in appropriate positions on the door 6. A plurality of full-color LEDs (light effects LEDs) as the decorative lamps 45 are provided around the pachinko gaming machine 1, for example, on the periphery of the door 6 or inside the side unit 10.

[0018] The configuration of the game board 3 will be described with reference to FIG. The illustrated game board 3 has a ball guide rail 5 attached in a ring shape as a board surface partition member to guide the launched game balls, and the approximately circular area surrounded by this ball guide rail 5 is the game area 3a, while the four corners are non-game areas.

[0019] Approximately in the center of this game area 3a, there is provided a liquid crystal display device (LCD) 36 which is capable of independently displaying (displaying changes and stopping) multiple types of decorative patterns (for example, a left pattern (corresponding to the left display area), a middle pattern (corresponding to the middle display area), and a right pattern (corresponding to the right display area)) using numbers, characters, symbols, etc. in, for example, three (left, middle, right) display areas (pattern change display areas). This liquid crystal display device 36 displays various effects as images, in addition to the changing display operation of decorative symbols, under the control of the effect control board 30 described later.

[0020] Also, within the gaming area 3a, a center ornament 48 is provided in a manner that surrounds the display surface of the liquid crystal display device 36 at a distance. The center ornament 48 is provided along the front side of the gaming board 3, and protects the display surface of the liquid crystal display device 36 from surrounding gaming balls, and also functions as a flow path sorting means that enables the flow path of the gaming balls to be sorted to the left or right depending on the strength or stroke length of the gaming ball's launch. In this embodiment, the center ornament 48 is disposed in the approximate center of the play area 3a so that flow paths for game balls are formed on both upper sides (left and right sides) of the play area 3a due to the presence of the center ornament 48. Game balls shot into the upper side of the play area 3a by the launching device 32 are sorted to the left and right at the upper side of the armor frame portion 48b, and flow down either the left flow path 3b on the left side of the center ornament 48 or the right flow path 3c on the right side.

[0021] In addition, the non-play area at the bottom of the game board 3 is a display area for various functions, and is provided with a special pattern display device 38a (first special pattern display means) and a special pattern display device 38b (second special pattern display means) using dot displays. The various function display sections including the special symbol display devices 38a and 38b are shown enlarged in FIG.

[0022] The special symbol display devices 38a, 38b are configured to execute a special symbol variable display game by varying the display operation of "special symbols" represented by dot displays. The liquid crystal display device 36 is configured to variably display decorative symbols by images in synchronization with the variable display of special symbols by the special symbol display devices 38a, 38b, and to execute a decorative symbol variable display game together with various preview effects (effect images) (these symbol variable display games will be explained in detail later).

[0023] The various function display section also includes a composite display device (LED display for reserved composite display) 38c, which is made up of dot displays similar to the special symbol display devices 38a and 38b. It is called a composite because it is a reserved, time-saving, and high-probability composite display device (hereinafter simply referred to as the "composite display device") that has five display functions: displaying special symbols 1 and 2, the number of reserved balls for normal symbols, and notifying the status when the variable time-saving function is in operation (during time-saving) and when in a high-probability state (during high probability).

[0024] The various function display section is also provided with a composite display device 38d, which is also made up of dot displays. In this composite display device 38d, a round number display is performed to notify the specified number of rounds (maximum number of rounds) related to a jackpot by a combination of the on / off states of four LEDs. For example, the specified number of rounds (maximum number of rounds) related to a jackpot is notified by a combination of the on / off states of four LEDs. In addition, in the composite display device 38d, a normal symbol variable display game is executed by a variable display operation of a normal symbol represented by one LED as a normal symbol display. Furthermore, the composite display device 38d is configured to display right-hit information using three LEDs.

[0025] A start hole 34 (first special symbol start hole: first start means) is provided inside the center ornament 48 in Fig. 2. A detection sensor 34a (start hole sensor 34a, see Fig. 3) that detects the passage of the game ball is formed inside the start hole 34. In addition, a start port 35 (second special pattern start port: second start means) that opens and closes is provided in the right flow path 3c, and a detection sensor 35a (start port sensor 35a: see Figure 3) that detects the passage of the game ball is formed inside.

[0026] The first special symbol starting hole 34 is a winning hole related to the starting condition of the variable display operation of the first special symbol (hereinafter, the first special symbol is referred to as "special symbol 1" and sometimes abbreviated as "special symbol 1") in the special symbol display device 38a, and is configured as a fixed winning rate winning device that does not have a starting hole opening / closing means (means for opening or enlarging the starting hole). In this embodiment, due to the action of a game ball falling direction changing member (for example, a game nail, a windmill 44, a center ornament 48, etc.) in the game area 3a, the starting hole 34 is configured so that game balls flowing down the left flow path 3b can easily enter (win) the ball, but it is configured so that game balls flowing down the right flow path 3c can hardly or cannot enter.

[0027] The starting port 35 is a winning port related to the starting conditions for the variable display operation of the second special pattern (hereinafter, the second special pattern will be referred to as "special pattern 2" and sometimes abbreviated as "special pattern 2") in the special pattern display device 38b, and the winning area of ​​this starting port 35 is configured to be able to open and close between an open state in which a winning is possible and a closed state in which a winning is not possible.

[0028] The start opening 35 is a winning opening related to the start conditions for the variable display operation of the special symbol 2 in the special symbol display device 38b, and is configured as a variable start opening whose opening and closing is controlled by the normal electric device 41. The normal electric accessory 41 is controlled to an open state that allows a game ball to enter the starting hole 35 and a closed state that makes it difficult or impossible for the game ball to enter the starting hole 35.

[0029] Two general winning openings 43 are provided on the left and right lower sides of the game area 3a, and a general winning opening sensor 43a for detecting the passage of a gaming ball is formed inside each of them. Additionally, within the area of ​​the game board, movable accessories (not shown) that create visual effects are arranged in positions that do not interfere with the flow of the game balls.

[0030] Additionally, diagonally above the normal electric device 41, i.e., above the middle of the right flow path 3c, there is provided a normal symbol start port 37 (third start means) consisting of a passage gate (specific passage area) through which game balls can pass. This normal symbol start port 37 is a winning port related to the variable display operation of the normal symbol on the composite display device 38d, and inside it is formed a normal symbol start port sensor 37a (see FIG. 3) that detects game balls passing through. Note that in this embodiment, the normal symbol start port 37 is formed only on the right flow path 3c side, and not on the left flow path 3b side. However, the present invention is not limited to this, and it may be formed only on the left flow path 3b, or on both flow paths.

[0031] A special variable prize winning device 52 (special electric device) is provided midway along the path from the normal pattern starting port 37 in the right flow path 3c, which is configured to be able to open or expand the large prize winning port 50 using an opening door 52b, and inside it is formed a large prize winning port sensor 52a (see Figure 3) which detects game balls that have entered the large prize winning port 50. Around the big prize opening 50, there are provided a guide section 55 and a windmill 53 which function to guide the game balls flowing down in the direction of the big prize opening 50.

[0032] The process of the game ball entering the big prize opening 50 is as follows. The gaming ball passes through the free movement area between the upper surface of the center ornament 48 and the ball guide rail 5 and then passes through the right flow path 3c, and is guided in the direction of the big prize opening 50 by the guide section 55. If the big prize opening 50 is in an open state (big prize opening open state), the gaming ball is guided into the big prize opening 50.

[0033] In the gaming machine 1 of this embodiment, when the player aims the launch position toward the special variable winning device 52 (when the player aims so that the gaming ball passes through the right flow path 3c), the gaming ball is difficult to guide or cannot be guided toward the starting hole 34. Therefore, if the "big winning hole closed state", it is difficult or impossible for the gaming ball to enter the starting hole 34. In addition, when the game state is entered with the electric support state described below, the starting port 35 operates in an opening and closing pattern that is more advantageous than in the normal state.

[0034] In this embodiment, the type of hitting technique that is advantageous for the player varies depending on the game state. Specifically, in a game state that includes a "no electric support state" described below, a "left hit" that aims the game ball to pass through the left flow path 3b is considered advantageous, and in a game state that includes a "electric support state" described below, a "right hit" that aims the game ball to pass through the right flow path 3c is considered advantageous.

[0035] In the gaming machine 1 of this embodiment, when a winning ball is won in a winning hole other than the normal symbol start hole 37 among the various winning holes provided in the gaming area 3a, the number of prize balls per winning ball promised for each winning hole (for example, 3 balls for start hole 34 or start hole 35, 13 balls for the large prize hole 50, and 10 balls for the general prize hole 43) is paid out from the gaming ball payout device 19 (see FIG. 3). Gaming balls that do not win in the above winning holes are discharged from the gaming area 3a through the outlet hole 49.

[0036] Here, "winning" refers to a game ball being drawn into a winning opening, or, if the winning opening is a gate-type winning opening (e.g., normal symbol start opening 37) rather than a winning opening that draws in game balls, a game ball passing through the gate. In practice, when a game ball is detected by the winning detection switch formed for each winning opening, that winning opening is considered to have "won." The winning ball is also referred to as a "winning ball." Note that, since a game ball entering a winning opening will be detected by the winning detection switch, unless otherwise specified, the term "winning" may be used in this specification to refer to a game ball entering a winning opening, regardless of whether the game ball is detected by the winning detection switch.

[0037] <2. Control configuration of gaming machine> The configuration (control configuration) for realizing the gaming operation control of the gaming machine 1 will be described with reference to the block diagram of FIG. The gaming machine 1 of this embodiment is configured to include a main control board (main control means) 20 that comprehensively controls all game operations (game operation control), a presentation control board 30 (presentation control means) that receives presentation control commands from the main control board 20 and comprehensively controls the execution control (appearance control) of presentations by the presentation means, a payout control board (payout control means) 29 that controls the payout of prize balls, and a power supply board (power supply control means (not shown)) that generates and supplies the power required for the gaming machine 1 from an external power source (not shown). In FIG. 3, the power supply routes to each part are omitted.

[0038] [2.1 Main control board] The main control board 20 is equipped with a microprocessor that incorporates a CPU (Central Processing Unit) 20a (main control CPU), as well as a ROM (Read Only Memory) 20b (main control ROM) that stores a control program that describes the game operation control procedures, as well as various data necessary for game operation control, and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area and buffer memory, and as a whole constitutes a microcomputer.

[0039] Although not shown, the main control board 20 also includes a CTC (Counter Timer Circuit) for implementing periodic interrupts, a function for generating pulse outputs at fixed intervals (bit rate generator), and a time measurement function, an interrupt controller circuit that performs interrupt enable / disable functions such as timer interrupts that issue interrupt signals to the main control CPU 20a, a reset circuit that can detect power-on / power-off and power supply abnormalities and output a system reset signal to reset the main control CPU 20a, a watchdog timer (WDT) circuit that monitors for abnormal operation of the control program, an IAT (Inhibit Outside Designated Area) circuit that monitors whether the program is being executed correctly within a preset address range, and a counter circuit for generating random numbers within a certain range in hardware.

[0040] The counter circuit is comprised of a random number generation circuit that generates random numbers and a sampling circuit that samples random numbers from the random number generation circuit at predetermined timing, and functions as a 16-bit counter as a whole. The main control CPU 20a sends instructions to the sampling circuit according to the processing status to obtain the number indicated by the random number generation circuit as a random number value for internal lottery (random number for determining jackpot (size of random number: 65536)), and uses this random number value for the jackpot lottery. Note that the random number for internal lottery is obtained by adding a software random number value generated by appropriate software processing and a hard random number value to prevent cheating such as aiming for a jackpot.

[0041] Connected to the main control board 20 are a start gate sensor 34a that detects winning (ball entry) into start gate 34, a start gate sensor 35a that detects winning into start gate 35, a normal pattern start gate sensor 37a that detects passage through normal pattern start gate 37, a special prize gate sensor 52a that detects winning into special prize gate 50, a general prize gate sensor 43a that detects winning into general prize gate 43, and an OUT monitoring switch 49a that detects game balls (out balls) discharged from outlet 49, and the main control board 20 is capable of receiving detection signals output from these. Based on the detection signals from each sensor, the main control board 20 is able to determine which prize gate the game ball has entered.

[0042] In addition, the main control board 20 is connected to a normal electric role solenoid 41c for controlling the opening and closing of the movable wing piece of the starting opening 35, and a large prize opening solenoid 52c for controlling the opening and closing of the opening door 52b of the large prize opening 50, and the main control board 20 is capable of transmitting control signals for controlling these.

[0043] Furthermore, the main control board 20 is connected to a special symbol display device 38a and a special symbol display device 38b, and the main control board 20 is capable of transmitting control signals for controlling the display of special symbols 1 and 2. Furthermore, the main control board 20 is connected to a composite display device 38c, and is capable of transmitting control signals for controlling the display of the number of reserved symbols and the status display.

[0044] In addition, a composite display device 38d is connected to the main control board 20, and the main control board 20 is capable of transmitting control signals for controlling the display of the normal pattern display, right-hit display, and round display displayed on the composite display device 38d.

[0045] Furthermore, an external centralized terminal board 21 for the frame is connected to the main control board 20, and the main control board 20 is capable of transmitting predetermined game information (e.g., jackpot information, number of winning balls information, pattern change execution information, etc.) to a hall computer HC installed outside the gaming machine via the external centralized terminal board 21 for the frame. The hall computer HC is an information processing device (computer device) that monitors game information from the main control board 20 and comprehensively manages the operating status of the gaming machines in the pachinko hall.

[0046] Furthermore, a payout control board (payout control unit) 29 is connected to the main control board 20, and when it is necessary to pay out prize balls, a control command regarding the payout (a payout control command specifying the number of prize balls) can be sent to the payout control board 29.

[0047] A launch control board (launch control unit) 28 that controls the launch device 32, and a game ball payout device (game ball payout means) 19 that pays out game balls are connected to the payout control board 29. The main role of this payout control board 29 is to receive payout control commands from the main control board 20, control the payout of prize balls by the game ball payout device 19 based on the payout control commands, and send status signals to the main control board 20.

[0048] The game ball payout device 19 is provided with a supply shortage detection sensor 19a that detects a shortage of game balls and a ball counting sensor 19b that detects the game balls (prize balls) to be paid out, and the payout control board 29 is capable of receiving these detection signals. The game ball payout device 19 is also provided with a payout motor 19c that drives a ball payout mechanism (not shown) for paying out game balls, and the payout control board 29 is capable of transmitting a control signal for controlling the payout motor 19c.

[0049] Furthermore, the payout control board 29 is connected to a fullness detection sensor 60 (in this embodiment, a detection sensor that detects the storage state of game balls stored in the upper tray 9) that detects whether the upper tray 9 is full of game balls, and a front door open sensor 61 (for example, a detection sensor that detects the open state of the door 6 or inner frame 2).

[0050] The payout control board 29 can transmit various status signals to the main control board 20 based on detection signals from the full detection sensor 60, the front door open sensor 61, the out-of-supply detection sensor 19a, and the ball count sensor 19b. These status signals include a ball jam signal indicating a full state, a door open signal indicating that at least the inner frame 2 is open, an out-of-supply signal indicating a shortage of game balls from the game ball payout device 19, a count error signal indicating a shortage of prize balls or an abnormality in the ball count sensor 19b, and a payout completion signal indicating the completion of the payout operation. Based on these status signals, the main control board 20 monitors the open state of the inner frame 2 (door open error), whether the payout operation of the game ball payout device 19 is normal (out-of-supply error), and whether the upper tray 9 is full (ball jam error).

[0051] Furthermore, the payout control board 29 is connected to a launch control board 28, which is capable of transmitting an authorization signal to the launch control board 28 to authorize launching. Based on the authorization signal output from the payout control board 29, the launch control board 28 controls the energization of a launch solenoid (not shown) provided in the launcher 32, thereby realizing the launch of a gaming ball by operating the launch operation handle 15. Specifically, the launch of a gaming ball is permitted under the following conditions: a launch authorization signal is output from the payout control board 29 (launch authorization signal ON state), a touch sensor provided on the launch operation handle 15 detects that the player is touching the handle, and a launch stop switch (not shown) provided on the launch operation handle 15 has not been operated. Therefore, when the launch authorization signal is not output (launch authorization signal OFF state), the launch operation is not executed even if the launch operation handle 15 is operated, and the gaming ball is not launched. Furthermore, the strength of the launch of the gaming ball can be changed depending on the amount of operation of the launch operation handle 15. Furthermore, when the payout control board 29 detects the above-mentioned ball jam error, it sends a ball jam signal to the main control board 20 and stops outputting the launch permission signal to the launch control board 28 (launch permission signal OFF), and controls the firing operation to stop until the upper tray 9 is no longer full. In addition, the payout control board 29 outputs a launch permission signal to the launch control board 28 on the condition that the main control board 20 has instructed the launch permission.

[0052] A RAM clear switch 98 is connected to the main control board 20, and detection signals from these switches can be received.

[0053] The RAM clear switch 98 is, for example, a push button switch for inputting an instruction to initialize a predetermined area of ​​the main control RAM 20c.

[0054] The RAM clear switch 98 is turned on / off in response to the operation of a RAM clear button that is provided so as to be operable when the inner frame 2 is open. The RAM clear switch 98 is provided at an appropriate location inside the gaming machine 1. For example, it is disposed on the main control board 20.

[0055] Furthermore, a performance indicator 97 is connected to the main control board 20. The performance indicator 97 is configured to have, for example, a 7-segment display, and functions as a display means capable of displaying performance information (described later). The performance indicator 97 is mounted, for example, at an easily visible position on the main control board 20.

[0056] (Performance display) The main control board 20 is capable of transmitting a control signal to the performance display 97 to cause the performance display 97 to display predetermined performance information. Performance information is information that pachinko halls and relevant authorities want to confirm, and typical examples include information regarding the presence or absence of illegal prize ball cheating, such as excessive prize balls in the gaming machine 1, and the original ball output performance of the gaming machine 1. Therefore, unlike preview effects, the performance information itself is information that is not directly related to the progress of the game itself when a player is enjoying the game.

[0057] For this reason, the performance display 97 is provided inside the gaming machine 1, for example, on the main control board 20, payout control board 29, launch control board 28, the relay board, the performance control board 30, or in the board case (protective cover that protects the board), in a position where the display information can be seen when the inner frame 2 is in the open state.

[0058] Here, the performance information may specifically include the following information:

[0059] (1) Information (specific ratio information) based on the value (α / β) obtained by dividing the total number of payout balls paid out as a result of winning during a specific state (total number of prize balls during a specific state: α) by the total number of balls discharged from the game area 3a during the specific state (number of balls discharged during a specific state: β) can be adopted as performance information. The "total number of payouts" is the total number of game balls (prize balls) paid out when a ball enters a prize slot (starting slot 34, starting slot 35, general prize slot 43, large prize slot 50). In this embodiment, the number of payouts is 3 for starting slot 34 or starting slot 35, 13 for large prize slot 50, and 10 for general prize slot 43. Furthermore, which state is adopted as the specific state can be determined as appropriate depending on the state under which performance information is desired to be grasped. In the case of this embodiment, any of the normal state, the potential probability state, the time-saving state, the probability variable state, and the state during a jackpot game can be adopted. Furthermore, multiple types of states may be used as the measurement target. For example, the normal state and the probability variable state, or all game states except during a jackpot game, etc., and the type to be measured can be determined as appropriate. Furthermore, the period during the specific state may be a period during which the probability of winning a jackpot is either low or high. In addition, the total number of payouts may be calculated by excluding one or more specific winning ports from the measurement target (total number of payouts excluding specific winning ports). For example, the total number of payouts may be calculated by excluding the large winning port 50 from the measurement target among the winning ports.

[0060] (2) Alternatively, the total number of payouts, the total number of payouts excluding specific winning slots, or the total number of balls that have been released may be measured, and the measurement results may be used as performance information.

[0061] In this embodiment, the total number of dispensed balls in the normal state (number of dispensed balls in normal state) and the total number of balls out in the normal state (number of out balls in normal state) are measured in real time, and the value obtained by dividing the number of dispensed balls in normal state by the number of out balls in normal state and multiplying this value by 100 (value calculated as number of dispensed balls in normal state ÷ number of out balls in normal state × 100) is displayed as performance information (hereinafter referred to as "normal state ratio information"). Note that the displayed value at this time is rounded to one decimal place. Therefore, the data on the number of payouts during normal play, the number of outs during normal play, and the normal play ratio information are stored (memorized) in the corresponding areas of the main control RAM 20c (the storage area for the total number of prize balls during specific play, the storage area for the number of outs during specific play, and the specific ratio information storage area). However, rather than simply measuring continuously and displaying performance information, measurement is temporarily terminated when the total number of out balls reaches a predetermined number (e.g., 60,000). This specified number is not the total number of out balls during normal play, but the total number of out balls during all play states (including during winning play) (hereinafter referred to as the "number of outs in all states"). This number of outs in all states is also measured in real time and stored in the corresponding areas of the main control RAM 20c (the storage area for the number of outs in all states). For ease of explanation, the storage area for the total number of prize balls during specific play, the storage area for the number of outs during specific play, the specific ratio information storage area, and the storage area for the number of outs in all states will be abbreviated as the "measurement information storage area."

[0062] Then, the normal time ratio information at the end point is stored in a predetermined area (performance display storage area) of the main control RAM 20c (the current normal time ratio information is stored), and then the measurement information storage area (the number of balls dispensed during normal time, the number of balls out during normal time, and the number of balls out under all conditions) is cleared, and measurement begins again (measurement of the number of balls dispensed during normal time, the number of balls out during normal time, the normal time ratio information, and the number of balls out under all conditions begins).The performance display 97 then displays the previous normal time ratio information (measurement history information) and the normal time ratio information currently being measured. Note that the configuration is not limited to the previous information, and history from the time before that or the time before that (three times before) may also be displayed, and the number of previous times of information to be displayed can be determined as appropriate.

[0063] (Performance control command) Depending on the processing status, the main control board 20 can transmit various performance control commands, including information about the special symbol variation display game and information about errors, to the performance control board 30. However, in order to prevent fraudulent activities such as cheating, the main control board 20 is configured for one-way communication, where it can only transmit signals to the performance control board 30 and cannot receive signals from the performance control board 30.

[0064] Here, the performance control command defines its function using a two-byte structure consisting of a one-byte mode (MODE) and a one-byte event (EVENT). To distinguish between MODE and EVENT, Bit 7 of MODE is ON and Bit 7 of EVENT is OFF. When this information is transmitted as valid, a strobe signal is output corresponding to each mode (MODE) and event (EVENT). That is, when there is a command to transmit, the main control CPU 20a sets and outputs mode (MODE) information for transmitting the command to the performance control board 30, and transmits the first strobe signal a predetermined time after this setting. Furthermore, after a predetermined time has passed since transmitting this strobe signal, it sets and outputs event (EVENT) information, and transmits a second strobe signal a predetermined time after this setting. The strobe signal is controlled to an active state by the main control CPU 20a for a predetermined period of time to ensure that the performance control CPU 30a can receive commands reliably.

[0065] [2.2 Performance control board] The performance control board 30 is equipped with a microprocessor that incorporates a performance control CPU 30a, and is composed mainly of a microcomputer that is equipped with a performance control ROM 30b that stores the performance data required for performance control processing, and a performance control RAM 30c that functions as a work area and buffer memory.In addition, it is equipped with an audio control unit (sound source IC), an RTC (Real Time Clock) function unit, a counter circuit, an interrupt controller circuit, a reset circuit, a WDT circuit, etc., which control the overall performance operation.

[0066] The performance control CPU 30a performs calculations for various performance operations and controls each performance means based on the performance control program and performance control commands received from the main control unit 20. In the case of the pachinko gaming machine 1 of this embodiment, the performance means are the liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), the light display device 45a, the sound generating device 46a, and movable role objects not shown.

[0067] The performance control ROM 30b stores a control program for the performance operation by the performance control CPU 30a and various data required for performance operation control. The performance control RAM 30c is used as a work area used by the performance control CPU 30a for various calculation processes, a table data area, a buffer area for various input / output data and processing data, etc. The performance control board 30 is configured to have, for example, a one-chip microcomputer and its peripheral circuits mounted on it, but various configurations are possible for the performance control board 30. For example, in addition to the microcomputer, it may also have an interface circuit with each section, a random number generation circuit that generates random numbers for lottery use in performances, a CTC for counting various times, a watchdog timer (WDT) circuit, an interrupt controller circuit that gives an interrupt signal to the performance control CPU 30a, and the like.

[0068] The main roles of this performance control board 30 are to receive performance control commands from the main control unit 20, select and decide on performances based on the performance control commands, control the display of the LCD display device 36 (supply of display data), control the sound output of the sound generating device 46a, control the light emission of the light display device 45a (LED), and control the operation of the movable body role device (drive control of the movable body role device motor 80c).

[0069] This performance control board 30 also functions as a control device for the liquid crystal display device 36, so the performance control board 30 also has the functions of a so-called VDP (Video Display Processor), image ROM, and VRAM (Video RAM), and the performance control CPU 30a also functions as a liquid crystal control unit. VDP refers to the function that controls all video output processes, such as image expansion and image drawing. Image ROM refers to memory that stores image data (performance image data) that the VDP uses for image development processing. VRAM is an image memory area that temporarily stores image data developed by the VDP.

[0070] With this configuration, the performance control board 30 generates various image data based on commands from the main control unit 20 and outputs it to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various performance images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S. 2 is the "main liquid crystal display device 36M." The sub liquid crystal display device 36S is not shown in FIG.

[0071] Furthermore, the performance control board 30 has an audio control section (for example, sound controller 230 in FIG. 4) for an audio generating device 46a including multiple speakers 46, and the audio signals output by the audio control section are amplified by an amplifier section 46d and supplied to the speakers 46. Note that while the sound controller 230 as the audio control section will be described as being built into the performance control board 30, the audio control section may also use a sound source IC separate from the performance control board 30. Also connected to the performance control board 30 are a lamp driver unit 45d that functions as a light display control unit for the light display device 45a, which includes decorative lamps 45 and various LEDs, and a motor driver unit 80d (motor drive circuit) that functions as a drive control unit for the movable body role motor 80c that operates the movable body (not shown). The performance control board 30 issues instructions to the lamp driver unit 45d and motor driver unit 80d to control the light display operation of the light display device 45a and the operation of the movable body role motor 80c. For example, the performance control board 30 is equipped with a serial output circuit 30d, which generates serial data that controls the light display operation and the operation of the movable body role motor 80c, and supplies it to the lamp driver unit 45d and motor driver unit 80d.

[0072] The performance control board 30 is also connected to an origin switch 81 and a position detection sensor 82 for monitoring the operation of the movable props. The origin switch 81 is composed of, for example, a photointerrupter, and detects whether the movable body role motor 80c is at the origin position. The origin position is, for example, a position where the movable body is not normally exposed on the board surface of Figure 2. The performance control board 30 is capable of determining whether the movable body role motor 80c is at the origin position based on the detection information of this origin switch 81. In addition, the performance control board 30 controls the operation mode while monitoring the current operating position of the movable role object (for example, the amount of movement from the origin position) based on the detection information from the position detection sensor 82. Furthermore, the performance control board 30 monitors malfunctions in the operation of the movable role object based on the detection information from the position detection sensor 82, and if a malfunction occurs, it detects it as an error.

[0073] In addition, the performance control board 30 is connected to the switches for the performance button 13, cross key 15a, and decision button 15b, which are shown as operation unit 17 in the figure, i.e., the operation detection switches for the performance button 13, cross key 15a, and decision button 15b, and the performance control board 30 is capable of receiving operation detection signals from the performance button 13, cross key 15a, and decision button 15b, respectively.

[0074] Furthermore, the performance control board 30 is provided with a handle sensor 83 (touch sensor) for detecting whether or not the firing operation handle 15 shown in Fig. 1 is being touched by a user such as a player. Based on the detection information of this handle sensor 83, the performance control board 30 is able to determine whether or not the firing operation handle 15 is being touched by a user.

[0075] Based on the performance control command sent from the main control unit 20, the performance control board 30 selects (determines) a performance pattern by lottery or uniquely from multiple types of performance patterns prepared in advance, and controls various performance means at the required timing to produce the desired performance. This realizes the display of a performance image on the liquid crystal display device 36 corresponding to the performance pattern, the playback of sound from the speaker 46, and the lighting and flashing of the decorative lamps 45 and LEDs, and the chronological development of various performance patterns (such as decorative symbol variation display operations and preview performances), thereby realizing a "performance scenario" in the broad sense.

[0076] Here, for the performance control command, the performance control board 30 (performance control CPU 30a) receives and analyzes it by generating an interrupt process based on the input of the above-mentioned strobe signal sent by the main control unit 20 (main control CPU 20a). Specifically, the performance control CPU 30a executes a control program for command reception interrupt processing based on the input of the above-mentioned strobe signal, and in the interrupt process realized by this, it obtains the performance control command and analyzes the command content. In this case, if an interrupt occurs based on the input of a strobe signal, the performance control CPU 30a interrupts the interrupt processing based on another interrupt (a timer interrupt processing that is executed periodically) even if that processing is in progress, and performs command reception interrupt processing, and even if other interrupts occur at the same time, the command reception interrupt processing is given priority.

[0077] <3. Overview of operation> Next, an outline of the gaming operation of the gaming machine 1 realized by the above-described control configuration (FIG. 3) will be described.

[0078] [3.1 Game Status] The gaming machine 1 is configured to be able to set a plurality of types of gaming states in addition to a jackpot game, which is a special gaming state. To facilitate understanding of this embodiment, first, various gaming states will be described.

[0079] In the gaming machine 1, a game progresses in one of the game states that combines either a low probability state or a high probability state with either a non-time-shortening state or a time-shortening state.

[0080] The low probability state is a state in which the probability of winning the jackpot lottery is relatively low, and the high probability state is a state in which the probability of winning the jackpot lottery is relatively high. The non-time-shortening state is a state in which it is relatively difficult for a gaming ball to enter the starting hole 35, and the time-shortening state is a state in which it is relatively easy for a gaming ball to enter the starting hole 35. For example, the opening time of the starting hole 35 when the regular winning lottery is won is set longer in the time-shortening state than in the non-time-shortening state. However, if it is easier for a gaming ball to enter the starting hole 35 in the time-shortening state than in the non-time-shortening state, the time-shortening state may, for example, have a higher probability of winning the regular winning lottery or a shorter fluctuation time of the regular symbol than in the non-time-shortening state.

[0081] In this embodiment, the "normal state" refers to a low probability state and a non-time-saving state, and corresponds to the initial state.

[0082] [3.2 Game with changing symbols] The variable symbol display game will now be described.

[0083] (Special pattern change display game) In the pachinko gaming machine 1 of this embodiment, a "jackpot lottery" is conducted by random number lottery on the main control board 20 based on a predetermined starting condition, specifically, based on the game ball entering (winning) the start hole 34 or the start hole 35. Based on the lottery result, the main control board 20 variably displays special patterns 1 and 2 on the special pattern display devices 38a and 38b to start the special pattern variable display game, and after a predetermined time has passed, the result is derived and displayed on the special pattern display device, thereby ending the special pattern variable display game.

[0084] In this embodiment, the jackpot lottery based on winning at starting hole 34 and the jackpot lottery based on winning at starting hole 35 are conducted separately and independently. For this reason, the jackpot lottery result for starting hole 34 is derived on the special pattern display device 38a side, and the jackpot lottery result for starting hole 35 is derived on the special pattern display device 38b side. Specifically, on the special pattern display device 38a side, on the condition that a gaming ball has entered starting hole 34, special pattern 1 is variably displayed and a first special pattern variable display game is started, while on the special pattern display device 38b side, on the condition that a gaming ball has entered starting hole 35, special pattern 2 is variably displayed and a second special pattern variable display game is started. Then, when the special pattern variable display game is started on the special pattern display device 38a or the special pattern display device 38b, after a predetermined variable display time has elapsed, if the result of the jackpot lottery is a "jackpot", the special pattern being displayed in a static state will be displayed in a predetermined "jackpot" mode, or in a predetermined "miss" mode otherwise, thereby deriving the game result (jackpot lottery result).

[0085] For convenience of explanation, the first special symbol change display game on the special symbol display device 38a side will be referred to as "special symbol change display game 1," and the second special symbol change display game on the special symbol display device 38b side will be referred to as "special symbol change display game 2." Unless otherwise necessary, "special symbol 1" and "special symbol 2" will be simply referred to as "special symbols" (sometimes abbreviated to "special symbols"), and "special symbol change display game 1" and "special symbol change display game 2" will be simply referred to as "special symbol change display games."

[0086] (Decorative pattern changing game) Furthermore, when the above-mentioned special symbol variation display game is started, the decorative symbol variation display game is started by variably displaying decorative symbols (game symbols for dramatic effects) on the main liquid crystal display device 36M, and various effects are developed in association with this. When the special symbol variation display game ends, the decorative symbol variation display game also ends, and a predetermined special symbol indicating the result of the jackpot lottery is displayed on the special symbol display device, and a decorative symbol reflecting the result of the jackpot lottery is derived and displayed on the main liquid crystal display device 36M. In other words, the result of the special symbol variation display game is reflected and displayed by the decorative symbol variation display game for dramatic effects, including the variably displaying operation of the decorative symbols.

[0087] Therefore, for example, if the result of the special symbol variation display game is a "jackpot" (if the result of the jackpot lottery is a "jackpot"), an effect that reflects that result will be developed in the decorative symbol variation display game. Then, when the special symbol is stopped and displayed in a display mode that indicates a jackpot (for example, the 7-segment display shows "7") on the special symbol display device, the decorative symbols are stopped and displayed in a display mode that reflects the "jackpot" in each of the "left," "center," and "right" display areas on the main liquid crystal display device 36M (for example, three decorative symbols are displayed as "7," "7," and "7") in each of the "left," "center," and "right" display areas.

[0088] When this "jackpot" occurs, specifically, the special pattern change display game ends, followed by the decorative pattern change display game, and as a result, the pattern form of the "jackpot" is derived and displayed, and then the large prize opening solenoid 52c of the special variable prize winning device 52 is activated and the opening door 52b opens and closes in a predetermined pattern, thereby opening and closing the large prize opening 50, and a special game state (jackpot game) which is more advantageous to the player than the normal game state is generated. In this jackpot game, the opening door 52b opens or expands the prize area until the opening time of the large prize opening has elapsed for a predetermined time (maximum opening time: for example, 29.8 seconds) or until the number of game balls that have entered the large prize opening (prize balls entering the large prize opening 50) reaches a predetermined number (maximum number of prizes: the upper limit of the number of prize balls allowed for the opening or expanded prize opening with one operation of the device: for example, 9), and when either of these conditions is met, the large prize opening is closed. This "round game" is repeated for a predetermined number of rounds (for example, up to 16 rounds).

[0089] When the jackpot game starts, an opening effect is first performed to notify the player that the jackpot has started, and after the opening effect ends, round games are played multiple times up to a predetermined number of rounds. After the specified number of rounds have ended, an ending effect is performed to notify the player that the jackpot has ended, thereby ending the jackpot game.

[0090] Regarding the information necessary to execute the decorative pattern change display game, first, the main control board 20 conducts a jackpot lottery that includes a 'win / lose lottery (win / lose type lottery)' to draw whether there will be a jackpot or a 'loss', and a 'pattern lottery (win type (win type) lottery)' to draw the type of jackpot if there is a jackpot, and the type of loss if there is a loss, based on the game ball entering (winning) the start port 34 or the start port 35, specifically, on the condition that the game ball is detected by the start port sensor 34a or the start port sensor 35a and the start condition (start condition related to the special pattern) is met (if there is only one type of loss, there is no need to draw a type lottery for the loss, so that lottery can be omitted), and based on the lottery result information, determines the change pattern of the special pattern and the special pattern (hereinafter referred to as the 'special stop pattern') to be finally stopped and displayed depending on the type of win.

[0091] Then, the main control board 20 transmits a "variation pattern designation command" including at least special symbol variation pattern information (for example, information on the jackpot lottery result and the variation time of the special symbols) to the performance control board 30 as a performance control command that specifies the processing state. This sends basic information required for the decorative symbol variation display game to the performance control board 30. In this embodiment, in order to increase the variety of performances, a "decorative symbol designation command" including special stop symbol information (symbol lottery result information (information on the type of win)) is also transmitted to the performance control board 30.

[0092] The special symbol variation pattern information can include information specifying whether or not a specific preview effect (such as a "reach effect" or "pseudo consecutive effect" described below) will occur. Specifically, the variation patterns of the special symbols are roughly divided into a "win variation pattern" in the case of a win and a "miss variation pattern" in the case of a miss, depending on the result of the jackpot lottery. These variation patterns include, for example, a "reach variation pattern" that specifies the occurrence of a reach effect (described below), a "normal variation pattern" that does not specify the occurrence of a reach effect, a "reach variation pattern with pseudo consecutive effects" that specifies the occurrence (overlapping occurrence) of a pseudo consecutive effect and a reach effect, and a "normal variation pattern with pseudo consecutive effects" that specifies the occurrence of a pseudo consecutive effect but does not specify the occurrence of a reach effect. Note that, in order to ensure the duration of the reach effect or pseudo consecutive effect, the variation time of a variation pattern that specifies a reach effect or pseudo consecutive effect is usually set to be longer than that of a normal variation pattern.

[0093] Based on information contained in the effect control commands (here, the variation pattern designation command and the decorative symbol designation command) sent from the main control board 20, the effect control board 30 determines the effect content (effect scenario, such as preview effects) to be developed in chronological order during the decorative symbol variation display game and the decorative symbols (decorative stop symbols) to be ultimately displayed. The effect control board 30 then executes the decorative symbol variation display game by displaying the decorative symbols in a variable manner according to a time schedule based on the variation pattern of the special symbols. As a result, the decorative symbols displayed by the main LCD display device 36M are displayed in a variable manner in time with the variable display of the special symbols by the special symbol display devices 38a and 38b, so that the duration of the special symbol variation display game and the duration of the decorative symbol variation display game are substantially the same. The effect control board 30 also controls the main LCD display device 36M, the light display device 45a, or the sound generating device 46a in accordance with the effect scenario to develop various effects in the decorative symbol variation display game. This allows the main liquid crystal display device 36M to reproduce images (image effects), reproduce sound effects (sound effects), and light and flash the decorative lamps 45, LEDs, etc. (light effects).

[0094] In this way, the special symbol variation display game and the decorative symbol variation display game have an inseparable relationship, and the display results of the special symbol variation display game are reflected in the decorative symbol variation display game, so these two symbol variation display games can be considered as equivalent symbol games. In this specification, unless otherwise necessary, the above two symbol variation display games may be simply referred to as "pattern variation display games."

[0095] (Normal pattern change display game) Furthermore, in the gaming machine 1, when a gaming ball passes (wins) through the normal symbol starting hole 37, a "auxiliary win lottery" is conducted by random number lottery on the main control board 20. Based on the result of this lottery, the normal symbol represented by the LED is displayed variably on the composite display device 38d to start the normal symbol variable display game, and after a certain time has passed, the result is displayed as a combination of lit and unlit LEDs. For example, if the result of the normal symbol variable display game is a "auxiliary win," the normal symbol display section of the composite display device 38d is displayed as a static display in a specific lighting state (for example, all two LEDs 39 are lit, or of the LEDs representing a "circle" and an "x," only the LED on the "circle" side is lit).

[0096] When this "auxiliary win" occurs, the normal electric accessory solenoid 41c (see Figure 3) is activated, which opens the movable wing piece and opens or enlarges the starting hole 35, making it easier for game balls to flow in (starting hole open state), creating an auxiliary game state (hereinafter referred to as "normal electric open game") that is more advantageous to the player than the normal game state. In this normal electric open game, the movable wing piece opens or enlarges the winning area until the opening time of the starting hole 35 has elapsed for a predetermined time (e.g., 0.2 seconds) or until the number of game balls that have entered the starting hole 35 reaches a predetermined number (e.g., 4), and when either of these conditions is met, the starting hole 35 is closed, and this operation is repeated a predetermined number of times (e.g., up to twice).

[0097] (Regarding reservations) In this embodiment, when a winning entry occurs in the start slot 34, 35, or 37 during a special / decorative symbol change display game, a normal symbol change display game, a jackpot game, or a normal power-on game, i.e., when a detection signal is input from the start slot sensor 34a, 35a, or 37a and the corresponding start condition (symbol game start condition) is met, this data is reserved and stored as data related to the right to start the change display game, up to a predetermined maximum number of reserved data (e.g., up to four), excluding data related to the change display. This reserved data not used for the change display operation, or the game balls related to this reserved data, are also referred to as "activated reserved balls." To inform the player of the number of activated reserved balls, a dedicated reserved ball indicator (not shown) located in an appropriate location on the gaming machine 1 or a reserved ball indicator displayed as an icon image on the LCD display 36 (main LCD display 36M or sub LCD display 36S) is illuminated.

[0098] In this embodiment, up to four activation reserved balls for each of special symbol 1, special symbol 2, and normal symbol are reserved and stored in the corresponding storage area of ​​the main control RAM 20c, and are reserved as the number of times the special symbol or normal symbol changes. Note that there is no particular limit on the maximum number of activation reserved balls (maximum reserved memory number) for special symbol 1, special symbol 2, and normal symbol. Also, all or part of the maximum reserved memory number for each symbol may be different, and the number can be determined appropriately depending on the gameplay.

[0099] [3.3 About winning] Next, a "win" in the gaming machine 1 will be described. In the gaming machine 1 of this embodiment, a jackpot lottery (winning lottery) is conducted for multiple types of winnings. In this example, the winning types include, for example, "normal 4R," "normal 6R," "probable 6R," and "probable 10R" belonging to the jackpot type. The above notation "R" means the specified number of rounds (maximum number of rounds).

[0100] The type of jackpot is the hit that triggers the activation of the conditional device. Here, the "conditional device" refers to a device whose operation is a necessary condition for the activation of the consecutive device for playing rounds, and which is activated when a specific combination of special symbols is displayed or when the game ball passes through a specific area inside the jackpot opening.

[0101] The probability variable state is a so-called "number cut probability variable machine (ST machine)" that ends the high probability state and transitions to a low probability state when the special symbol variation display game has been executed a predetermined number of times (for example, 70 times: the specified ST number of times) without winning a jackpot type, and when the specified ST number of times has been completed, the next game will transition to a normal state. However, it may also be a "general probability variable machine" that continues until the next jackpot is won.

[0102] The number of times the special symbol variation display game is executed may be the total number of times the special symbol variation display game 1 and the special symbol variation display game 2 are executed (the total number of changes in special symbol 1 and special symbol 2), or it may be the number of times either one of them is executed (for example, the number of times the special symbol variation display game 2 is executed). In addition, the number of times the time-saving state is executed is not limited to 60 times or 100 times, and can be determined appropriately depending on the gameplay. In addition, there is no particular restriction on the type of winning to be set, and it can be determined appropriately.

[0103] In this example, similar to the jackpot types, multiple types of "losses" are provided. Specifically, three types of losses, "loss 1," "loss 2," and "loss 3," are provided. As mentioned above, if the result of the lottery is a "lose," a lottery for the type of loss will be held in the pattern lottery.

[0104] [3.4 Production] (Performance mode) Next, the presentation modes (presentation states) will be explained. The gaming machine 1 of this embodiment is provided with a plurality of presentation modes for producing presentations related to the game state, and is configured to be able to switch between these presentation modes. Specifically, a normal presentation mode, a time-saving presentation mode, a potential probability presentation mode, and a probability variable presentation mode are provided, which correspond to the normal state, the time-saving state, the potential probability state, and the probability variable state, respectively. In each presentation mode, the background display as the background of the decorative pattern variation display screen is displayed with a different background presentation, so that the player can understand what game state he or she is currently in.

[0105] The presentation control board 30 (presentation control CPU 30a) has a functional unit (presentation state transition control means) that controls transitions between multiple presentation modes. The presentation control board 30 (presentation control CPU 30a) is configured to grasp the current game state and control transitions between multiple presentation modes in a manner that maintains consistency with the game state managed by the main control board 20 based on specific presentation control commands sent from the main control board 20 (main control CPU 20a), specifically, presentation control commands that include game state information managed by the main control board 20. Examples of such specific presentation control commands include a variation pattern designation command, a decorative symbol designation command, and a game state designation command sent when a change occurs in the game state.

[0106] (Preview performance) Next, the preview effects will be explained. The effect control board 30 is configured to be able to control the appearance of various "preview effects" related to the current presentation mode and the result of the jackpot lottery, based on the contents of the presentation control command from the main control board 20, specifically, based on at least the variation pattern information included in the variation pattern designation command. Such preview effects suggest (preview) the expected probability of winning a particular type of win (hereinafter referred to as "expected probability of winning"), and act as "hype effects" to heighten the player's anticipation of winning. Typical preview effects include "reach effects," "pseudo consecutive effects," and even "predictive preview effects." The effect control board 30 functions as a preview effect control means capable of controlling the execution (appearance) of these effects.

[0107] "Reach effect" refers to an effect mode accompanying a reach state (variable display mode accompanying a reach state: reach variation pattern), and more specifically, an effect mode in which the final game result is derived and displayed via a reach state. Reach effects include multiple types of reach effects associated with the probability of winning. For example, there are some in which the probability of winning is relatively higher than when a normal reach effect appears. Such reach effects are called 'super reach effects'. Many of these "super reaches" have a relatively longer presentation time (variation time) than normal reaches to increase the expectation of winning. Furthermore, normal reaches and super reaches include multiple types of reach effects. In this example, super reaches include multiple types of reach effects, namely Super Reach 1, 2, 3, and 4, and the probability of winning of these Super Reaches 1 to 4 has the following relationship: "Super Reach 1 < Super Reach 2 < Super Reach 3 < Super Reach 4."

[0108] "Pseudo consecutive effects" refers to an effect mode accompanied by a pseudo continuous change display state (pseudo consecutive changes) of decorative symbols, and "pseudo consecutive changes" refers to a change display mode in which, during a decorative symbol change display game, some or all of the decorative symbols are temporarily stopped, and then a change display operation of the decorative symbols is executed again from that temporary stop state, and this display operation is repeated once or multiple times. In this respect, it differs from the "prediction notice effect (continuous notice effect)" described below, which is developed across multiple symbol change display games. The occurrence rate (appearance rate) of such "pseudo consecutive effects" is basically set so that the more pseudo changes there are, the higher the probability of winning. For example, depending on the number of pseudo changes, effects that stimulate expectations such as a super reach are more likely to be selected.

[0109] "Prediction prediction effect" (hereinafter sometimes abbreviated as "prediction prediction" or "prediction effect") refers to an effect that notifies the player of the possibility of being controlled to an advantageous state before the variable display of the symbol to be judged is carried out based on the results of the prediction judgment. "Advantageous state" means a state that is advantageous to the player. Specifically, the pre-reading effect in this example is performed in a presentation mode that can notify the winning expectation in advance of an activation reserved ball (an unconsumed activation reserved ball) that has not yet been used for the execution of a pattern change display game (the operation of displaying the variation of special patterns), by mainly utilizing the reserved display mode and the background presentation of the pattern change display game that is executed first, before the activation reserved ball is used for the pattern change display game. In addition to the above-mentioned "reach presentation," various presentations such as the so-called "SU (step-up) notice presentation," "timer notice presentation," "revival presentation," and "premium notice presentation" are generated in the pattern change display game, to liven up the game content.

[0110] Here, with reference to FIG. 4, the "hold change notice effect" will be described as an example of the above-mentioned look-ahead notice effect. In the gaming machine 1 of this embodiment, the upper display area of ​​the screen of the main liquid crystal display device 36M is provided with a display area for displaying the decorative symbol change display game (a display area for displaying decorative symbol change display effects and preview effects), and the lower display area of ​​the screen is provided with a reserved display area 76 (reserved display sections a1 to d1) that displays the number of activated reserved balls on the special symbol 1 side, and a reserved display area 77 (reserved display sections a2 to d2) that displays the number of activated reserved balls on the special symbol 2 side. The presence or absence of activated reserved balls is notified by a predetermined reserved display mode. Figure 5 shows an example in which the presence or absence of activated reserved balls is indicated by a lit state (activated reserved ball present: "○ (white circle)" shown in the figure) or an unlit state (no activated reserved ball present: dashed circle shown in the figure), and information regarding the current number of activated reserved balls is notified.

[0111] The display (reserved display) indicating the presence or absence of activated reserved balls is displayed sequentially in the order of occurrence (winning order), and in each reserved display area 76, 77, the leftmost activated reserved ball is displayed as the activated reserved ball that occurred first on the time axis (i.e., the oldest) among all activated reserved balls in that reserved display. Also, to the left of the reserved display areas 76, 77, a changing display area 78 is provided to indicate the activated reserved ball currently being used in the special symbol variable display game. In this embodiment, the changing display area 78 is configured to display an image in which the icon of the game-in-progress reserved ball K currently being used in the game is placed on the icon of the seat J. That is, when the variable display of special symbol 1 or special symbol 2 begins, the icon (icon image) of the oldest reserved ball a1 or a2 displayed in the reserved display area 76, 77 moves to the icon of the seat J in the changing display area 78 as the icon of the game-in-progress reserved ball K, and this state is maintained for a predetermined display time.

[0112] When an activated pending ball occurs, the main control board 20 sends a "pending addition command" to the performance control board 30, which specifies the advance reading judgment information related to the jackpot lottery result and the number of activated pending balls at the time of advance reading judgment (the number of currently existing activated pending balls, including the activated pending ball that has occurred this time) (see steps S1309 to S1312 in Figure 28). In this embodiment, the above-mentioned reserve addition command is composed of two bytes, and the reserve addition command is composed of data on the upper byte side that enables the number of active reserved balls to be identified at the time of the pre-reading judgment, and data on the lower byte side that enables the pre-reading judgment information to be identified.

[0113] As can be understood from the above explanation, in this embodiment, when a winning entry occurs in the start hole 34 or the start hole 35 and a new reserved ball is generated, a jackpot lottery is held for the symbol variation display game related to the reserved ball as a pre-reading judgment for the reserved ball. As will be described later, the main control board 20 reserves and stores information representing the result of the jackpot lottery held as such a pre-reading judgment in a corresponding storage area of ​​the main control RAM 20c. The information on the jackpot lottery result obtained at the time of the look-ahead judgment is used to select (lottery) the pattern variation pattern in the pattern variation display game, and can be said to be "variation pattern selection information." Therefore, it can be said that the main control board 20 performs the look-ahead judgment and reserves and stores the "variation pattern selection information" obtained as a result in a predetermined area of ​​the main control RAM 20c.

[0114] When the performance control board 30 receives the above-mentioned hold addition command sent by the main control board 20, it performs performance control processing for the "pre-reading notice performance" as part of the display control processing related to the above-mentioned hold display based on the pre-reading judgment information contained therein. Specifically, it performs a "pre-reading notice lottery" to draw whether or not the pre-reading notice performance can be executed, and if it is won, it makes the pre-reading notice performance appear.

[0115] Here, the pre-reading judgment information is specifically game information obtained by pre-reading the jackpot lottery result (jackpot lottery result at the start of the variation) executed when the activation reserved ball is provided to the pattern variation display game in the main control board 20 and the variation pattern at the start of the variation. That is, this information includes at least information that pre-reads and judges the lottery result at the start of the variation (pre-reading win / loss information), and can also include information that pre-reads and judges the pattern lottery result (pre-reading pattern information) and information that pre-reads and judges the variation pattern at the start of the variation (pre-reading variation pattern information). The information included in the reserved addition command to be sent to the performance control board 30 can be determined appropriately depending on the content to be notified in the pre-reading notice. In this example, the pending addition command includes pre-reading winning / losing information, pre-reading pattern information, and pre-reading variation pattern information.

[0116] It should be noted that the "pre-read fluctuation pattern" obtained by the pre-read judgment when the activation pending ball occurs does not necessarily have to be the "fluctuation pattern at the start of fluctuation" itself obtained when the activation pending ball is actually used for the fluctuation display operation. For example, to explain a representative case where the fluctuation pattern at the start of fluctuation is a fluctuation pattern that specifies "Super Reach 1", in this case, it is possible to specify that the content specified by the pre-read fluctuation pattern is not the type of reach performance itself called "Super Reach 1", but rather its essential "Super Reach type".

[0117] In this embodiment, if the advance notice lottery is won, a "hold display change" advance notice performance (also referred to as a "hold change notice") is performed in which the hold icon that is the subject of the advance notice among the hold icons in the hold display sections a1 to d1, a2 to d2 is changed from the white of the normal hold display (normal hold display mode) to a hold display (special hold display mode) with a notice display of blue, green, red, or a danger pattern (or special colors or patterns such as rainbow colors). In Figure 5, the hatched reserved ball in the reserved display section b1 is shown as an example of a change to a special reserved display. Here, the display of the reserved icon in blue, green, red, and danger pattern indicates a higher probability of winning in this order, and the display of the reserved icon in danger pattern is a premium reserved icon that indicates an extremely high probability of winning a jackpot.

[0118] (Direction means) Various effects in the gaming machine 1 are produced by the effect means provided in the gaming machine 1. These effect means may be any stimulus transmission means capable of producing effects by appealing to human senses, such as sight, hearing, or touch. Representative examples include light-generating means (light display device 45a: light effect means) such as decorative lamps 45 and LED devices, sound-generating devices (sound generating device 46a: sound effect means) such as speakers 46, effect display devices (display means) such as the main LCD display device 36M and the sub-LCD display device 36S, pressure devices that transmit contact pressure to the operator's body, wind pressure devices that apply wind pressure to the player's body, and movable gadgets that produce visual effects through their movement. Here, effect display devices, like image display devices, are visually appealing displays, but differ from image display devices in that they also include devices that do not rely on images (e.g., 7-segment displays). The term "image display device" primarily refers to a type that produces effects by displaying images; devices that produce effects through means other than images, such as 7-segment displays, are included within the concept of effect display devices.

[0119] <4. Opening and closing structure and board layout> The configuration shown in Figure 3 is actually realized via multiple boards. Below, we will explain the arrangement of some of the boards installed in the gaming machine 1. We will also explain the opening and closing structure of the gaming machine 1 in relation to the installation position of the boards.

[0120] FIG. 5 shows the door 6 in an open state. When the door 6 is opened, the inner frame 2 and the game board 3 attached to the inner frame 2 are directly exposed. The board arranged on the door 6 and the board arranged on the inner frame 2 are connected by wiring using a harness as a transmission line H8.

[0121] The gaming machine 1 is also configured so that the inner frame 2 can be opened relative to the outer frame 4. Figure 6 shows the state in which the inner frame 2 is open. When the inner frame 2 is opened, the game board 3 attached to the inner frame 2 is also released from the outer frame 4. Figure 6 shows the state in which the back cover 18 attached to the position on the back side of the game board 3 is visible. Although the game board 3 is not shown in Figure 6, the back side of the game board 3 is exposed when the back cover 18 is removed (opened). In reality, the back cover 18 is transparent or semi-transparent, so the back side of the game board 3 can be seen in the state shown in Figure 6. The game board 3 can also be removed from the inner frame 2.

[0122] Thus, the gaming machine 1 is broadly composed of an outer frame 4, an inner frame 2 attached to the outer frame 4, a gaming board 3 attached to the inner frame 2, and a door 6 located in front of the gaming board 3 and the inner frame 2. Various boards are attached to either the gaming board 3, the inner frame 2, or the door 6.

[0123] Figure 7 shows the positions of some of the boards attached to the game board 3. Note that Figure 7 shows the boards attached to the back side of the play area 3a when the game board 3 is viewed from the rear side. Therefore, the right side of the figure is the left side when the game board 3 is viewed from the front side. In the figure, the outline of the frame of the game board 3 is shown with a dashed line to indicate the position.

[0124] As shown in the figure, on the back side of the game board 3, the performance control board 30 is placed slightly above the center, and the main control board 20 is placed below that. In addition, a liquid crystal control board 901 is placed so as to overlap with the performance control board 30, and a ROM board 902 and a liquid crystal interface board 903 are placed nearby.

[0125] An LED connection board 700 is disposed on the left side of the rear surface of the game board 3, and a power supply module board 904 is disposed near the top thereof. In addition, an upper connection board 905 is disposed above the game board 3.

[0126] Near the main control board 20, a relay board 800, a frame LED relay board 840, a power supply relay board 40, a game board connection board 906, etc. are arranged. Although not shown, there is also a substrate attached to a movable accessory (not shown) attached to the game board 3.

[0127] 8 shows the positions of some of the circuit boards attached to the door 6 as seen from the front side of the gaming machine 1. As a guide to the positions of the components inside the gaming machine 1, the door 6, the effect button 13, the firing operation handle 15, and the upper speaker 46 are shown by dashed lines.

[0128] A relay board 550 is provided above the door 6 . Similarly, a side unit upper LED board 630 is provided above the door 6, a side unit upper right LED board 600 is provided at the top right of the door 6, and a side unit lower right LED board 620 is provided below that. The side unit upper right LED board 600, side unit lower right LED board 620, and side unit upper LED board 630 are attached inside the side unit 10 (see FIG. 1), and when the side unit 10 is attached to the door 6, each board is positioned as shown in FIG.

[0129] A frame left LED board 907 is disposed at the upper left side of the door 6, and a frame left lower LED board 908 is disposed below it. In addition, a front frame LED connection board 500 is disposed below the door 6. In addition, a button LED connection board 640 is arranged at the bottom right, and a button LED board 660 is arranged inside the performance button 13.

[0130] Next, we will explain the position of the board attached to the inner frame 2. Figure 9 is a view of the gaming machine 1 as seen from the back. Most of the back side of the gaming machine 1 is protected by a transparent or semi-transparent back cover 18. Below this rear side, a power supply board 300 and a dispensing control board 29 are arranged in front and behind. Also, an inner frame LED relay board 400 is attached to the lower right side when viewed from the rear side.

[0131] 10 shows the positions of various devices arranged on the door 6 and the game board 3. The outlines of the game board 3 and the door 6 are shown by dashed lines to indicate the position of each device.

[0132] 10, the devices provided in the side unit 10 of the door 6 are a side unit device 101, a side unit lower right movable object position detection switch 102, a side unit lower right movable object motor 103, a side unit upper right movable object motor 104, a side unit upper right movable object solenoid 105, a blower 106, and photocouplers PC1F, PC2F, and PC3F, which are arranged at the positions shown in the figure. The photocouplers PC1F, PC2F, and PC3F are attached to the side unit lower right LED board 620.

[0133] In addition, in Figure 10, the devices attached to the game board 3 include a lower rear movable object upper position detection switch 120, a lower rear movable object right position detection switch 121, a distribution position detection switch 122, a lower front movable object position detection switch 123, a lower front movable object motor 124, a lower rear movable object left position detection switch 125, a lower rear movable object left motor 126, a lower rear movable object lower right position detection switch 127, a lower rear movable object lower left position detection switch 128, an upper movable object left motor 129, an upper movable object left position detection switch 130, a left movable object motor 131, an upper movable object position detection switch 132, an upper movable object right motor 133, a left movable object position detection switch 134, and a lower rear movable object right motor 135, each of which is arranged at the positions shown in the figure.

[0134] 7, 8, and 9 are merely a part of the boards provided in the gaming machine 1. The device shown in FIG.

[0135] <5. Circuit board configuration> [5.1 Connection status of each board] The connection configuration of each board arranged as described above will be explained, and the supply path of the power supply voltage will be mentioned.

[0136] FIG. 11 shows an example of the boards arranged on the game board 3, the inner frame 2, and the door 6, respectively. The figure shows the boards mounted on the game board 3 as main control board 20, performance control board 30, power supply relay board 40, relay board 800, decorative board 820, frame LED relay board 840, LED board 850, and LED board 860. The boards mounted on the inner frame 2 include a power supply board 300, a dispensing control board 29, and an inner frame LED relay board 400. The boards mounted on the door 6 include a front frame LED connection board 500, a relay board 550, a side unit upper right LED board 600, a side unit lower right LED board 620, a side unit upper LED board 630, a button LED connection board 640, and a button LED board 660.

[0137] Each of these boards is a part of the boards mounted on the gaming machine 1, and there are various types of boards other than those shown in the figure that are mounted on the gaming board 3, inner frame 2, and door 6. This Figure 11 shows the connection system of selected boards for use in explaining the technology as an embodiment, and does not show all of the boards.

[0138] The power supply board 300 is a board that supplies DC voltage as operating power to each part based on AC input power. The main control board 20, the performance control board 30, and the payout control board 29 are as described in Figure 3.

[0139] The front frame LED connection board 500 is a board for supplying operation control signals and power supply voltage to the LEDs provided on the door 6, the motors of the movable bodies, the solenoids, the blowers, and other performance means.

[0140] The side unit upper right LED board 600, the side unit lower right LED board 620, and the side unit upper LED board 630 are boards arranged inside the side unit 10, and constitute a drive control system for the LEDs and the modes of the movable props. These boards also constitute a detection system that transmits detection signals from the motor position sensors, touch sensors, and various other sensors to the performance control board 30. As described above, the side unit 10 is attached to the door 6 as one of the decorative units, and the side unit 10 is detachable and replaceable with respect to the door 6. The side unit upper right LED board 600, the side unit lower right LED board 620, and the side unit upper LED board 630 are detachable along with the side unit 10. When the side unit 10 is mounted and the relay board 550 and the transmission line H10 of the upper right LED board 600 of the side unit are connected, the electrical configuration shown in FIG. 11 is obtained.

[0141] The button LED board 660 configures the LEDs in the effect buttons 13 and their light emission drive system, and also includes circuits for transferring detection signals from various detection sensors. The button LED connection board 640 relays control signals and power supply voltage to the button LED board 660, and also transfers detection signals from various sensors.

[0142] The inner frame LED relay board 400 relays signals between the frame LED relay board 840, which is connected to the performance control board 30, and the front frame LED connection board 500, and also performs the necessary signal processing and generates and supplies power supply voltage. The frame LED relay board 840 relays the signal path between the inner frame LED relay board 400 and the performance control board 30.

[0143] The decorative board 820 and LED boards 850, 860 are mounted with LEDs on the game board 3 and emit light. The relay board 800 relays the light emission drive signals for the LEDs. In addition to those shown in the figure, multiple LED boards are mounted on the game board 3. Some of these LED boards are attached to movable role devices. For example, the relay board 800 and the decorative board 820 are attached to movable role devices. The decorative board 820 is also provided with a circuit for supplying a motor drive signal to the motor of the movable role device, for example.

[0144] The LED connection board 700 performs various signal processing required to drive the light emission of performance means such as LEDs and motors based on control signals from the performance control board 30.

[0145] These boards are electrically connected by harnesses and cables via transmission lines H. "Transmission lines H" is a general term for the transmission lines H1, H2, ... H41 shown in the figure. Each transmission line H generally comprises an individual wiring path for transmitting signals, power supply voltage, etc., and connectors connected to both ends of the path. In each transmission line H, when the individual wiring paths that transmit signals, power supply voltages, etc., that is, the electric wire portions, are to be distinguished from the connectors, they are also simply called "lines."

[0146] A transmission line H refers to a set of one or more lines. The transmission line H may take various forms such as a flexible harness, a flexible substrate, a wire harness, etc. The transmission line H may also be an integrated line formed by integrating multiple lines, or individual lines may be bound together with a binder, tape, or the like. Furthermore, when connectors are directly connected to each other, the terminals of the connectors become the transmission line H. In other words, even when there is no wire material such as a harness, it is included in the "transmission line H". That is, the transmission line H does not refer to a specific type or shape, but rather refers broadly to anything that forms electrical wiring between substrates, etc.

[0147] The power supply board 300 and the dispensing control board 29 are connected by a transmission line H1. The power supply board 300 and the inner frame LED relay board 400 are connected by a transmission line H3. These transmission lines H1 and H3 are formed by harnesses or the like arranged within the inner frame 2.

[0148] The power supply board 300 and the power supply relay board 40 are connected by a transmission line H2, and the power supply relay board 40 and the performance control board 30 are connected by a transmission line H18. The dispensing control board 29 and the main control board 20 are connected by a transmission line H4. The inner frame LED relay board 400 and the frame LED relay board 840 are connected by a transmission line H7. The transmission lines H2, H4, and H7 are formed by harnesses or the like that connect the inner frame 2 and the game board 3 across each other.

[0149] The main control board 20 and the performance control board 30 are connected by a transmission line H5. The performance control board 30 and the frame LED relay board 840 are connected by a transmission line H6. The performance control board 30 and the LED connection board 700 are connected by a transmission line H20. The LED connection board 700 and the relay board 800 are connected by a transmission line H30. The relay board 800 and the decorative board 820 are connected by a transmission line H31. The LED connection board 700 and the LED board 850 are connected by a transmission line H40. The LED connection board 700 and the LED board 860 are connected by a transmission line H41. These transmission lines H5, H6, H18, H20, H30, H31, H40, and H41 are formed by harnesses arranged within the game board 3.

[0150] The inner frame LED relay board 400 and the front frame LED connection board 500 are connected by a transmission line H8. This transmission line H8 is formed by a harness or the like that connects the inner frame 2 and the door 6 across the space between them.

[0151] The front frame LED connection board 500 and the relay board 550 are connected by a transmission line H9. The relay board 550 and the side unit upper right LED board 600 are connected by a transmission line H10. The side unit upper right LED board 600 and the side unit lower right LED board 620 are connected by a transmission line H11. The side unit upper right LED board 600 and the side unit upper LED board 630 are connected by a transmission line H12. The front frame LED connection board 500 and the button LED connection board 640 are connected by a transmission line H15. The button LED connection board 640 and the button LED board 660 are connected by a transmission line H16. These transmission lines H9, H10, H11, H12, H15, and H16 are formed by harnesses or the like arranged inside the door 6.

[0152] Between these boards, the transmission lines mentioned above carry out the transmission of control signals for effects such as LED illumination, motor-driven operation of movable props, sound output, sensor signals for performance control, and even power supply voltage.

[0153] Here, FIG. 11 shows a serial output circuit 30d in the performance control board 30 that outputs light emission drive data as serial data mainly for the performance of LED light emission operation. As previously explained in Fig. 3, the performance control board 30 generates serial data that controls the operation of the optical display and the operation of the movable part motor 80c, and supplies it to the lamp driver unit 45d and the motor driver unit 80d from the serial output circuit 30d. In Fig. 11, the serial output circuit 30d outputs two lines of serial data via transmission lines H20 and H6.

[0154] The serial output circuit 30d outputs drive data for effects to be supplied to the boards on the gaming board 3 via the transmission line H20 to the LED connection board 700. The drive data for effects includes light emission drive data for controlling LED light emission, motor drive data for operating motors for movable role objects, etc. The serial output circuit 30d also outputs drive data for effecting the display to the frame LED relay board 840 via the transmission line H6. In this way, the performance control board 30 outputs drive data by serial data, which can be broadly divided into drive data to the game board 3 side and drive data to the frame / door side.

[0155] The power supply board 300 shown in FIG. 11 will be described. The power supply board 300 supplies power supply voltage to each part via transmission lines H1, H2, and H3. FIG. 12 shows the power supply inputs and outputs for the power supply board 300. The power supply board 300 is equipped with connectors CN1A to CN7A. The connectors CN5A, CN6A, and CN7A are the transmission line ends of the transmission lines H40, H41, and H42, which are not shown in FIG.

[0156] Hereinafter, the connectors CN1A to CN7A, as well as connectors appearing in other drawings, will be collectively referred to as "connectors CN." In this specification, "connector CN" refers to a connector terminal component provided on a substrate. The connector CN formed at the end of a transmission line H may be called a "transmission line end." In this case, the connector CN is generally formed of a socket housing side fixed on the substrate and a contact housing side joined to the socket housing, and these socket housing and contact housing are collectively called the "transmission line end."

[0157] A 24V AC power supply is supplied from the power plug 301 of the gaming machine 1 to the three-terminal connector CN5A via a transmission line H40 (AC-IN(A), AC-IN(B)). Also, an FG (frame ground) path (FG) is formed via the ground terminal 302, the transmission line H40, and the connector CN5A. The ground terminal 302 is connected to the outside of the gaming machine main body, for example.

[0158] A transmission line H41 is connected to the two-terminal connector CN6A, and an FG path (FG-1) is formed via ground terminals 303 and 304. The ground terminals 303 and 304 are connected to, for example, a metal plate portion of the gaming machine 1 that the gaming ball does not come into contact with. A transmission line H42 is connected to the two-terminal connector CN7A, forming an FG path (FG-2) via ground terminals 305 and 306. The ground terminals 305 and 306 are connected to, for example, sheet metal parts in the gaming machine 1 that the gaming balls come into contact with, such as the ball tank, the sheet metal of the upper tray, and the launch rail. The purpose of this is to separate earths with low noise from earths with high noise.

[0159] In the power supply board, AC 24V power is input to an AC / DC converter 311, which outputs an internal DC voltage V1 of a predetermined voltage value. The internal DC voltage V1 is then input to a DC / DC converter 312, which generates a 5V DC voltage (DC5V) as an output. The internal DC voltage V1 is input to a DC / DC converter 313, which generates a 12V DC voltage (DC12V) as an output. The internal DC voltage V1 is also input to a DC / DC converter 314, which generates a 35V DC voltage (DC35V) as an output.

[0160] The generated 5V DC voltage (DC5V), 12V DC voltage (DC12V), and 35V DC voltage (DC35V) are then supplied to each component via connectors CN1A, CN2A, and CN3A. That is, it outputs 5V DC voltage (DC5VA) (DC5VB) based on 5V DC voltage (DC5V), 12V DC voltage (DC12VA) (DC12VB) based on 12V DC voltage (DC12V), and 35V DC voltage (DC35VA) (DC35VB) based on 35V DC voltage (DC35V).

[0161] A transmission line H1-1 is connected to the 14-terminal connector CN1A. A transmission line H1-2 is also connected to the 3-terminal connector CN4A. These two transmission lines H1-1 and H1-2, which serve as harnesses, are shown as the transmission line H1 in Figure 11. A 35V DC voltage (DC35VA), a 12V DC voltage (DC12VA), and a 5V DC voltage (DC5VA) are supplied to the dispensing control board 29 via the transmission line H1-1, and a ground path (GND) is also formed. A 24V AC voltage (AC24VA, AC24VB) is supplied to the dispensing control board 29 via the transmission line H1-2, and an FG path (FG) is also formed.

[0162] A 35V DC voltage (DC35VA), a 12V DC voltage (DC12VA), and a 5V DC voltage (DC5VA) are supplied to the main control board 20 via the dispensing control board 29, and a ground path (GND) is also formed.

[0163] A transmission line H2 is connected to the 20-terminal connector CN2A. Transmission line H2 supplies 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) to the performance control board 30 via the power supply relay board 40, and also forms a ground path (GND).

[0164] Based on the power supply via this transmission line H2, 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) are supplied from the performance control board 30 to the LED connection board 700, and are used as operating power sources for the LED connection board 700 and each downstream board (relay board 800, decorative board 820, LED boards 850, 860, etc.). On the other hand, the frame LED relay board 840 is a board that simply has relay wiring and does not require a power supply voltage, and no power supply voltage is supplied from the performance control board 30.

[0165] For the purpose of explanation, the terms "upstream" and "downstream" are used, but in terms of data and control signals, the main control board 20 is the most upstream, followed by the performance control board 30, and the "downstream" direction is from the performance control board 30 toward the actual performance devices such as LEDs and motors. With regard to the power supply voltage, power supply board 300 is the most upstream, and is "downstream" toward the actual performance device.

[0166] The transmission line H3 is connected to the six-terminal connector CN3A. A 12V DC voltage (DC12VB) is supplied to the inner frame LED relay board 400 via the transmission line H3, and a ground path (GND) is also formed. In other words, the inner frame LED relay board 400 is a board that is controlled by the performance control board 30, but is configured to receive power supply voltage directly from the power supply board 300. The inner frame LED relay board 400 supplies power supply voltage to each board (such as the front frame LED connection board 500) provided on the door 6 downstream of the inner frame LED relay board 400.

[0167] Components mounted on the power supply board 300 are shown in Fig. 13. Connectors CN1A to CN7A shown in Fig. 12 are arranged near the edges of the approximately rectangular board. Electrolytic capacitors C106, C201, C202, C203, C501, C502, C601, C701, and C801, transformer L1A, coils L201, L501, L601, L701, and L801, etc. are also arranged. IC chips 201A, 202A, and 501A, switch SW1, etc. are also arranged. The IC chip 201A is a power factor correction circuit, the IC chip 202A is a full-wave rectifier circuit, and the IC chip 501A is a DC / DC converter. Although only some electronic components have been mentioned above, these are insertion-mount components that are mounted by inserting lead wires into through-hole vias.

[0168] Also available are tube-type, for example glass tube-type fuses FZ1A, FZ301, and FZ401, as well as terminal insertion-type lead wire fuses FV501, FZ601, and FZ701, which are fixed by inserting lead wires into through-hole vias. Tube-type fuses include those with a structure in which a fuse cartridge with a fuse element inside a glass tube is held by a fuse holder fixed to a circuit board, those with a mounting part connected to a base of the glass tube and fixed to the circuit board with a bolt, and those with lead wires attached to the base of the glass tube that are inserted into through-hole vias and fixed in place by soldering. There are also fuses that use ceramic tubes instead of glass tubes.

[0169] A terminal insertion type fuse is a fuse in which connection terminals are provided on a highly heat-resistant exterior resin. As described above, a fuse in which lead wires are attached to the base of a glass tube can be said to be both a tube-type fuse and a terminal insertion-type fuse.

[0170] Generally, tube-type and terminal insertion-type fuses are used in locations where a higher fusing current is required than chip-type and surface-mount fuses, and are larger in component size than chip-type fuses.

[0171] Although a detailed description will be omitted, surface-mounted components such as resistors and capacitors are also mounted on the front surface layer shown in FIG. 13 and the back surface layer (not shown).

[0172] [5.2 Transmission path between the performance control board and the LED connection board] Below, we will focus on the transmission line H20 between the performance control board 30 and the LED connection board 700 and explain examples of single-line transmission and double-line transmission as transmission line configurations.

[0173] First, an example of single-system transmission will be described with reference to Fig. 14. The single-system transmission example is an example in which a transmission line H20 between the performance control board 30 and the LED connection board 700 is configured using a pair of connectors. FIG. 14 shows an example of pin assignments for the connector CNe1 on the performance control board 30 and the connector CN1 on the LED connection board 700.

[0174] In the embodiment, the pins serving as the terminals of the connector CN are considered to be approximately cylindrical, but examples of terminal shapes other than pin shapes are also considered for the connector CN. In the case of approximately cylindrical pins, the cross-sectional size of the pin means the diameter of the pin, but if plate-shaped pins, elliptical pins, and the like are also considered, the cross-sectional size of the pin can be considered to be the longest size of the pin cross section. Alternatively, since the cross section of the pin affects the current capacity, the cross-sectional size of the pin may be considered as the area of ​​the cross section.

[0175] The connectors CNe1 and CN1 are 40-pin connectors, and lines are formed corresponding to each of the 40 pins, through which various signals are transmitted.

[0176] As shown in FIG. 14, a total of 16 pins, namely, pin 1, pin 2, pin 8, pin 9, pin 10, pin 16, pin 18, pin 19, pin 20, pin 22, pin 29, pin 32, pin 33, pin 34, pin 39, and pin 40, are assigned to ground (GND).

[0177] A total of six pins, pins 12, 14, 24, 26, 28, and 30, are assigned to the first power supply voltage, 12V DC (DC12VB). The two pins, pins 4 and 6, are assigned to the second power supply voltage, 5V DC (DC5VB). Two pins, pins 36 and 38, are assigned to the third power supply voltage, 35V DC (DC35VB).

[0178] In addition, various performance control signals are transmitted via transmission line H20. The term "performance control signal" refers to various signals used to operate the performance means, including, for example, a light emission control signal for illuminating the LED of the performance means, a motor drive control signal for driving and controlling the motor of the movable role of the performance means, and a drive control signal for driving and controlling the blower or vibration device. Also included in the performance control signal are signals transmitted to the performance control board 30 for performance control, such as detection signals from various sensors related to the performance, such as a movable body origin sensor or a sensor that detects user operation, or signals that have been converted from detection signals into serial data. This is because the performance control board determines the game status based on these detection signals and controls the performance.

[0179] These performance control signals are often transmitted as a set of multiple signals for performance control of a specific purpose. For example, a set of light emission control signals, which is a type of performance control signal, may be a set of a light emission control data signal based on serial data and a clock signal, or may also include an enable signal, a reset signal, and other signals.

[0180] In the example of FIG. 14, four sets of performance control signals are transmitted. The first set is a set of a clock signal LED_CLK, a data signal LED_DATA, and an enable signal LED_ENABLE. The clock signal LED_CLK is assigned to pin 13, the data signal LED_DATA to pin 15, and the enable signal LED_ENABLE to pin 17.

[0181] The clock signal LED_CLK, data signal LED_DATA, and enable signal LED_ENABLE are performance control signals (light-emission control signals) supplied to the LED connection board 700 and LED drivers on further downstream boards. The data signal LED_DATA is a serial data signal for controlling the light-emission brightness of the LEDs connected to the LED drivers downstream of the LED connection board 700 using PWM control.

[0182] The second set consists of the clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST. The clock signal LSI_CLK is assigned to pin 3, the serial data signal LSI_IN_DATA to pin 5, the enable signal LSI_ENABLE to pin 7, the data signal LSI_DATA to pin 35, and the reset signal LSI_RST to pin 37.

[0183] The clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST are performance control signals (motor drive control signals) supplied to an IC for motor control in the LED connection board 700. The data signal LSI_DATA is a serial data signal including control data for motor control. In addition, the IC for motor control has the function of converting various detection signals into serial data, and can transmit this as a serial data signal LSI_IN_DATA to the upstream performance control board 30.

[0184] The third group is a group consisting of a clear signal CLR_X, a data signal DATA_X, and a latch signal LATCH_X. The clear signal CLR_X is assigned to pin 21, the data signal DATA_X to pin 25, and the latch signal LATCH_X to pin 27. These clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X are unused signals in the configuration example of the LED connection board 700 described later. However, when using the performance control board 30 due to a model change, etc., they can be used as performance control signals.

[0185] The fourth set is a set of a load signal S_IN_LOAD, a clock signal S_IN_CLK, and a serial data signal S_IN_DATA. The load signal S_IN_LOAD is assigned to pin 11, the clock signal S_IN_CLK to pin 23, and the serial data signal S_IN_DATA to pin 31. The LED connection board 700 is equipped with a parallel / serial conversion circuit (P / S conversion circuit) and has the function of converting various detection signals input in parallel into serial data. The P / S conversion circuit performs P / S conversion processing based on the load signal S_IN_LOAD and clock signal S_IN_CLK supplied from the performance control board 30 to the LED connection board 700, and outputs a plurality of detection signals collectively as a serial data signal S_IN_DATA. This serial data signal S_IN_DATA is transmitted to the upstream performance control board 30.

[0186] The above pin assignment is an example, but in a single-system transmission example, the various power supply voltages, grounds, and performance control signals are transmitted as described above via a pair of connectors CNe1, CN1 and the lines between them.

[0187] Next, an example of multiplex transmission will be explained. The duplicated transmission example is an example in which two pairs of connectors are used to configure transmission lines H20a and H20b between the performance control board 30 and the LED connection board 700. The transmission lines H20a and H20b are substitutes for the transmission line H20.

[0188] FIG. 15 shows an example of pin assignments for two connectors CNe1a and CNe1b mounted on the performance control board 30 and two connectors CN1a and CN1b mounted on the LED connection board 700. These two pairs of connectors are connected to form two transmission lines H20a and H20b between the performance control board 30 and the LED connection board 700. In other words, the transmission line that was combined in the single-system transmission example is now divided into two.

[0189] In this case, as an example, the transmission line H20a of the connectors CNe1a and CN1a has 16 lines as a 16-pin configuration. Therefore, the transmission line H20b of the connectors CNe1b and CN1b has 24 lines as a 24-pin configuration. This forms 40 lines, the same as the single-system transmission example.

[0190] In the pin assignment of the connectors CNe1a and CN1a, a total of seven pins, namely, the first pin, the second pin, the fourth pin, the sixth pin, the eighth pin, the ninth pin, and the tenth pin, are assigned to ground (GND).

[0191] Additionally, a total of six pins, from pin 11 to pin 16, are assigned to the first power supply voltage, 12V DC (DC12VB).

[0192] Of the above-mentioned performance control signals, the first set of clock signal LED_CLK, data signal LED_DATA, and enable signal LED_ENABLE are transmitted on the CNe1a, CN1a side. The clock signal LED_CLK is assigned to pin 3, the data signal LED_DATA to pin 5, and the enable signal LED_ENABLE to pin 7.

[0193] In the pin assignment of the connectors CNe1b and CN1b, a total of eight pins, namely the 5th pin, the 8th pin, the 10th pin, the 12th pin, the 14th pin, the 16th pin, the 17th pin, and the 18th pin, are assigned to ground (GND).

[0194] In addition, two pins, pin 1 and pin 3, are assigned to the second power supply voltage, 5V DC voltage (DC5VB). In addition, three pins, the second, fourth, and sixth pins, are assigned to the third power supply voltage, 35V DC (DC35VB).

[0195] Of the above-mentioned performance control signals, the second, third and fourth groups are transmitted on the connectors CNe1b and CN1b side.

[0196] For the second set of performance control signals, the clock signal LSI_CLK is assigned to pin 7, the serial data signal LSI_IN_DATA to pin 9, the enable signal LSI_ENABLE to pin 11, the data signal LSI_DATA to pin 13, and the reset signal LSI_RST to pin 15.

[0197] For the third set of performance control signals, the clear signal CLR_X is assigned to the 20th pin, the data signal DATA_X is assigned to the 22nd pin, and the latch signal LATCH_X is assigned to the 24th pin.

[0198] For the fourth set of performance control signals, the load signal S_IN_LOAD is assigned to the 19th pin, the clock signal S_IN_CLK is assigned to the 21st pin, and the serial data signal S_IN_DATA is assigned to the 23rd pin.

[0199] For ease of explanation, the transmission line H20a side, whose transmission line ends at connectors CNe1a and CN1a in the dual-system transmission example, will be called "system a," and the transmission line H20b side, whose transmission line ends at connectors CNe1b and CN1b, will be called "system b."

[0200] The connectors CNe1 and CN1 in the single-system transmission example can be connectors with two rows of 40 pins, as will be described later with reference to FIG. In the example of multiplexed transmission, the connectors CNe1a and CN1a of system a can be connectors with two rows of 16 pins, as will be described later with reference to FIG. In the example of multiple-system transmission, the connectors CNe1b and CN1b of system b can be connectors with two rows of 24 pins, as will be described later with reference to FIG.

[0201] By using such a two-row connector for the connectors CNe1a and CN1a of system a and the connectors CNe1a and CN1a of system b in the example of multiple-system transmission, the pin assignment arrangement on the connectors will be as shown in Figure 16. In Figure 16, the row of odd-numbered pin numbers is shown on the left side, and the row of even-numbered pin numbers is shown on the right side.

[0202] The odd-numbered rows of the a-system connectors CNe1a and CN1a are lined with ground (GND), clock signal LED_CLK, data signal LED_DATA, enable signal LED_ENABLE, ground, 12V DC voltage (DC12VB), 12V DC voltage, and 12V DC voltage pins. In addition, the even-numbered rows have the following pins lined up: ground (GND), ground, ground, ground, ground, 12V DC voltage (DC12VB), 12V DC voltage, and 12V DC voltage.

[0203] In the odd-numbered rows of the b-system connectors CNe1b and CN1b, there are pins for 5V DC voltage (DC5VB), 5V DC voltage, ground (GND), clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, reset signal LSI_RST, ground, load signal S_IN_LOAD, clock signal S_IN_CLK, and serial data signal S_IN_DATA. In addition, the odd-numbered columns are lined with pins for 35V DC voltage (DC35VB), 35V DC voltage, 35V DC voltage, ground (GND), ground, ground, ground, ground, ground, clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X.

[0204] The ground for system a and the ground for system b are a common ground. In other words, they are connected to a common ground line for the performance control board 30 and the LED connection board 700. It is possible to aggregate the grounds in either the harness for system a or system b, but a ground is assigned to each harness as a noise countermeasure.

[0205] In FIG. 16, the first, second, third, and fourth sets of performance control signals are indicated by the symbols "GP1," "GP2," "GP3," and "GP4."

[0206] [5.3 LED connection board] Next, the LED connection board 700 will be described. First, the circuit configuration formed on the LED connection board 700 will be explained using block diagrams in FIGS.

[0207] The LED connection board 700 transmits and receives power supply voltage and performance control signals to and from the performance control board 30. The performance control signals include signals that affect the operation of the performance means, such as control signals for performances such as light emission and various sensing signals. FIG. 17 shows the configuration around the above-mentioned connector CN1 (or CN1a, CN1b).

[0208] When a single-system transmission example is adopted, a transmission line H20 between the performance control board 30 and the connector CN1 is formed. When adopting the example of dual-system transmission, transmission lines H20a and H20b between the performance control board 30 are formed by the connectors CN1a and CN1b.

[0209] A 12V DC voltage (DC12VB) is supplied from the connector CN1 (or CN1a) to the LED connection board 700. A fuse FZ2 is arranged as the element closest in wiring to the terminal (pin) of the 12V DC voltage (DC12VB) in the connector CN1 (or CN1a).

[0210] A 5V DC voltage (DC5VB) and a 35V DC voltage (DC35VB) are supplied from the connector CN1 (or CN1b) to the LED connection board 700. A fuse FZ1 is arranged as the closest element in terms of wiring to the terminal (pin) of the 5V DC voltage (DC5VB) in the connector CN1 (or CN1b).

[0211] Furthermore, a ground is connected to the performance control board 30 via the connector CN1 (or CN1a, CN1b). Note that in Figures 17, 18, and 19, the notation of grounds other than the connector CN1 (or CN1a, CN1b) is omitted.

[0212] The performance control signal transmitted through the connector CN1 (or CN1a, CN1b) is input to the buffer circuits 701, 703, where it is subjected to buffering, i.e., signal compensation processing by waveform shaping. In other words, buffering processing can be considered as noise suppression processing for the signal. The buffer circuit 701 receives the first group (GP1) and the second group (GP2) of performance control signals, and the buffer circuit 703 receives the fourth group (GP4) of performance control signals.

[0213] Of the performance control signals buffered by buffer circuit 701, the first set (GP1) of clock signal LED_CLK and data signal LED_DATA are further buffered by buffer circuit 702 and then output as three systems of light emission control signals SA (CLK_A, DATA_A), SB (CLK_B, DATA_B), and SC (CLK_C, DATA_C). In this example, the enable signal LED_ENABLE is unused in the first set.

[0214] Of the performance control signals buffered by buffer circuit 701, the second set (GP2) of clock signal LSI_CLK, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST are supplied to motor drive unit 760 in Fig. 19 as shown as motor control signal LSIS. In addition, serial data signal LSI_IN_DATA output from motor drive unit 760 in Fig. 19 is buffered by buffer circuit 701 and transmitted to performance control board 30 from connector CN1 (or CN1b).

[0215] The buffer circuit 703 buffers the load signal S_IN_LOAD and clock signal S_IN_CLK of the fourth group (GP4) of the performance control signals. The load signal S_IN_LOAD and clock signal S_IN_CLK are then supplied to the P / S conversion circuit 704.

[0216] The P / S conversion circuit 704 performs parallel / serial conversion processing based on the load signal S_IN_LOAD and the clock signal S_IN_CLK. That is, the P / S conversion circuit 704 receives the sense signals SENS0, SENS1, and SENS2 input from the connectors CN3 and CN4 and the connector CN23 in Fig. 19, and outputs a serial data signal S_IN_DATA including these signals. The serial data signal S_IN_DATA is buffered by the buffer circuit 703 and then transmitted to the performance control board 30 from the connector CN1 (or CN1b).

[0217] The buffer circuits 701, 702, and 703 and the P / S conversion circuit 704 shown in FIG. 17 are supplied with a 5V DC voltage (DC5VB) as an operating power supply. 12V DC voltage (DC12VB) is transmitted downstream from connectors CN3 and CN4.

[0218] FIG. 18 shows a circuit portion of the LED connection board 700 to which the light emission control signals SA and SB are supplied from the buffer circuit 702. The LED driving unit 750 is a circuit unit that controls the driving of the LEDs and includes an LED driver. The LED driver in the LED driving unit 750 generates a light emission driving current based on the light emission control signal SA (CLK_A, DATA_A).

[0219] The LED drivers of the LED driving unit 750 are connected to downstream LED boards from connectors CN5, CN8, CN11, CN13, and CN6 and connectors CN7, CN9, CN12, and CN14, and pass light emission drive current to the LEDs mounted on the downstream LED boards. Examples of downstream LED boards include LED boards 850 and 860 in FIG.

[0220] A 12V DC voltage (DC12VB) is supplied to the LED drive unit 750 as a power supply voltage for the LED driver, etc. Also, a 12V DC voltage (DC12VB) is transmitted to the downstream LED boards from the connectors CN5, CN8, CN11, CN13, CN6 and the connectors CN7, CN9, CN12, CN14 as a power supply for the LED light emission operation, that is, a power supply for the light emission drive current.

[0221] The light emission control signal SB (CLK_B, DATA_B) from the buffer circuit 702 is buffered by buffer circuits 708, 717, and 718, and then transmitted to downstream boards from connectors CN10, CN25, and CN26. The downstream boards are, for example, boards on which LED drivers and LEDs are mounted.

[0222] The buffer circuits 708, 717, and 718 are supplied with a 5V DC voltage (DC5VB) as an operating power supply. A 12V DC voltage (DC12VB) is transmitted from connectors CN10, CN25, and CN26 to the downstream LED board as the power supply voltage for the LED driver and the power supply for the light-emitting drive current flowing through the LED.

[0223] FIG. 19 shows the circuit portion around the motor drive unit 760 in the LED connection board 700 to which the motor control signal LSIS is supplied from the buffer circuit 702.

[0224] The motor driving unit 760 is a circuit unit that includes a motor control IC (motor controller) and, for example, four motor driving ICs (motor drivers). The motor control IC operates based on the second set (GP2) of clock signals LSI_CLK, enable signals LSI_ENABLE, data signals LSI_DATA, and reset signals LSI_RST input as motor control signals LSIS, and controls multiple motor drive ICs. Each motor drive IC generates motor drive signals MD1, MD2, MD3, and MD4 for its corresponding motor (e.g., the motor of a movable body component). These motor drive signals MD1, MD2, MD3, and MD4 are transmitted from connectors CN21, CN22, CN23, and CN24 to downstream motors and to circuit boards that relay the wiring to the motors.

[0225] For example, sense signals SENS0, SENS1, SENS2, SENS3, SENS4, and SENS5 from various motor-related sensors (e.g., origin sensors) are input to connectors CN16, CN17, CN18, CN19, CN20, and connector CN23. These sense signals SENS0, SENS1, SENS2, SENS3, SENS4, and SENS5 are buffered by a buffer circuit 709 and then input to a motor control IC in a motor drive unit 760.

[0226] The motor control IC has a function to convert the parallel-input multiple sense signals SENS0, SENS1, SENS2, SENS3, SENS4, and SENS5 into serial data, performs P / S conversion, and outputs the serial data signal LSI_IN_DATA. As described above, this serial data signal LSI_IN_DATA is input to the buffer circuit 701 in FIG. 17.

[0227] The motor control IC and motor drive IC in the motor drive unit 760 are supplied with a 5V DC voltage (DC5VB) and a 35V DC voltage (DC35VB) as operating power supply voltages. The buffer circuit 709 is supplied with a 5V DC voltage (DC5VB) as an operating power supply voltage. Furthermore, a 12V DC voltage (DC12VB) is transmitted via connectors CN16, CN17, CN18, CN19, and CN20 as an operating power source for downstream sensors and the like.

[0228] The light emission control signal SC (CLK_C, DATA_C) from the buffer circuit 702 in Fig. 17 is buffered by the buffer circuit 714 in Fig. 19 and then transmitted from the connector CN23 to the downstream board. The downstream board is, for example, the relay board 800 in Fig. 11. The relay board 800 and the decorative board 820 are boards that are attached to the movable body accessory, and the decorative board 820 is equipped with an LED driver and LEDs, and also has a relay circuit for the motor of the movable body accessory.

[0229] Therefore, the light emission control signal SC (CLK_C, DATA_C) and the motor drive signal MD3 are transmitted to the decorative substrate 820 via the relay substrate 800 by the connector CN23. 17. Also, a sense signal SENS2 from the origin sensor of the movable body motor is input from connector CN23 via decorative substrate 820 and relay substrate 800. As described above, sense signal SENS2 is input to P / S conversion circuit 704 in FIG.

[0230] A 12V DC voltage (DC12VB) and a 5V DC voltage (DC5VB) are transmitted via the connector CN23 as operating power sources for the relay board 800 and the decorative board 820. Here, a flexible flat cable, for example, is used for the transmission line H31 between the relay board 800 attached to the movable accessory and the decorative board 820. In some cases, a flexible flat cable is used for the transmission line H30 between the relay board 800 and the LED connection board 700.

[0231] In this case, a fuse FZ7 is placed between the 12V DC voltage (DC12VB) terminal of connector CN23 and the 12V DC voltage (DC12VB) power supply line (12V power supply line), and a fuse FZ8 is placed between the 5V DC voltage (DC5VB) terminal of connector CN23 and the 5V DC voltage (DC5VB) power supply line (5V power supply line). The fuses FZ7 and FZ8 are the elements closest in wiring to the power supply voltage terminals of the connector CN23. The buffer circuit 714 is supplied with a 5V DC voltage (DC5VB) as an operating power supply voltage.

[0232] The circuit configuration of the LED connection board 700 shown in FIGS. 17, 18, and 19 will now be described in part using specific circuit diagrams.

[0233] Figure 20 is a circuit diagram corresponding to the portion shown in Figure 17. Here, the circuit is shown using the 40-pin connector CN1 as an example of single-system transmission. The pin assignment of connector CN1 is as shown in Figure 14. A circuit diagram of an example of multiple-system transmission will be described later in Figure 21.

[0234] The 12V DC voltage (DC12VB) transmitted from pins 12, 14, 24, 26, 28, and 30 of connector CN1 is supplied to the 12V power line within the board via fuse FZ2. Capacitors C1 and C4 are connected between the 12V power line and ground as noise suppression means, and a test point TP51 ​​is formed at a position corresponding to the position between capacitors C1 and C4 and the 12V DC voltage (DC12VB) terminal (pin) of connector CN1.

[0235] The 5V DC voltage (DC5VB) transmitted from the fourth and sixth pins of the connector CN1 is supplied to the 5V power supply line within the board via the fuse FZ1. Capacitors C2 and C3 are connected between the 5V power line and ground as noise suppression means, and a test point TP50 is formed at a position corresponding to the position between capacitors C2 and C3 and the 5V DC voltage (DC5VB) terminal (pin) of connector CN1.

[0236] The 35V DC voltage (DC35VB) transmitted from the 36th and 38th pins of the connector CN1 is supplied to the 35V power supply line within the board.

[0237] The first, second, eighth, ninth, tenth, sixteenth, eighteenth, nineteenth, twentieth, twenty-second, twenty-ninth, thirty-second, thirty-third, thirty-fourth, thirty-ninth, and fortieth pins of connector CN1 are each connected to a ground line on the board.

[0238] The performance control signals input from connector CN1, i.e., the clock signal LED_CLK, data signal LED_DATA of the first group (GP1), the clock signal LSI_CLK, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST of the second group (GP2), are input to buffer circuit 701. The load signal S_IN_LOAD and clock signal S_IN_CLK of the fourth set (GP4) are input to a buffer circuit 703.

[0239] Between the connector CN1 and the buffer circuits 701 and 703, test points TP1 to TP10 are formed on the signal paths (wiring patterns) of the above-mentioned performance control signals.

[0240] In connector CN1, the unused terminal for the enable signal LSI_ENABLE (pin 17) and the unused terminals for the clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X of the third group (GP3) (pins 21, 25, and 27) are left unconnected.

[0241] The buffer circuits 701, 702, and 703 (and the buffer circuit 709 in FIG. 19) use an IC that functions as an inverter when the CONT terminal of the first pin is at L level and as a buffer when it is at H level. In this case, the IC functions as a buffer by applying an H level using a 5V DC voltage (DC5VB). In addition, a 5V DC voltage (DC5VB) is applied to the VCC terminal of pin 20 as the operating power supply.

[0242] Buffer circuits 701, 702, 703, and 709 are Schmitt trigger buffers with eight CMOS circuits, which buffer signals input from pins 2 (A1 terminal) to 9 (A8 terminal), i.e., perform signal compensation (restore degraded H / L signal waveforms), and output the signals from pins 18 (Y1 terminal) to 11 (Y8 terminal), respectively. That is, a signal input to the A1 terminal is buffered and output from the Y1 terminal, a signal input to the A2 terminal is buffered and output from the Y2 terminal, and so on, and a signal input to the A8 terminal is buffered and output from the Y8 terminal.

[0243] A clock signal LSI_CLK, an enable signal LSI_ENABLE, a data signal LSI_DATA, and a reset signal LSI_RST are input to the A1 terminal, A3 terminal, A4 terminal, and A5 terminal of the buffer circuit 701. These clock signal LSI_CLK, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST are buffered by the buffer circuit 701 and output from the Y1 terminal, Y3 terminal, Y4 terminal, and Y5 terminal, and are supplied as a motor control signal LSIS to the motor drive unit 760 in Fig. 19 via chip resistor RA1 or RA2.

[0244] In addition, the serial data signal LSI_IN_DATA from the motor drive unit 760 is input to the A2 terminal of the buffer circuit 701, buffered, and then output from the Y2 terminal, sent to the connector CN1 via the chip resistor RA1, and transmitted to the upstream performance control board 30.

[0245] The clock signal LED_CLK and the data signal LED_DATA are input to the A6 terminal and A7 terminal of the buffer circuit 701 and buffered, and then output from the Y6 terminal and Y7 terminal, and input to the buffer circuit 702 via the chip resistor RA2.

[0246] The clock signal CLK_CLK is branched and input to the A1 terminal, A3 terminal, and A5 terminal of the buffer circuit 702. The data signal LED_DATA is branched and input to the A2 terminal, A4 terminal, and A6 terminal of the buffer circuit 702.

[0247] These three systems of clock signal LED_CLK and data signal LED_DATA are buffered and output. The signals output from the Y1 terminal and Y2 terminal are light emission control signals SA (CLK_A, DATA_A), the signals output from the Y3 terminal and Y4 terminal are light emission control signals SB (CLK_B, DATA_B), and the signals output from the Y5 terminal and Y6 terminal are light emission control signals SC (CLK_C, DATA_C).

[0248] In the buffer circuit 703, the clock signal S_IN_CLK is input to the A2 terminal, and the load signal S_IN_LOAD is input to the A4 terminal. After being buffered, these signals are output from the Y2 terminal and the Y4 terminal, and are supplied to the P / S conversion circuit 704 via the resistors R2 and R4.

[0249] The P / S conversion circuit 704 is, for example, a CMOS 8-bit shift register, which has 8-bit parallel input / output, serial input, and serial output, and performs parallel-to-serial conversion of data. When the P / S CONT terminal is low, the eight terminals Q / D1 to Q / D8 become parallel outputs, and data from the SI terminal is stored in each register at the rising edge of the input waveform to the CK terminal and output to the Q / D1 to Q / D8 terminals. In addition, by setting the CLR / LOAD terminal to low, each register is reset asynchronously with the input to the CK terminal. When the P / S CONT terminal is high, the eight terminals Q / D1 to Q / D8 become parallel inputs, and when the CLR / LOAD terminal is low, the input data of terminals Q / D1 to Q / D8 is stored in each register asynchronously with the CK terminal input.

[0250] In this example, when a 5V DC voltage (DC5VB) is applied to the P / S CONT terminal of the P / S conversion circuit 704, the P / S CONT terminal is set to H, and the eight terminals Q / D1 to Q / D8 are set to parallel input. Furthermore, the clock signal S_IN_CLK input from the buffer circuit 703 is input to the CK terminal, and the load signal S_IN_LOAD is input to the CLR / LOAD terminal.

[0251] Of the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 704, the sense signal SENS0 is input to the Q / D1 terminal, the sense signal SENS1 to the Q / D2 terminal, and the sense signal SENS2 to the Q / D3 terminal. The Q / D4, Q / D5, Q / D6, Q / D7, and Q / D8 terminals are connected to ground, meaning that each input is "0" (L level).

[0252] The sense signals SENS0, SENS1, and SENS2 are, for example, detection signals from a sensor in a downstream motor or the like, such as an origin sensor or a sensor for detecting a movement position. The sense signal SENS0 is input from connector CN3. The sense signal SENS1 is also input from connector CN3. Connectors CN3 and CN4 each have a 12V DC voltage (DC12VB) assigned to the first pin and ground (GND) assigned to the second pin, supplying operating power to the connected sensors.

[0253] The signal line of the sense signal SENS0 is connected to the 5V power supply line via a resistor R7 and pulled up. The signal line of the sense signal SENS1 is connected to the 5V power supply line via a resistor R8 and pulled up.

[0254] The sense signal SENS2 is input from a connector CN23 shown in Fig. 19 and Fig. 25, which will be described later. A 5V power supply line is connected to the signal line of the sense signal SENS2 via a resistor R135 and is pulled up.

[0255] These sense signals SENS0, SENS1, and SENS2 are input to the P / S conversion circuit 704 after high frequency noise is removed by CR filter circuits (resistor R5 and capacitor C11, resistor R8 and capacitor C12, and resistor R11 and capacitor C14).

[0256] The P / S conversion circuit 704 converts the input sense signals SENS0, SENS1, and SENS2 into serial data and outputs it from the Q8 terminal as the serial data signal S_IN_DATA. This serial data signal S_IN_DATA is filtered by a CR filter circuit consisting of resistor R3 and capacitor C10 to remove high-frequency noise, and is then input to the A7 terminal of the buffer circuit 703. It is then output from the Y7 terminal, passes through resistor R1, and is transmitted to the upstream performance control board 30 from pin 31 of connector CN1.

[0257] Up to this point, the circuit configuration employing the single-system transmission example has been explained with reference to FIG. 20, but FIG. 21 shows the circuit configuration when employing the double-system transmission example. 21 differs from FIG. 20 only in the connectors CN1a and CN1b and the connection configuration of each terminal thereof, and the configurations of buffer circuits 701, 702, 703, P / S conversion circuit 704, connectors CN3, CN4, etc. are the same as in FIG.

[0258] In the case of the example of multiple system transmission in FIG. 21, a connector CN1a with 16 pins and a connector CN1b with 24 pins are used. Connector CN1a, which is system a, transmits 12V DC voltage (DC12VB) and the first set of performance control signals (GP1). Furthermore, connector CN1b, which is system b, transmits 5V DC voltage (DC5VB), 35V DC voltage (DC35VB), and the second set (GP2) and fourth set (GP4) of performance control signals.

[0259] The 12V DC voltage (DC12VB) transmitted from pins 11 to 16 of the connector CN1a is supplied to the 12V power supply line within the board via fuse FZ2. Capacitors C2 and C3 are connected between the 12V power line and ground as noise suppression means. In addition, a test point TP51 ​​is formed at a position corresponding to the position between capacitors C2 and C3 and the 12V DC voltage (DC12VB) terminal (pin) of connector CN1a.

[0260] The first, second, fourth, sixth, eighth, ninth, and tenth pins of the connector CN1a are connected to the ground line on the board.

[0261] The performance control signals input from the connector CN1a, that is, the clock signal LED_CLK (third pin) and data signal LED_DATA (fifth pin) of the first group (GP1), are input to a buffer circuit 701. In the connector CN1a, the unused terminal (7th pin) of the enable signal LSI_ENABLE is left unconnected.

[0262] Meanwhile, the 5V DC voltage (DC5VB) transmitted from pins 1 and 3 of connector CN1b is supplied to the 5V power line within the board via fuse FZ1. Capacitors C1 and C4 are connected between the 5V power line and ground as noise suppression means. Test point TP50 is also formed at a position corresponding to the positions between capacitors C1 and C4 and the 5V DC voltage (DC5VB) terminal (pin) of connector CN1b.

[0263] The 35V DC voltage (DC35VB) transmitted from the second and fourth pins of the connector CN1b is supplied to the 35V power supply line within the board.

[0264] The 5th, 8th, 10th, 12th, 14th, 16th, 17th, and 18th pins of the connector CN1b are connected to the ground line on the board.

[0265] The performance control signal input from connector CN1b, the clock signal LSI_CLK (7th pin), the enable signal LSI_ENABLE (11th pin), the data signal LSI_DATA (13th pin), and the reset signal LSI_RST (15th pin) of the second group (GP2) are input to the buffer circuit 701. The load signal S_IN_LOAD (pin 19) and clock signal S_IN_CLK (pin 21) of the fourth set (GP4) are input to a buffer circuit 703.

[0266] Between the connectors CN1a, CN1b and the buffer circuits 701, 703, test points TP1 to TP10 are formed on the signal paths (wiring patterns) of the above-mentioned performance control signals.

[0267] In the connector CN1b, the unused terminals (20th pin, 22nd pin, 24th pin) of the third group (GP3) for the clear signal CLR_X, the data signal DATA_X, and the latch signal LATCH_X are left unconnected.

[0268] The serial data signal LSI_IN_DATA transmitted from the buffer circuit 701 via the chip resistor RA1 is transmitted to the upstream performance control board 30 from the 9th pin of the connector CN1b. The serial data signal S_IN_DATA transmitted from the buffer circuit 703 via the resistor R1 is transmitted to the upstream performance control board 30 from the 23rd pin of the connector CN1b.

[0269] The circuit example of the multiplexed transmission example in FIG. 21 differs from FIG. 20 in the above points, but these are due to differences in the pin assignments of the connector CN1 and the connectors CN1a and CN1b, and are the same from a circuit perspective.

[0270] Next, FIGS. 22 and 23 show specific circuit examples of the LED driving unit 750 shown in FIG. 18 and the connector connected downstream.

[0271] 18 includes the LED driver 705 in FIG. 22 and the LED driver 707 in FIG.

[0272] As shown in FIG. 22, the light emission control signal SA (CLK_A, DATA_A) from the buffer circuit 702 in FIG. 20 or FIG. A test point TP12 is formed on the wiring of the clock signal CLK_A extending from the buffer circuit 702 to the LED driver 705, and a test point TP11 is formed on the wiring of the data signal DATA_A extending from the buffer circuit 702 to the LED driver 705.

[0273] The LED driver 705 generates a light emission drive current in response to the clock signal CLK_A and the data signal DATA_A. The LED driver 705 has light emission drive current terminals LEDR1, LEDG1, LEDB1... LEDR8, LEDG8, and LEDB8, and can control the drive current of 24 systems. In this case, all 24 light emission drive current terminals are used to perform LED light emission of 24 systems.

[0274] The light emission drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 are connected to six LED circuits on a downstream board (not shown) that are electrically connected from a connector CN5. An LED circuit is a circuit that has one LED or multiple LEDs connected in series. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN5 as a power source, the terminal voltages of light emission drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 in LED driver 705 are controlled to flow light emission drive currents 01-R1, 01-G1, 01-B1, 01-R2, 01-G2, and 01-B2 into each of the six LED circuits, causing each of the six LEDs to emit light.

[0275] The light emission drive current terminals LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 ​​are connected to six LED circuits on a downstream board (not shown) that are electrically connected from a connector CN8. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN8 as a power source, the terminal voltages of light emission drive current terminals LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 ​​in LED driver 705 are controlled to flow light emission drive currents 01-R3, 01-G3, 01-B3, 01-R4, 01-G4, and 01-B4 into each of the six LED circuits, causing the LEDs in each of the six systems to emit light.

[0276] The light emission drive current terminals LEDR5, LEDG5, and LEDB5 are connected to three LED circuits on a downstream board (not shown) that are electrically connected from a connector CN11. Similarly, the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN11 is used as a power source, and the terminal voltages of the light emission drive current terminals LEDR5, LEDG5, and LEDB5 in the LED driver 705 are controlled to flow light emission drive currents 01-R5, 01-G5, and 01-B5 into each of the three LED circuits, causing the LEDs in each of the three systems to emit light.

[0277] The light emission drive current terminals LEDR6, LEDG6, and LEDB6 are connected to three LED circuits on a downstream board (not shown) that are electrically connected from a connector CN13. Similarly, the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN13 is used as a power source, and the terminal voltages of the light emission drive current terminals LEDR6, LEDG6, and LEDB6 in the LED driver 705 are controlled to flow light emission drive currents 01-R6, 01-G6, and 01-B6 into each of the three LED circuits, causing the LEDs in each of the three systems to emit light.

[0278] The light emission drive current terminals LEDR7, LEDG7, LEDB7, LEDR8, LEDG8, and LEDB8 are connected to six LED circuits on a downstream board (not shown) that are electrically connected from a connector CN6. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN13 as a power source, the terminal voltages of light emission drive current terminals LEDR7, LEDG7, LEDB7, LEDR8, LEDG8, and LEDB8 in LED driver 705 are controlled to flow light emission drive currents 01-R7, 01-G7, 01-B7, 01-R8, 01-G8, and 01-B8 into each of the six LED circuits, causing each of the six LEDs to emit light. Note that the lines of the light emission drive currents 03-R8, 03-G8, and 03-B8 are connected between connector CN6 and connector CN10 shown in Figure 24, and the light emission drive current terminals of the LED driver on the downstream board connected to either connector CN6 or connector CN10 are connected to the three LED circuits on the other downstream board, so that the light emission drive currents 03-R8, 03-G8, and 03-B8 flow through the three LED circuits.

[0279] Next, as shown in FIG. 23, the light emission control signal SA (CLK_A, DATA_A) from the buffer circuit 702 in FIG. 20 or 21 is also input to the 48th terminal (SCLK) and the 47th terminal (SDATA) of the LED driver 707. A test point TP16 is formed on the wiring of the clock signal CLK_A extending from the buffer circuit 702 to the LED driver 707, and a test point TP15 is formed on the wiring of the data signal DATA_A extending from the buffer circuit 702 to the LED driver 707.

[0280] The LED driver 707 is the same IC chip as the LED driver 705, and generates a light emission drive current in response to a clock signal CLK_A and a data signal DATA_A. The LED driver 707 uses 23 light emission drive current terminals excluding the light emission drive current terminal LEDB8 to cause 23 systems of LEDs to emit light.

[0281] The light emission drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 are connected to six LED circuits on a downstream board (not shown) that are electrically connected from connector CN7 via current limiting resistors R17, R18, R16, R20, R21, and R19. Similarly, using the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN7 as a power source, the terminal voltages of light emission drive current terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, and LEDB2 in LED driver 707 are controlled to flow light emission drive currents 10-R1, 10-G1, 10-B1, 10-R2, 10-G2, and 10-B2 into each of the six LED circuits, causing each of the six LED circuits to emit light.

[0282] The light emission drive current terminals LEDR3, LEDG3, and LEDB3 are connected to three LED circuits on a downstream board (not shown) electrically connected from a connector CN9 via current limiting resistors R22, R23, and R24. Similarly, the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN9 is used as a power source, and the terminal voltages of the light emission drive current terminals LEDR3, LEDG3, and LEDB3 in the LED driver 707 are controlled to flow light emission drive currents 10-R3, 10-G3, and 10-B3 into each of the three LED circuits, causing the LEDs in each of the three systems to emit light.

[0283] The light emission drive current terminal LEDR4 is connected via a current limiting resistor R27 to one LED circuit system on a downstream board (not shown) that is electrically connected from the connector CN12. Similarly, the 12V DC voltage (DC12VB) supplied to the downstream board via connector CN12 is used as a power source, and the terminal voltage of the light emission drive current terminal LEDR4 in the LED driver 707 is controlled to flow a light emission drive current 10-R4 through one LED circuit, causing the LED to emit light.

[0284] The light emission drive current terminals LEDG4, LEDB4, LEDR5, LEDG5, LEDB5, LEDR6, LEDG6, LEDB6, LEDR7, and LEDG7 are connected to 10 LED circuits on a downstream board (not shown) that are electrically connected from connector CN14 via current limiting resistors R28, R29, R30, R31, R32, R33, R34, R35, R36, and R37. The light emission drive current terminals LEDB7, LEDR8, and LEDG8 are connected to 3 LED circuits on a downstream board that are electrically connected from connector CN14 without using current limiting resistors. Similarly, the 12V DC voltage (DC12VB) supplied to the downstream board by connector CN14 is used as a power source, and by controlling the terminal voltages of light emission drive current terminals LEDG4, LEDB4, LEDR5, LEDG5, LEDB5, LEDR6, LEDG6, LEDB6, LEDR7, LEDG7, LEDB7, LEDR8 and LEDG8 in LED driver 707, light emission drive currents 10-G4, 10-B4, 10-R5, 10-G5, 10-B5, 10-R6, 10-G6, 10-B6, 10-R7, 10-G7, 10-B7, 10-R8 and 10-G8 are passed through a total of 13 LED circuits, respectively, causing the LEDs in each of the 13 systems to emit light.

[0285] In the LED driver 705 in Fig. 22 and the LED driver 707 in Fig. 23, a 6-bit slave address is set by address terminals A0 to A5. However, the address terminal A5 is fixed to "0," and a 5-bit slave address is set by address terminals A0 to A4. Therefore, by connecting each of the address terminals A0 to A4 to a terminal VREF that outputs a reference voltage (5V) or to ground, "1" or "0" is set for each bit.

[0286] This slave address is set to a different value for all LED drivers to which the first set of clock signal LED_CLK and data signal LED_DATA, i.e., light emission control signals SA, SB, and SC, is supplied. In other words, this address distinguishes among all LED drivers, including those mounted on other boards (not shown) downstream from the LED connection board 700. In this way, in the system of the clock signal LED_CLK and the data signal LED_DATA, the address terminal A5 is set to all "0" and connected to ground, and the other 5 bits are set to slave addresses each having a unique value.

[0287] FIG. 24 shows the circuitry of the portion where the light emission control signal SB (CLK_B, DATA_B) is output. The clock signal CLK_B and the data signal DATA_B output from the buffer circuit 702 in FIG. 20 or FIG. 21 are branched into three systems as shown in FIG. 24 and input to buffer circuits 708, 717, and 718, which are dual Schmitt buffers. The buffer circuits 708, 717, and 718 are supplied with a 5V DC voltage (DC5VB) as an operating power source.

[0288] The clock signal CLK_B and data signal DATA_B buffered by the buffer circuit 708 are supplied to the fourth and sixth pins of the 12-pin connector CN10 via resistors R25 and R26, respectively. A 12V DC voltage (DC12VB) is supplied to the first, second, and third pins of the connector CN10. The fifth, seventh, eighth, and twelfth pins of the connector CN10 are assigned to ground. The ninth, tenth, and eleventh pins are assigned to the above-mentioned light-emitting drive currents 03-R8, 03-G8, and 03-B8. As a result, the light emission control signal SB and the 12V DC voltage (DC12VB) are transmitted from the connector CN10 to the downstream board, and the operation of the downstream LED driver is controlled.

[0289] The clock signal CLK_B and data signal DATA_B buffered by the buffer circuit 717 are supplied to the fourth and sixth pins of the nine-pin connector CN25 via resistors R136 and R137, respectively. A 12V DC voltage (DC12VB) is supplied to the first, second, and third pins of the connector CN25. The fifth, seventh, eighth, and ninth pins of the connector CN25 are assigned to ground. As a result, the light emission control signal SB and the 12V DC voltage (DC12VB) are transmitted from the connector CN25 to the downstream board, and the operation of the downstream LED driver is controlled.

[0290] The clock signal CLK_B and data signal DATA_B buffered by the buffer circuit 718 are supplied to the fourth and sixth pins of the nine-pin connector CN26 via resistors R138 and R112, respectively. A 12V DC voltage (DC12VB) is supplied to the first and second pins of the connector CN26. The third, fifth, seventh, eighth, and ninth pins of the connector CN25 are assigned to ground. As a result, the light emission control signal SB and the 12V DC voltage (DC12VB) are transmitted from the connector CN26 to the downstream board, and the operation of the downstream LED driver is controlled.

[0291] FIG. 25 shows a circuit portion where the light emission control signal SC (CLK_C, DATA_C) is output. The clock signal CLK_C and the data signal DATA_C output from the buffer circuit 702 in FIG. 20 or FIG. 21 are input to a buffer circuit 714 which is a dual Schmitt buffer as shown in FIG.

[0292] The clock signal CLK_C and the data signal DATA_C buffered by the buffer circuit 714 are supplied to the 8th pin and the 12th pin of the 18-pin connector CN23 via resistors R109 and R110, respectively.

[0293] A 12V DC voltage (DC12VB) is supplied to pins 2, 4, and 6 of connector CN23. In this case, fuse FZ7 is placed between pins 2, 4, and 6 and the 12V power line. A 5V DC voltage (DC5VB) is supplied to pin 9 of connector CN23. In this case, fuse FZ8 is placed between pin 9 and the 5V power line.

[0294] The first, third, tenth, eleventh, thirteenth, and fourteenth pins of the connector CN23 are assigned to ground.

[0295] The fifth pin is assigned to a sense signal SENS4, which is one of the sense signals input to the buffer circuit 709 in FIG. The seventh pin is assigned to a sense signal SENS2, which is one of the sense signals input to the P / S conversion circuit 704 in FIG. 17 (FIG. 20 or FIG. 21). The 15th, 16th, 17th, and 18th pins are assigned to the motor drive signal MD3 (MOTzA+, MOTzB-, MOTzA-, MOTzB+) from the motor drive unit in FIG.

[0296] As a result, the light emission control signal SC, motor drive signal, 12V DC voltage (DC12VB), and 5V DC voltage (DC5VB) are transmitted from connector CN23 via transmission line H30 to the downstream board, in this case relay board 800 mounted on the movable body accessory, and the operation of the downstream LED driver and motor is controlled. In addition, sense signals SENS2 and SENS4 from the downstream sensors are input to LED connection board 700.

[0297] 26 shows a circuit related to the 35V DC voltage (DC35VB) input from the connector CN1 or CN1b. In particular, the motor drive unit 760 in FIG. 19 is configured to obtain the motor drive power supply voltage from the 35V power line.

[0298] As shown in FIG. 26, a protection circuit consisting of a Schottky barrier diode D10 and an electrolytic capacitor C57, and a protection circuit consisting of a Schottky barrier diode D11 and an electrolytic capacitor C63 are connected to the 35V power supply line.

[0299] Fuses FZ3 and FZ4 are connected to the connection point between Schottky barrier diode D10 and electrolytic capacitor C57, and the power supply voltages for driving the motors MOT35Vx and MOT35Vz are taken out. Fuses FZ5 and FZ6 are connected to the connection point between Schottky barrier diode D11 and electrolytic capacitor C63, and motor drive power supply voltages MOT35Vy and MOT35Vu are taken out. These motor drive power supply voltages MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu are supplied to four motor drive ICs in the motor drive unit 760 of FIG.

[0300] 6. Characteristic Configuration and Effects of the Embodiments The gaming machine 1 of this embodiment has the following configurations (Configuration A1-1) to (Configuration F11-2). These configurations will be explained mainly using the transmission line H20 (H20a, H20b) between the performance control board 30 and the LED connection board 700, the configuration of the LED connection board 700, and the configuration of the performance control board 30 as examples.

[0301] (Configuration A1-1) The gaming machine 1 is a first control unit provided at a first position; a second control unit provided at a second position; a transmission line connecting the first control unit and the second control unit, A predetermined effect can be executed by activating a performance means different from the light-emitting means while emitting light from the light-emitting means, The transmission line is a first transmission means for transmitting, via a first connector, a light emission control signal for causing the light emitting means to emit light and a first power supply voltage for driving the light emission; The device includes second transmission means for transmitting a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector different from the first connector.

[0302] In the case of this (Configuration A1-1), the following corresponding example (Specific Example 1) is assumed. (Example 1) First control unit: performance control board 30 Second control unit: LED connection board 700 (configuration example of FIG. 21) First transmission means: Transmission line H20a Second transmission means: Transmission line H20b 1st connector: Connector CN1a, CNe1a Second connector: Connector CN1b, CNe1b Light-emitting control signals for emitting light from the light-emitting means: the first set of performance control signals, the data signal LED_DATA and the clock signal LED_CLK First power supply voltage for light emission: 12V DC voltage (DC12VB) Performance control signals for controlling performance means: the second set of performance control signals, which are the clock signal LSI_CLK, the enable signal LSI_ENABLE, the data signal LSI_DATA, and the reset signal LSI_RST Second power supply voltage for signal processing: 5V DC voltage (DC5VB)

[0303] The performance control board 30 is positioned at a specific first position on the game board 3 as shown in Figure 7, and the LED connection board 700 is also positioned at a specific first position on the game board 3 as shown in Figure 7, so they correspond to the first control unit and the second control unit. The light emitting means corresponds to a light emitting unit using decorative LEDs. For example, it is an LED light emitting unit on a board downstream of the LED connection board 700 that is driven to emit light by LED drivers 705 and 707. An example of a performance means different from the light emitting means is the motor of a movable accessory.

[0304] The 12V DC voltage (DC12VB) is the operating power supply for LED drivers 705 and 707, and is also used as the power supply voltage for the light emission drive current of the LEDs mounted on the downstream board. In other words, it is the first power supply voltage for light emission drive.

[0305] The 5V DC voltage (DC5VB) is used in buffer circuits 701, 702, 703, 709, P / S conversion circuit 704, and the motor control IC in motor drive unit 760. In other words, it is a power supply voltage for signal processing, and is a second power supply voltage. In addition, since the 35V DC voltage (DC35VB) is the motor drive power supply voltages MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu used in the motor drive IC in the motor drive unit 760, the 35V DC voltage (DC35VB) can also be said to correspond to the second power supply voltage for signal processing.

[0306] As explained in Figure 15, the transmission line H20a of system a, whose transmission line ends at connectors CN1a and CNe1a, transmits a first set of data signals LED_DATA and clock signals LED_CLK, which are performance control signals that serve as light emission control signals, and also transmits 12V DC voltage (DC12VB). In addition, the b-system transmission line H20b, whose transmission line ends at connectors CN1b and CNe1b, transmits the second set of performance control signals: clock signal LSI_CLK, enable signal LSI_ENABLE, data signal LSI_DATA, reset signal LSI_RST, as well as 5V DC voltage (DC5VB) and 35V DC voltage (DC35VB).

[0307] Essentially, as shown as an example of single-system transmission, it is sufficient to provide a single system of transmission line H20 between the performance control board 30 and the LED connection board 700, with the 40-pin connectors CN1 and CN1e as the transmission line ends. By dividing this into system A and system B, it is possible to achieve more efficient board configuration.

[0308] For example, instead of the 40-pin connectors CN1 and CNe1, 16-pin connectors CN1a and CNe1a and 24-pin connectors CN1b and CNe1b, along with their respective harnesses, can be used. This allows multiple relatively small connectors to be used instead of large connectors, reducing the overall area occupied by connectors on the board and improving flexibility in placement.

[0309] For example, FIG. 27 shows an example of a 40-pin connector that can be used as connectors CN1 and CNe1. FIG. 28 shows an example of a connector with a 16-pin configuration that can be used for the connectors CN1a and CNe1a, and FIG. 29 shows an example of a connector with a 24-pin configuration that can be used for the connectors CN1b and CNe1b.

[0310] Although Figures 27, 28, and 29 show examples of top-type connectors in which connector terminals are coupled from above the board, side-type connectors in which connector terminals are coupled parallel to the board plane may also be used.

[0311] 27, 28, and 29 show the layout of pads Pd formed on the substrate corresponding to the connectors. The dashed dotted line SCA corresponds to the outline of the connectors to be placed. Each pad Pd electrically corresponds to a respective terminal (pin) of the connector, and the pitch PW of the pads Pd corresponds to the pitch of the terminals (pins). In order to avoid complication, only some of the reference symbols for pads, pins, etc. are shown in each drawing.

[0312] Each figure shows a contact housing 1000 and a socket housing 1001 that constitute the connector, and the socket housing 1001 is attached to a substrate 2000. A predetermined number of pins 1002 are arranged in two rows on the socket housing 1001 side. Electric wires 1003 to be electrically connected to the pins 1002 are attached on the contact housing 1000 side. The specifications of each connector are as follows:

[0313] Connector CN1 / CNe1 in Figure 27 Socket housing 1001 width Xs: 33.7mm Socket housing 1001 vertical size Ys: 7.6mm Socket housing 1001 height size Zs: 8.6mm Contact housing 1000 width xc: 33.7mm Contact housing 1000 vertical size Yc: 7.6mm Contact housing 1000 height size Zc: 5.7mm Terminal pitch PW: 1.5mm Pad width W1: 0.7mm Pin diameter: 0.6mm ·Rated current: 1.5A Applicable wire range / conductor size: AWG28 (diameter 0.3200 mm / cross-sectional area 0.08046 mm) 2 )from AWG24 (diameter 0.5105mm / cross-sectional area 0.2047mm 2 ) Applicable wire range / insulator outer diameter: 0.76mm~1.2mm

[0314] Connector CN1a / CNe1a in Figure 28 Socket housing 1001 width Xs: 15.7mm Socket housing 1001 vertical size Ys: 7.6mm Socket housing 1001 height size Zs: 8.6mm Contact housing 1000 width xc: 15.7mm Contact housing 1000 vertical size Yc: 7.6mm Contact housing 1000 height size Zc: 5.7mm Terminal pitch PW: 1.5mm Pad width W1: 0.7mm Pin diameter: 0.6mm ·Rated current: 2A Applicable wire range / conductor size: from AWG28 (diameter 0.3200 mm / cross-sectional area 0.08046 mm2) AWG24 (diameter 0.5105mm / cross-sectional area 0.2047 mm2) Applicable wire range / insulator outer diameter: 0.76mm~1.2mm

[0315] Connector CN1b / CNe1b in Figure 29 Socket housing 1001 width Xs: 13.2mm Socket housing 1001 vertical size Ys: 5.6mm Socket housing 1001 height size Zs: 6.8mm Contact housing 1000 width xc: 14.2mm Contact housing 1000 vertical size Yc: 4.25mm Contact housing 1000 height size Zc: 4.36mm Terminal pitch PW: 1.0mm Pad width W1: 0.6mm Pin diameter: 0.5mm ·Rated current: 1A Applicable wire range / conductor size: AWG32 (diameter 0.2032 mm / cross-sectional area 0.03243 mm) 2 )from AWG28 (diameter 0.3200mm / cross-sectional area 0.08046mm 2 ) Applicable wire range / insulator outer diameter: 0.4mm~0.8mm

[0316] For example, in the case of a single-system transmission example, the 40-pin connector in Figure 27 can be used, whereas in the case of a multiple-system transmission example, the 16-pin connector in Figure 28 and the 24-pin connector in Figure 29 can be used. In other words, in the case of a multiple-system transmission example, the large 40-pin connector is not used, but the small 16-pin and 24-pin connectors are used.

[0317] FIG. 30 shows a schematic diagram of a single-system transmission example in which 40-pin connectors CN1 and CNe1 are used between the performance control board 30 and the LED connection board 700. Figures 31, 32, and 33 each show a schematic diagram of a dual-system transmission example in which 16-pin connectors CN1a and CNe1a and 24-pin connectors CN1b and CNe1b are used between the performance control board 30 and the LED connection board 700.

[0318] In the case of Figure 30, the connectors CN1 and CNe1, which are large in width (for example, 33.7 mm), are placed near one side of the board, occupying a relatively large area. In addition, the wiring patterns around the connectors are congested.

[0319] In contrast, in the case of multiplexed transmission examples, as shown in Figures 31, 32, and 33, there is greater freedom in the placement of the two connectors, which in turn increases the freedom in the pattern design of the board, making it easier to miniaturize the board through placement.

[0320] In the example of Fig. 31, for example, the connectors CN1a and CN1b are arranged side by side on the LED connection board 700, so the area occupied by one side is wide as in Fig. 30, but still not as wide as the connector CN1 in Fig. 30. For example, the widths of the socket housings 1001 of the connectors CN1a and CN1b in Fig. 28 and Fig. 29 are 15.7 mm and 13.2 mm, respectively, for a total of 28.9 mm, and even with the addition of the gap for arrangement, the occupied area can be smaller than the width of 33.7 mm of the connector CN1 in Fig. 27.

[0321] 32, the congestion of wiring patterns around the connectors can be alleviated by arranging the connectors CN1a and CN1b apart on the LED connection board 700. Also, by arranging various components according to the power supply voltage using the performance control signals transmitted by each of the connectors CN1a and CN1b, efficient wiring and component arrangement can be easily achieved.

[0322] In particular, in the example of FIG. 32, the spacing d2 between the connectors CN1a and CN1b on the LED connection board 700 is wider than the spacing d1 between the connectors CNe1a and CN1eb on the performance control board 30. On the performance control board 30 side, each signal is output from one CPU output port, so it is more convenient in terms of wiring if the connectors CNe1a and CN1eb are close to each other. On the other hand, if the circuits related to each of the effect means (for example, LED light emission and motor drive) are separate on the LED connection board 700, it is easier to design the wiring pattern if the connectors CN1a and CN1b are placed apart. Furthermore, the LED-related light emission control signals and the 12V DC voltage (DC12VB) for driving light emission are the same a-system, which is advantageous in terms of wiring on the LED connection board 700.

[0323] 33, arranging the connectors CN1a and CN1b along different sides of the LED connection board 700 is an effective arrangement when it is desired to avoid occupying one side with the connectors. For example, when arranging the connectors CN1a and CN1b on one side becomes inefficient in terms of wiring patterns and component arrangement due to the arrangement of other connectors, ICs, etc., or the shape of the board, the arrangement of the connectors CN1a and CN1b as shown in FIG.

[0324] The gaming machine 1 of the embodiment has the following (Configuration A1-2) in addition to the above (Configuration A1-1).

[0325] (Configuration A1-2) The first power supply voltage and the second power supply voltage are power supply voltages used to produce the predetermined effect.

[0326] For example, a first power supply voltage of 12V DC (DC12VB) and a second power supply voltage of 5V DC (DC5VB) are power supply voltages used to produce a certain effect. The predetermined effect is an effect using a certain effect means.

[0327] In this case, the predetermined effect may be, for example, a decorative LED light emission effect as an effect means. For example, LED drivers 705 and 707 cause LEDs on downstream LED boards 850 and 860 to emit light. In this case, a 12V DC voltage (DC12VB) is used as a power supply voltage for LED drivers 705 and 707 and a power supply for a light emission drive current to be passed through the LEDs. Also, a 5V DC voltage (DC5VB) is used as a power supply voltage for buffer circuits 701 and 702 that process light emission control signals SA to be supplied to LED drivers 705 and 707.

[0328] In this way, 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are used to illuminate decorative LEDs. In the case of a multiple-system transmission example, these 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are transmitted over different transmission lines, namely, transmission line H20a of system a and transmission line H20b of system b.

[0329] Another example of a predetermined effect is the effect of LEDs mounted on a movable prop. Furthermore, the predetermined effect can also be the overall effect of a moving part, such as the movement of a motor in a moving part or the illumination of an LED mounted on the moving part.

[0330] In this case, the first power supply voltage is a 12V DC voltage (DC12VB), and the second power supply voltage can be a 5V DC voltage (DC5VB) or a 35V DC voltage (DC35VB). The relay board 800 and decorative board 820 shown in FIG. 11 are mounted on the movable accessory.

[0331] A 12V DC voltage (DC12VB) is transmitted from connector CN23 (see Figures 19 and 25) to the relay board 800 and decorative board 820, for example as a power supply voltage for the LED driver mounted on the decorative board 820 and as a power supply for the light-emitting drive current flowing through the LEDs.

[0332] Furthermore, the clock signal CLK_C and the data signal DATA_C serving as the light emission control signal SC are processed by buffer circuits 701, 702, and 714, and then transmitted from connector CN23 to relay board 800 and decorative board 820, and supplied to, for example, an LED driver mounted on decorative board 820. A 5V DC voltage (DC5VB) is used as the power supply voltage for processing in buffer circuits 701, 702, and 714.

[0333] The 35V DC voltage (DC35VB) is used as the motor drive power supply voltages MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu used in the motor drive unit 760 (see FIGS. 19 and 26).

[0334] In other words, 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) are used to light up the LEDs installed in the moving parts. In addition, 12V DC voltage (DC12VB), 5V DC voltage (DC5VB), and 35V DC voltage (DC35VB) are used to drive the motors and LEDs of the moving parts, and are used for the overall performance of the moving parts.

[0335] In this way, the 12V DC voltage (DC12VB) for the lighting effects of the LEDs mounted on the movable props or for the overall effects of the movable props are transmitted via different transmission lines, namely, transmission line H20a of system a and transmission line H20b of system b.

[0336] For example, as in each of the above examples, the first and second power supply voltages for the same "predetermined performance" are transmitted via separate systems, system a and system b, although a single transmission means would normally suffice. This achieves the effect of (Configuration A1-1) described above. Furthermore, by dividing the power supply voltages into system a and system b, it is possible to avoid concentration of the power supply voltage on one side, and to avoid excessive current capacity burden on only one of the transmission lines H20a and H20b, for example.

[0337] In particular, if the current capacity burden becomes excessive, it becomes necessary to use connectors and lines (electric wires) with a high rated current, which increases the line diameter (diameter of the electric wire) and connector size. By not making the current capacity burden excessive, it is possible to avoid increasing the size of the connectors CN1a and CN1b, which is advantageous for miniaturizing the connectors, miniaturizing the board, and improving the efficiency of the pattern, as described in (Configuration A1-1).

[0338] (Configuration A2-1) The gaming machine 1 is a first control unit provided at a first position; a second control unit provided at a second position; a transmission line connecting the first control unit and the second control unit; A predetermined effect can be executed by activating a performance means different from the light-emitting means while emitting light from the light-emitting means, The transmission line is a first transmission means for transmitting, via a first connector, a light emission control signal for causing the light emitting means to emit light and a first power supply voltage for driving the light emission; a second transmission means for transmitting a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector different from the first connector; The amount of current flowing due to the first power supply voltage is greater than the amount of current flowing due to the second power supply voltage, and the first transmission means has fewer lines than the second transmission means.

[0339] Each component of this (Configuration A2-1) also corresponds to the above-mentioned (Specific Example 1). In addition to the effects described in (Configuration A1-1), (Configuration A2-1) also provides the effects described below.

[0340] The first power supply voltage, 12V DC voltage (DC12VB), is a power supply voltage used by a large number of LEDs and their corresponding LED drivers, but for example, from the performance control board 30 to the LED connection board 700, it is designed to supply a maximum of approximately 9A of 12V DC voltage (DC12VB).

[0341] The 5V DC voltage (DC5VB), which is the second power supply voltage, is used in buffer circuits 701, 702, 703, 709 of LED connection board 700, P / S conversion circuit 704, and the motor control IC in motor drive unit 760. It is also used in buffer circuits on boards downstream of LED connection board 700. In other words, this 5V DC voltage (DC5VB) is mainly used as the power supply voltage for ICs. For example, the 5V DC voltage (DC5VB) from performance control board 30 to LED connection board 700 is designed to flow a maximum of approximately 2A.

[0342] In addition, the 35V DC voltage (DC35VB) is used in the motor drive IC in the motor drive unit 760, but for example, from the performance control board 30 to the LED connection board 700, the 35V DC voltage (DC35VB) is designed to flow a maximum of approximately 3A.

[0343] Here, regarding 12V DC voltage (DC12VB), transmission line H20a transmits electricity using six lines. The current capacity required for each line of 12V DC voltage (DC12VB) is 9A / 6, or 1.5A.

[0344] On the other hand, transmission line H20b uses two lines for 5V DC voltage (DC5VB) and three lines for 35V DC voltage. The current capacity required for each line of 5V DC voltage (DC5VB) is 2A / 2, or 1A. The current capacity required for each line of 35V DC voltage (DC35VB) is 3A / 3, or 1A.

[0345] This allows the connectors CN1b and CNe1b to have a smaller rated current than the connectors CN1a and CNe1a. The rated current of the connectors CN1a and CNe1a shown in FIG. 28 is 2A, and the rated current of the connectors CN1b and CNe1b shown in FIG. In the example of multiplex transmission, systems A and B have 16 and 24 lines, respectively, rather than 20 lines each.

[0346] In this embodiment, when the amount of current flowing due to the first power supply voltage, 12V DC voltage (DC12VB), is greater than the amount of current flowing due to the second power supply voltage, 5V DC voltage (DC5VB) or 35V DC voltage (DC35VB), the number of lines in system a that transmits the first power supply voltage is made smaller than the number of lines in system b that transmits the second power supply voltage. In this case, harnesses and connectors with a higher rated current can be used for system a as the first transmission means, and harnesses and connectors with a lower rated current can be used for system b as the second transmission means.

[0347] Generally, in order to ensure the current capacity of a connector CN, the larger the rated current, the thicker the pin diameter and the larger the housing.

[0348] For example, if we configure a single transmission means including the connectors CN1 and CNe1 in the single-system transmission example, we will have a 40-pin connector and a 40-wire harness, but the rated current will need to be adjusted to the 12V side, requiring a rated current of 1.5A or more. In other words, we will need a connector with the specifications shown in Figure 27 at the very least, which will result in the connector becoming larger.

[0349] In contrast, in the example of multiple system transmission, system a, which transmits 12V DC voltage (DC12VB), must have a rated current of 1.5A or more, and system b can use a rated current of 1A or more, as shown in Figure 29, for example. In the a system, by reducing the number of lines, even connectors with a rated current of 1.5A or more can be made smaller with a relatively small number of pins. In system B, smaller connectors can be used to begin with, so the number of tracks can be increased. This can facilitate miniaturization of the connectors CN1a and CNe1a and the connectors CN1b and CNe1b.

[0350] For example, in the case of a single-system transmission example, on the LED connection board 700, the 40-pin connector CN1 in Fig. 27 occupies an area of ​​33.7 mm wide and 7.6 mm long, but in the case of a multiple-system transmission example, the 16-pin connector CN1a in Fig. 28 occupies an area of ​​15.7 mm wide and 7.6 mm long, and the 24-pin connector CN1b in Fig. 29 occupies an area of ​​13.2 mm wide and 5.6 mm long. In this way, even when the two connectors CN1a and CN1b are combined, the area occupied is smaller than that of the 40-pin connector CN1.

[0351] As a result, for example, the LED connection board 700 is provided with two connectors, a 16-pin connector CN1a and a 24-pin connector CN1b, but the area occupied by the connectors on the board can be reduced compared to when a 40-pin connector CN1 is provided. In other words, the overall area occupied by the connectors on the board can be reduced. This also facilitates miniaturization of the substrate.

[0352] In the example of multiplex transmission, the number of lines in system a and system b is divided into 16 and 24, respectively, but this is just an example. Other divisions, such as 12 and 28 lines, are also acceptable. In particular, as can be seen by comparing the connectors in Figures 28 and 29, the connector in Figure 29 has a larger number of lines, but is smaller in size than the connector in Figure 28. In that sense, even if the number of lines in connector CN1a is reduced, it is possible to reduce the overall connector area.

[0353] Also, while the example in Figure 28 shows a connector with a rated current of 2 A, a smaller connector can be used as connector CN1a as long as it has a rated current of 1.5 A or more, which also makes it possible to further reduce the area that the entire connector occupies on the board.

[0354] The gaming machine 1 of the embodiment has the following (Configuration A2-2) in addition to the above (Configuration A2-1).

[0355] (Configuration A2-2) The number of lines for the performance control signal in the second transmission means is greater than the number of lines for the light emission control signal in the first transmission means.

[0356] As explained so far, in the example of multiple system transmission, system a transmits the first set (GP1) as the performance control signal (light emission control signal), and system b transmits the second set (GP2), third set (GP3), and fourth set (GP4) as the performance control signal. That is, the number of lines for the performance control signals of the first transmission means (connectors and lines of system a) is three, and the number of lines for the performance control signals of the second transmission means (connectors and lines of system b) is eleven.

[0357] Even if we exclude the enable signal LED_ENABLE, clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X, which are performance control signals not used in the LED connection board 700, the number of lines for performance control signals in the first transmission means (system a) is two, and the number of lines for performance control signals in the second transmission means (system b) is eight.

[0358] In other words, in either case, the number of lines for the performance control signal in the second transmission means is greater than the number of lines for the light emission control signal in the first transmission means. The performance control signals (including serial data signals for light emission control signals and detection signals) are transmitted between ICs, and the amount of current is extremely small compared to LED light emission or motor drive. Considering this, each performance control signal can be transmitted via either system a or system b. Therefore, by allocating more performance control signals to the smaller connector with a lower amount of current, the above (Configuration A2-1) is realized. In other words, the allocation of performance control signals makes it possible to appropriately set the number of pins.

[0359] (Configuration A3) The gaming machine 1 is a first control unit provided at a first position; a second control unit provided at a second position; a transmission line connecting the first control unit and the second control unit; A predetermined effect can be executed by activating a performance means different from the light-emitting means while emitting light from the light-emitting means, The transmission line is a first transmission means for transmitting, via a first connector, a light emission control signal for causing the light emitting means to emit light and a first power supply voltage for driving the light emission; a second transmission means for transmitting a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector different from the first connector; The second connector has a larger number of pins and a narrower pin pitch than the first connector.

[0360] Each component of this (Configuration A3) also corresponds to the above (Specific Example 1). In addition to the effects described in (Configuration A1-1), (Configuration A3) also provides the effects described below.

[0361] As described above, the connectors CN1a and CNe1a in the example of multiplexed transmission have a 16-pin configuration with a pin pitch of 1.5 mm. The connectors CN1b and CNe1b each have a 24-pin configuration with a pin pitch of 1.0 mm.

[0362] As in the example of multiple system transmission, when using the first transmission means (connector and line of system a) and the second transmission means (connector and line of system b), the connector with the narrower pitch is used for the one with the larger number of lines to be transmitted, i.e., the connector with the larger number of pins. By using a connector with a narrower pitch for the one with the larger number of pins, it is possible to make the connector more compact.

[0363] The connectors CN1b and CNe1b have a narrow pitch, which results in a small rated current, but the first power supply voltage, which requires a high rated current, can be transmitted on the side with a wider pitch and a higher rated current. This allows the connector on the second transmission means side to be made smaller, and also allows the connector on the first transmission means side to be made smaller by using a connector with a smaller number of pins.

[0364] (Configuration A4) The gaming machine 1 is a first control unit provided at a first position; a second control unit provided at a second position; a transmission line connecting the first control unit and the second control unit; A predetermined effect can be executed by activating a performance means different from the light-emitting means while emitting light from the light-emitting means, The transmission line is a first transmission means for transmitting, via a first connector, a light emission control signal for causing the light emitting means to emit light and a first power supply voltage for driving the light emission; a second transmission means for transmitting a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector different from the first connector; The connector of the second transmission means has a smaller rated current value than the connector of the first transmission means.

[0365] Each component of this (Configuration A4) also corresponds to the above-mentioned (Specific Example 1). In addition to the effects described in (Configuration A1-1), the effects described below can be obtained in (Configuration A4).

[0366] As described above, in the example of multiplexed transmission, the connectors CN1a and CNe1a have a rated current of 2A, and the connectors CN1b and CNe1b have a rated current of 1A.

[0367] As described in the explanation of (Configuration A2-1) above, when the first transmission means (connector and line of system a) and the second transmission means (connector and line of system b) are used, there is no need to make both transmission means correspond to the one with the larger current amount, either the first power supply voltage or the second power supply voltage. Therefore, the second transmission means is designed to have a small rated current value and transmit a small amount of power supply voltage, which makes it possible to reduce the size of the connectors CN1b and CNe1b on the second transmission means side.

[0368] (Configuration A5-1) The gaming machine 1 is a first control unit provided at a first position; a second control unit provided at a second position; a transmission line connecting the first control unit and the second control unit; A predetermined effect can be executed by activating a performance means different from the light-emitting means while emitting light from the light-emitting means, The transmission line is a first transmission means for transmitting, via a first connector, a light emission control signal for causing the light emitting means to emit light and a first power supply voltage for driving the light emission; a second transmission means for transmitting a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector different from the first connector; The connector of the second transmission means has a pin with a smaller cross-sectional size than the connector of the first transmission means.

[0369] Each component of this (Configuration A5-1) also corresponds to the above-mentioned (Specific Example 1). In addition to the effects described in (Configuration A1-1), (Configuration A5-1) also provides the effects described below.

[0370] As mentioned above, the pin diameter of the connectors CN1a and CNe1a is 0.6 mm, and the pin diameter of the connectors CN1b and CNe1b is 0.5 mm. Because cylindrical pins are assumed, the cross-sectional size of the pins of the connectors CN1b and CNe1b of the second transmission means is smaller than that of the connectors CN1a and CNe1a of the first transmission means.

[0371] When the first power supply voltage and the second power supply voltage are transmitted by the first transmission means and the second transmission means, respectively, there is no need to make both transmission means compatible with the first power supply voltage or the second power supply voltage, whichever has the larger current amount. Therefore, the connector of the second transmission means has a smaller pin diameter than the connector of the first transmission means, i.e., a smaller current capacity, and transmits a power supply voltage with a smaller current amount. This makes it possible to miniaturize the connector of the second transmission means. In particular, the connectors CN1a and CNe1a not only have a small current capacity, but also use pins with small cross-sectional sizes, which allows for more reliable miniaturization and a reduction in the area they occupy on the board.

[0372] The terminals of the connector CN are not only cylindrical pins, but also plate-shaped and elliptical cylindrical, etc., but in terms of cross-sectional size, if we consider the size in the direction in which the pins are arranged, or the size in the pitch direction, this is advantageous for miniaturizing the connector. Also, in terms of current capacity, the cross-sectional size of the pin may be considered as the cross-sectional area or the maximum size of the cross section.

[0373] The gaming machine 1 of the embodiment has the following (Configuration A5-2) in addition to the above (Configuration A5-1).

[0374] (Configuration A5-2) The diameter of the line in the second transmission means is smaller than the diameter of the line in the first transmission means.

[0375] As the above (Specific Example 1), the applicable wire range for the wire material of the line was shown. The connectors CN1a and CNe1a have a conductor size ranging from AWG28 to AWG24, and an insulator outer diameter of 0.76 mm to 1.2 mm. The connectors CN1b and CNe1b have a conductor size ranging from AWG32 to AWG28, and an insulator outer diameter of 0.4 mm to 0.8 mm. Within each applicable wire range, the diameter of the line in the second transmission means can be made smaller than the diameter of the line in the first transmission means. For example, the line connected to the connector CN1a has a diameter of 0.8 mm, and the line connected to the connector CN1b has a diameter of 0.6 mm.

[0376] As described above, the second transmission means can have a smaller current capacity than the first transmission means, and therefore the diameter of the wires can be smaller. This not only allows the connectors CN1b and CNe1b to be smaller, but also allows the wires to be thinner, making them easier to handle.

[0377] (Configuration A6-1) The gaming machine 1 is a first control unit provided at a first position; a second control unit provided at a second position; a transmission line connecting the first control unit and the second control unit; A predetermined effect can be executed by activating a performance means different from the light-emitting means while emitting light from the light-emitting means, The transmission line is a first transmission means for transmitting, via a first connector, a light emission control signal for causing the light emitting means to emit light and a first power supply voltage for driving the light emission; a second transmission means for transmitting a performance control signal for controlling the performance means and a second power supply voltage for signal processing via a second connector different from the first connector; the second transmission means has a larger number of ground transmission lines than the first transmission means; The performance control signal is configured by a plurality of sets of signal lines, each set including a plurality of signal lines; The connector of the second transmission means is assigned to each pin so that some or all of the pins assigned to ground are located between pins assigned to one set of performance control signals and pins assigned to another set of performance control signals when viewed in the longitudinal direction of the connector.

[0378] Each component of this (Configuration A6-1) also corresponds to the above-mentioned (Specific Example 1). In addition to the effects described in (Configuration A1-1), (Configuration A6-1) also provides the effects described below.

[0379] In the multiplexed transmission example, the first transmission means (the connectors and lines of the a system) has seven ground lines, and the second transmission means (the connectors and lines of the b system) has eight ground lines.

[0380] The performance control signals are made up of a plurality of sets of signal lines, each set consisting of a plurality of signal lines, as shown as first to fourth sets (GP1 to GP4).

[0381] The performance control signals transmitted through multiple sets of signal lines that make up one set can be considered as a set of signals related to the same IC chip. For example, there are multiple performance control signals that are input to the same IC chip to control that IC chip, and multiple performance control signals that are input signals and output signals to the same IC chip.

[0382] For example, the clock signal LED_CLK and the data signal LED_DATA, which are signals of the first set (GP1), are input to the same chip as the LED drivers 705, 707, etc. Note that the enable signal LED_ENABLE is not used in the LED drivers 705, 707, etc., and is therefore considered unused. However, depending on the type of driver, the enable signal LED_ENABLE is also input to the same LED driver as the clock signal LED_CLK and the data signal LED_DATA, and therefore G can be treated as a set in terms of the transmission path.

[0383] In a similar way, the second set (GP2) of clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST is a set of control signals for the motor control IC. The fourth set (GP4) of the load signal S_IN_LOAD, the clock signal S_IN_CLK, and the serial data signal S_IN_DATA is a set of control signals for the P / S conversion circuit 704. The third set (GP3) of clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X are unused in this embodiment, but may be used in some models and serve as signals for a certain IC, so they can be considered as one set.

[0384] The connectors CN1b and CNe1b of the second transmission means are assigned pins so that some of the pins assigned to ground are located between pins assigned to one set of performance control signals and pins assigned to another set of performance control signals when viewed in the longitudinal direction of the connectors CN1b and CNe1b.

[0385] That is, as shown in Figure 16, in the odd-numbered pin row of connectors CN1b and CNe1b, the second set of performance control signals (GP2) is arranged from pins 7 to 15, and across the ground at pin 17, the fourth set of performance control signals (GP4) is arranged from pins 19 to 23.

[0386] By arranging a ground pin between the pins of a certain set of performance control signals and the pins of another set of performance control signals, the sets of performance control signals can be separated via the ground, thereby reducing crosstalk noise between each set. For example, as shown in Figure 16, by having a ground pin between the second group (GP2), which is a group of performance control signals for the motor LSI, and the fourth group (GP4), which is a group of serial signal transmissions for transmitting detection signals from various sensors, crosstalk between the signals of these different groups can be reduced.

[0387] Furthermore, among the performance control signals for each group, the clock signal is the one that is most likely to affect other groups as high-frequency noise. Therefore, as shown in Figure 16, it is recommended to separate the clock signal LSI_CLK for group 2 (GP2) from group 4, and the clock signal S_IN_CLK for group 4 (GP4) from group 2 (GP2), with a ground in between. In other words, it is desirable not to assign clock signals to pins 15 and 19, which are adjacent to the ground terminal for pin 17. This will greatly reduce crosstalk.

[0388] The odd and even rows are physically far apart. For example, looking at the pad layout in the bottom row of Figure 29, we can see that the pins on the odd and even rows are far apart. Therefore, crosstalk between adjacent terminals on the odd and even rows is almost not an issue. What is effective is to place a ground between pairs in the longitudinal direction.

[0389] In the example of Figure 16, one of the 17 pins is used as a ground terminal between the second group (GP2) and the fourth group (GP4), but multiple pins in the longitudinal direction may be used as ground terminals to further separate the second group (GP2) and the fourth group (GP4).

[0390] Meanwhile, Figures 34A and 34B show other examples of assignments for connectors CN1b and CNe1b of system b. This is an example in which the third group (GP3) and the fourth group (GP4) in Figure 16 are swapped. Figure 34A shows the pin assignments from pin 1 to pin 24, and Figure 34B shows the actual arrangement of connectors CN1b and CNe1b.

[0391] As the third group (GP3), the clear signal CLR_X is assigned to the 19th pin, the data signal DATA_X is assigned to the 21st pin, and the latch signal LATCH_X is assigned to the 23rd pin. As the fourth group (GP4), the load signal S_IN_LOAD is assigned to the 20th pin, the clock signal S_IN_CLK is assigned to the 22nd pin, and the serial data signal S_IN_DATA is assigned to the 24th pin.

[0392] In the embodiment, the third set of clear signal CLR_X, data signal DATA_X, and latch signal LATCH_X are unused signals, but a circuit configuration using these signals may be adopted, for example, in the LED connection board 700. For example, the third set of performance control signals may be used as motor drive control signals to a motor driver for motor control without using an LSI. In this case, if the second group (GP2) and the third group (GP3) are in the same column as shown in Figure 34B, it is effective to use pin 17 as a ground terminal to achieve crosstalk reduction between the second group (GP2) and the third group (GP3).

[0393] In addition, in the embodiment, only the first set (GP1) is transmitted in system a, but if multiple sets are transmitted in system a, it is preferable to interpose ground terminals between sets of performance control signals lined up in the longitudinal direction on the connectors CN1a and CNe1a side as well. As mentioned earlier in the explanation of Figure 16, the ground for system a and the ground for system b are a common ground, and it is possible to consolidate the grounds in either the system a or system b harness. However, by separating the grounds for system a and system b, the above noise countermeasures can be taken for both systems a and b. For example, in the example of Figure 16, system a transmits only the first set (GP1) of performance control signals, but it may also be assigned to transmit multiple sets of performance control signals. In that case, it is recommended that some or all of the pins assigned to ground in system a be positioned between the pins of the performance control signal sets in the longitudinal direction of the connector.

[0394] The gaming machine 1 of the embodiment has the following (Configuration A6-2) in addition to the above (Configuration A6-1).

[0395] (Configuration A6-2) The number of lines for the performance control signal in the second transmission means is greater than the number of lines for the light emission control signal in the first transmission means.

[0396] As described above, in the example of multiple system transmission, system a transmits the first set (GP1) as the performance control signal (light emission control signal), and system b transmits the second set (GP2), third set (GP3), and fourth set (GP4) as the performance control signal. That is, the number of lines for the performance control signals of the first transmission means (connectors and lines of system a) is three, and the number of lines for the performance control signals of the second transmission means (connectors and lines of system b) is eleven. Even excluding unused signals, the number of lines for the performance control signals of the first transmission means (system a) is two, and the number of lines for the performance control signals of the second transmission means (system b) is eight.

[0397] In such a case, it is highly effective to separate the performance control signals by the ground on the b system side, which has many performance control signals.

[0398] The gaming machine 1 of the embodiment includes the following (Configuration A6-3) in addition to the above (Configuration A6-1) or (Configuration A6-2).

[0399] (Configuration A6-3) The first power supply voltage and the second power supply voltage are power supply voltages used to produce the predetermined effect.

[0400] As explained above in (Configuration A1-2), the predetermined effect in this case is, for example, a light-emitting effect of decorative LEDs as the effect means. Another example of a predetermined effect is the effect of LEDs mounted on a movable prop. Furthermore, the predetermined effect can also be the overall effect of a moving part, such as the movement of a motor in a moving part or the illumination of an LED mounted on the moving part.

[0401] Although we will avoid redundant explanation of specific examples, as in each of the above examples, the first and second power supply voltages for achieving the same "predetermined performance" are transmitted via separate systems, system a and system b, although a single transmission means would normally suffice. By dividing the power supply voltages into system a and system b, it is possible to avoid the power supply voltage concentrating on one side, and to avoid the current capacity burden becoming excessive on only one of the transmission lines H20a and H20b, for example. This is advantageous for miniaturizing connectors, miniaturizing circuit boards, and improving pattern efficiency.

[0402] (Configuration B1-1) The gaming machine 1 is a first substrate; a second substrate to which a power supply voltage is supplied from the first substrate; and On the second board, the power supply voltage terminal of the connector that electrically connects to the first board is connected to noise suppression means, and a test point for the power supply voltage wiring pattern on the board is provided between the power supply voltage terminal and the noise suppression means.

[0403] In the case of this (Configuration B1-1), the following corresponding example (Specific Example 2) is assumed. (Example 2) 1st board: Performance control board 30 2nd board: LED connection board 700 Connector: Connector CN1 Power supply voltage: 12V DC (DC12VB), 5V DC (DC5VB) Power supply voltage terminals: 12V DC voltage (DC12VB) terminals (pins 12, 14, 24, 26, 28, and 30) of connector CN1 in Figure 14, and 5V DC voltage (DC5VB) terminals (pins 4 and 6) Noise suppression means: Capacitors C1, C4, Capacitors C2, C3 Test points: Test points TP51, TP50

[0404] The performance control board 30 supplies the LED connection board 700 with a power supply voltage of 12V DC (DC12VB) or 5V DC (DC5VB). The 12V DC (DC12VB) terminals, pins 12, 14, 24, 26, 28, and 30, of the connector CN1 of the LED connection board 700 are connected to a capacitor C4, and a test point TP51 ​​is provided in the connection path. Furthermore, the fourth and sixth pins of the connector CN1, which are terminals for a 5V DC voltage (DC5VB), are connected to a capacitor C3, and a test point TP50 is provided in the connection path.

[0405] The actual pattern on the circuit board for the circuit configuration of FIG. 20 will be described. As the wiring patterns of the LED connection board 700, the front layer is shown in FIG. 35, the back layer in FIG. 36, the first inner layer in FIG. 37, and the second inner layer in FIG. 35. Also, Fig. 39 is an enlarged view of area AR1 on the front surface layer in Fig. 35, Fig. 41 is an enlarged view of area AR2, and Fig. 42 is an enlarged view of area AR3 on the back surface layer in Fig. 36.

[0406] Moreover, the wiring patterns of the back surface layer in Fig. 36, the first inner layer in Fig. 37, and the second inner layer in Fig. 38 are all shown in a perspective state as seen from the front surface layer side in Fig. 35. Therefore, Fig. 36 shows a mirror image of the back surface layer of the actual LED connection board 700.

[0407] In each of these figures, the gray colored areas are conductive pattern wiring, and the white square areas are pads to which the terminals of electronic components are soldered. The uncolored areas other than pads are insulating areas where no conductive pattern is formed. The black circles represent holes such as through-holes or vias. The areas surrounded by a continuous gray color around the black circle are areas where the wiring pattern on that surface is conductive to the via (or through-hole). The areas with an uncolored area around the black circle are areas where the surrounding conductive pattern and the via are insulated. The areas with circles on a gray background are conductive areas such as test points and pads.

[0408] Although through holes and vias are strictly distinguished, in this embodiment they are collectively referred to as "vias" in the sense of interlayer conductive portions. "Via" collectively refers to through-hole vias, blind vias, pellet vias, etc.

[0409] The reference numerals in each figure indicate the location of the components by adding "p" before the reference numerals of the components in the circuit diagrams shown in Figures 20, 22 to 26. For example, "pCN1" indicates the location where the connector CN1 is located, and "p701" indicates the location where the buffer circuit 701 is located. In the following, the "circuit diagrams shown in Figures 20 and 22 to 26" will be simply referred to as "circuit diagrams."

[0410] As shown in FIG. 35, connectors CN1, CN2, CN3, . . . are arranged at positions pCN1, pCN2, pCN3, . Also, on the surface layer, buffer circuits 701, 702, 703 and P / S conversion circuit 704 shown in FIG. 20 and LED driver 707 shown in FIG. 23 are arranged at positions p701, p702, p703, p704, and p707, respectively. Also, on the surface layer, buffer circuits 708, 717, and 718 shown in FIG. 24 are arranged at positions p708, p717, and p718, respectively. Also, on the surface layer, the buffer circuit 714 shown in FIG. 25 is disposed at a position p714.

[0411] Although no circuit diagram is shown on the back surface layer of Fig. 36, the motor control IC (motor controller) in the motor drive unit 760 of Fig. 19 is placed at position p710, and four motor drive ICs (motor drivers) are placed at positions p712, p713, p715, and p716. Also, the buffer circuit 709 shown in Fig. 19 is placed at position p709. Also, on the back surface layer, the LED driver 705 shown in FIG. 22 is disposed at a position p705.

[0412] 37 is a layer on which solid power supply patterns are formed, including a pattern PT5V for a 5V DC voltage (DC5VB) and a pattern PT12V for a 12V DC voltage (DC12VB), as well as patterns PT35Va and PT35Vb for a 35V DC voltage (DC35VB). The second inner layer in FIG. 38 is a layer on which a ground pattern PTg is formed as a solid ground.

[0413] Area AR1 around connector CN1 (position pCN1) is explained in an enlarged manner in Figure 39. At position pCN1 in the bottom center of Figure 39, 40 pads (20 pads in each of two rows) are formed corresponding to the terminals of the 40-pin connector CN1. For ease of explanation, numbers such as "1" to "40" corresponding to the pin numbers are assigned nearby the 1st to 40th pins in the figure (see Figure 14 for the pin assignment of connector CN1).

[0414] First, the ground wiring will be described. On the surface layer, a ground pattern PTg is formed as a solid ground over almost the entire surface of the board. The pads corresponding to pins 1, 2, 8, 9, 10, 16, 18, 19, 20, 22, 29, 32, 33, 34, 39, and 40 of connector CN1 are connected to the ground pattern PTg. The ground pattern PTg is connected to the ground pattern PTg of the second inner layer by a large number of vias.

[0415] The pads for pins 12, 14, 24, 26, 28, and 30, which are supplied with 12V DC voltage (DC12VB), are connected to the power supply pattern PT12V. The power supply pattern PT12V continues to the distant power supply pattern PT12V (also called power supply pattern PT12Va for distinction) via fuse FZ2 (position pFZ2). The power supply pattern PT12Va has pads (positions pC1 and pC4) on which capacitors C1 and C4 are placed. Furthermore, four vias BR3 are provided in the pattern PT12Va, and the pattern PT12V is connected to the power supply pattern PT12V of the first inner layer in FIG. Furthermore, the pattern PT12Va is provided with a test point TP51 ​​near the via BR3.

[0416] The pads for pins 4 and 6 of connector CN1, to which a 5V DC voltage (DC5VB) is supplied, are connected to power supply pattern PT5V. Power supply pattern PT5V continues to a separate power supply pattern PT5V (also referred to as power supply pattern PT5Va for distinction) via fuse FZ1 (position pFZ1). Pads on which capacitors C2 and C3 are placed are formed on power supply pattern PT5Va (positions pC2 and pC3). Furthermore, two vias BR1 are provided in the power supply pattern PT5Va, and the power supply pattern PT5V is connected to the power supply pattern PT5V on the first inner layer in FIG. Furthermore, the power supply pattern PT5Va is provided with a test point TP50 near the via BR1.

[0417] The pads of pins 36 and 38 of connector CN1, to which a 35V DC voltage (DC35VB) is supplied, are connected to the power supply pattern PT35V. The pads of Schottky barrier diodes D10 and D11 shown in Figure 26 are formed on the power supply pattern PT35V (positions pD10 and pD11). The power supply pattern PT35V is connected to two separate power supply patterns PT35V (PT35Va, PT35Vb) via Schottky barrier diodes D10 and D11.

[0418] The power supply pattern PT35Va has a pad for an electrolytic capacitor C57 (position pC57) and four vias BR4 formed therein. This power supply pattern PT35Va is connected to the power supply pattern PT35Va on the first inner layer in FIG. 37 by the vias BR4. Furthermore, a pad for an electrolytic capacitor C63 (position pC63) and four vias BR5 are formed in the power supply pattern PT35Vb in Fig. 39. This power supply pattern PT35Vb is connected to the power supply pattern PT35Vb in the first inner layer in Fig. 37 by the vias BR5.

[0419] The power supply pattern PT35Va that reaches the first inner layer in Fig. 37 is connected to the fuses FZ3 and FZ4 shown in Fig. 26. In addition, the power supply pattern PT35Vb is connected to the fuses FZ5 and FZ6 in Fig. 26. That is, as shown in Figures 37 and 35, vias BR6 and BR9 are formed in the power supply pattern PT35Va, and vias BR7 and BR8 are formed in the power supply pattern PT35Vb, and they are connected to the surface layer, respectively. Then, as shown in Figure 35, fuses FZ3, FZ4, FZ5, and FZ6 are placed at positions pFZ3, pFZ4, pFZ5, and pFZ6, forming the circuit of Figure 26.

[0420] So far we have explained the wiring pattern of the LED connection board 700, but as can be seen from the circuit diagram and wiring pattern, a test point TP51 ​​is provided between the 12V DC voltage (DC12VB) terminal of the connector CN1 and the capacitors C1 and C4, which are noise suppression means. A test point TP50 is provided between the 5V DC voltage (DC5VB) terminal of the connector CN1 and the capacitors C2 and C3, which are noise suppression means.

[0421] Various test points are provided on the board, but by providing test points on the power supply voltage wiring, it is possible to check the stability of the power supply voltage transmitted from other boards. Ideally, the state of the power supply voltage on the power supply pattern on the board should be constant, but in reality this is not always the case. Therefore, for the 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) transmitted from the performance control board 30, test points are provided between the connector terminals and the noise suppression means. This allows the most accurate detection of the power supply voltage status at the input stage, making it ideal for checking the power supply voltage transmission status between boards.

[0422] In terms of the circuit, providing a test point between the connector terminal and the noise suppression means providing the test point at a location that does not pass through any electronic components such as resistors, capacitors, or IC chips, except for fuses (FZ1, FZ2), which do not normally affect voltage or current, when viewed from the power terminal of the connector. This is because the noise suppression means here is the capacitors (C1, C4 or C2, C3) connected between the power supply line and the ground. Therefore, the test points TP51 ​​and TP50 can properly detect the power supply voltage state at the input stage without being affected by electronic components.

[0423] Furthermore, if a fuse is placed between the connector terminal and the noise suppression means, it is appropriate to place the test point closer to the noise suppression means than the fuse (FZ1, FZ2) in order to detect the input stage state of the power supply voltage actually applied to each circuit on the board.

[0424] In terms of the circuit, it is sufficient to set up a test point between the connector terminal and the noise suppression means, but in terms of physical location on the board, it is best to set up the test point on the wiring between the connector terminal and the noise suppression means, as far away from the connector as possible.

[0425] For example, if test point TP51 ​​were located anywhere on the power supply pattern PT12V (including PT12Va), it would be located between the connector terminal and the noise suppression means, but it is located on the power supply pattern PT12Va, particularly away from the connector CN1. Furthermore, in terms of the circuit, the test point TP51 ​​may be provided anywhere on the power supply pattern PT5V (including PT5Va), but it is provided on the power supply pattern PT5Va, particularly away from the connector CN1.

[0426] The connector CN is one of the tallest electronic components mounted on a circuit board. If a test point is placed too close to the connector CN, it will be difficult to apply the probe of the testing equipment. As in the above example, by providing test points TP51 ​​and TP50 at positions as far away as possible from connector CN1, it becomes easier to apply the probes. Specifically, it is recommended to place the test points at a position that is at least half the shortest linear distance between the connector and the farthest part of the pattern area where the test points can be placed, as seen from the connector CN. Test points TP51 ​​and TP50 in Figure 39 satisfy this condition.

[0427] The test point refers to a portion on the substrate that is not covered with an insulating protective film and is therefore electrically conductive to the wiring pattern. Specific examples of test points include those formed in the shape of a pad, those in which part of a line in a wiring pattern is formed in the shape of a circular pad, those formed as a conductive portion around a via, and those formed by piling up solder. For example, the circular portions in the wiring continuing to the pads for the third pin, the fifth pin, etc. of the connector CN1 in FIG. 39 correspond to the test points TP1, TP2, etc. in FIG. Whatever the form, any conductive part that can be inspected by applying a probe to it on an insulating coated board can be a test point.

[0428] The wiring patterns in Figures 35 to 39 correspond to the circuit in Figure 20, but in the case of the circuit in Figure 21, the test points TP51 ​​and TP50 are similarly provided between the power supply voltage terminals of the connectors CN1a and CN1b and the capacitors (C1 and C4, or C2 and C3) that serve as noise suppression means. Therefore, the same effect as above can be obtained in the case of the circuit example in Figure 21. The following (Configuration B1-2) to (Configuration C7) will also be explained using the example circuit and pattern of FIG. 20, but they can also be applied to the circuit of FIG.

[0429] The gaming machine 1 of the embodiment has the following (Configuration B1-2) in addition to the above (Configuration B1-1).

[0430] (Configuration B1-2) On the second board, the ground terminal of the connector is also connected to the noise suppression means, and a test point for the ground wiring pattern on the board is provided between the ground terminal and the noise suppression means.

[0431] Capacitors (C1, C4) that are noise suppression means are arranged between the power supply pattern PT12V and the ground pattern PTg. Furthermore, capacitors (C2, C3) that are noise suppression means are arranged between the power supply pattern PT5V and the ground pattern PTg. As described above, the ground terminal of the connector CN1 is connected to the ground pattern PTg. That is, in the LED connection board 700, the ground terminal of the connector CN1 is also connected to the noise suppression means.

[0432] 39, a test point TP30 is formed on the ground pattern PTg. This test point TP30 is provided between the ground terminal of the connector CN1 and the noise suppression means (C1, C4 or C2, C3).

[0433] With this configuration, it becomes possible to inspect the 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) transmitted from the performance control board 30 at the position that is most suitable for checking the transmitted power supply voltage on both the power line side and the ground side.

[0434] The gaming machine 1 of the embodiment includes the following (Configuration B1-3) in addition to the above (Configuration B1-1) or (Configuration B1-2).

[0435] (Configuration B1-3) The test points are pad-type and are arranged on the mounting surface of the connector.

[0436] In this case, the pad type refers to a type that is formed as a circle, a square, or the like on the surface of the substrate, and serves as a conductive portion to which a probe can be applied, and is not a hole such as a via.

[0437] FIG. 40A shows an enlarged view of the test point TP50 in FIG. The test point TP50 in Fig. 40A is a pad type, i.e., a circular area formed as a conductive portion on the surface of the substrate, and is not a via to another layer. Test point TP51 ​​in FIG. 39 is also a similar pad type.

[0438] On the other hand, FIGS. 40B and 40C show an example in which the test point TP50 is a land type around a via. FIG. 40B shows an example in which a via BR1 and the land around it are used as a test point TP50 as a conductive part without performing surface insulation treatment on the surface of the board. FIG. 40C shows an example in which only the land on the upper surface side of the via BR1 is used as a conductive part, without surface insulation treatment, as a test point TP50. 40B and 40C show examples of forming test points using vias.

[0439] The test points may be of the land type as described above, or may be formed using the top surface of a via. However, in FIG. 39, the test points TP51 ​​and TP50 are not of the via top surface type, but are instead of the pad type shown in FIG. 40A. The area around the connector is particularly densely packed with wiring, and there are many interlayer wirings, so by making the test points TP51 ​​and TP50 pad-type, it is possible to prevent them from affecting the wiring patterns on the back surface or inner layers.

[0440] The test points TP1 to TP10 shown in FIGS. 20 and 21 are test points for each performance control signal, and as shown in FIG. 39, are provided as pads on the mounting surface side of the connector CN1. In Figure 39, only the symbols "TP1," "TP2," and "TP10" are shown to avoid cluttering the diagram. In the case of connector CN1, test points TP1 to TP10 are arranged in ascending order of the connector's terminal numbers, so the positions of test points TP3 to TP9 should be understood as circular pads on the wiring path in the diagram. In other words, test points TP3 to TP9 are circular pads on the wiring that follow the pads of pins 7, 11, 13, 15, 23, 31, and 35.

[0441] These test points TP1 to TP10 are also pad-type, but if they are provided around the connector, using pad-type test points will prevent them from affecting the wiring patterns on the back surface layer or inner layer.

[0442] The test points TP1 to TP10 are provided relatively close to the position pCN1 where the connector CN1 is located. For example, they are provided at positions closer to the connector CN1 than the center of the wiring length from the terminal pad of the connector CN1 to the buffer circuit 701 or 703. As mentioned above, the test point TP has the advantage of being easier to apply a probe to by being separated from the connector CN, which is a relatively tall component, but this is contrary to that.

[0443] This is because test points TP1 to TP10 are test points related to each performance control signal. By forming the test points related to performance control signals as close as possible to connector CN1, it is possible to obtain the advantage that the correspondence with the terminal numbers is easy to understand. In other words, it is easy for the operator to distinguish the performance control signal to be tested. It should be noted that the power supply pattern and ground pattern are easy to identify on the board, so it is advisable to place them away from components such as connectors as described above to make it easier to apply probes to them.

[0444] Furthermore, by not providing test points for the unused terminals of connector CN1, 17th pin, 21st pin, 25th pin, and 27th pin, it is possible to obtain the effect of mitigating the complexity of the pattern on the mounting surface.

[0445] (Configuration B2-1) The gaming machine 1 is a first substrate; a second board to which a control signal is supplied from the first board; and The second substrate is an IC chip to which the control signal is input; one or more noise suppression means for the control signal; The noise suppression means includes a test point formed in a wiring pattern between one or more of the noise suppression means that is provided closest to the IC chip on the wiring path and the input terminal of the control signal of the IC chip.

[0446] In the case of this (Configuration B2-1), the following corresponding example (Specific Example 3) is assumed. (Example 3) 1st board: Performance control board 30 2nd board: LED connection board 700 Control signals: Clock signal LED_CLK (CLK_A), data signal LED_DATA (DATA_A) IC chip: LED driver 705, 707 One or more noise suppression means: buffer circuits 701, 702 Noise suppression means provided closest to the IC chip: buffer circuit 702 Input terminal: LED driver 705, 707 terminal 48 (SCLK), terminal 47 (SDATA) Test points: Test points TP11, TP12, TP15, TP16

[0447] The clock signal LED_CLK and the data signal LED_DATA are transmitted from the performance control board 30 to the LED connection board 700, where they are waveform-shaped by buffer circuits 701 and 702 and input to LED drivers 705 and 707 as the clock signal CLK_A and the data signal DATA_A. As can be seen from FIG. 20 (or FIG. 21) and FIG. 22, the test point TP11 is provided on the wiring of the data signal DATA_A between the buffer circuit 702 and the LED driver 707. The test point TP12 is provided on the wiring of the clock signal CLK_A between the buffer circuit 702 and the LED driver 707.

[0448] As can be seen from FIG. 20 (or FIG. 21) and FIG. 23, the test point TP15 is provided on the wiring of the data signal DATA_A between the buffer circuit 702 and the LED driver 707. The test point TP16 is provided on the wiring of the clock signal CLK_A between the buffer circuit 702 and the LED driver 707.

[0449] Figure 42 is an enlarged view of area AR3 on the back surface layer of Figure 36. As shown in the figure, at position p705 where the LED driver 705 is placed, a test point TP11 is formed on the wiring between pad Pd47 corresponding to terminal 47 (SDATA) and via BR21, and a test point TP12 is formed on the wiring between pad Pd48 corresponding to terminal 48 (SCLK) and via BR22.

[0450] Figure 41 is an enlarged view of area AR2 on the surface layer of Figure 35, and as shown, at position p707 where the LED driver 707 is located, a test point TP15 is formed on the wiring between pad Pd47 corresponding to terminal 47 (SDATA) and via BR25, and a test point TP16 is formed on the wiring between pad Pd48 corresponding to terminal 48 (SCLK) and via BR26.

[0451] The vias BR21 and BR25 are connected to the 17th terminal (Y2) of the buffer circuit 702, and the vias BR22 and BR26 are connected to the 18th terminal (Y1) of the buffer circuit 702.

[0452] That is, with this configuration, the data signal DATA_A and clock signal CLK_A, which are input to the LED drivers 705 and 707 and have been waveform-shaped and noise-suppressed by the buffer circuits 701 and 702, can be observed at the test points TP11, TP12, TP15, and TP16. This means that the signals themselves input to the IC chip can be inspected, making this the most suitable way to check control signals.

[0453] The gaming machine 1 of the embodiment has the following (Configuration B2-2) in addition to the above (Configuration B2-1).

[0454] (Configuration B2-2) The test points are pad-type and are arranged on the mounting surface of the IC chip.

[0455] As shown in Figures 41 and 42, test points TP11, TP12, TP15, and TP16 are formed as pads. As explained in (Configuration B1-2), using pads prevents the test points TP from affecting the wiring patterns on other layers. In particular, the areas around IC chips such as LED drivers 705 and 707 are densely packed with wiring and have many interlayer wirings, making pads ideal. Furthermore, by using the surface as the mounting surface of the IC chip, when the probe is applied, it is easy to visually check the relationship with the terminals of the IC chip.

[0456] The gaming machine 1 of the embodiment includes the following (Configuration B2-3) in addition to the above (Configuration B2-1) or (Configuration B2-2).

[0457] (Configuration B2-3) The control signals include a plurality of control signals that are input to the same IC chip as a set, On the second substrate, the test points for each of the plurality of control signals forming a set are arranged on the same surface.

[0458] As previously exemplified as the first set (GP1), the second set (GP2), and the fourth set (GP4), a plurality of control signals are grouped into sets. The first group (GP1) of performance control signals is a clock signal LED_CLK and a data signal LED_DATA (the enable signal LED_ENABLE is not used in this embodiment). For the clock signal LED_CLK, a test point TP5 is provided on the wiring from pin 13 of connector CN1, and for the data signal LED_DATA, a test point TP6 is provided on the wiring from pin 15. These test points TP5 and TP6 are provided on the surface layer of the LED connection board 700 as shown in FIG.

[0459] Test points TP1, TP2, TP3, TP9, and TP10 for the second group (GP2) of performance control signals, namely, clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, and reset signal LSI_RST, are also provided on the surface layer of the LED connection board 700. Test points TP4, TP7, and TP8 for the fourth group (GP4) of performance control signals, ie, the load signal S_IN_LOAD, the clock signal S_IN_CLK, and the serial data signal S_IN_DATA, are also provided on the surface layer of the LED connection board 700.

[0460] In this way, the test points for each of the multiple control signals in a group are arranged on the same surface, making it easier for the operator to check each of the performance control signals that make up the same group. In the embodiment, all of the test points TP1 to TP10 are formed on the surface layer as shown in FIG. 39, but by forming them on the mounting surface of the connector CN1, it becomes easier to distinguish each performance control signal in relation to the terminal. However, some or all of the sets may be formed on the back surface layer. By forming test points for multiple performance control signals of the same set on the same surface, checking work becomes easier.

[0461] (Configuration B3-1) The gaming machine 1 is a first substrate that is a multilayer substrate having a front surface layer, a back surface layer, and one or more inner layers; The first substrate is a power supply voltage pattern to which a power supply voltage terminal of a connector attached to the front surface layer or the back surface layer is connected and a ground pattern to which a ground terminal of the connector is connected are provided on the inner layer; A test point of either the power supply voltage pattern or the ground pattern is provided on the front surface layer or the back surface layer near an interlayer conductive portion for electrical connection with the inner layer.

[0462] In the case of this (Configuration B3-1), the following corresponding example (Specific Example 4) is envisioned. (Example 4) 1st board: LED connection board 700 Connector: Connector CN1 Power supply pattern: Power supply pattern PT12V, PT5V Ground pattern: Ground pattern PTg Test points: Test points TP51, TP50

[0463] As described above, the test point TP51 ​​is provided on the power supply pattern PT12V (PT12Va), and the test point TP50 is provided on the power supply pattern PT5V (PT5Va), which are provided on the surface layer of FIG. For the sake of explanation, the surface in Fig. 35 is referred to as the "surface layer," but this is merely one surface of the LED connection board 700. If the surface in Fig. 36 is referred to as the "surface layer," the surface in Fig. 35 would be the back surface layer. In that sense, "the surface layer or the back surface layer" in (Configuration B3-1) refers to the surface that becomes the surface of the board, and not an inner layer.

[0464] The power supply patterns PT12V and PT5V are formed on the first inner layer in FIG. 37, and the ground pattern PTg is formed on the second inner layer in FIG. The test point TP50 is provided near a via BR1, which is an interlayer conductive portion connecting the power supply pattern PT5V of the first inner layer and the power supply pattern PT5V of the surface layer (see FIGS. 39 and 40A). The test point TP51 ​​is provided near a via BR3, which is an interlayer conductive portion connecting the power supply pattern PT12V of the first inner layer and the power supply pattern PT12V of the surface layer (see FIG. 39).

[0465] With this configuration, the test points TP50 and TP51 ​​are suitable for checking the power supply state on the inner layer side at the boundary between the front layer (or back layer) and the inner layer.

[0466] In particular, the test point TP50 is near the via BR1 that connects the power supply pattern PT5V on the surface layer and the first inner layer. The test point TP51 ​​is located near the via BR3 that connects the power supply pattern PT12V on the surface layer and the first inner layer. This also eliminates the need to create test point vias from the first inner layer just to check the first inner layer, making the board pattern configuration more efficient.

[0467] For the ground, a test point TP30 is provided near the via BR35 as shown in Figure 39. This makes it possible to use the test point TP30 to check the ground on the inner layer at the boundary between the top layer (or bottom layer) and the inner layer.

[0468] In addition, power supply patterns and ground patterns are often thick or solid patterns even on the surface layer. By placing test points near vias in areas with large conductive pattern wiring, the test points become more visible.

[0469] The gaming machine 1 of the embodiment has the following (Configuration B3-2) in addition to the above (Configuration B3-1).

[0470] (Configuration B3-2) The test points are pad-type points near the interlayer conductive portions or land-type points around the interlayer conductive portions.

[0471] In the example of Figure 39, as shown in Figure 40A, the test point TP50 is provided as a pad near the via BR1. This allows the test point to be formed without affecting the patterns on other layers. The same applies to the test point TP51 ​​and the test point TP30.

[0472] On the other hand, the land portion on the top surface of via BR1 may be used as test point TP50, as shown in Figures 40B and 40C. This eliminates the need to provide test point TP50 separately from the via, further improving the efficiency of the board pattern configuration. Similarly, test point TP51 ​​may be formed using the land portion on the top surface of via BR3. Furthermore, the test point TP30 of the ground pattern PTg may also be formed using the land portion of the via BR35 instead of being provided in the vicinity of the via BR35.

[0473] (Configuration C1) The gaming machine 1 is a first substrate; a second substrate to which a power supply voltage is supplied from the first substrate; Equipped with The second substrate is a connector that receives the power supply voltage from the first board; Chip type fuses, and The fuse is the element closest to the power supply voltage terminal of the connector in terms of wiring.

[0474] In this case (Configuration C1), the following corresponding example (Specific Example 5) is assumed. (Example 5) 1st board: Performance control board 30 2nd board: LED connection board 700 Connector: Connector CN1 Power supply voltage: 12V DC (DC12VB), 5V DC (DC5VB) Power supply voltage terminals: 12V DC voltage (DC12VB) terminals (pins 12, 14, 24, 26, 28, and 30) of connector CN1 in Figure 14, and 5V DC voltage (DC5VB) terminals (pins 4 and 6) Fuse: Fuse FZ2, FZ1

[0475] In the LED connection board 700, the fuses FZ1 and FZ2 are respectively arranged at positions pFZ1 and pFZ2 shown in Fig. 39. As can be seen from the pads at positions pFZ1 and pFZ2, the fuses FZ1 and FZ2 are surface-mounted chip-type fuses.

[0476] For example, Fig. 43 shows an example of the appearance of a rectangular chip fuse FZc that can be used as fuses FZ1 and FZ2. This rectangular chip fuse FZc has external electrodes 1101 and 1102 connected to pads, and has a structure with an internal fusing element.

[0477] The fuse FZ1 is the element closest in wiring to the terminal for the 5V DC voltage (DC5VB) in the connector CN1. The fuse FZ2 is the element closest in wiring to the terminal for the 12V DC voltage (DC12VB) in the connector CN1.

[0478] The 5V DC voltage (DC5VB) and the 12V DC voltage (DC12VB) are also transmitted from the LED connection board 700 to downstream boards. On the other hand, the 35V DC voltage (DC35VB) is used by the motor driving section 760 in the LED connection board 700, but is not transmitted to downstream boards.

[0479] The fuses FZ1 and FZ2 arranged for the 5V DC voltage (DC5VB) and 12V DC voltage (DC12VB) are arranged immediately after the connector CN1 on the LED connection board 700. In other words, the fuses FZ1 and FZ2 are arranged at the most upstream position within the LED connection board 700, excluding the connector CN1, and are electrically closest to the performance control board 30.

[0480] The LED connection board 700 is a board directly below the performance control board 30 on the game board 3, and downstream of the LED connection board 700, multiple performance-related boards are connected. In this case, fuses FZ1 and FZ2 are located downstream of the performance control board 30, at the most upstream position of the many performance-related boards.

[0481] Therefore, it functions most suitably as a protection circuit that protects the performance control board 30 in the event of a short circuit downstream of the LED connection board 700. This is because even if a short circuit occurs anywhere downstream of the LED connection board 700 on the game board 3, the performance control board 30 will not be affected due to the blowing of fuses FZ1 and FZ2.

[0482] Since the fuses FZ1 and FZ2 are chip types, if they blow, the LED connection board 700 itself needs to be replaced, but the expensive performance control board 30 on the upstream side does not need to be replaced. In addition, in the gaming machine 1, the performance control board 30 is usually difficult to replace because it is housed in a crimped board case. To replace the performance control board 30, the board case must be destroyed. The LED connection board 700 can be easily replaced because it can be removed without using tools or is simply covered with a cover that can be removed without destruction. In this respect, protection of the performance control board 30 is also useful. Furthermore, some of the multiple performance-related boards downstream of the LED connection board 700 cannot be removed without disassembling them using tools. In this sense, it is relatively easy to replace the LED connection board 700, and it is suitable to use chip-type fuses for the LED connection board 700.

[0483] Furthermore, the fact that fuses FZ1 and FZ2 are chip types makes a significant contribution to the miniaturization of boards required for downstream performance boards.

[0484] For the 35V DC voltage (DC35VB), fuses FZ3, FZ4, FZ5, and FZ6 are provided as shown in Fig. 26. Because the 35V DC voltage (DC35VB) is not transmitted downstream from the LED connection board 700, is branched into four systems of motor drive power supply voltages MOT35Vx, MOT35Vz, MOT35Vy, and MOT35Vu, and is provided with a protection circuit consisting of Schottky barrier diodes (D10, D11) and electrolytic capacitors (C57, C63), it is not the closest element in terms of wiring to the power supply voltage terminal of connector CN1.

[0485] (Configuration C2) The gaming machine 1 is a first substrate; a second substrate to which a power supply voltage is supplied from the first substrate; a plurality of third substrates to which the power supply voltage is supplied from the second substrate; Equipped with The second substrate is an input connector that receives the power supply voltage from the first board; a plurality of output connectors each supplying the power supply voltage to the third board; Chip type fuses, and The fuse is the element closest in wiring to the terminal of the power supply voltage in the input connector.

[0486] In this case (Configuration C2), the following corresponding example (Specific Example 6) is assumed. (Example 6) 1st board: Performance control board 30 2nd board: LED connection board 700 Input connector: Connector CN1 Output connector: Connectors CN3, CN4, CN5, CN8, CN11, CN13, CN6, CN7, CN9, CN12, CN14, CN10, CN25, CN26, etc. Power supply voltage: 12V DC voltage (DC12VB) Power supply voltage terminals: 12V DC voltage (DC12VB) terminals on connector CN1 (pins 12, 14, 24, 26, 28, and 30) Fuse: Fuse FZ2 Third board: Board connected to the output connector

[0487] As explained in the circuit diagram, the LED connection board 700 transmits the 12V DC voltage (DC12VB) received at connector CN1 via connectors CN3, CN4, CN5, CN8, CN11, CN13, CN6, CN7, CN9, CN12, CN14, CN10, CN25, CN26, etc. to downstream boards as a power source for the LED light emission operation and a power source for the LED driver.

[0488] In this configuration, fuse FZ2 is located downstream of performance control board 30, at the most upstream of the 12V DC voltage (DC12VB) line for the many performance-related boards. Therefore, it functions optimally as a protection circuit to protect the upstream performance control board 30 in the event of a short circuit on either LED connection board 700 or the third board. When the LED connection board 700 is configured to supply power to multiple third boards, the protection function can handle a wider range of short circuit occurrence locations, making this a suitable configuration for protecting the performance control board 30. Furthermore, the FZ2 fuse is a chip type, which contributes to the miniaturization of downstream boards.

[0489] (Configuration C3) The gaming machine 1 is a first substrate; a second substrate to which a power supply voltage is supplied from the first substrate; a third substrate to which the power supply voltage is supplied from the second substrate; Equipped with The second substrate is an input connector that receives the power supply voltage from the first board; an output connector that supplies the power supply voltage to the third board; a fuse provided on the wiring of the power supply voltage; and a transmission line using a flexible flat cable as an inter-board transmission line through which the power supply voltage is transmitted after the output connector; The fuse is the element closest in wiring to the terminal of the power supply voltage in the output connector.

[0490] In this case (Configuration C3), the following corresponding example (Specific Example 7) is envisioned. (Example 7) 1st board: Performance control board 30 2nd board: LED connection board 700 Third board: Relay board 800 Power supply voltage: 12V DC (DC12VB), 5V DC (DC5VB) Input connector: Connector CN1 Output connector: Connector CN23 Flexible flat cable transmission line: Transmission line H31 Fuse: Fuse FZ7, FZ8

[0491] As explained in FIG. 25, the 12V DC voltage (DC12VB) and the 5V DC voltage (DC5VB) are transmitted from the connector CN23 to the relay board 800 and the decorative board 820. Of the inter-board transmission lines that transmit 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) after connector CN23, transmission line H31 between relay board 800 and decorative board 820 uses a flexible flat cable.

[0492] For example, connectors CN101 and CN102 are shown in Figures 45 and 46 as connectors CN that connect the relay board 800 and the decorative board 820. These are connectors that connect flexible flat cables (FFC). 44 and 45 will be described in detail later, but FIG. 44 shows a series supply path from the power supply board 300 for a 5V DC voltage (DC5VB), and FIG. 45 shows a series supply path from the power supply board 300 for a 12V DC voltage (DC12VB).

[0493] As shown in FIG. 25, the LED connection board 700 is provided with fuses FZ7 and FZ8. FIG. 39 shows the position pCN23 where the connector CN23 is arranged, and for the sake of explanation, terminal numbers are attached to some of the pads. The pads for pins 2, 4, and 6, which are terminals for the 12V DC voltage (DC12VB), are connected to the pad (position pFZ7) where the fuse FZ7 is located. The pad of pin 9, which is the terminal for 5V DC voltage (DC5VB), is connected to the pad (position pFZ8) where the fuse FZ8 is located.

[0494] As can be seen from FIGS. 25 and 39, the fuses FZ7 and FZ8 are the elements closest in wiring to the power supply voltage terminal of the connector CN23.

[0495] In connectors like connectors CN101 and CN102, where flexible flat cables are inserted and removed, short circuits can occur when the cable ends are inserted at an angle. This means that the possibility of a short circuit is relatively high. Therefore, fuses FZ7 and FZ8 are located in the LED connection board 700 as the closest elements to connector CN23, which is the upstream output connector of the flexible flat cable. This minimizes the impact of a short circuit occurring in the relay board 800, decorative board 820, or flexible flat cable. This optimal fuse placement protects the upstream performance control board 30 and other boards (e.g., LED boards 850 and 860) that are in parallel with the relay board 800 when fuse FZ7 or FZ8 blows.

[0496] 25 shows an example in which pads are formed for the fuses FZ7 and FZ8 as chip types. In the case of chip types, if the fuse FZ7 or FZ8 melts, the LED connection board 700 also needs to be replaced. The fuses FZ7 and FZ8 may be implemented as glass tube fuses, for example. In this case, even if a short circuit occurs in the flexible flat cable, the LED connection board 700 can also be protected, and only the fuse needs to be replaced.

[0497] There are also cases where a flexible flat cable is used for the transmission line H30 between the LED connection board 700 and the relay board 800. That is, the connectors CN23 and CN100 are connectors for the flexible flat cable. In such a case, the output connector upstream of the flexible flat cable within the LED connection board 700 is the connector CN23. Therefore, by arranging the fuses FZ7 and FZ8 as the elements closest to the connector CN23, the same effect as above can be obtained. In other words, when transmitting a power supply voltage such as 12V DC voltage (DC12VB) or 5V DC voltage (DC5VB) downstream from connector CN23, if a flexible flat cable is used after connector CN23, configuration C3 is effective.

[0498] (Configuration C4-1) The gaming machine 1 is a power supply board that generates and outputs a first DC power supply voltage based on an AC input power supply; a plurality of substrates on which a serial supply path of the first power supply voltage is formed so as to sequentially receive the supply of the first power supply voltage from the power supply substrates; Equipped with the plurality of substrates includes a substrate attached to a replaceable part; A plurality of fuses are arranged on the series supply path; One of the plurality of fuses is a chip-type fuse that is the closest element in wiring to the first power supply voltage terminal of the input connector on the board that is highest in the series relationship of the series supply path among one or more boards arranged in the replaceable component.

[0499] In this case (Configuration C4-1), the following corresponding example (Specific Example 8) is envisioned. (Example 8) Power supply board: Power supply board 300 First power supply voltage: 5V DC voltage (DC5VB), 12V DC voltage (DC12VB) A plurality of substrates on which serial supply paths are formed: a plurality of substrates shown in FIGS. 44 and 45 Substrate attached to replaceable parts: Substrate of the game board 3 shown in Figures 44 and 45 Multiple fuses: Multiple fuses as shown in Figure 44 and Figure 45 Input connector: Connector CN40 One of several fuses: Fuse FZz in Figure 44, Fuse FZw in Figure 45

[0500] Figures 44 and 45 show the series supply path of the first power supply voltage in (configuration C4-1) of the board shown in Figure 11. Figure 44 shows the series supply path when the first power supply voltage is a 5V DC voltage (DC5VB), and Figure 45 shows the series supply path when the first power supply voltage is a 12V DC voltage (DC12VB). In the boards shown in Figures 44 and 45, the power supply board 300 is placed on the inner frame 2, and the rest are placed on the game board 3. Although only some of the connectors CN are shown in FIGS. 44 and 45, it goes without saying that each board is provided with a connector CN as an end of a transmission line.

[0501] The series supply path of the 5V DC voltage (DC5VB) in FIG. 44 will be described. As previously described with reference to FIG. 12, the 5V DC voltage (DC5VB) generated by the power supply board 300 based on the AC input power is sent from the connector CN2A to the power supply relay board 40 via the transmission line H2.

[0502] In the power supply board 300, the fuse FZx is connected to the terminal for the 5V DC voltage (DC5VB) of the connector CN2A as the closest element in terms of wiring. In other words, there is only wiring and no other electronic components between the terminal for the 5V DC voltage (DC5VB) of the connector CN2A and the fuse FZx. The fuse FZx is mounted as, for example, a tubular or terminal insertion type fuse on the power supply board 300. For example, the terminal insertion type fuse FZ601 or the tubular type fuse FZ301 shown in Fig. 13 is used as the fuse FZx in Fig. 44. The fusing current value of the fuse FZx is set to, for example, 10A.

[0503] As shown in Figure 44, the power relay board 40 is provided with a connector CN40, which serves as the transmission line end of the transmission line H2. A fuse FZw is connected to the 5V DC voltage (DC5VB) terminal of the connector CN40 as the closest element in terms of wiring. In other words, there is only wiring between the 5V DC voltage (DC5VB) terminal of the connector CN40 and the fuse FZw, and no other electronic components are provided. The fuse FZw is a chip-type fuse, and its fusing current value is set to, for example, 5A.

[0504] From the power supply relay board 40, the 5V DC voltage (DC5VB) is transmitted to the performance control board 30 via a transmission line H18, and is further sent to the LED connection board 700 via a transmission line H20 (or transmission line H20b). In the LED connection board 700, a 5V DC voltage (DC5VB) is input via connector CN1 (or connector CN1b). A fuse FZ1 is provided for this 5V DC voltage (DC5VB). As shown in Figures 20, 21, and 39, the fuse FZ1 is connected to the 5V DC voltage (DC5VB) terminal of connector CN1 (or connector CN1b) as the closest element in terms of wiring. In other words, there is only wiring and no other electronic components between the 5V DC voltage (DC5VB) terminal of connector CN1 (or connector CN1b) and the fuse FZ1. The fuse FZ1 is a chip-type fuse, and its fusing current value is set to, for example, 4A.

[0505] The 5V DC voltage (DC5VB) is transmitted from the connector CN23 of the LED connection board 700 to the relay board 800 via the transmission line H30. 25, in the LED connection board 700, the fuse FZ8 is connected to the 5V DC voltage (DC5VB) terminal of the connector CN23 as the closest element in terms of wiring. That is, there is only wiring and no other electronic components between the 5V DC voltage (DC5VB) terminal of the connector CN23 and the fuse FZ8. The fuse FZ8 is a chip-type fuse, and its fusing current value is set to, for example, 2A.

[0506] The 5V DC voltage (DC5VB) is also transmitted from the relay board 800 to the decorative board 820 via the transmission line H31.

[0507] As described above, a series supply path for 5V DC voltage (DC5VB) is formed through the power supply relay board 40, performance control board 30, LED connection board 700, relay board 800, and decorative board 820, with the power supply board 300 being the most upstream.

[0508] FIG. 45 explains the series supply path for 12V DC voltage (DC12VB). The 12V DC voltage (DC12VB) generated by the power supply board 300 based on the AC input power is sent to the power supply relay board 40 from the connector CN2A (see FIG. 12) via the transmission line H2.

[0509] In the power supply board 300, the fuse FZy is connected to the terminal for the 12V DC voltage (DC12VB) of the connector CN2A as the closest element in terms of wiring. In other words, there is only wiring between the terminal for the 12V DC voltage (DC12VB) of the connector CN2A and the fuse FZy, and no other electronic components are provided. The fuse FZy is mounted as, for example, a tubular or terminal insertion type fuse on the power supply board 300. For example, the terminal insertion type fuse FZ501 or the tubular type fuse FZ401 shown in Fig. 13 is used as the fuse FZy in Fig. 45. The fusing current value of the fuse FZy is set to, for example, 15A.

[0510] The fuse FZz is connected as the closest element in terms of wiring to the 12V DC voltage (DC12VB) terminal of the connector CN40, which is the transmission line end of the transmission line H2 in the power relay board 40. In other words, there is only wiring and no other electronic components between the 12V DC voltage (DC12VB) terminal of the connector CN40 and the fuse FZz. The fuse FZz is a chip-type fuse, and its fusing current value is set to, for example, 10A.

[0511] From the power supply relay board 40, the 12V DC voltage (DC12VB) is transmitted to the performance control board 30 via a transmission line H18, and further sent to the LED connection board 700 via a transmission line H20 (or a transmission line H20a). In the LED connection board 700, a 12V DC voltage (DC12VB) is input via connector CN1 (or connector CN1a). A fuse FZ2 is provided for this 12V DC voltage (DC12VB). As shown in Figures 20, 21, and 39, the fuse FZ2 is connected to the 12V DC voltage (DC12VB) terminal of connector CN1 (or connector CN1a) as the closest element in terms of wiring. In other words, there is only wiring and no other electronic components between the 12V DC voltage (DC12VB) terminal of connector CN1 (or connector CN1a) and the fuse FZ2. The fuse FZ2 is a chip-type fuse, and its fusing current is set to, for example, 8A.

[0512] The 12V DC voltage (DC12VB) is transmitted from the LED connection board 700 to a number of other boards. As one of them, a 12V DC voltage (DC12VB) is transmitted from the connector CN23 to the relay board 800 via the transmission line H30. 25, the fuse FZ7 is connected to the 12V DC voltage (DC12VB) terminal of the connector CN23 as the closest element in terms of wiring. In other words, there is only wiring between the 12V DC voltage (DC12VB) terminal of the connector CN23 and the fuse FZ7, and no other electronic components are provided. The fuse FZ7 is a chip type fuse, and its fusing current value is set to, for example, 2A.

[0513] The 12V DC voltage (DC12VB) is also transmitted from the relay board 800 to the decorative board 820 via the transmission line H31. As described above, a series supply path for 12V DC voltage (DC12VB) is formed through the power supply relay board 40, performance control board 30, LED connection board 700, relay board 800, and decorative board 820, with the power supply board 300 being the most upstream.

[0514] Furthermore, a 12V DC voltage (DC12VB) is supplied from the LED connection board 700 to the LED board 850 via a transmission line H40 including a connector CNv. Therefore, with the power supply board 300 as the most upstream, a series supply path of 12V DC voltage (DC12VB) is formed through the power supply relay board 40, performance control board 30, LED connection board 700, and LED board 850.

[0515] Furthermore, a 12V DC voltage (DC12VB) is supplied from the LED connection board 700 to the LED board 860 via a transmission line H41 including a connector CNU. Therefore, with the power supply board 300 as the most upstream, a series supply path of 12V DC voltage (DC12VB) is formed through the power supply relay board 40, performance control board 30, LED connection board 700, and LED board 860.

[0516] The connectors CNv and Cnu in FIG. 45 correspond to, for example, the connectors CN5, CN8, CN11, CN13, and CN6, and the connectors CN7, CN9, CN12, and CN14 shown in FIG.

[0517] In the series supply path of the 5V DC voltage (DC5VB) in FIG. 44, a fuse FZw is mounted on the power supply relay board 40. In the series supply path of the 12V DC voltage (DC12VB) in FIG. 45, a fuse FZz is mounted on the power supply relay board 40. Although detailed circuit configuration is omitted, fuses FZw and FZz are on the 5V power line and 12V power line, respectively, and are the most upstream electrical components within power relay board 40 excluding connector CN40.

[0518] Furthermore, the game board 3 is a replaceable part for the frame member including the inner frame 2, and the power supply relay board 40 is the board that is the highest in the series relationship of the series supply path of 5V DC voltage (DC5VB) or 12V DC voltage (DC12VB) among one or more boards placed on the replaceable part (for example, the game board 3).

[0519] In this way, mounting fuses FZw and FZz on the power supply relay board 40 is suitable for protecting the frame members. Even if a short circuit occurs in the 5V DC voltage (DC5VB) system or the 12V DC voltage (DC12VB) system in the components inside the game board 3, the fuse FZw or FZz will blow, protecting the power supply board 300 side, i.e., the inner frame 2 side. By protecting the circuitry on the frame member side, the gaming machine 1 can be repaired by replacing the gaming board 3. Alternatively, the frame member can be used for a different model. In gaming machines 1, replacing the gaming board 3 with the frame member can be used to create a new model, so protecting the frame member is a major advantage. It is also environmentally friendly because it eliminates the need to dispose of the frame member indiscriminately.

[0520] Furthermore, the fuses FZw and FZz are chip types, which are also suitable for miniaturizing the power relay board 40.

[0521] The gaming machine 1 of the embodiment has the following (Configuration C4-2) in addition to the above (Configuration C4-1).

[0522] (Configuration C4-2) The power supply board is disposed in a frame member, The replaceable part is a part that can be replaced with respect to the frame member.

[0523] As described above, the power supply board 300 is disposed in the inner frame 2 (frame member), and the replaceable part is the game board 3 that is replaceable with respect to the frame member. The fuses FZw and FZz are connected to the connector CN40 of the power supply relay board 40, which is the boundary between the inner frame 2 and the game board 3 in the serial supply path, which is extremely suitable for protecting the frame members.

[0524] (Configuration C5) The gaming machine 1 is a power supply board that generates and outputs a first DC power supply voltage based on an AC input power supply; a plurality of substrates on which a serial supply path of the first power supply voltage is formed so as to sequentially receive the supply of the first power supply voltage from the power supply substrates; Equipped with The plurality of boards include a performance control board that outputs a performance control signal, and one or more boards that are lower in the series relationship of the serial supply path than the performance control board, A plurality of fuses are arranged on the series supply path; One of the plurality of fuses is a chip-type fuse that is the closest element in the wiring to the first power supply voltage terminal of the input connector on the board directly below the performance control board in the series relationship of the series supply path.

[0525] In this case (Configuration C5), the following corresponding example (Specific Example 9) is assumed. (Example 9) Power supply board: Power supply board 300 First power supply voltage: 5V DC voltage (DC5VB), 12V DC voltage (DC12VB) A plurality of substrates on which serial supply paths are formed: a plurality of substrates shown in FIGS. 44 and 45 ·Performance control board:Performance control board 30 Directly below the performance control board: LED connection board 700 Multiple fuses: Multiple fuses as shown in Figure 44 and Figure 45 Input connector: Connector CN1 (or CN1a, or CN1b) One of several fuses: fuse FZ1, FZ2

[0526] As described in FIGS. 44 and 45, a plurality of fuses are arranged in both the series supply path for the 5V DC voltage (DC5VB) and the series supply path for the 12V DC voltage (DC12VB). Fuse FZ1, one of multiple fuses in the series supply path of 5V DC voltage (DC5VB), is a chip-type fuse that is the closest element in the wiring to the power supply voltage terminal of connector CN1 (or CN1b) on the LED connection board 700, which is directly below the performance control board 30. Fuse FZ2, one of multiple fuses in the series supply path of 12V DC voltage (DC12VB), is a chip-type fuse that is the closest element in the wiring to the power supply voltage terminal of connector CN1 (or CN1a) on the LED connection board 700, which is directly below the performance control board 30.

[0527] In this case, fuses FZ1 and FZ2 are located downstream of the performance control board 30, at the most upstream position of the many performance-related boards. Therefore, it functions most suitably as a protection circuit that protects the performance control board 30 in the event of a short circuit downstream of the LED connection board 700. This is because even if a short circuit occurs anywhere downstream of the LED connection board 700 on the game board 3, the performance control board 30 will not be affected due to the blowing of fuses FZ1 and FZ2.

[0528] Since the fuses FZ1 and FZ2 are chip types, if they blow, the LED connection board 700 itself needs to be replaced, but the expensive performance control board 30 on the upstream side does not need to be replaced. Furthermore, in a typical gaming machine 1, the performance control board 30 is difficult to replace because it is housed in a crimped board case, but the LED connection board 700 is easily replaced because it is simply covered by a removable cover without the use of tools. In this respect, protecting the performance control board 30 is also useful. Furthermore, the fact that fuses FZ1 and FZ2 are chip types makes a significant contribution to the miniaturization of boards required for downstream performance boards.

[0529] Note that the specific example of the "performance control board" in (Configuration C5) above is performance control board 30, but in reality, this performance control board 30 may consist of a single board, or may be divided into multiple boards. In either case, the performance control board is housed in a board case in which one or more boards are crimped. The "performance control board" refers to one or more boards housed in a board case. Therefore, the "performance control board" in (Configuration C5) can be defined as "one or more boards housed in a board case," or "one or more boards housed in a board case and attached to the gaming machine as a whole." Furthermore, since the board on which the fuse is attached is the board directly below such a "performance control board," that is, the board directly below the board case of the performance control board, even if a short circuit occurs downstream, it is possible to have the effect of not having to replace the expensive performance control board 30, which is made up of one or more boards housed in a board case.

[0530] (Configuration C6) The gaming machine 1 is a power supply board that generates and outputs a DC power supply voltage based on an AC input power supply; A plurality of performance boards are provided, to which power supply voltage is supplied from the power supply board; The power supply board is a board on which insertion-mounted components related to the generation of power supply voltage are mounted, and a tube-type or terminal-insertion-type fuse is mounted, The plurality of performance boards include a performance board on which all surface-mounted components except for connectors are chip components and on which chip-type fuses are mounted.

[0531] In this case (Configuration C6), the following corresponding example (Specific Example 10) is envisioned. (Example 10) Power supply board: Power supply board 300 Power supply voltage: 5V DC (DC5VB), 12V DC (DC12VB) Multiple performance boards: Multiple boards shown in Figures 44 and 45 All surface-mounted components except for connectors are chip components, and chip-type fuses are mounted on the LED connection board 700.

[0532] The electrical components mounted on the LED connection board 700 include a connector CN, an IC chip, a resistor, a capacitor, a diode, and a fuse. The IC chip is, of course, a chip component, but the resistors, capacitors, and diodes used are chip resistors, chip capacitors, and chip diodes. Fuses FZ1, FZ2 (see FIG. 20 or 21), FZ3, FZ4, FZ5, FZ6 (see FIG. 26), FZ27, and FZ28 (see FIG. 25) are all chip types. 35 and 36 show pads and wiring patterns for surface mounting these chip-type components.

[0533] On the other hand, as explained in FIG. 13, the power supply board 300 is a board on which insertable components related to the generation of the power supply voltage are mounted, and tubular or terminal insertion type fuses FZ301, FZ401, FZ501, FZ601, FZ701, and FZ1A are mounted.

[0534] The power supply board 300 requires fuses with a large fusing current, so tube-type or terminal-insertion type fuses are used, but downstream performance boards require a small fusing current. Therefore, chip-type fuses are used as boards for mounting surface-mounted components. This means that all electrical components except for the connector CN are chip-type. This is a configuration that is particularly suitable for miniaturizing the board area required for downstream performance boards. Furthermore, since all surface-mounted components, including fuses, are chip components, there is an advantage in terms of cost.

[0535] (Configuration C7) The gaming machine 1 is a power supply board that generates and outputs a first DC power supply voltage based on an AC input power supply; a plurality of substrates on which a serial supply path of the first power supply voltage is formed so as to sequentially receive the supply of the first power supply voltage from the power supply substrates; Equipped with The power supply board is a board on which insertion-mounted components related to the generation of power supply voltage are mounted, and a tube-type or terminal-insertion-type fuse is mounted, The plurality of performance boards include a performance board on which all surface-mounted components except for connectors are chip components and on which chip-type fuses are mounted, A board on which a tube-type or terminal insertion-type fuse is mounted is not provided on a board that is lower in the series relationship of the series supply path than a board on which a chip-type fuse is mounted.

[0536] In this case (Configuration C7), the following corresponding example (Specific Example 11) is envisioned. (Example 11) Power supply board: Power supply board 300 First power supply voltage: 5V DC voltage (DC5VB), 12V DC voltage (DC12VB) Multiple boards: Multiple boards as shown in Figures 44 and 45 All surface-mounted components except for connectors are chip components, and chip-type fuses are mounted on the LED connection board 700. Boards on which chip-type fuses are mounted: power relay board 40, LED connection board 700

[0537] As described above in the description of configuration C6, the LED connection board 700 is a performance board in which all of the surface-mounted components mounted thereon, except for connectors, are chip components and on which chip-type fuses are mounted. In the examples of Figures 44 and 45, chip-type fuses are mounted on the power supply relay board 40 and the LED connection board 700, but no board on which tubular or terminal-insertion type fuses are mounted is provided downstream of the power supply relay board 40.

[0538] The power supply board 300 requires fuses with a large fusing current, so tube-type or terminal insertion-type fuses are used, but downstream performance boards require a small fusing current. Therefore, chip-type fuses are used as boards for mounting surface-mounted components. Furthermore, if chip-type fuses are used on one board, all fuses installed downstream from that board must also be chip-type. This facilitates the miniaturization required for downstream boards.

[0539] (Configuration D1-1) The gaming machine 1 is A first substrate is provided on which wiring is formed to transmit a performance control signal output from an IC chip component including an active circuit, and which inputs the performance control signal from another substrate and / or outputs the performance control signal to another substrate; the first board has a connector in which terminals are arranged in two rows, one of the terminal rows facing the board edge side and the other terminal row facing inward of the board, and the connector is arranged near the board edge side; The connector has terminals for all of the performance control signals transmitted between the connector and another board via the connector as terminals in the other terminal row.

[0540] In the case of this (Configuration D1-1), the following corresponding example (Specific Example 12) is assumed. (Example 12) 1st board: Performance control board 30 Connector: Connector CNe1 Other boards: LED connection board 700

[0541] In addition, in the case of (Configuration D1-1), the following corresponding example (Specific Example 13) is also conceivable. (Example 13) 1st board: LED connection board 700 Connector: Connector CN1 Other boards: 30 performance control boards

[0542] In these specific examples 12 and 13, the performance control signals output from the IC chip components including active circuits are the first set of clock signal LED_CLK, data signal LED_DATA, enable signal LED_ENABLE, the second set of clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, reset signal LSI_RST, the third set of clear signal CLR_X, data signal DATA_X, latch signal LATCH_X, and the fourth set of load signal S_IN_LOAD, clock signal S_IN_CLK, serial data signal S_IN_DATA.

[0543] The IC chip components including active circuits are the performance control CPU 30a in the performance control board 30, the buffer circuits 701, 702, 703, LED drivers 705, 707, P / S conversion circuit 704, etc. in the LED connection board 700, and each of the above performance control signals is a signal generated and output by the performance control CPU 30a, or a signal generated and output by the P / S conversion circuit 704 in the LED connection board 700 or the motor driver of the motor drive unit 760, etc.

[0544] The terminal assignments of the connectors CN1 and CNe1 have been explained with reference to FIG. 14, and it has also been explained that the connectors CN1 and CNe1 have pins arranged in two rows as shown in FIG. FIG. 46 shows the pin assignments of the connectors CN1 and CNe1 for each row. In the figure, the terminal row with odd pin numbers is shown on the left side, and the terminal row with even pin numbers is shown on the right side. The pins assigned to the above-mentioned "performance control signals" are shaded.

[0545] As is clear from the diagram, all performance control signals are assigned to pins in odd-numbered terminal rows. Pins in even-numbered terminal rows are assigned 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), 35V DC voltage (DC35VB), or ground (GND), and no performance control signals are assigned.

[0546] FIG. 47 shows a schematic diagram of the connection between the performance control board 30 and the LED connection board 700 by the connectors CN1 and CNe1, and the wiring of the performance control signals on each board. Connectors CN1 and CNe1 have rows separated by dashed lines, and pin numbers "1," "2," "39," and "40" are shown.

[0547] The performance control board 30 as the above (specific example 12) will be described. In the performance control board 30, a wiring pattern is formed so that the above-mentioned performance control signal is transmitted between the performance control CPU 30a and the connector CNe1. Note that a buffer circuit, a filter circuit, etc. may be provided between the performance control CPU 30a and the connector CNe1, but these are omitted here. In any case, in the performance control board 30, the performance control signal generated and output by the performance control CPU 30a is sent to the connector CNe1, and transmitted to the LED connection board 700 by a harness that serves as the transmission line H20. In addition, the performance control signal transmitted from the LED connection board 700 is finally sent from the connector CNe1 to the performance control CPU 30a.

[0548] Figure 48 shows the transmission signal between the performance control CPU 30a and the connector CNe1. The performance control CPU 30a outputs a clock signal LED_CLK, a data signal LED_DATA, an enable signal LED_ENABLE, a clock signal LSI_CLK, an enable signal LSI_ENABLE, a data signal LSI_DATA, a reset signal LSI_RST, a clear signal CLR_X, a data signal DATA_X, a latch signal LATCH_X, a load signal S_IN_LOAD, and a clock signal S_IN_CLK, which are sent to connector CNe1. In addition, the serial data signal LSI_IN_DATA and the serial data signal S_IN_DATA transmitted from the LED connection board 700 are sent from the connector CNe1 to the performance control CPU 30a.

[0549] In this case, as shown in FIG. 47, on the performance control board 30, the connector CNe1 is placed near the board end edge 30T with its long side aligned with the board end edge 30T. Being disposed in the vicinity of the board end edge 30T can also be said to mean a state in which no other electronic components are disposed between the connector CNe1 and the board end edge 30T. The terminal rows with even pin numbers are attached to the board edge 30T side, and the terminal rows with odd pin numbers are attached to the inside of the board. Therefore, all pins assigned to performance control signals are attached to the inside of the board.

[0550] When viewed from the connector CNe1 located near the edge, the performance control CPU 30a is located on the inner side of the board. Also, since the performance control CPU 30a requires many wires around it, it is generally located closer to the center of the board.

[0551] This puts the performance control CPU 30a in a position facing the odd-numbered terminal row on the connector CNe1. Therefore, the wiring pattern for the performance control signal between the performance control CPU 30a and the connector CNe1 does not need to go around the periphery of the connector CNe1, and can be designed as a very simple and efficient pattern.

[0552] In addition, in terms of wiring, buffer circuits, filter circuits, etc. may be provided between the performance control CPU 30a and connector CNe1, but since connector CNe1 is located near the edge of the board, in either case, the odd-numbered terminal rows of connector CNe1 will face the chips and electronic elements that make up those circuits, so the wiring pattern can still be simplified.

[0553] Additionally, wiring patterns for 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), 35V DC voltage (DC35VB), and ground (GND) are required between connector CNe1 and board edge 30T, and these power supply voltage patterns and ground patterns are usually formed over almost the entire surface of the board. For example, they are configured as solid power supply patterns and solid ground patterns. Each is also assigned to multiple terminals. Therefore, the wiring pattern between the connector CNe1 and the edge of the board does not become complicated.

[0554] Next, the LED connection board 700 as the above-mentioned (Specific Example 13) will be described. In the LED connection board 700, a wiring pattern is formed so that the performance control signal is transmitted between the buffer circuits 701 and 703 as described in FIG. In the LED connection board 700, the performance control signals (serial data signal LSI_IN_DATA, serial data signal S_IN_DATA) output from the buffer circuits 701 and 703 are sent to the connector CN1 and transmitted to the performance control board 30 by the harness which serves as the transmission line H20. In addition, the performance control signal transmitted from the performance control board 30 is sent to the buffer circuits 701 and 703 from the connector CN1.

[0555] 47, the connector CN1 is disposed near the board edge 700T on the LED connection board 700, with its long side aligned along the board edge 700T. No other electronic components are disposed between the connector CN1 and the board edge 700T. The terminal rows with even pin numbers are attached to the board edge 700T side, and the terminal rows with odd pin numbers are attached to the board inward. Therefore, all pins assigned to performance control signals are attached to the board inward.

[0556] When viewed from the connector CN1 arranged near the edge, the buffer circuits 701 and 703 are arranged on the inner side of the board. This places the buffer circuits 701 and 703 opposite the odd-numbered terminal rows in the connector CN1. Therefore, the wiring pattern for the performance control signals between the buffer circuits 701 and 703 and the connector CNe1 does not need to go around the periphery of the connector CN1, and can be designed as a very simple and efficient pattern.

[0557] A specific wiring pattern is shown in Fig. 39. In the figure, it is shown that the wiring between positions p701 and p703 where the buffer circuits 701 and 703 are arranged and position pCN1 of the connector CN1 is simple. The performance control signals transmitted on the board between connector CN1 and buffer circuits 701, 703 are clock signal LED_CLK, data signal LED_DATA, clock signal LSI_CLK, serial data signal LSI_IN_DATA, enable signal LSI_ENABLE, data signal LSI_DATA, reset signal LSI_RST, load signal S_IN_LOAD, clock signal S_IN_CLK, and serial data signal S_IN_DATA (see Figure 20).

[0558] Furthermore, since the wiring pattern can be simplified, the test points TP1 to TP10 for the above-mentioned performance control signals can also be formed with ample area.

[0559] Furthermore, wiring patterns for 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), 35V DC voltage (DC35VB), and ground (GND) are formed between connector CN1 and the edge of the board, but as is clear from Figure 39, this is an extremely simple pattern. Moreover, because there is no wiring for the performance control signal, it is easier to form a wider solid pattern than normal wiring, realizing a configuration that is advantageous for ensuring current capacity.

[0560] The gaming machine 1 of the embodiment has the following (Configuration D1-2) in addition to the above (Configuration D1-1).

[0561] (Configuration D1-2) a capacitor is connected between a power supply line connected to the connector and ground; The capacitor is disposed on the surface of the first substrate opposite to the mounting surface of the connector, at a position where a part or the whole of the capacitor overlaps with the connector when viewed in the thickness direction of the substrate.

[0562] The following will be explained using the performance control board 30 as the above (Specific Example 12). The performance control board 30 is also a board that outputs 5V DC voltage (DC5VB), 12V DC voltage (DC12VB), and 35V DC voltage (DC35VB) to the downstream LED connection board 700. In other words, the connector CNe1 is also a power output connector.

[0563] For power output connectors, it is best to place the bypass capacitor connected between the power line and ground as close to the connector as possible. In particular, connecting a relatively small capacitor in parallel can cause noise to leak into the output side. Therefore, it is desirable to place the bypass capacitor near the power supply voltage terminal of connector CNe1.

[0564] FIG. 48 shows an example in which capacitors C1e and C4e are connected to a line of a 5V DC voltage (DC5VB) and capacitors C2e and C3e are connected to a line of a 12V DC voltage (DC12VB) as bypass capacitors Cp.

[0565] However, if the odd-numbered pin terminal rows of connector CNe1 are oriented inward on the board as shown in Figure 47 and no electronic components are placed between the connector CNe1 and the edge of the board, it becomes difficult to place the bypass capacitor Cp near connector CNe1.

[0566] Therefore, as shown in Figures 49A and 49B, the bypass capacitor Cp is placed on the back surface of the connector CNe1. In particular, the bypass capacitor Cp is positioned so that it overlaps part or all of the connector CNe1 in the thickness direction of the board, so as to be as close to the power supply terminal as possible. For example, bypass capacitors C2e and C3e for the 5V DC voltage (DC5VB) line are placed immediately below and near pins 4 and 6, and bypass capacitors C1e and C4e for the 12V DC voltage (DC12VB) line are placed immediately below and near pins 26 to 30. In particular, it is preferable that a portion of the bypass capacitors C2e and C3e overlaps with pin 4 or pin 6 in the thickness direction of the board, and it is also preferable that a portion of the bypass capacitors C1e and C4e overlaps with pin 24, pin 26, pin 28, pin 30, pin 12, or pin 14 in the thickness direction of the board.

[0567] This allows the bypass capacitor Cp to be placed in a position that is neither on the inner side of the board of the connector CNe1 nor on the board edge 30T side, and is extremely close to the po...

Claims

[Claim 1] a first substrate; The first substrate is a heat dissipation means disposed at a position spaced a predetermined distance in a height direction from the component mounting surface of the board; a first electronic component disposed below the heat dissipation means when the component mounting surface is viewed from the upper surface side of the substrate; a first component information notation portion on which characters or symbols as information about the first electronic component are notated on the component mounting surface; and The first component information notation portion is provided at a position that is visible while the heat dissipation means is attached. Gaming machine.

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