Electro-optical device and electronic apparatus

Abstract

To prevent light from being reflected and entering a semiconductor layer.SOLUTION: A pixel electrode, a relay electrode having a light shielding property, and a transistor that switches the pixel electrode, in which the transistor includes a semiconductor layer 131 and a gate electrode 132 that overlaps the semiconductor layer 131 via a gate insulating film 153 in a plan view and is supplied with a scanning signal, and the relay electrode 162 includes a side wall light shielding portion 192 that is electrically coupled to a drain region of the transistor, overlaps a part of the semiconductor layer 131 in a plan view, and covers a part of the semiconductor layer 131 to a position lower than the semiconductor layer 131 in a cross-sectional view.SELECTED DRAWING: Figure 21

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] Electro-optical devices are known that include an element substrate on which multiple pixel circuits and transistors functioning as switching elements are provided, and an opposing substrate disposed opposite the element substrate, with an electro-optical material such as liquid crystal sandwiched between them. When such electro-optical devices are used, for example, as light valves in projectors, they are exposed to intense light from a light source. When light penetrates the semiconductor layers of the transistors, optical leakage occurs, resulting in a degradation of display quality. Therefore, a technique is known in which a data line is used outside the gate electrode of the transistor to block light entering from the side of the semiconductor layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-137526 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technology described in Patent Document 1 above has a problem in that light incident from a 45-degree angle relative to the scanning line or data line in a plan view, and also at a 45-degree angle in a cross-sectional view, may be reflected by wiring located above or below the semiconductor layer and enter the semiconductor layer. [Means for solving the problem]

[0005] In order to solve the above problem, an electro-optical device according to one aspect of the present disclosure comprises a pixel electrode, a relay electrode having light-shielding properties, and a transistor for switching the pixel electrode, wherein the transistor includes a semiconductor layer and a gate electrode that overlaps the semiconductor layer in a planar view via a gate insulating film and is supplied with a scanning signal, and the relay electrode is electrically connected to a source region or a drain region of the transistor, overlaps with a portion of the semiconductor layer in a planar view, and has a sidewall light-shielding portion that covers a portion of the semiconductor layer to a position lower than the semiconductor layer in a cross-sectional view. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a diagram showing a projection display device to which an electro-optical device according to a first embodiment is applied. [Figure 2] FIG. 2 is a block diagram showing the electrical configuration of the projection display device. [Figure 3] FIG. 1 is a perspective view illustrating a configuration of an electro-optical device. [Figure 4] FIG. 1 is a cross-sectional view showing the structure of an electro-optical device. [Figure 5] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device. [Figure 6] FIG. 2 is a diagram illustrating a configuration of a pixel circuit in an electro-optical device. [Figure 7] 5A to 5C are plan views illustrating a manufacturing process of an element substrate in an electro-optical device. [Figure 8] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 9] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 10] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 11] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 12] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 13] 5A to 5C are cross-sectional views illustrating a manufacturing process of an element substrate. [Figure 14]5A to 5C are cross-sectional views illustrating a manufacturing process of an element substrate. [Figure 15] 5A to 5C are cross-sectional views illustrating a manufacturing process of an element substrate. [Figure 16] 5A to 5C are cross-sectional views illustrating a manufacturing process of an element substrate. [Figure 17] 5A to 5C are cross-sectional views illustrating a manufacturing process of an element substrate. [Figure 18] FIG. 2 is a cross-sectional view showing a main part of an element substrate. [Figure 19] FIG. 2 is a cross-sectional view showing a main part of an element substrate. [Figure 20] FIG. 10 is a cross-sectional view showing the penetration of light into an element substrate in a comparative example. [Figure 21] FIG. 3 is a cross-sectional view showing the penetration of light into the element substrate in the first embodiment. [Figure 22] 10A to 10C are plan views illustrating a manufacturing process for an element substrate in an electro-optical device according to a modified example of the first embodiment. [Figure 23] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 24] 10A to 10C are plan views illustrating a manufacturing process for an element substrate in an electro-optical device according to a second embodiment. [Figure 25] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 26] 1A to 1C are plan views showing a manufacturing process of an element substrate. [Figure 27] FIG. 2 is a cross-sectional view showing a main part of an element substrate. DETAILED DESCRIPTION OF THE INVENTION

[0007] Electro-optical devices according to embodiments will be described below with reference to the drawings. Note that the dimensions and scale of each part in each drawing are appropriately different from those of the actual device. Furthermore, the embodiments described below are preferred specific examples, and therefore various technically preferable limitations are applied. However, the scope of the present disclosure is not limited to these embodiments unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0008] FIG. 1 is a diagram showing the optical configuration of a projection display device to which the electro-optical device according to the first embodiment is applied. As shown in the figure, the projection display device 10 includes electro-optical devices 100R, 100G, and 100B. The projection display device 10 is also provided with a lamp unit 2102 consisting of a white light source such as a halogen lamp or an LED. The projection light emitted from this lamp unit 2102 is separated into three primary colors, red (R), green (G), and blue (B), by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Of these, the R light enters the electro-optical device 100R, the G light enters the electro-optical device 100G, and the B light enters the electro-optical device 100B. Since the optical path of B is longer than the optical paths of R and G, it is necessary to prevent loss in the optical path of B. For this reason, a relay lens system 2121 consisting of an input lens 2122, a relay lens 2123, and an output lens 2124 is provided in the optical path of B.

[0009] The electro-optical devices 100R, 100G, and 100B are, for example, transmissive liquid crystal panels, each having a plurality of pixel circuits. Each of the plurality of pixel circuits includes a liquid crystal element. The liquid crystal element of the electro-optical device 100R is driven based on a data signal corresponding to R, as described below, to have a transmittance that corresponds to the voltage of the data signal. Therefore, in the electro-optical device 100R, an R transmission image is generated by individually controlling the transmittance of the liquid crystal elements. Similarly, in the electro-optical device 100G, a G transmission image is generated based on a data signal corresponding to G, and in the electro-optical device 100B, a B transmission image is generated based on a data signal corresponding to B.

[0010] The transmitted images of each color generated by the electro-optical devices 100R, 100G, and 100B are incident on the dichroic prism 2112 in three directions. In the dichroic prism 2112, the R and B light are refracted at 90 degrees, while the G light travels straight. Therefore, the images of each color are combined in the dichroic prism 2112 to generate a color image through additive color mixing. The combined image generated by the dichroic prism 2112 is incident on the projection lens 2114, which enlarges and projects the combined image onto the screen Scr.

[0011] The transmission images of the electro-optical devices 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the electro-optical device 100G is projected in a straight line. Therefore, the transmission images of the electro-optical devices 100R and 100B are left-right inverted relative to the transmission image of the electro-optical device 100G.

[0012] 2 is a block diagram showing the electrical configuration of the projection display device 10. The projection display device 10 includes a display control circuit 20 and the electro-optical devices 100R, 100G, and 100B described above.

[0013] Video data Vid-in is supplied from a host device or other higher-level device (not shown) in synchronization with a synchronization signal Sync. The video data Vid-in specifies the gradation level of pixels in an image to be displayed, for example, by 8 bits for each RGB.

[0014] In the projection display device 10, a color image projected onto the screen Scr is expressed by combining the transmitted images of the electro-optical devices 100R, 100G, and 100B as described above. Therefore, a pixel, which is the smallest unit of a color image, can be divided into a red subpixel of the electro-optical device 100R, a green subpixel of the electro-optical device 100G, and a blue subpixel of the electro-optical device 100B. However, when it is not necessary to specify the color of the subpixels in the electro-optical devices 100R, 100G, and 100B, or when only brightness is an issue, there is no need to refer to them as subpixels. Therefore, in this description, the display unit in the electro-optical devices 100R, 100G, and 100B will be referred to simply as a pixel.

[0015] The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid-in, a horizontal synchronization signal that instructs the start of horizontal scanning, and a clock signal that indicates the timing of one video pixel in the video data Vid-in.

[0016] The display control circuit 20 separates the video data Vid-in from the higher-level device into R, G, and B components, converts them into analog voltage data signals, and supplies them to the electro-optical devices 100R, 100G, and 100B. Specifically, the display control circuit 20 converts the R component of the video data Vid-in into analog and supplies it to the electro-optical device 100R as a data signal Vid-R. Similarly, the display control circuit 20 converts the G component of the video data Vid-in into analog and supplies it to the electro-optical device 100G as a data signal Vid-G, and converts the B component into analog and supplies it to the electro-optical device 100B as a data signal Vid-B. The display control circuit 20 supplies the data signals Vid_R, Vid_G, and Vid_B in sequence in synchronization with a control signal Ctr for controlling the driving of the electro-optical devices 100R, 100G, and 100B.

[0017] Next, the electro-optical devices 100R, 100G, and 100B will be described. The electro-optical devices 100R, 100G, and 100B have a common structure, with the only difference being the color, i.e., wavelength, of the incident light. Therefore, the electro-optical devices 100R, 100G, and 100B will be generally described, with the reference numeral 100, without specifying the color.

[0018] FIG. 3 is a perspective view showing the appearance of the electro-optical device 100, and FIG. 4 is a cross-sectional view taken along line Hh in FIG. As shown in these figures, in the electro-optical device 100, an element substrate 100a on which a pixel electrode 126 is provided and an opposing substrate 100b on which a common electrode 72 is provided are bonded together with a sealing material 90 so that the electrode forming surfaces face each other while maintaining a certain gap, and a liquid crystal 62 is sealed in this gap.

[0019] The element substrate 100a and the counter substrate 100b are each made of a substrate having optical transparency and insulating properties, such as glass or quartz. As shown in FIG. 3, one side of the element substrate 100a protrudes beyond the counter substrate 100b. A plurality of terminals 7 are provided in this protruding area along the horizontal direction in the figure. One end of an FPC (Flexible Printed Circuits) substrate (not shown) is connected to the plurality of terminals 7. The other end of the FPC substrate is connected to the display control circuit 20, and the various signals described above are supplied to the FPC substrate.

[0020] On the surface of the element substrate 100a facing the counter substrate 100b, pixel electrodes 126 are provided by patterning a transparent conductive layer, as will be described in detail later. Various elements other than the electrodes are also provided on the opposing surfaces of the element substrate 100a and the counter substrate 100b, but these are omitted from FIG.

[0021] 5 is a block diagram showing the electrical configuration of the electro-optical device 100. In the electro-optical device 100, a scanning line driving circuit 30 and a data line driving circuit 40 are provided on the periphery of the display area 5.

[0022] In the display region 5 of the electro-optical device 100, pixel circuits 50 are arranged in a matrix. More specifically, in the display region 5, a plurality of scanning lines 12 are provided extending along the horizontal X-axis in the figure. Furthermore, a plurality of data lines 14 are provided extending along the vertical Y-axis and are electrically insulated from the scanning lines 12. The pixel circuits 50 are provided in a matrix corresponding to the intersections of the plurality of scanning lines 12 and the plurality of data lines 14.

[0023] If the number of scanning lines 12 is m and the number of data lines 14 is n, the pixel circuits 50 are arranged in a matrix of m rows and n columns. Both m and n are integers greater than or equal to 2. To distinguish between the rows of the matrix in the scanning lines 12 and pixel circuits 50, they may be referred to as 1, 2, 3, ..., (m-1), m rows from top to bottom in the drawings. Similarly, to distinguish between the columns of the matrix in the data lines 14 and pixel circuits 50, they may be referred to as 1, 2, 3, ..., (n-1), n ​​columns from left to right in the drawings.

[0024] The scanning line driving circuit 30 selects the scanning lines 12 one by one in the order of, for example, the 1st, 2nd, 3rd, ..., mth rows in accordance with a control signal Ctr from the display control circuit 20, and sets the scanning signal to the selected scanning line 12 to H level. Note that the scanning line driving circuit 30 sets the scanning signals to the scanning lines 12 other than the selected scanning line 12 to L level. The data line driving circuit 40 latches one row of data signals of the corresponding color from the data signals supplied from the display control circuit 20, and outputs the data signals to the pixel circuit 50 located on the scanning line 12 via the data line 14 during the period when the scanning signal to the scanning line 12 is at H level.

[0025] 6 is a diagram showing an equivalent circuit of four pixel circuits 50 arranged in two rows and two columns corresponding to the intersections of two adjacent scanning lines 12 and two adjacent data lines 14. The pixel circuits 50 all have the same circuit configuration.

[0026] The pixel circuit 50 includes a liquid crystal element 60, a transistor 130, and a storage capacitor 140. The transistor 130 is, for example, an n-channel thin film transistor. In the pixel circuit 50, the gate electrode of the transistor 130 is electrically connected to the scan line 12, while its source region is electrically connected to the data line 14, and its drain region is electrically connected to the pixel electrode 126 and one end of the storage capacitor 140.

[0027] In the transistor 130, when the direction of current flow is reversed, the source and drain are swapped, but in this description, the region electrically connected to the data line 14 is referred to as the source region, and the region electrically connected to the pixel electrode 126 is referred to as the drain region. In addition, in this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, a case where different wiring is connected via a contact hole even if two or more elements are not directly connected to each other on an element substrate.

[0028] A common electrode 72 is provided in common to all pixels so as to face the pixel electrode 126. A voltage LCcom is applied to the common electrode 72. As described above, the liquid crystal 62 is sandwiched between the pixel electrode 126 and the common electrode 72. Therefore, for each pixel circuit 50, a liquid crystal element 60 is formed in which the liquid crystal 62 is sandwiched between the pixel electrode 126 and the common electrode 72. Furthermore, a storage capacitor 140 is provided electrically in parallel with the liquid crystal element 60. One end of the storage capacitor 140 is connected to the pixel electrode 126, and the other end is connected to a capacitance line 74. A time-constant voltage, for example, a voltage LCcom that is the same as the voltage applied to the common electrode 72, is applied to the capacitance line 74.

[0029] The pixel circuits 50 are arranged in a matrix along the X axis along the scanning lines 12 and the Y axis along the data lines 14, and therefore the pixel electrodes 126 included in the pixel circuits 50 are also arranged along the X axis and the Y axis.

[0030] When the scanning signal for a scanning line 12 is at H level, the transistor 130 of the pixel circuit 50 provided corresponding to that scanning line 12 is turned on. When the transistor 130 is turned on, the data line 14 and the pixel electrode 126 are electrically connected, and the data signal supplied to the data line 14 reaches the pixel electrode 126 via the transistor 130 that is turned on. When the scanning line 12 is turned to L level, the transistor 130 is turned off, but the voltage of the data signal that has reached the pixel electrode 126 is held by the liquid crystal element 60 and the storage capacitor 140.

[0031] As is well known, in the liquid crystal element 60, the orientation of the liquid crystal molecules changes in response to the electric field generated by the pixel electrode 126 and the common electrode 72. Therefore, the liquid crystal element 60 has a transmittance that corresponds to the effective value of the applied voltage. If the liquid crystal element 60 is in a normally black mode, the transmittance increases as the voltage applied to the liquid crystal element 60 increases. The region that functions as a pixel in the liquid crystal element 60, i.e., the region that exhibits transmittance according to the effective value of the voltage, is the region where the pixel electrode 126 overlaps the common electrode 72 when the element substrate 100a and the counter substrate 100b are viewed in a plan view. Since the pixel electrode 126 has, for example, a square shape in a plan view, the shape of the pixel in the electro-optical device 100 also has a square shape in a plan view. In this description, a plan view refers to viewing the substrate from a direction along the perpendicular axis to the substrate surface, and a cross-sectional view refers to viewing the substrate cut along a plane perpendicular to the substrate surface.

[0032] The operation of supplying data signals to the pixel electrodes 126 of the liquid crystal elements 60 is executed in the order of the first, second, third, ..., mth rows in one vertical scanning period. As a result, a voltage corresponding to the data signal is held in each of the liquid crystal elements 60 of the pixel circuits 50 arranged in m rows and n columns, each liquid crystal element 60 has the target transmittance, and a transmitted image of the corresponding color is generated by the liquid crystal elements 60 arranged in m rows and n columns. In this way, a transmission image is generated for each of the R, G, and B colors, and a color image obtained by combining the R, G, and B colors is projected onto the screen Scr.

[0033] Next, the configuration of the element substrate 100a in the electro-optical device 100 will be described.

[0034] 7 to 12 are plan views showing the manufacturing process for the main part of the element substrate 100a. Note that the plan views of Fig. 7 to 12 are plan views showing part of the manufacturing process for the two rows of scanning lines 12, the two columns of data lines 14, and the pixel circuits 50, and various insulating layers and dielectric layers are omitted as appropriate. 13 to 19 are partial cross-sectional views showing the manufacturing process of the main part of the element substrate 100a. Figures 13 to 18 are partial cross-sectional views taken along line Aa in Figure 11, and Figure 19 is a partial cross-sectional view taken along line Bb in Figure 11.

[0035] 7, scanning lines 12 are provided on the upper surface of a substrate 151 (see FIG. 13) that is optically transparent and insulating, such as quartz. The scanning lines 12 are formed to extend along the X-axis by patterning a conductive layer made of, for example, tungsten (W) or tungsten silicide (WSi) that is light-shielding and conductive.

[0036] The dashed dotted line in FIG. 7 indicates the center line along which the data line 14 is to be provided. The scanning line 12 includes a protrusion 121 that branches upward and a protrusion 122 that branches downward in the drawing from a point where the scanning line 12 is to intersect with the data line 14 in a plan view. The scanning line 12 is wider than other portions at the point where it is to intersect with the data line 14 in order to receive the two contact holes Ctg. More specifically, the two contact holes Ctg are provided on either side of the center line of the data line 14 where the scanning line 12 is to intersect.

[0037] Here, attention is focused on two rows of scanning lines 12, but the scanning lines 12 are provided for each row as described above. Similarly, attention is focused on two columns of data lines 14, but the data lines 14 are provided for each column as described above. In addition, in the plan view, contact holes are indicated by two types of marks: a simple square frame and a square frame with an X overlaid on it. Of these, the former simple square frame indicates the position of the lower wiring (closer to the substrate 151) of the two wirings to be connected, and the latter square frame with an X overlaid on it indicates the position of the upper wiring (farther from the substrate 151) of the two wirings to be connected.

[0038] 13, an interlayer insulating film 152 is provided so as to cover the substrate 151 or the scanning lines 12. The interlayer insulating film 152 is preferably an oxide film such as silicon oxide. 8, the semiconductor layer 131 of the transistor 130 is provided by patterning the high-temperature polysilicon film in correspondence with the scanning line 12 and the location where the data line 14 is to be provided. Specifically, the semiconductor layer 131 is provided along the Y axis so as to be included in the scanning line 12 from the protrusion 121 to the protrusion 122 at the location where the scanning line 12 is to intersect with the data line 14.

[0039] The straight line portion of the semiconductor layer 131 connecting both ends in a plan view is narrower than both ends. Of the two ends of the semiconductor layer 131, the upper one in the drawing is the region that will become the source of the transistor 130, and this region is the region that will receive the contact hole Cts1. Of the two ends of the semiconductor layer 131, the lower one in the drawing is the region that will become the drain of the transistor 130, and this region is the region that will receive the contact hole Ctd1. In this way, the semiconductor layer 131 is provided above the scanning lines 12, which have light blocking properties. Therefore, it is possible to prevent light from the substrate 151 side from reaching the semiconductor layer 131.

[0040] In this description, the term "upper layer" refers to a layer (or film) formed later in time than the layer (or film) being compared in the manufacturing process. In other words, the term "lower layer" refers to a layer (or film) formed earlier in time than the layer (or film) being compared in the manufacturing process.

[0041] 13, a gate insulating film 153 is provided so as to cover the interlayer insulating film 152 or the semiconductor layer 131. The gate insulating film 153 and the interlayer insulating film 152 are opened at the contact hole Ctg to expose the scanning line 12. do.

[0042] Next, as shown in FIG. 9, the gate electrode 132 is provided in an island shape on the upper surface of the gate insulating film 153 so as to be included in the scanning line 12 in a planar view, to fill the two contact holes Ctg, and to overlap the narrow portion of the semiconductor layer 131. As a result, the gate electrode 132 is electrically connected to the scanning line 12 via the two contact holes Ctg.

[0043] The gate electrode 132 has an inverted T shape in plan view in the figure, and the vertical line of the T overlaps with the semiconductor layer 131. Furthermore, the distance along the Y-axis direction in the region of the gate electrode 132 surrounding the contact hole Ctg is defined as L1.

[0044] LDD regions 131a and 131b are provided in the semiconductor layer 131 by ion implantation using the gate electrode 132 as a mask. In Fig. 9, the LDD regions 131a and 131b are hatched regions. As shown in Fig. 9, the region of the semiconductor layer 131 below the LDD region 131a and including the contact hole Ctd1 is the drain region, and the region above the LDD region 131b and including the contact hole Cts1 is the source region. The drain region is a doped region with a higher concentration than the lightly doped LDD region 131a, and the source region is a doped region with a higher concentration than the lightly doped LDD region 131b.

[0045] Next, as shown in FIG. 13, an interlayer insulating film 154 is provided so as to cover the gate insulating film 153 or the gate electrode 132. In this embodiment, a sidewall light shielding portion 192 (see FIGS. 18 and 19) is provided to prevent light from entering the LDD region 131a and the channel region of the semiconductor layer 131. As a preparatory step for forming this sidewall light shielding portion 192, a sidewall step 191 is provided by etching a portion of the interlayer insulating film 154, the gate insulating film 153, and the interlayer insulating film 152, in that order.

[0046] In detail, first, as shown in FIG. 14, a photoresist Reg1 is provided on the upper surface of the interlayer insulating film 154 by patterning using photolithography. The region where the photoresist Reg1 is provided is the hatched region in FIG. 10 in plan view, and is provided for each pixel circuit 50. Specifically, the photoresist Reg1 is provided in an island shape outside the gate electrode 132 in plan view and inside the scanning line 12. More specifically, the photoresist Reg1 is provided outside the semiconductor layer 131 and the gate electrode 132 and inside the protruding portions 121 and 122 of the scanning line 12 in the direction along the Y axis, and is provided inside the relay electrode 162 (see FIG. 11), which will be described next, in the direction along the X axis. In the first embodiment, the photoresist Reg1 is provided outside the planned locations where the contact holes Cts1 and Ctd1 are to be provided.

[0047] Second, using the photoresist Reg1 as a mask, the interlayer insulating film 154, the gate insulating film 153, and a portion of the interlayer insulating film 152 are removed by etching. After that, when the photoresist Reg1 is removed, a sidewall step 191 is formed by etching the interlayer insulating film 154, the gate insulating film 153, and the interlayer insulating film 152, as shown in FIG. The sidewall step 191 is formed at the outer edge of the photoresist Reg1 shown in FIG. 10 in plan view.

[0048] If the interlayer insulating film 152 is excessively etched during the formation of the sidewall step 191, exposing the scan line 12, the relay electrode 162 will come into contact with the scan line 12 when the relay electrode 162 is provided. Even if the relay electrode 162 and the scan line 12 are not in contact with each other, if the distance between them is short, potential fluctuations in the scan line 12 will be more likely to propagate to the relay electrode 162 due to parasitic capacitance. On the other hand, if the interlayer insulating film 152 is not etched enough, the light-shielding effect will not be sufficient. When the pitch of the pixel circuits 50 is about 4 to 6 μm in plan view, the sidewall step 191 is formed so that the bottom 191a of the sidewall step 191 in FIG. 15 is lower than the semiconductor layer 131 (closer to the substrate 151) and the distance (thickness) t1 from the scanning line 12, which is a light-shielding film, is about 100 nm.

[0049] In the first embodiment, after the sidewall step 191 is formed, the interlayer insulating film 154 and the gate insulating film 153 are opened in this order to provide contact holes Cts1 and Ctd1, although this is omitted in the cross-sectional view. 16, a wiring layer 160 is formed. The wiring layer 160 is a conductive layer having a light-shielding property, and is a conductive layer that becomes the relay electrodes 161 and 162. The wiring layer 160 is made of, for example, aluminum.

[0050] 17, photoresist Reg2 is provided on the upper surface of the wiring layer 160 by patterning using photolithography. Thereafter, the wiring layer 160 is etched using the photoresist Reg2 as a mask. By this etching, relay electrodes 161 and 162 are provided for each pixel circuit 50. Thereafter, the photoresist Reg2 is removed, and the relay electrodes 161 and 162 are provided as shown in FIG. 11 in plan view and as shown in FIGS. 18 and 19 in cross-sectional views. As a result, the relay electrode 161 is electrically connected to the source region of the semiconductor layer 131 via the contact hole Cts1, and the relay electrode 162 is electrically connected to the drain region of the semiconductor layer 131 via the contact hole Ctd1.

[0051] The relay electrode 162 is provided so as to cover the sidewall step 191, except for the side 162b at the outer edge of the relay electrode 162 where the protrusion 121 branches off from the scanning line 12. The portion of the relay electrode 162 that is provided on the sidewall step 191 becomes a sidewall light-shielding portion 192. That is, the sidewall light-shielding portion 192 is formed in the portions of the interlayer insulating film 154, the gate insulating film 153, and the interlayer insulating film 152 that have been removed by etching. Therefore, the sidewall light-shielding portion 192 surrounds the drain region, the LDD region 131a, and the gate electrode 132 excluding the side 162b in plan view. In the sidewall light-shielding portion 192, the distance (thickness) t2 in the direction along the surface of the substrate 151 (horizontal in the cross-sectional view, see Figure 18) is designed to be 50 nm or more, as it is necessary to ensure light-shielding properties. Although a cross-sectional view is omitted, the relay electrode 161 has a sidewall light-shielding portion 192 provided on the outer edge thereof so as to cover the sidewall step 191 except for the side 161b.

[0052] In this description, a wall refers to something that separates a certain element and has a component in a direction perpendicular to the surface direction of the base material 151 or in the thickness direction of the base material 151. In other words, although the sidewall light-shielding portion 192 is aligned along the thickness direction of the base material 151 in a cross-sectional view in the drawing, it may be aligned along an oblique direction of the base material 151. Furthermore, the wall does not need to surround the entire element in plan view, and therefore the sidewall light shielding portion 192 does not need to surround part of the source region and the drain region in the semiconductor layer 131 in plan view, as in a modified example described later.

[0053] A bottom 191a of the sidewall step 191 is located lower than the semiconductor layer 131 and is located a distance t1 higher than the scanning line 12. Therefore, the position of the lower end of the sidewall light shielding portion 192 is also located lower than the semiconductor layer 131 and is located a distance t1 higher than the scanning line 12. The lower end of the sidewall light-shielding portion 192 refers to the portion of the sidewall light-shielding portion 192 that contacts the bottom portion 191a. In this description, "higher than A" means that, in a cross-sectional view, the distance from base material 151 in the thickness direction of base material 151 is longer than A. In other words, "lower than A" means that, in a cross-sectional view, the distance from base material 151 in the thickness direction of base material 151 is shorter than A.

[0054] After the relay electrodes 161 and 162 are formed, an interlayer insulating film (not shown) is provided, and contact holes Cts2 and Ctd2 are formed by opening the interlayer insulating film. Furthermore, the formed wiring layer is patterned to provide the data line 14 and the relay electrode 171, as shown in FIG. As a result, the data line 14 is electrically connected to the source region of the semiconductor layer 131 via the contact hole Cts2, the relay electrode 161, and the contact hole Cts1 in this order. The relay electrode 171 is electrically connected to the drain region of the semiconductor layer 131 via the contact hole Ctd2, the relay electrode 162, and the contact hole Ctd1 in this order.

[0055] Although details of the subsequent manufacturing process will be omitted, in summary, interlayer insulating layers (or dielectric layers) and wiring layers are alternately provided, the relay electrode 171 is connected to another relay electrode via a contact hole Ctd3, and the other relay electrode is connected via a contact hole to the pixel electrode 126, which has a square shape in plan view. The relay electrode via the contact hole Ctd3 sandwiches the dielectric layer with a separate wiring or the like, and becomes one end of the storage capacitor 140.

[0056] 18 is a cross-sectional view taken along line Aa in FIG. 11, which includes the relay electrode 162, the LDD region 131a, the gate electrode 132, and the scanning line 12. The line Aa is at an angle of 45 degrees to the scanning line 12 or the data line 14 in a plan view. 19 is a cross-sectional view of the scanning line 12 in FIG. 11, taken along line Bb along the X-axis, including the wide portion of the scanning line 12, and shows the state in which the gate electrode 132 is connected to the scanning line 12 via two contact holes Ctg.

[0057] To explain the advantages of the electro-optical device 100 according to the first embodiment, an electro-optical device according to a comparative example will be described.

[0058] FIG. 20 is a cross-sectional view of a main part for explaining the penetration of light into a semiconductor layer 131 in an electro-optical device according to a comparative example. 18 , the comparative example does not include a sidewall light-shielding portion 192. Therefore, in the comparative example, light Z3 incident from the counter substrate 100b side at an angle relative to the surface of the base material 151 is reflected by the scanning line 12 and reaches the semiconductor layer 131. Similarly, in the comparative example, light Z4 incident from the opposite side of the counter substrate 100b at an angle relative to the surface of the base material 151 is reflected by the relay electrode 162 and reaches the semiconductor layer 131. If light is incident on the semiconductor layer 131, particularly the channel region and the LDD region, the resistance value in the off state decreases, causing a phenomenon (light leakage) in which charges stored in the liquid crystal element 60 and the storage capacitor 140 leak, resulting in degradation of display quality such as flicker and unevenness.

[0059] FIG. 21 is a cross-sectional view of a main part for explaining the penetration of light into the semiconductor layer 131 in the electro-optical device according to the first embodiment. In the first embodiment, light Z3 incident obliquely with respect to the surface of the base material 151 is prevented from penetrating into the semiconductor layer 131 by the sidewall light shielding portion 192. Similarly, in the first embodiment, light Z4 incident obliquely with respect to the surface of the base material 151 from the opposite side of the counter substrate 100b is prevented from penetrating into the semiconductor layer 131 by the sidewall light shielding portion 192. Therefore, in the first embodiment, compared to the comparative example, it is possible to prevent light from penetrating into the semiconductor layer 131, particularly the channel region and LDD region, thereby suppressing degradation of display quality such as flicker and unevenness caused by light leakage. In short, the sidewall light-shielding portion 192 in the first embodiment is a portion added to the relay electrode 162 in the comparative example of FIG.

[0060] In the first embodiment described above, the etching for forming the sidewall step 191 and the etching for opening the contact holes Cts1 and Ctd1 are performed in separate processes, but they may also be performed in the same process as in the modified example described below.

[0061] Figures 22 and 23 are plan views showing the manufacturing process of an element substrate according to a modified example of the first embodiment, in which Figure 22 shows the shape of photoresist Reg1 provided on the upper surface of the interlayer insulating film 154, and Figure 23 shows relay electrodes 161 and 162. The modified example differs from the shape shown in FIG. 10 in that the photoresist Reg1 does not reach the ends of the source region and the drain region in plan view.

[0062] In the modification, the interlayer insulating film 154 and the gate insulating film 153 are etched by exposing the photoresist Reg1, forming a sidewall step 191 and exposing the source and drain regions of the semiconductor layer 131. In this state, the relay electrodes 161 and 162 with the sidewall light-shielding portions 192 are provided by forming and patterning a wiring layer. In the modified example, a relay electrode 161 is stacked on the portion Ctdb where the interlayer insulating film 154 and the gate insulating film 153 have been removed by etching, thereby establishing connection with the drain region, and a relay electrode 162 is stacked on the portion Ctsb where the interlayer insulating film 154 and the gate insulating film 153 have been removed by etching, thereby establishing connection with the source region.

[0063] According to the modification, a sidewall step 191 is formed by etching the interlayer insulating film 154 and the gate insulating film 153 (and the interlayer insulating film 152) once, and the source region and the drain region of the semiconductor layer 131 are exposed. Therefore, in the modification, light leakage can be reduced with fewer steps than in the first embodiment.

[0064] In the electro-optical device 100, the temperature is likely to rise due to absorption of light incident on the wiring layer. In the electro-optical device 100, an increase in temperature changes the electro-optical response of the liquid crystal 62, so there is a strong desire to avoid an increase in temperature as much as possible. If the temperature rise is caused predominantly by the absorption of light in the wiring layer, the area of ​​the region that is shielded from light by the wiring layer per unit area in plan view should be reduced. Therefore, a second embodiment will be described, which can reduce the area of ​​the light-blocked region more than the first embodiment.

[0065] 24 to 26 are plan views showing the manufacturing process for the main part of the element substrate 100a in the second embodiment, and correspond to FIGS. 9 to 11 in the first embodiment, respectively. FIG. 27 is a partial cross-sectional view taken along line Dd in FIG. 26, and corresponds to FIG. 19 in the first embodiment.

[0066] 24, in the second embodiment, a distance L2 along the Y-axis direction in a region of the gate electrode 132 surrounding the contact hole Ctg is shorter than the distance L1 in the first embodiment. Note that in the second embodiment, similar to the modified example of the first embodiment (see FIG. 22), the photoresist Reg1 does not reach the ends of the source region and the drain region in plan view, but similar to the first embodiment (see FIG. 10), it may be provided outside the planned locations for the contact holes Cts1 and Ctd1.

[0067] FIG. 27 is a partial cross-sectional view taken along line Dd in FIG. 26, and corresponds to FIG. 19 in the first embodiment. In the second embodiment, the sidewall light shielding portion 192 of the relay electrode 162 and the scanning line 12 prevent light incident from an oblique direction along the X axis from entering the semiconductor layer 131.

[0068] In the second embodiment, the distance L2 of the contact hole Ctg for connecting the scanning line 12 to the gate electrode 132 is shorter than the distance L1 in the first embodiment, so the wide portion of the scanning line 12 can be made compact. Therefore, since the wide portion of the scanning line 12 is made more compact, the area of ​​the region that is shielded by the wiring layer per unit area in a plan view can be reduced accordingly, and light absorption can be suppressed. Therefore, in the electro-optical device 100 according to the second embodiment, in addition to reducing light leakage, temperature rise can be suppressed compared to the first embodiment.

[0069] The electro-optical device 100 can also be applied to electronic devices other than the projection display device 10. For example, the electro-optical device 100 can also be applied to a display panel of a head-mounted display, an electronic viewfinder in a video camera or a digital camera with interchangeable lenses, a display unit of a personal digital assistant, a wristwatch, and the like.

[0070] From the above-described exemplary embodiments, the following aspects can be understood, for example.

[0071] In order to solve the above problem, an electro-optical device according to one aspect of the present disclosure comprises a pixel electrode, a relay electrode having light-shielding properties, and a transistor for switching the pixel electrode, wherein the transistor includes a semiconductor layer and a gate electrode that overlaps the semiconductor layer in a planar view via a gate insulating film and is supplied with a scanning signal, and the relay electrode is electrically connected to a source region or a drain region of the transistor, overlaps with a portion of the semiconductor layer in a planar view, and has a sidewall light-shielding portion that covers a portion of the semiconductor layer to a position lower than the semiconductor layer in a cross-sectional view. In the electro-optical device according to the first aspect, the sidewall light-shielding portion can block light that would otherwise enter the semiconductor layer, thereby reducing light leakage.

[0072] . In the electro-optical device according to a second specific aspect of the first aspect, the scanning signal is supplied to a scanning line, which is located below the semiconductor layer and has a light-shielding property. According to the electro-optical device of the second aspect, the scanning lines can block light that attempts to enter the semiconductor layer from the lower layer side.

[0073] In an electro-optical device according to a third specific example of the second example, the lower end of the sidewall light-shielding portion is located higher than the scanning line in a cross-sectional view. According to the electro-optical device of the third aspect, electrical contact between the scanning lines and the source regions or drain regions can be prevented.

[0074] In an electro-optical device according to a fourth specific aspect of the first aspect, the relay electrode is electrically connected to the source region or the drain region via a contact hole that opens an interlayer insulating film. In the electro-optical device according to the fourth aspect, the relay electrode is electrically connected to the source region or the drain region through the contact hole.

[0075] In the electro-optical device according to a fifth specific example of the fourth example, the relay electrode is electrically connected to the drain region, and the sidewall light-shielding portion is provided outside the drain region and the gate electrode in a plan view. In the electro-optical device according to the fifth aspect, the sidewall light-shielding portion of the relay electrode can prevent oblique light from entering the drain electrode and the gate electrode.

[0076] In an electro-optical device according to a specific embodiment 6 of embodiment 1, the relay electrode is electrically connected to the source region or the drain region in a portion where a portion of the interlayer insulating film has been removed, the sidewall light-shielding portion is provided on a sidewall step formed by the removal of a portion of the interlayer insulating film, and the removal of the portion of the interlayer insulating film for connecting the relay electrode and the removal of the portion of the interlayer insulating film for the sidewall step are performed by the same etching process. According to the electro-optical device of embodiment 6, etching of the interlayer insulating film for connecting the relay electrodes and etching of the interlayer insulating film for providing sidewall steps are performed simultaneously, so that light leakage can be reduced without adding any additional processes.

[0077] An electronic device according to a seventh aspect includes the electro-optical device according to any one of the first to sixth aspects. [Explanation of symbols]

[0078] 10...projection type display device, 30...display control circuit, 50...pixel circuit, 60...liquid crystal element, 100...electro-optical device, 118...pixel electrode, 120...liquid crystal element, 130...transistor, 131...semiconductor layer, 161, 162...relay electrodes, 191...sidewall step, 191a...bottom, 192...sidewall light-shielding portion

Claims

1. A pixel electrode; a relay electrode having a light-shielding property; a transistor for switching the pixel electrode; Equipped with The transistor is a semiconductor layer; a gate electrode that overlaps the semiconductor layer in a plan view with a gate insulating film interposed therebetween and to which a scanning signal is supplied; Including, The relay electrode is electrically connected to the source region or the drain region of the transistor; overlapping a portion of the semiconductor layer in a plan view; A sidewall light-shielding portion covers a part of the semiconductor layer up to a position lower than the semiconductor layer in a cross-sectional view. Electro-optical device.

2. the scanning signal is supplied by a scanning line; The scanning lines are located below the semiconductor layer and have a light-shielding property. The electro-optical device according to claim 1 .

3. The lower end of the sidewall light-shielding portion is In cross-sectional view, it is located at a position higher than the scanning line. The electro-optical device according to claim 2 .

4. The relay electrode is A contact hole is formed in the interlayer insulating film, and the contact hole is electrically connected to the source region or the drain region. The electro-optical device according to claim 1 .

5. The relay electrode is electrically connected to the drain region; The sidewall light-shielding portion is provided outside the drain region and the gate electrode in a plan view.

5. The electro-optical device according to claim 4.

6. The relay electrode is a portion where a part of the interlayer insulating film is removed is electrically connected to the source region or the drain region; The sidewall light-shielding portion is provided on a sidewall step formed by removing a portion of the interlayer insulating film, The removal of the part of the interlayer insulating film for connecting the relay electrode and the removal of the part of the interlayer insulating film for forming the sidewall step are performed in the same etching process. The electro-optical device according to claim 1 .

7. 7. An electronic device comprising the electro-optical device according to claim 1.

Images