Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of improving the dielectric strength between a polysilicon wiring and a semiconductor substrate.SOLUTION: The semiconductor element (DEV1, DEV2) includes a semiconductor element substrate (SUB), a first insulating film (IF1, IF4), a second insulating film (IF2, IF5), a third insulating film (IF3, IF6), and a polysilicon wire (PW1,). PW2. The substrate has a first F1 and a first lower F2 opposite to the first upper surface. The first upper surface has a trench (side TR1, TR2) extending toward the first lower surface. The first insulating film is formed in the trench. The third insulating film is formed above the first insulating film so as to cover an upper surface of the second insulating film. The polysilicon wiring is formed on the third insulating film and electrically insulated from the semiconductor substrate by at least the second insulating film and the third insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The semiconductor device disclosed in JP 2019-192741 A (Patent Document 1) has a semiconductor substrate, an isolation insulating film, a gate insulating film, and a gate electrode. The semiconductor substrate has an upper surface and a lower surface. The semiconductor substrate has a source layer formed in the semiconductor substrate and a drain layer formed in the semiconductor substrate. The source layer is disposed on the upper surface of the semiconductor substrate. The drain layer is disposed on the upper surface of the semiconductor substrate so as to be spaced apart from the source layer. A trench is formed on the upper surface of the semiconductor substrate. The trench is located between the source layer and the drain layer. The isolation insulating film is formed in the trench. The gate insulating film is formed on the upper surface of the semiconductor substrate located between the source layer and the trench, and is also formed on the isolation insulating film. The gate electrode is formed on the gate insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-192741 Summary of the Invention [Problem to be solved by the invention]

[0004] When attempting to form a trench by etching the upper surface of a semiconductor substrate, a pillar-shaped portion (pillar-shaped residue) extending upward from the bottom surface of the trench may remain in the semiconductor substrate. If a pillar-shaped portion remains in the semiconductor substrate, the dielectric strength between the semiconductor substrate and the gate electrode may become insufficient. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, a first insulating film, a second insulating film, a third insulating film, and polysilicon wiring. The semiconductor substrate has a first upper surface and a first lower surface located opposite the first upper surface. The first upper surface has a trench extending toward the first lower surface. The first insulating film is formed in the trench. The third insulating film is formed above the first insulating film so as to cover the upper surface of the second insulating film. The polysilicon wiring is formed on the third insulating film and is electrically insulated from the semiconductor substrate by at least the second insulating film and the third insulating film. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, it is possible to improve the dielectric strength between the polysilicon wiring and the semiconductor substrate. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device DEV1. [Figure 2] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 3] FIG. 10 is a cross-sectional view illustrating an insulating film forming step S2. [Figure 4] FIG. 10 is a cross-sectional view illustrating an insulating film forming step S3. [Figure 5] FIG. 10 is a cross-sectional view illustrating an ion implantation step S4. [Figure 6] FIG. 10 is a cross-sectional view illustrating an insulating film removing step S5. [Figure 7] FIG. 10 is a cross-sectional view illustrating an insulating film forming step S6. [Figure 8] FIG. 10 is a cross-sectional view illustrating a polysilicon wiring forming step S7. [Figure 9A] FIG. 10 is a first cross-sectional view illustrating the cause of formation of a columnar portion PL. [Figure 9B] FIG. 2 is a second cross-sectional view illustrating the cause of formation of the columnar portion PL. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device DEV1a in which a columnar portion PL is formed. [Figure 11]FIG. 2 is a cross-sectional view of the semiconductor device DEV1 in which a columnar portion PL is formed. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor device DEV1 according to a modified example. [Figure 13] FIG. 10 is a cross-sectional view of the semiconductor device DEV2 when a columnar portion PL is formed. [Figure 14] FIG. 10 is a first cross-sectional view illustrating an insulating film forming step S3 in the manufacturing method of the semiconductor device DEV2. [Figure 15] FIG. 10 is a second cross-sectional view illustrating an insulating film forming step S3 in the manufacturing method of the semiconductor device DEV2. [Figure 16] 10 is a cross-sectional view illustrating an insulating film removing step S5 in the manufacturing method of the semiconductor device DEV2. FIG. [Figure 17] FIG. 2 is a cross-sectional view of the semiconductor device DEV3. [Figure 18] FIG. 10 is a cross-sectional view of the semiconductor device DEV3 when a columnar portion PL is formed. [Figure 19] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV3. [Figure 20] 10 is a cross-sectional view illustrating an insulating film forming step S6 in the manufacturing method of the semiconductor device DEV3. FIG. [Figure 21] 10 is a cross-sectional view illustrating an insulating film removing step S9 in the manufacturing method of the semiconductor device DEV3. FIG. [Figure 22] 10 is a cross-sectional view illustrating a polysilicon wiring formation step S7 in the manufacturing method of the semiconductor device DEV3. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of semiconductor device DEV1> As shown in FIG. 1, the semiconductor device DEV1 has a semiconductor substrate SUB, insulating films IF1, IF2, and IF3, and a polysilicon wiring PW1.

[0011] The semiconductor substrate SUB is made of, for example, single crystal silicon and has an upper surface F1 and a lower surface F2 located on the opposite side of the upper surface F1.

[0012] The semiconductor substrate SUB has a source layer SL, a body layer BL, a drift layer DL, a drain layer DRA, and a back gate layer BG. The source layer SL is formed in the semiconductor substrate SUB and disposed on an upper surface F1. The body layer BL is formed in the semiconductor substrate SUB and disposed on an upper surface F1 so as to surround the source layer SL in a planar view. The drift layer DL is formed in the semiconductor substrate SUB and disposed on an upper surface F1 so as to be adjacent to the body layer BL. The drain layer DRA is formed in the semiconductor substrate SUB and disposed on an upper surface F1 so as to be surrounded by the drift layer DL in a planar view. That is, the drain layer DRA is separated from the source layer SL in a first direction DR1 along the upper surface F1. The back gate layer BG is formed in the semiconductor substrate SUB and disposed on an upper surface F1 so as to be surrounded by the body layer BL. The conductivity type of the source layer SL, the conductivity type of the drift layer DL, and the conductivity type of the drain layer DRA are the first conductivity type. The conductivity type of the body layer BL and the back gate layer BG is a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is n-type and the second conductivity type is p-type.

[0013] A trench TR1 is formed in the upper surface F1 of the semiconductor substrate SUB. The trench TR1 extends toward the lower surface F2 of the semiconductor substrate SUB. The trench TR1 is located between the source layer SL and the drain layer DRA in the first direction DR1. The trench TR1 is surrounded by, for example, the drift layer DL in plan view. The trench TR1 has a first end TR1a and a second end TR1b located on the opposite side of the first end TR1a in the first direction DR1. The first end TR1a faces the drain layer DRA, and the second end TR1b faces the source layer SL.

[0014] The insulating film IF1 is formed in the trench TR1. The insulating film IF1 is formed of, for example, silicon oxide. The trench TR1 and the insulating film IF1 have an STI (Shallow Trench Isolation) structure. The insulating film IF2 is formed on the insulating film IF1. However, the insulating film IF2 is not formed between the insulating film IF3 and the upper surface F1. The insulating film IF2 is formed of, for example, silicon oxide. The insulating film IF3 is formed on the upper surface F1 located between the source layer SL and the trench TR1. The insulating film IF3 is also formed on the insulating film IF2. That is, the insulating film IF3 is formed above the insulating film IF1 so as to cover the upper surface of the insulating film IF2. The insulating film IF3 is formed of, for example, silicon oxide.

[0015] The polysilicon wiring PW1 is formed on the insulating film IF3. The polysilicon wiring PW1 is made of polycrystalline silicon (polysilicon) containing a dopant. The insulating film IF3, the polysilicon wiring PW1, the source layer SL, the body layer BL, the drift layer DL, and the drain layer DRA constitute an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor. The polysilicon wiring PW1 constitutes the gate electrode of the LDMOS transistor, and the insulating film IF3 constitutes the gate insulating film of the LDMOS transistor.

[0016] <Method of Manufacturing Semiconductor Device DEV1> As shown in FIG. 2, the manufacturing method of the semiconductor device DEV1 includes a preparation step S1, an insulating film formation step S2, an insulating film formation step S3, an ion implantation step S4, an insulating film removal step S5, an insulating film formation step S6, a polysilicon wiring formation step S7, and an ion implantation step S8.

[0017] In the preparation step S1, a semiconductor substrate SUB is prepared. As shown in FIG. 3, in the insulating film formation step S2, a trench TR1 is formed, and then an insulating film IF1 is formed. In the insulating film formation step S2, first, a hard mask HM (see FIGS. 9A and 9B) is formed on the upper surface F1. The hard mask HM has, for example, a silicon oxide film HM1 formed on the upper surface F1, a polysilicon film HM2 formed on the silicon oxide film HM1, and a silicon nitride film HM3 formed on the polysilicon film HM2. Second, an anti-reflection film BARC is formed on the hard mask HM, and then a resist pattern RP is formed on the anti-reflection film BARC. Third, the hard mask HM is patterned by dry etching the hard mask HM through openings in the resist pattern RP. Fourth, a trench TR1 is formed in the semiconductor substrate SUB by dry etching the hard mask HM through openings in the hard mask HM.

[0018] Fifth, a constituent material of the insulating film IF1 is formed on the upper surface F1 so as to fill the trench TR1, for example, by a CVD (Chemical Vapor Deposition) method. Sixth, the constituent material of the insulating film IF1 formed outside the trench TR1 is removed, for example, by a CMP (Chemical Mechanical Polishing) method or etch-back, resulting in the formation of the insulating film IF1 in the trench TR1. This completes the insulating film formation step S2. After the trench TR1 and the insulating film IF1 are formed, the hard mask HM is removed.

[0019] As shown in Fig. 4, in the insulating film formation step S3, an insulating film IF2 is formed on the upper surface F1 and the insulating film IF1 by a plasma CVD method using, for example, TEOS (Tetra Ethoxy Silane). As shown in Fig. 5, in the ion implantation step S4, ion implantation is performed to form the body layer BL and the drift layer DL. As shown in Fig. 6, in the insulating film removal step S5, first, a resist pattern having openings is formed on the insulating film IF1. Second, the insulating film IF2 formed on the upper surface F1 is removed by dry etching through the openings in the resist pattern, while the insulating film IF2 formed on the insulating film IF1 is left.

[0020] As shown in FIG. 7, in the insulating film forming step S6, an insulating film IF3 is formed on the upper surface F1 by, for example, thermal oxidation. Also, in the insulating film forming step S6, an insulating film IF3 is also formed on the insulating film IF2. As shown in FIG. 8, in the polysilicon wiring forming step S7, a polysilicon wiring PW1 is formed on the insulating film IF3. In the polysilicon wiring forming step S7, first, a constituent material of the polysilicon wiring PW1 is deposited on the insulating film IF3 by, for example, a CVD method. Second, a resist pattern is formed on the constituent material of the polysilicon wiring PW1. Third, the constituent material of the polysilicon wiring PW1 is patterned by dry etching through openings in the resist pattern. In this way, the polysilicon wiring PW1 is formed. Note that, during the dry etching, the insulating films IF2 and IF3 located other than under the polysilicon wiring PW1 are also removed.

[0021] In the ion implantation step S8, ions are implanted to form the source layer SL, the drain layer DRA, and the back gate layer BG. In this way, the structure of the semiconductor device DEV1 shown in FIG.

[0022] <Effects of semiconductor device DEV1> As shown in FIGS. 9A and 9B, in the insulating film forming step S2, particles may remain on the anti-reflective film BARC. If particles remain on the anti-reflective film BARC, etching may be difficult to proceed near the particles, and the hard mask HM may remain on the position where the trench TR1 is to be formed (see the dotted line in FIG. 9B). As shown in FIGS. 10 and 11, if the hard mask HM remains on the position where the trench TR1 is to be formed, a pillar-shaped portion PL may remain in the semiconductor substrate SUB after etching. The pillar-shaped portion PL extends upward from the bottom surface of the trench TR1. Not only particles remaining on the anti-reflective film BARC, but also abnormal growth of the polysilicon film HM2 and particles remaining on the upper surface F1 can cause the pillar-shaped portion PL to remain.

[0023] 10, in the semiconductor device DEV1a according to the comparative example in which the insulating film IF2 is not formed, if the columnar portion PL remains, the polysilicon wiring PW1 (gate electrode of the LDMOS transistor) may be electrically insulated from the semiconductor substrate SUB (columnar portion PL) only by the insulating film IF3 (gate insulating film of the LDMOS transistor). Furthermore, in the semiconductor device DEV1a, if the columnar portion PL remains, the thickness of the insulating film IF1 formed between the insulating film IF3 and the semiconductor substrate SUB (columnar portion PL) may be insufficient. Therefore, if the columnar portion PL remains, the electrical insulation between the polysilicon wiring PW1 and the semiconductor substrate SUB may become insufficient.

[0024] Such a lack of dielectric strength voltage between the polysilicon wiring PW1 and the semiconductor substrate SUB can usually be screened out by testing. However, when the columnar portion PL is located between the center position P and the second end TR1b of the trench TR1 in the first direction DR1, the electric field is relaxed near the columnar portion PL. Therefore, the insulating film IF3 located between the columnar portion PL and the polysilicon wiring PW1 and the thin insulating film IF1 located between the columnar portion PL and the polysilicon wiring PW1 may not be broken down and may not be screened out by testing.

[0025] As shown in FIG. 11 , in the semiconductor device DEV1, even when the columnar portion PL remains on the semiconductor substrate SUB, the semiconductor substrate SUB (columnar portion PL) and the polysilicon wiring PW1 are electrically insulated by at least the insulating films IF2 and IF3. Therefore, in the semiconductor device DEV1, even when the columnar portion PL remains, particularly when the columnar portion PL is located between the central position P and the second end TR1b, sufficient electrical insulation between the polysilicon wiring PW1 and the semiconductor substrate SUB can be ensured. Furthermore, in the semiconductor device DEV1, the insulating film IF2 is formed on the insulating film IF1 but is not formed between the insulating film IF3 and the upper surface F1 of the semiconductor substrate SUB. This prevents the gate insulating film of the LDMOS transistor from becoming thicker, and the threshold voltage of the LDMOS transistor from increasing with the formation of the insulating film IF2. The width W of the columnar portion PL in the first direction DR1 is, for example, 0.02 μm or less. The width W is measured at the top surface of the columnar portion PL.

[0026] <Modification> As shown in FIG. 12, in the semiconductor device DEV1, a trench TR2 may be formed in the upper surface F1 of the semiconductor substrate SUB. The trench TR2 extends toward the lower surface F2 of the semiconductor substrate SUB. The semiconductor device DEV1 may further include insulating films IF4, IF5, and IF6, and a polysilicon wiring PW2. The insulating films IF4, IF5, and IF6 are made of, for example, silicon oxide. The polysilicon wiring PW2 is made of, for example, polycrystalline silicon containing a dopant. The polysilicon wiring PW2 functions as, for example, a resistor element.

[0027] The insulating film IF4 is formed in the trench TR2. The insulating film IF5 is formed on the insulating film IF4, and the insulating film IF6 is formed on the insulating film IF5. The polysilicon wiring PW2 is formed on the insulating film IF6. Therefore, even if the columnar portion PL remains in the semiconductor substrate SUB, the polysilicon wiring PW2 and the semiconductor substrate SUB (columnar portion PL) are electrically insulated at least by the insulating films IF5 and IF6. As a result, sufficient electrical insulation is ensured between the polysilicon wiring PW2 and the semiconductor substrate SUB.

[0028] The trench TR2 and the insulating film IF4 are formed in the insulating film forming step S2 in the same manner as the trench TR1 and the insulating film IF1. The insulating film IF5 is formed in the insulating film forming step S3 and the insulating film removing step S5 in the same manner as the insulating film IF2. The insulating film IF6 is formed in the insulating film forming step S6 in the same manner as the insulating film IF3. The polysilicon wiring PW2 is formed in the polysilicon wiring forming step S7 in the same manner as the polysilicon wiring PW1.

[0029] (Second embodiment) A semiconductor device DEV2 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0030] <Configuration of semiconductor device DEV2> As shown in FIG. 13, in the semiconductor device DEV2, the insulating film IF1 has an upper surface F3 and a lower surface F4 located on the opposite side of the upper surface F3. A step RCS is formed on the upper surface F3. The step RCS is recessed toward the lower surface F4. In the semiconductor device DEV2, the insulating film IF2 is formed within the step RCS. Therefore, in the semiconductor device DEV2, when the columnar portion PL remains in the semiconductor substrate SUB, the semiconductor substrate SUB (columnar portion PL) and the polysilicon wiring PW1 are electrically insulated by the insulating films IF2 and IF3. In the semiconductor device DEV2, the insulating film IF2 is formed within the step RCS but is not formed on the insulating film IF1. Therefore, the insulating film IF3 has a portion that is not disposed between the insulating film IF3 and the insulating film IF1 and faces the insulating film IF1.

[0031] <Method of manufacturing semiconductor device DEV2> 14, in the insulating film formation step S3 in the manufacturing method of the semiconductor device DEV2, first, an insulating film IF2 is formed on the upper surface F1 so as to cover the insulating film IF1 by, for example, a plasma CVD method using TEOS. That is, the insulating film IF2 is formed inside the step RCS and outside the step RCS. The thickness T of the insulating film IF2 formed outside the step RCS is, for example, at least twice the width W of the columnar portion PL in the first direction DR1. Since the width of the step RCS in the first direction DR1 is approximately the same as the width W of the columnar portion PL in the first direction DR1, if the thickness T is at least twice the width W, the insulating film IF2 is integrated into the step RCS during conformal growth from the sidewall surface thereof, and the step RCS is thereby filled with the insulating film IF2.

[0032] 15, in an insulating film formation step S3 in the manufacturing method of the semiconductor device DEV2, secondly, the entire insulating film IF2 is wet-etched. As a result, the insulating film IF2 becomes thinner, and the insulating film IF2 formed on the insulating film IF1 is removed while the insulating film IF2 is left in the step RCS. As shown in FIG. 16, in an insulating film removal step S5 in the manufacturing method of the semiconductor device DEV2, the insulating film IF2 formed on the upper surface F1 is removed by dry etching through the openings in the resist pattern while the insulating film IF2 is left in the step RCS.

[0033] <Effects of semiconductor device DEV2> In the semiconductor device DEV2, the insulating film IF2 is formed in the step RCS, and therefore, even if the columnar portion PL remains, the polysilicon wiring PW1 and the semiconductor substrate SUB are electrically insulated at least by the insulating films IF2 and IF3. Therefore, according to the semiconductor device DEV2, even if the columnar portion PL remains, it is possible to sufficiently ensure electrical insulation between the polysilicon wiring PW1 and the semiconductor substrate SUB.

[0034] (Third embodiment) A semiconductor device DEV3 according to the third embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0035] <Configuration of semiconductor device DEV3> As shown in FIG. 17, the semiconductor device DEV3 does not have the insulating film IF2. In the semiconductor device DEV3, the insulating film IF3 is formed on the upper surface F1 located between the source layer SL and the trench TR1, and is also formed on the insulating film IF1. Therefore, the polysilicon wiring PW1 has a portion where the insulating film IF3 is not disposed between the polysilicon wiring PW1 and the insulating film IF1 and faces the insulating film IF1. Therefore, as shown in FIG. 18, when a columnar portion PL is formed in the semiconductor substrate SUB, the polysilicon wiring PW1 faces the semiconductor substrate SUB (columnar portion PL) without the insulating film IF3 interposed therebetween. That is, when a columnar portion PL is formed in the semiconductor substrate SUB, the polysilicon wiring PW1 is electrically connected to the semiconductor substrate SUB (columnar portion PL).

[0036] <Method of manufacturing semiconductor device DEV3> 19, the method for manufacturing the semiconductor device DEV3 does not perform the insulating film forming step S3 and the insulating film removing step S5. Therefore, as shown in Fig. 20, in the insulating film forming step S6 in the method for manufacturing the semiconductor device DEV3, the insulating film IF3 is formed on the upper surface F1 of the semiconductor substrate SUB and on the insulating film IF1. As shown in Fig. 19, the method for manufacturing the semiconductor device DEV3 further includes the insulating film removing step S9. The insulating film removing step S9 is performed after the insulating film forming step S6 and before the polysilicon wiring forming step S7.

[0037] 21, in the insulating film removing step S9, dry etching is performed through openings in a resist pattern formed on the insulating film IF1, thereby partially removing the insulating film IF3 formed on the insulating film IF1. Therefore, in the polysilicon wiring forming step S7 in the manufacturing method of the semiconductor device DEV3, a portion facing the insulating film IF3 and a portion facing the insulating film IF1 without the insulating film IF3 being disposed between the polysilicon wiring PW1 and the insulating film IF1 are formed, as shown in FIG.

[0038] <Effects of semiconductor device DEV3> In the semiconductor device DEV3, the insulating film IF2 is not formed, and the polysilicon wiring PW1 has a portion facing the insulating film IF1 without disposing the insulating film IF3 between the polysilicon wiring PW1 and the insulating film IF1. Therefore, in the semiconductor device DEV3, if a columnar portion PL remains in the semiconductor substrate SUB, a portion of the polysilicon wiring PW1 faces the semiconductor substrate SUB (columnar portion PL) without disposing the insulating film IF3 between the polysilicon wiring PW1 and the semiconductor substrate SUB (columnar portion PL). In other words, if a columnar portion PL remains in the semiconductor substrate SUB, the semiconductor substrate SUB (columnar portion PL) and the polysilicon wiring PW1 are electrically connected. Therefore, by performing a test to confirm whether there is conduction between the polysilicon wiring PW1 and the semiconductor substrate SUB, it is possible to screen the semiconductor device DEV3 in which the columnar portion PL remains in the semiconductor substrate SUB.

[0039] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0040] BARC anti-reflection film, BG back gate layer, BL body layer, DEV1 semiconductor device, DEV1a semiconductor device, DEV2 semiconductor device, DEV3 semiconductor device, DR1 first direction, DL drift layer, DRA drain layer, F1 top surface, F2 bottom surface, F3 top surface, F4 bottom surface, HM hard mask, HM1 silicon oxide film, HM2 polysilicon film, HM3 silicon nitride film, IF1, IF2, IF3, IF4, IF5, IF6 insulating film, P central position, PL pillar-shaped portion, PW1 polysilicon wiring, PW2 polysilicon wiring, RCS step, RP resist pattern, S1 preparation step, S2 insulating film formation step, S3 insulating film formation step, S4 ion implantation step, S5 insulating film removal step, S6 insulating film formation step, S7 polysilicon wiring formation step, S8 ion implantation step, S9 insulating film removal step, SL source layer, SUB Semiconductor substrate, T thickness, TR1, TR2 trench, TR1a first end, TR1b second end, W width.

Claims

1. a semiconductor substrate; a first insulating film; A second insulating film; A third insulating film; and polysilicon wiring. the semiconductor substrate has a first upper surface and a first lower surface located opposite the first upper surface; the first upper surface has a trench extending toward the first lower surface; the first insulating film is formed in the trench, the third insulating film is formed above the first insulating film so as to cover an upper surface of the second insulating film, the polysilicon wiring is formed on the third insulating film and is electrically insulated from the semiconductor substrate by at least the second insulating film and the third insulating film.

2. The semiconductor substrate is a source layer formed in the semiconductor substrate and disposed on the first top surface; a drain layer formed in the semiconductor substrate, spaced apart from the source layer, and disposed on the first upper surface; and the trench is located between the source layer and the drain layer, the second insulating film is formed on the first insulating film, 2. The semiconductor device according to claim 1, wherein said third insulating film is formed on said first upper surface located between said source layer and said trench, and is also formed on said second insulating film.

3. the semiconductor substrate has a pillar-shaped portion extending upward from a bottom surface of the trench, 3. The semiconductor device according to claim 2, wherein said polysilicon wiring faces said columnar portion with at least said second insulating film and said third insulating film interposed therebetween.

4. 3. The semiconductor device according to claim 2, wherein said second insulating film is formed on said first insulating film, but is not formed between said third insulating film and said first upper surface.

5. the trench has a first end facing the drain layer and a second end facing the source layer in a first direction in which the source layer and the drain layer are aligned, The semiconductor device according to claim 3 , wherein the columnar portion is located between a center of the trench and the second end in the first direction.

6. The semiconductor substrate is a source layer formed in the semiconductor substrate and disposed on the first top surface; a drain layer formed in the semiconductor substrate, spaced apart from the source layer, and disposed on the first upper surface; and the trench is located between the source layer and the drain layer, the semiconductor substrate has a pillar-shaped portion extending upward from a bottom surface of the trench, the first insulating film has a second upper surface and a second lower surface located on the opposite side of the second upper surface; the second upper surface has a step recessed toward the second lower surface so as to overlap the columnar portion in a plan view, the second insulating film is formed within the step, 2. The semiconductor device according to claim 1, wherein said third insulating film is formed on said first upper surface located between said source layer and said trench, and is also formed on said first insulating film and said second insulating film.

7. the trench has a first end facing the drain layer and a second end facing the source layer in a first direction in which the source layer and the drain layer are aligned, The semiconductor device according to claim 6 , wherein the columnar portion is located between a center of the trench and the second end in the first direction.

8. a semiconductor substrate; a first insulating film; A third insulating film; and polysilicon wiring. the semiconductor substrate has a first upper surface and a first lower surface located opposite the first upper surface; the first upper surface has a trench extending toward the first lower surface; the first insulating film is formed in the trench, the third insulating film is formed on the first insulating film, The polysilicon wiring is formed on the first insulating film and the third insulating film.

9. The semiconductor substrate is a source layer formed in the semiconductor substrate and disposed on the first top surface; a drain layer formed in the semiconductor substrate, spaced apart from the source layer, and disposed on the first upper surface; and the trench is located between the source layer and the drain layer, 9. The semiconductor device according to claim 8, wherein said third insulating film is formed on said first upper surface located between said source layer and said trench, and is also formed on said first insulating film.

10. the semiconductor substrate has a pillar-shaped portion extending upward from a bottom surface of the trench, 10. The semiconductor device according to claim 9, wherein said polysilicon wiring faces said pillar-shaped portion without said third insulating film being disposed between said polysilicon wiring and said pillar-shaped portion.

11. the trench has a first end facing the drain layer and a second end facing the source layer in a first direction in which the source layer and the drain layer are aligned, The semiconductor device according to claim 10 , wherein the columnar portion is located between a center of the trench and the second end in the first direction.

12. providing a semiconductor substrate having a first upper surface and a first lower surface opposite the first upper surface; forming a trench in the first top surface; forming a first insulating film in the trench; forming a second insulating film; forming a third insulating film above the first insulating film so as to cover an upper surface of the second insulating film; and forming a polysilicon wiring on the third insulating film.

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein in the step of forming the second insulating film, the second insulating film is formed on the first insulating film.

14. After the step of forming the trench, a pillar-shaped portion extending upward from a bottom surface of the trench remains in the semiconductor substrate, 14. The method for manufacturing a semiconductor device according to claim 13, wherein in the step of forming a polysilicon wiring, the polysilicon wiring is formed so as to face the columnar portion with at least the second insulating film and the third insulating film interposed therebetween.

15. forming a source layer and a drain layer in the semiconductor substrate; the source layer and the drain layer are disposed on the first upper surface so as to be spaced apart from each other, the trench is located between the source layer and the drain layer, the trench has a first end facing the drain layer and a second end facing the source layer in a first direction in which the source layer and the drain layer are aligned, The method for manufacturing a semiconductor device according to claim 14 , wherein the columnar portion is located between a center of the trench and the second end in the first direction.

16. 14. The method for manufacturing a semiconductor device according to claim 13, wherein in the step of forming the second insulating film, the second insulating film is partially removed so as not to be formed between the third insulating film and the first upper surface.

17. the first insulating film has a second upper surface and a second lower surface located on the opposite side of the second upper surface; the second upper surface has a step recessed toward the second lower surface, 13. The method for manufacturing a semiconductor device according to claim 12, wherein in the step of forming the second insulating film, the second insulating film is formed by forming the second insulating film within the step and outside the step, and then removing the second insulating film formed outside the step.

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the thickness of said second insulating film formed outside said step is at least twice the width of said step.

19. After the step of forming the trench, a pillar-shaped portion extending upward from a bottom surface of the trench remains in the semiconductor substrate, In the step of forming the polysilicon wiring, the polysilicon wiring is formed so as to face the columnar portion with at least the second insulating film and the third insulating film interposed therebetween; The method for manufacturing a semiconductor device according to claim 17 , wherein the step overlaps with the columnar portion in a plan view.

20. forming a source layer and a drain layer in the semiconductor substrate; the source layer and the drain layer are disposed on the first upper surface so as to be spaced apart from each other, the trench is located between the source layer and the drain layer, the trench has a first end facing the drain layer and a second end facing the source layer in a first direction in which the source layer and the drain layer are aligned, 20. The method for manufacturing a semiconductor device according to claim 19, wherein the columnar portion is located between a center of the trench and the second end in the first direction.

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