Semiconductor device, dc / dc converter, and ldo regulator

Abstract

To output a safe output voltage even when the operation of a control circuit becomes unstable.SOLUTION: The open detection circuit (40) includes a first resistor (41) connected to the second power source node (PN21) and the second ground node (PN22), and a source connected to the second power source node (PN21) or the first ground node (PN12), the open detection circuit (40) includes a detection MOS transistor (43, PN22) having a gate connected to the first resistor (41) and the second ground node (43A), and a second resistor connected to the second power node (PN21) or the first ground node (PN12) and to a drain of the detection MOS transistor (43, 43A), and outputs a voltage level at a connection point (43A) between the drain of the detection MOS transistor (43, P3) and the second resistor (42) as an open detection signal (S _ OP).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a DC / DC converter, and an LDO regulator. [Background technology]

[0002] Conventional power supply control devices have a ground terminal for the control circuit and a ground terminal for the output stage (power circuit) (see, for example, Patent Document 1). In order to suppress the effects of noise from the output stage, the ground terminal for the control circuit and the ground terminal for the output stage are each provided with independent wiring (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-183815

[0004] [overview] There is an increasing demand for power supply control devices to output a safe output voltage even when the ground terminal for the control circuit becomes open and the operation of the control circuit becomes unstable.

[0005] According to one aspect of the present disclosure, a semiconductor device includes a first power supply terminal connected to a first power supply configured to supply a first power supply voltage, a first ground terminal connected to a first ground, a second power supply terminal independent of the first power supply and connected to a second power supply configured to supply a second power supply voltage, a second ground terminal connected to a second ground independent of the first ground, and an open detection circuit configured to output an open detection signal indicating that the second ground and the second ground terminal are in an open state. The open detection circuit includes a first resistor connected to the second power supply terminal and the second ground terminal, a detection MOS transistor having a source connected to the second power supply terminal or the first ground terminal and a gate connected to the first resistor and the second ground terminal, and a second resistor connected to the second power supply terminal or the first ground terminal and connected to the drain of the detection MOS transistor. The open detection circuit is configured to output the open detection signal based on the voltage level of a connection point between the drain of the detection MOS transistor and the second resistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a DC / DC converter using a semiconductor device. [Figure 2] FIG. 2 is a timing chart showing the operation of the DC / DC converter. [Figure 3] FIG. 3 is a block diagram showing a state in which the second ground terminal of the semiconductor device is open. [Figure 4] FIG. 4 is a block diagram showing a schematic configuration of a semiconductor device according to a first modified example. [Figure 5] FIG. 5 is a block diagram showing a schematic configuration of an LDO regulator according to the second modification. [Figure 6] FIG. 6 is a timing chart showing the operating state of the LDO regulator. [Figure 7]FIG. 7 is a block diagram showing a schematic configuration of a semiconductor device according to the third modification. [Figure 8] FIG. 8 is a timing chart showing the operation state of the semiconductor device shown in FIG.

[0007] [Detailed explanation]

[0008] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. A MOS field effect transistor may also be simply referred to as a MOS transistor. A P-channel MOS transistor will be referred to as a PMOS transistor, and an N-channel MOS transistor will be referred to as an NMOS transistor.

[0009] When referring to multiple parts that form a circuit, such as any elements or lines, the term "connection" includes mechanical connection as well as electrical connection, i.e., a state in which electricity flows. In other words, "connect" includes "electrical connection."

[0010] <DC / DCコンバータ200> Fig. 1 is a block diagram showing a schematic configuration of a DC / DC converter 200 using a semiconductor device 100. As shown in Fig. 1, the DC / DC converter 200 includes the semiconductor device 100, an inductor L1, and a capacitor C1. The DC / DC converter 200 outputs an output voltage obtained by smoothing a switching voltage Vsw output from an output unit 50 (described later) of the semiconductor device 100 using the inductor L1 and the capacitor C1. Note that the DC / DC converter 200 of this embodiment is a step-down type that outputs an output voltage obtained by stepping down an input voltage (here, a first power supply voltage V1), but may also be a step-up type that outputs an output voltage obtained by stepping up an input voltage.

[0011] <Semiconductor device 100> As shown in FIG. 1, the semiconductor device 100 includes a first circuit section 10, a second circuit section 20, a level shift circuit 30, an open detection circuit 40, and an output section 50. The semiconductor device 100 is connected to a first power supply PVIN supplied with a first power supply voltage V1 and a second power supply AVIN supplied with a second power supply voltage V2. The first power supply voltage V1 is a power supply voltage for a power system that generates a switching voltage Vsw. The second power supply voltage V2 is a power supply voltage for a control circuit that drives a circuit that controls the semiconductor device 100, and is a voltage lower than the first power supply voltage V1.

[0012] The semiconductor device 100 has a circuit supplied with a first power supply voltage V1 and a circuit supplied with a second power supply voltage V2. The circuits connected to the first power supply PVIN (for example, the first circuit section 10, the output section 50) are connected to a first ground PGND, and the circuits connected to the second power supply AVIN (for example, the second circuit section 20) are connected to a second ground AGND.

[0013] <Output unit 50> 1, the output unit 50 is driven based on a drive signal S_SW from a signal processing circuit 11 (described later) of the first circuit unit 10. The output unit 50 has a high-side switching element 51 and a low-side switching element 52. In the semiconductor device 100 according to the present disclosure, the high-side switching element 51 is a PMOS transistor, and the low-side switching element 52 is an NMOS transistor. The output unit 50 is a circuit that constitutes an output stage, and is connected to a first power supply terminal PN11 connected to a first power supply PVIN and a first ground terminal PN12 connected to a first ground PGND.

[0014] The drain of the high-side switching element 51 and the drain of the low-side switching element 52 are connected together, thereby connecting them in series. The source of the high-side switching element 51 is connected to a first power supply terminal PN11 connected to a first power supply PVIN to which a first power supply voltage V1 is supplied. The source of the low-side switching element 52 is connected to a first ground terminal PN12 connected to a first ground PGND. The gates of the high-side switching element 51 and the low-side switching element 52 are connected together, and a drive signal S_SW is supplied from the signal processing circuit 11 of the first circuit section 10.

[0015] In the semiconductor device 100, the drive signal S_SW is a PWM (Pulse Width Modulation) signal. That is, the drive signal S_SW is a signal that switches between high and low voltage levels and can turn on or off the high-side switching element 51 and the low-side switching element 52.

[0016] In the output unit 50, when the drive signal S_SW is at a low level, the high-side switching element 51 is ON and the low-side switching element 52 is OFF. Also, when the drive signal S_SW is at a high level, the high-side switching element 51 is OFF and the low-side switching element 52 is ON. In this way, in the output unit 50, the high-side switching element 51 and the low-side switching element 52 operate so as to be switched ON or OFF in a complementary manner by the drive signal S_SW. Note that "complementary" refers to an operation in which one is ON and the other is OFF, but this may also include a dead time, which is a period during which they are both OFF at the same time.

[0017] A first connection point P1 between the drain of the high-side switching element 51 and the drain of the low-side switching element 52 is connected to an output terminal PN4 provided in the semiconductor device 100. The voltage at the first connection point P1 is output to the outside from the output terminal PN4 as a switching voltage Vsw. An inductor L1 and a capacitor C1 are connected to the outside of the output terminal PN4.

[0018] In the output unit 50, the high-side switching element 51 is configured with a PMOS transistor, but is not limited to this and may be configured with an NMOS transistor. In such a configuration, the signal processing circuit 11 may output, as drive signals, gate signals to the high-side switching element 51 and the low-side switching element 52 so that both switching elements are turned ON / OFF complementarily.

[0019] <1st circuit section 10> In the semiconductor device 100, the first circuit section 10 has a signal processing circuit 11. An adjustment instruction signal P_OD (described later) is input to the signal processing circuit 11 of the first circuit section 10. The adjustment instruction signal P_OD is generated by adjusting an instruction signal A_OD output from a control circuit 21 (described later) of the second circuit section 20 using a level shift circuit 30. The signal processing circuit 11 generates a drive signal S_SW that drives a high-side switching element 51 and a low-side switching element 52 of the output section 50 in response to the adjustment instruction signal P_OD.

[0020] 1, an enable signal S_EN (described later) of the open detection circuit 40 is input to the signal processing circuit 11. The signal processing circuit 11 is configured to operate in response to the enable signal S_EN and an adjustment instruction signal P_OD. The signal processing circuit 11 of the first circuit unit 10 is configured to output a drive signal S_SW corresponding to the adjustment instruction signal P_OD when the enable signal S_EN is at a high level, and to output the drive signal S_SW that stops the output of the switching voltage Vsw from the output unit 50 when the enable signal S_EN is at a low level.

[0021] The source of the high-side switching element 51 of the output section 50 is connected to a first power supply PVIN and is supplied with a first power supply voltage V1. The high-side switching element 51 is controlled to be turned on or off by the voltage at its gate. The voltage at the gate is determined by the voltage level of the drive signal S_SW. The signal processing circuit 11 that generates the drive signal S_SW is connected to a first power supply terminal PN11 and is supplied with the first power supply voltage V1. Note that circuits other than the signal processing circuit 11 are also arranged in the first circuit section 10.

[0022] In the semiconductor device 100, the area where the first circuit unit 10 is arranged is designed to have more space than the area where the second circuit unit 20 is arranged. Therefore, in the semiconductor device 100, the area where the first circuit unit 10 is arranged also has a plurality of first power supply terminals PN11 connected to a first power supply PVIN and a plurality of first ground terminals PN12 connected to a first ground PGND arranged therein.

[0023] Inside the semiconductor device 100, the first circuit section 10 is connected to a plurality of first power supply terminals PN11 connected to a first power supply PVIN. Also, inside the semiconductor device 100, the first circuit section 10 is connected to a plurality of first ground terminals PN12 connected to a first ground PGND. Then, inside the semiconductor device 100, a plurality of wirings connected to the first power supply PVIN are connected to each other. Also, inside the semiconductor device 100, a plurality of wirings connected to the first ground PGND are connected to each other.

[0024] A larger current is supplied to the first circuit section 10 and the output section 50 than to the second circuit section 20. By providing a configuration in which a plurality of first power supply terminals PN11 and a plurality of first ground terminals PN12 are provided, current can flow more easily. Furthermore, by connecting a portion of the first power supply terminals PN11 and a portion of the first ground terminals PN12 to the first power supply PVIN and the first ground PGND, respectively, voltage and current are supplied normally to the first circuit section 10, enabling stable operation.

[0025] <Second circuit section 20> In the semiconductor device 100, the second circuit unit 20 includes a control circuit 21 used for controlling elements, etc. The control circuit 21 is connected to an input terminal PN3 that is connected to an external device. An input signal AIN from the external device is supplied to the control circuit 21 via the input terminal PN3. The input signal AIN includes information about a target value of the output voltage VOUT output from the DC / DC converter 200. The control circuit 21 outputs an instruction signal A_OD for notifying the target output voltage based on the input signal AIN from the outside.

[0026] The second circuit unit 20 is configured to perform internal control, arithmetic processing, etc. of the semiconductor device 100. In the second circuit unit 20, if the resistance increases due to longer wiring, it is undesirable as it can cause signal delays and attenuation. For this reason, the second circuit unit 20 is designed to have a circuit configuration with as short wiring as possible. For this reason, the semiconductor device 100 is configured to have one second power supply terminal PN21 connected to the second power supply AVIN and one second ground terminal PN22 connected to the second ground AGND.

[0027] Within the semiconductor device 100, the wiring connected to the second power supply AVIN of each circuit is internally grouped together and connected to the second power supply terminal PN21. Also, within the semiconductor device 100, the wiring connected to the second ground AGND of each circuit is internally grouped together and connected to the second ground terminal PN22. That is, the wiring connected to the second power supply AVIN is connected to the second power supply AVIN via the single second power supply terminal PN21. Similarly, the wiring connected to the second ground AGND is connected to the second power supply AVIN via the single second ground terminal PN22.

[0028] In the output section 50, switching noise may occur due to the switching operations of the high-side switching element 51 and the low-side switching element 52. The circuits, elements, etc. included in the second circuit section 20 are prone to malfunction due to such switching noise.

[0029] To prevent this switching noise from acting on the second circuit section 20 via the second ground terminal PN22, the second ground terminal PN22 and the wiring connected to the second ground terminal PN22 are independent of the first ground terminal PN12 and the first ground terminal PN12 in the semiconductor device 100. To explain further, the wiring connected to the first ground terminal PN12 and the wiring connected to the second ground terminal PN22 and the second ground terminal PN22 are arranged physically separated to an extent that they are not affected by the switching noise.

[0030] The first ground PGND and second ground AGND of the semiconductor device 100 are connected to a grounding part (not shown) that has the same ground voltage, such as the frame of the DC / DC converter 200. The first ground PGND and second ground AGND are arranged at a distance such that switching noise from the first ground PGND does not affect the second ground AGND.

[0031] <Level shift circuit 30> As described above, the voltage level of the second circuit section 20 is lower than the voltage level of the first circuit section 10. Therefore, the signal from the second circuit section 20 may not be accurately recognized by the first circuit section 10. For this reason, the semiconductor device 100 uses a level shift circuit 30 to convert the voltage level of the signal from the second circuit section 20 to the voltage level of the first circuit section 10, making it usable by the first circuit section 10. For example, the level shift circuit 30 adjusts the voltage level of the instruction signal A_OD output from the control circuit 21 to a voltage level corresponding to the signal processing circuit 11, and outputs an adjusted instruction signal P_OD. The level shift circuit 30 uses a known circuit, and a detailed description thereof will be omitted.

[0032] <Open detection circuit 40> As described above, the first circuit section 10 is connected to the first ground PGND via the multiple first ground terminals PN12. Therefore, even if some of the multiple first ground terminals PN12 are disconnected (open state), the remaining first ground terminals PN12 are connected to the first ground PGND (closed state), so the first circuit section 10, and particularly the signal processing circuit 11, can continue to operate using the ground voltage as a reference voltage.

[0033] On the other hand, in the semiconductor device 100, the second circuit unit 20 has one second ground terminal PN22 connected to the second ground AGND. Therefore, if the connection between the second ground terminal PN22 and the second ground AGND becomes open, the second circuit unit 20 is not connected to the ground, and the reference voltage of the second circuit unit 20 becomes undefined. Note that an undefined reference voltage refers to a state in which the reference voltage is undefined and can take any value.

[0034] As a result, the instruction signal A_OD and the adjustment instruction signal P_OD sent from the second circuit unit 20 to the first circuit unit 10 also become unstable. Therefore, the switching voltage Vsw output from the output unit 50 driven by the drive signal S_SW from the signal processing circuit 11 may have a waveform different from the instruction included in the input signal AIN. As a result, the output voltage VOUT of the DC / DC converter 200 may have a value different from the target value notified by the input signal AIN.

[0035] Therefore, the semiconductor device 100 includes an open circuit detection circuit 40 configured to detect an open circuit between the second ground terminal PN22 and the second ground AGND. As shown in FIG. 1, the open circuit detection circuit 40 includes a first resistor 41, a second resistor 42, a detection MOS transistor 43, and a level shift circuit 44.

[0036] In the open circuit detection circuit 40, a first terminal of a first resistor 41 is connected to the second power supply terminal PN21. A second terminal of the first resistor 41 is connected to the first ground terminal PN12 at a second connection point P2. The second terminal of the first resistor 41 is connected to the second ground terminal PN22. A first terminal of a second resistor 42 is connected to the drain of the PMOS transistor 43 at a third connection point P3. The second terminal of the second resistor 42 is connected to the first ground terminal PN12.

[0037] The detection MOS transistor 43 is a PMOS transistor. The source of the detection MOS transistor 43 is connected to the second power supply terminal PN21. The drain of the detection MOS transistor 43 is connected to a first terminal of the second resistor 42. The second terminal of the second resistor 42 is connected to the first ground terminal PN12. The gate of the detection MOS transistor 43 is connected to the second connection point P2. In other words, the gate of the detection MOS transistor 4343 is connected to the second terminal of the first resistor 41 and also to the second ground terminal PN22.

[0038] The voltage at the third connection point P3 is output as an open detection signal S_OP. The open detection signal S_OP is a signal that can take on a high level, which is a voltage level higher than the threshold, and a low level, which is a voltage level lower than the threshold. The open detection signal S_OP is adjusted by the level shift circuit 44 to a voltage level suitable for the signal processing circuit 11 of the first circuit unit 10, and an enable signal S_EN is output. The level shift circuit 44 has a similar configuration to the level shift circuit 30, so a detailed description thereof will be omitted.

[0039] The enable signal S_EN is a signal that can take a high level or a low level, similar to the open detection signal S_OP, although the voltage level is different.

[0040] <Operation of the semiconductor device 100> The operation of the semiconductor device 100 will be described with reference to the drawings. Fig. 2 is a timing chart showing the operation of the DC / DC converter 200. Fig. 3 is a block diagram showing a state in which the second ground terminal PN22 of the semiconductor device 100 is open.

[0041] In the following description, the semiconductor device 100 is in a state in which the second ground terminal PN22 is connected to the second ground AGND (closed state) until time T1 shown in Fig. 3, and the second ground terminal PN22 goes into an open state at time T1. The state of the semiconductor device 100 when the second ground terminal PN22 is in the closed state is referred to as a normal operating state, and the state of the semiconductor device 100 when the second ground terminal PN22 is in the open state is referred to as an abnormality occurring state. That is, Fig. 1 shows the semiconductor device 100 in normal operation, and Fig. 3 shows the semiconductor device 100 in a transfer operation state.

[0042] An input signal AIN requesting output of an output voltage VOUT is input from an external device to the DC / DC converter 200. The input signal AIN is input to a control circuit 21 of the second circuit unit 20, and the control circuit 21 generates an instruction signal A_OD including an instruction to the signal processing circuit 11 based on the input signal AIN. Furthermore, a level shift circuit 30 adjusts the voltage level of the instruction signal A_OD and outputs an adjustment instruction signal P_OD.

[0043] In the semiconductor device 100 in a normal state during normal operation, the gate voltage Vg applied to the gate of the detection MOS transistor 43 is at a low level, and the detection MOS transistor 43 is in an ON state. As a result, the voltage at the second connection point P2 becomes the second power supply voltage V2 from the second power supply AVIN, and a high-level open detection signal S_OP is output.

[0044] The voltage level of the open detection signal S_OP is adjusted by the level shift circuit 44 to generate a high-level enable signal S_EN, which is then supplied to the signal processing circuit 11 of the first circuit unit 10. When the high-level enable signal S_EN is input, the signal processing circuit 11 recognizes that the state is normal. Therefore, when the high-level enable signal S_EN is input, the signal processing circuit 11 outputs the drive signal S_SW, which is a PWM signal that determines the ON duty of the high-side switching element 51 of the output unit 50, based on the adjustment instruction signal P_OD.

[0045] The high-side switching element 51 and the low-side switching element 52 of the output unit 50 are switched ON / OFF based on the drive signal S_SW. As a result, the voltage at the first connection point P1 is output to the outside from the output terminal PN4 as a switching voltage Vsw. The switching voltage Vsw is smoothed by the inductor L1 and the capacitor C1 and supplied to an external device.

[0046] 3, assume that at time T1, the second ground terminal PN22 enters an open state, causing the semiconductor device 100 to enter an abnormal state. At this time, the gate voltage of the detection MOS transistor 43 of the open detection circuit 40 becomes the second power supply voltage V2 from the second power supply AVIN. As a result, the source-gate voltage becomes approximately "0," and the detection MOS transistor 43 enters an OFF state. The second connection point P2 of the open detection circuit 40 is connected to the first ground terminal PN12 via the second resistor 42. Therefore, the voltage at the second connection point P2 becomes the voltage level of the first ground PGND connected via the first ground terminal PN12. Therefore, the open detection signal S_OP is at the voltage level of the first ground PGND and is output as a low-level signal.

[0047] The enable signal S_EN, obtained by adjusting the voltage level of the open detection signal S_OP by the level shift circuit 44, is output as a low-level signal. When the low-level enable signal S_EN is input, the signal processing circuit 11 of the first circuit unit 10 outputs a drive signal S_SW that maintains the high-side switching element 51 of the output unit 50 in the OFF state, regardless of the state of the adjustment instruction signal. In the semiconductor device 100 of this embodiment, when the low-level enable signal S_EN is input, the signal processing circuit 11 outputs a high-level drive signal S_SW, in other words, a drive signal S_SW that is a PWM signal with a high duty of 100%. This allows the high-side switching element 51 of the output unit 50, to which the first power supply voltage V1 is supplied, to be switched OFF, thereby fixing the switching voltage Vsw at a low level. In other words, the switching voltage Vsw can be stopped.

[0048] As a result, even if the second ground terminal PN22 is in an open state, the DC / DC converter 200 can prevent excessive voltage, current, etc. from being output.

[0049] In the semiconductor device 100, the open detection circuit 40 fixes the open detection signal S_OP to the voltage level of the second power supply AVIN (second power supply voltage V2) when the second ground terminal PN22 is in a closed state, and fixes it to the voltage level of the first ground PGND when the second ground terminal PN22 is in an open state. When the second ground terminal PN22 is open, the enable signal S_EN from the open detection circuit 40 can stop the switching voltage Vsw from the output unit 50 (set to low level).

[0050] If the signal processing circuit 11 is configured to be able to determine whether the voltage level of the open detection signal S_OP is high or low, the level shift circuit 44 of the open detection circuit 40 may be omitted.

[0051] <First Modification> A semiconductor device 100A of a first modification will be described with reference to the drawings. FIG. 4 is a block diagram showing a schematic configuration of the semiconductor device 100A of the first modification. The semiconductor device 100A of the first modification has an open circuit detection circuit 40A that is different from the open circuit detection circuit 40 of the semiconductor device 100. Other than this, the semiconductor device 100A has the same configuration as the semiconductor device 100. Therefore, parts of the semiconductor device 100A that are substantially the same as those of the semiconductor device 100 are given the same reference numerals, and detailed descriptions of the same parts will be omitted. Note that in the semiconductor device 100A shown in FIG. 4, inductors and capacitors are not shown.

[0052] 4, the open detection circuit 40A differs from the open detection circuit 40 in that an NMOS transistor is used as the detection MOS transistor 43. Furthermore, the open detection circuit 40A differs from the open detection circuit 40 in the position of the second resistor 42A.

[0053] 4, the open circuit detection circuit 40A of the semiconductor device 100A includes a detection MOS transistor 43A. The gate of the detection MOS transistor 43A is connected to a second connection point P2 at which the second end of the first resistor 41 of the open circuit detection circuit 40A and the second ground terminal PN22 are connected.

[0054] In the open-circuit detection circuit 40A, the detection MOS transistor 43A is an NMOS transistor. In the open-circuit detection circuit 40A, a first end of a second resistor 42A is connected to a second power supply terminal PN21 that is connected to a second power supply AVIN. A second end of the second resistor 42A is connected to the drain of the detection MOS transistor 43A at a third connection point P3. A source of the detection MOS transistor 43A is connected to a second ground terminal PN22 that is connected to a second ground AGND. A voltage at the third connection point P3 is output to a level shift circuit 44 as an open-circuit detection signal S_OP.

[0055] In the open circuit detection circuit 40A configured as described above, when the second ground terminal PN22 is in a closed state, the gate voltage of the detection MOS transistor 43A becomes the voltage level of the second ground AGND, and the detection MOS transistor 43A is in an OFF state. Therefore, the voltage at the third connection point P3 is fixed to the voltage level of the second power supply AVIN, i.e., the second power supply voltage V2. In other words, when the second ground terminal PN22 is in a closed state, a high-level open circuit detection signal S_OP is output.

[0056] In the open circuit detection circuit 40A configured as described above, when the second ground terminal PN22 is in an open state, the gate voltage of the detection MOS transistor 43A becomes the voltage level of the second power supply AVIN, and the detection MOS transistor 43A is turned on. As a result, the voltage of the third connection point P3 is fixed to the voltage level of the first ground PGND. In other words, when the second ground terminal PN22 is in an open state, a low-level open circuit detection signal S_OP is output.

[0057] As described above, even when the semiconductor device 100A uses the open detection circuit 40A that uses the detection MOS transistor 43A, the open detection signal S_OP is output in the same manner as when the semiconductor device 100 uses the open detection circuit 40. Therefore, by performing the same operation as the semiconductor device 100, the semiconductor device 100A can stop the output from the output unit 50 when the second ground terminal PN22 is in an open state.

[0058] <Second Modification> A second modified example will be described with reference to the drawings. FIG. 5 is a block diagram showing a schematic configuration of an LDO regulator 300 of the second modified example. FIG. 6 is a timing chart showing the operating state of the LDO regulator 300. The circuit shown in FIG. 5 is an LDO (Low Drop Out) regulator 300, and the output unit 60 has a configuration different from that of the output unit of the DC / DC converter 200. Also, the drive signal S_SWB output from the signal processing circuit 11B of the first circuit unit 10B of the semiconductor device 100B is different from the drive signal S_SW of the signal processing circuit 11. In other respects, the LDO regulator 300 has the same configuration as the DC / DC converter 200. Therefore, parts of the LDO regulator 300 that are substantially the same as those of the DC / DC converter 200 are assigned the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0059] 5 is a circuit that receives a first power supply voltage V1 as an input voltage and outputs an output voltage VOUT that is lower than the input voltage V1. The LDO regulator 300 is configured to output an adjusted output voltage VOUT in response to a drive signal S_SWB supplied from the signal processing circuit 11B.

[0060] The output section 60 of the LDO regulator 300 includes an operational amplifier 61, a first voltage dividing resistor 62, a second voltage dividing resistor 63, and a reference voltage source 64. The operational amplifier 61 is connected to a first power supply terminal PN11 connected to a first power supply PVIN and is driven by a first power supply voltage V1. The output terminal of the operational amplifier 61 is connected to an output terminal PN4 and a first terminal of the first voltage dividing resistor 62. The second terminal of the first voltage dividing resistor 62 and the first terminal of the second voltage dividing resistor 63 are connected at a fourth connection point P4. The second voltage dividing resistor 63 is connected to a first ground terminal PN12 connected to a first ground PGND.

[0061] A reference voltage source 64 is connected to the non-inverting input terminal of the operational amplifier 61. As a result, the reference voltage VREF is supplied to the non-inverting input terminal of the operational amplifier 61. Furthermore, the voltage V4 at the fourth connection point P4 is supplied to the inverting input terminal of the operational amplifier 61. With this configuration, the output voltage VOUT is determined by the ratio of the first voltage dividing resistor 62 and the second voltage dividing resistor 63 and the reference voltage VREF. In FIG. 6, the output voltage VOUT is at a high level when being output in a normal state and at a low level when it is stopped.

[0062] In the output unit 60, at least one of the first voltage dividing resistor 62 and the second voltage dividing resistor 63 has a variable resistance value. The output voltage VOUT is variable by changing the ratio between the first voltage dividing resistor 62 and the second voltage dividing resistor 63. Here, it is assumed that the second voltage dividing resistor 63 has a variable resistance value. In addition, in the output unit 60, a switch 65 is provided between the reference voltage source 64 and the non-inverting input terminal of the operational amplifier 61. When the switch 65 is in an ON state, the output unit 60 outputs the output voltage VOUT, and when the switch 65 is in an OFF state, the output voltage VOUT can be stopped.

[0063] In the semiconductor device 100B, the drive signal S_SWB output from the signal processing circuit 11B is a signal including information for adjusting the second voltage dividing resistor 63 in accordance with the adjustment instruction signal P_OD. The output section 60 is configured to adjust the resistance value of the second voltage dividing resistor 63 in accordance with the ratio information included in the drive signal S_SWB.

[0064] In the semiconductor device 100B, an enable signal S_EN is input to the output unit 60. The switch 65 is controlled in response to the enable signal S_EN. As described above, when the second ground terminal PN22 is in a closed state, the enable signal S_EN is at a high level. Therefore, when the enable signal S_EN is at a high level, the switch 65 is in an ON state. This causes the output unit 60 to output the output voltage VOUT.

[0065] 6, assume that the second ground terminal PN22 enters an open state at time T2. The second ground terminal PN22 is closed until time T2. Therefore, a high-level enable signal S_EN is input to the output unit 60. This turns on the switch 65, and the reference voltage VREF is input to the non-inverting input terminal of the operational amplifier 61. As a result, the output unit 60 outputs a high-level output voltage VOUT to the outside via the output terminal PN4.

[0066] 6, when the second ground terminal PN22 enters an open state at time T2, the enable signal S_EN input to the output unit 60 switches to low level. This switches the switch 65 OFF, and the input to the non-inverting input terminal of the operational amplifier 61 becomes HI-Z. This stops the output from the operational amplifier. As a result, the output voltage VOUT output from the output unit 6 stops (switches to low level).

[0067] As described above, when the semiconductor device 100B is used in the LDO regulator 300, the output voltage VOUT is not output when the second ground terminal PN22 of the semiconductor device 100B is open, thereby preventing the output of an erroneous output voltage VOUT due to the operation of the internal circuit of the semiconductor device 100B.

[0068] In this modification, the LDO regulator 300 is configured such that an enable signal S_EN is input to the output unit 60 and the switch 65 is driven according to the level of the enable signal S_EN, but this is not limiting. For example, as shown in the semiconductor device 100B, the enable signal S_EN may be input to the signal processing circuit 11B, and the switch 65 may be driven by a drive signal S_SWB from the signal processing circuit 11B.

[0069] <Third Modification> The third modified example will be described with reference to the drawings. FIG. 7 is a block diagram showing a schematic configuration of a semiconductor device 100C of the third modified example. FIG. 8 is a timing chart showing the operating state of the semiconductor device 100C shown in FIG. 7. The semiconductor device 100C shown in FIG. 7 differs from the semiconductor device 100 in that a determination circuit 12 provided separately from the signal processing circuit 11 is provided in the first circuit unit 10C, and an enable signal S_EN is input to the determination circuit 12. In other respects, the semiconductor device 100C has the same configuration as the semiconductor device 100, and therefore, substantially the same parts are assigned the same reference numerals and detailed description of the same parts will be omitted.

[0070] The semiconductor device 100C has a determination circuit 12. The determination circuit 12 receives an enable signal S_EN output from the open detection circuit 40. The determination circuit 12 outputs a determination signal S_GN to the outside of the semiconductor device 100C in response to the enable signal S_EN. The determination signal S_GN is at a high level when the enable signal S_EN is at a high level, and is at a low level when the enable signal S_EN is at a low level.

[0071] 8, assume that the second ground terminal PN22, which is in a closed state, changes to an open state at time T3. As shown in FIG. 8, since the second ground terminal PN22 is in a closed state until time T3 is reached, a high-level enable signal S_EN is input to the decision circuit 12. Therefore, the decision circuit 12 outputs a high-level decision signal S_GN until time T3 is reached.

[0072] When the second ground terminal PN22 is opened at time T3, the enable signal S_EN input to the determination circuit 12 switches from high to low. This causes the determination circuit 12 to switch the determination signal S_GN to low (see FIG. 8). Note that the level of the determination signal S_GN indicating each state may be reversed. In the semiconductor device 100C, the determination signal S_GN is output to an external device via a connection terminal PN5 connected to the external device.

[0073] The external device recognizes that there is an abnormality in the semiconductor device 100C (here, the second ground terminal PN22 is open) based on the determination signal S_GN. Then, the external device determines that the voltage supplied from the DC / DC converter 200 provided in the semiconductor device 100C is not appropriate, and suspends processing.

[0074] In this modification, the enable signal S_EN is supplied to the determination circuit 12, but it may also be supplied to the signal processing circuit 11. When the second ground terminal PN22 is in an open state, the output from the output unit 50 may be stopped and the determination circuit 12 may output a determination signal S_GN indicating a fault. The determination circuit 12 may be provided in the LDO regulator 300 having the output unit 60.

[0075] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0076] <Additional Notes> The semiconductor device (100, 100A, 100B, 100C) described above includes a first power supply terminal (PN11) connected to a first power supply (PVIN) configured to supply a first power supply voltage (V1); a first ground terminal (PN12) configured to be connected to a first ground (PGND); a second power supply terminal (PN21) that is provided independently of the first power supply (PVIN) and is connected to a second power supply (AVIN) configured to supply a second power supply voltage (V2); a second ground terminal (PN22) configured to be connected to a second ground (AGND) provided independently of the first ground (PGND); an open detection circuit (40) configured to output an open detection signal (S_OP) that notifies that a second ground (AGND) and a second ground terminal (PN22) are in an open state; The open circuit detection circuit (40) a first resistor (41) connected to a second power supply terminal (PN21) and a second ground terminal (PN22); a detection MOS transistor (43, 43A) having a source connected to the second power supply terminal (PN21) or the first ground terminal (PN12) and a gate connected to the first resistor (41) and the second ground terminal (PN22); a second resistor connected to the second power supply terminal (PN21) or the first ground terminal (PN12) and connected to the drain of the detection MOS transistor (43, 43A); The open circuit detection circuit (40) is configured (first configuration) to output the voltage level of the connection point (P3) between the drain of the detection MOS transistor (43, 43A) and the second resistor (42) as an open circuit detection signal (S_OP).

[0077] In the semiconductor device (100, 100B, 100C) of the first configuration, the detection MOS transistor (43) is composed of a P-channel MOS transistor, The source of the detection MOS transistor (43) is connected to the second power supply terminal (PN12) (second configuration).

[0078] In the semiconductor device (100A, 100B, 100C) of the first configuration, the detection MOS transistor (43A) is composed of an N-channel MOS transistor, This is a configuration (third configuration) in which the source of the detection MOS transistor (43A) is connected to the second ground terminal (PN22).

[0079] In the semiconductor device (100C) having any one of the first to third configurations, a determination circuit (12) is connected to a first power supply terminal (PN11) and a first ground terminal (PN12), and configured to output a determination signal (S_GN) to the outside in response to an enable signal (S_EN) corresponding to an open detection signal (S_OP), The judgment circuit (12) is configured (fourth configuration) to output a judgment signal (S_GN) indicating a fault judgment to the outside when it receives an enable signal (S_EN) notifying that the second ground terminal (PN22) and the second ground (AGND) are in an open state.

[0080] In the semiconductor device (100, 100A, 100B, 100C) having any one of the first to fourth configurations, an output section (50, 60) connected to a first power supply terminal (PN11) and a first ground terminal (PN12) and configured to output an output voltage (Vsw, VOUT); a signal processing circuit (11, 11B) connected to a first power supply terminal (PN11) and a first ground terminal (PN12) and configured to supply drive signals (S_SW, S_SWB) for driving the output units (50, 60) to the output units (50, 60); An enable signal (S_EN) corresponding to the open detection signal (S_OP) is input to the signal processing circuit (11, 11B), The signal processing circuit (11, 11B) is configured (fifth configuration) to output drive signals (S_SW, S_SWB) that drive the output section (50, 60) to stop outputting the output voltage (Vsw, VOUT) when it receives an enable signal (S_EN) notifying that the second ground terminal (PN22) and the second ground (AGND) are in an open state.

[0081] The DC / DC converter (200) described above has a configuration including the semiconductor device (100, 100A, 100C) of the fifth configuration, and the output section (50) has a configuration (sixth configuration) including a high-side switching element (51) and a low-side switching element (52) connected in series with the high-side switching element (51).

[0082] The LDO regulator (300) described above has a configuration (seventh configuration) including the semiconductor device (100B) of the fifth configuration.

[0083] The LDO regulator (300) described above has a configuration including a semiconductor device (100B) having any one of the first to third configurations described above, The semiconductor device (100B) has an output section (60) that is connected to a first power supply terminal (PN11) and a first ground terminal (PN12) and that outputs an output voltage (VOUT), The output unit (60) is configured to receive an enable signal (S_EN) corresponding to the open detection signal (S_OP), This is a configuration (eighth configuration) that stops outputting the output voltage (VOUT) when an enable signal (S_EN) notifying that the second ground terminal (PN22) and the second ground (AGND) are in an open state is received. [Explanation of symbols]

[0084] 100, 100A, 100B, 100C Semiconductor device 200 DC / DC converter 300 LDO regulator (power supply circuit) 10, 10C 1st circuit section 11, 11B Signal processing circuit 12 Judgment circuit 20 2nd circuit section 21 Control circuit 30 Level shift circuit 40, 40A open circuit detection circuit 41 1st resistor 42, 42A 2nd resistor 43 Detector MOS transistor (PMOS transistor) 43A detection MOS transistor (NMOS transistor) 44 Level shift circuit 50 Output section 51 High-side switching element 52 Low-side switching element 60 Output section 61 Operational Amplifier 62 1st voltage dividing resistor 62 Second voltage dividing resistor 63 Second voltage dividing resistor 64 Reference Voltage Source 65 Switch C1 capacitor L1 inductor P1 First connection point P2 Second connection point P3 Third connection point P4 4th connection point PN11 1st power supply terminal PN12 First ground terminal PN21 2nd power supply terminal PN22 Second ground terminal PN3 input terminal PN4 output terminal AVIN 2nd power supply AGND Secondary Ground PVIN 1st power supply PGND Primary Ground AIN input signal A_OD instruction signal P_OD Adjustment instruction signal S_EN Enable signal S_GN judgment signal S_OP Open detection signal S_SW drive signal S_SWB drive signal V1 First power supply voltage V2 Second power supply voltage VOUT Output voltage VREF Reference voltage Vg Gate voltage Vsw Switching voltage

Claims

1. a first power supply terminal connected to a first power supply configured to supply a first power supply voltage; a first ground terminal configured to be connected to a first ground; a second power supply terminal that is provided independently of the first power supply and is connected to a second power supply configured to supply a second power supply voltage; a second ground terminal configured to be connected to a second ground provided independently of the first ground; an open detection circuit configured to output an open detection signal notifying that the second ground and the second ground terminal are in an open state; The open detection circuit a first resistor connected to the second power supply terminal and the second ground terminal; a detection MOS transistor having a source connected to the second power supply terminal or the first ground terminal and a gate connected to the first resistor and the second ground terminal; a second resistor connected to the second power supply terminal or the first ground terminal and to a drain of the detection MOS transistor; The semiconductor device is configured such that the open detection circuit outputs a voltage level at a connection point between the drain of the detection MOS transistor and the second resistor as the open detection signal.

2. the detection MOS transistor is a P-channel MOS transistor, 2. The semiconductor device according to claim 1, wherein the source of said detection MOS transistor is connected to said second power supply terminal.

3. the detection MOS transistor is an N-channel MOS transistor, 2. The semiconductor device according to claim 1, wherein the source of the detection MOS transistor is connected to the first ground terminal.

4. a determination circuit connected to the first power supply terminal and the first ground terminal, and configured to output a determination signal to an external device in response to an enable signal corresponding to the open detection signal; 2. The semiconductor device according to claim 1, wherein the determination circuit is configured to output a determination signal indicating a fault determination to an external device when the determination circuit receives the enable signal notifying that the second ground terminal and the second ground are in an open state.

5. an output section connected to the first power supply terminal and the first ground terminal and configured to output an output voltage; a signal processing circuit connected to the first power supply terminal and the first ground terminal and configured to supply a drive signal to the output unit, the drive signal driving the output unit; an enable signal corresponding to the open detection signal is input to the signal processing circuit; 5. The semiconductor device according to claim 1, wherein the signal processing circuit is configured to output a drive signal that drives the output section to stop outputting the output voltage when the enable signal notifies that the second ground terminal and the second ground are in an open state.

6. A configuration including the semiconductor device according to claim 5, The DC / DC converter has an output section including a high-side switching element and a low-side switching element connected in series with the high-side switching element.

7. An LDO regulator comprising the semiconductor device according to claim 5.

8. A configuration including the semiconductor device according to any one of claims 1 to 3, the semiconductor device has an output section connected to the first power supply terminal and the first ground terminal and configured to output an output voltage; the output unit is configured to receive an enable signal corresponding to the open detection signal; The LDO regulator is configured to stop outputting the output voltage when the enable signal notifying that the second ground terminal and the second ground are in an open state is received.

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