Data storage device and method for using multiple models to predict a read threshold

Abstract

To provide a data storage device and a method for avoiding an undesirable bit error rate or programming latency, improving throughput and service quality, and reducing power consumption in the data storage device.SOLUTION: The method starts with a multi-objective model and tracks performance. The default multi-objective model can be trained across multiple conditions / datasets including, for example, BOL / MOL / EOL, etc., with or without data retention. It is then determined whether the average bit error rate (BER) is greater than a threshold (TH), and if the average BER is greater than the threshold, the model trained under conditions similar to the current conditions is identified and the other model is fetched from memory (host memory buffer; HMB).SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] One of the main challenges posed by NAND process shrinking and three-dimensional stacking is maintaining process uniformity. In addition, data storage devices may need to support a wide range of operating conditions (such as different program / erase cycles, retention times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variations, the read threshold (RT) used to read a memory page in some data storage devices is not fixed and can vary significantly as a function of physical location and operating conditions, especially for less mature memory nodes. [Brief explanation of the drawings]

[0002] [Figure 1A] FIG. 2 is a block diagram of a data storage device according to an embodiment. [Figure 1B] FIG. 2 is a block diagram illustrating a storage module of one embodiment. [Figure 1C] FIG. 1 is a block diagram illustrating a hierarchical storage system of one embodiment. [Figure 2A] 1B is a block diagram illustrating components of a controller of the data storage device illustrated in FIG. 1A according to one embodiment. [Figure 2B] 1B is a block diagram illustrating components of the data storage device illustrated in FIG. 1A, according to one embodiment. [Figure 3] FIG. 2 is a block diagram of a host and a data storage device of one embodiment. [Figure 4] 1 is a flowchart of an embodiment of a method for using a multi-condition model as a default. [Figure 5] 1 is a flowchart of an embodiment method starting with an early life model and progressing through write / erase cycles. [Figure 6]1 is a graph of sigma versus failed bit count (FBC) for one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0003] The following embodiments generally relate to data storage devices and methods for using multiple models to predict a read threshold. In one embodiment, a data storage device is provided that includes a memory and one or more processors. The one or more processors are configured to: generate a read threshold using models trained under multiple conditions, individually or in combination, track parameters resulting from using the read threshold, read the memory; and, in response to the parameter's value exceeding a threshold, generate a new read threshold using a different model trained under conditions similar to the current conditions of the data storage device, and read the memory using the new read threshold.

[0004] In another embodiment, a method is provided for execution in a data storage device including a memory, the method including generating a first read threshold using a model trained under first conditions, tracking a number of program / erase cycles, selecting a different model trained under different conditions to generate a different read threshold in response to the number of program / erase cycles exceeding a threshold for a current condition of the data storage device, and reading the memory using the different read thresholds.

[0005] In yet another embodiment, a data storage device is provided, comprising: a memory; and means for generating a read threshold using a model trained under multiple conditions; and, responsive to a bit error rate or read latency value exceeding the threshold, generating a new read threshold using a different model trained under conditions similar to the current conditions of the data storage device; and reading the memory using the new read threshold.

[0006] Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the accompanying drawings.

[0007] Embodiment The following embodiments relate to data storage devices (DSDs). As used herein, "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, hybrid drives, etc. Details of exemplary DSDs are provided below.

[0008] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in FIGS. 1A-1C. Note that these are examples only and other implementations may be used. FIG. 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to FIG. 1A, the data storage device 100 in this example includes a controller 102 coupled to nonvolatile memory, which may be comprised of one or more nonvolatile memory dies 104. As used herein, the term die refers to a collection of nonvolatile memory cells and associated circuitry for managing the physical operation of those nonvolatile memory cells formed on a single semiconductor substrate. The controller 102 interfaces with a host system and sends command sequences for read, program, and erase operations to the nonvolatile memory dies 104. Also, as used herein, the phrases "communicating with" or "coupled with" can mean communicating / coupled directly or communicating / coupled indirectly through one or more components, which may or may not be shown or described herein. The communication / coupling may be wired or wireless.

[0009] The controller 102 (which may be a non-volatile memory controller (e.g., flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include one or more components, individually or in combination, configured to perform certain functions, including but not limited to, the functions described herein and illustrated in the flowcharts. For example, as shown in FIG. 2A , the controller 102 may include one or more processors 138, individually or in combination, configured to perform functions, including but not limited to, the functions described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-transitory memories 139 (e.g., random access memory (RAM) 116 or read-only memory (ROM) 118) internal to the controller 102 and / or external to the controller 102. As another example, one or more components may include circuits such as, but not limited to, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0010] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device having any suitable operating system. The non-volatile memory controller 102 can have a variety of functions in addition to the specific functions described herein. For example, the non-volatile memory controller can format the non-volatile memory to ensure that the memory is operating properly, map out bad non-volatile memory cells, and allocate spare cells to replace future failed cells. Some of the spare cells can be used to hold firmware (and / or other metadata used for housekeeping and tracking) to operate the non-volatile memory controller and implement other features. During operation, the host can communicate with the non-volatile memory controller when it needs to read data from or write data to the non-volatile memory. If the host provides a logical address where data is to be read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address within the non-volatile memory. The non-volatile memory controller may also perform various memory management functions such as, but not limited to, wear leveling (distributing writes to avoid wearing out particular blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid pages of data to a new block after a block becomes full so that the full block can be erased and reused).

[0011] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be programmable once, a few times, or many times. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or may use other memory cell level technologies now known or later developed. The memory cells may also be fabricated using two-dimensional or three-dimensional methods.

[0012] The interface between the controller 102 and the non-volatile memory die 104 may be any suitable flash interface, such as toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system, such as a secure digital (SD) or micro-secure digital (microSD) card. In another embodiment, the data storage device 100 may be part of an embedded data storage device.

[0013] 1A, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104, although the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in FIGS. 1B and 1C), two, four, eight, or more memory channels may exist between the controller and the memory device, depending on the capabilities of the controller. In any of the embodiments described herein, even when a single channel is shown in the drawings, there may be two or more channels between the controller and the memory die.

[0014] 1B illustrates a storage module 200 including multiple non-volatile data storage devices 100. Accordingly, the storage module 200 may include a storage controller 202 that interfaces with a host and a data storage device 204 including multiple data storage devices 100. The interface between the storage controller 202 and the data storage device 100 may be a bus interface such as a serial advanced technology attachment (SATA), a peripheral component interconnect express (PCIe) interface, a double-data-rate (DDR) interface, or a serial attached small scale compute interface (SAS / SCSI). The storage module 200, in one embodiment, may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM) such as those found in server PCs or portable computing devices such as laptop and tablet computers.

[0015] FIG. 1C is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes multiple storage controllers 202, each of which controls a respective data storage device 204. A host system 252 may access memory in the storage system 250 through a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in FIG. 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as those found in data centers or other locations where mass storage is needed.

[0016] Referring again to FIG. 2A , the controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls internal bus arbitration for the controller 102. The modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. While illustrated in FIG. 2A as being located separately from the controller 102, in other embodiments, one or both of the RAM 116 and the ROM 118 may be located within the controller 102. In still other embodiments, portions of the RAM 116 and the ROM 118 may be located both within and outside the controller 102.

[0017] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with a host or next-level storage controller. The choice of host interface 120 type may depend on the type of memory being used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0018] The back-end module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, that are sent to the non-volatile memory die 104. A redundant array of independent drives (RAID) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data being written to the memory device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 can be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110 .

[0019] Data storage device 100 also includes other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that may interface with controller 102. In alternative embodiments, one or more of physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components not required for controller 102.

[0020] FIG. 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in two-dimensional and / or three-dimensional configurations. The non-volatile memory die 104 also includes a data cache 156 that caches data and address decoders 148, 150. The peripheral circuitry 141 in this example includes a state machine 152 that provides status information to the controller 102. The peripheral circuitry 141 may also include one or more components, individually or in combination, configured to perform certain functions, including, but not limited to, the functions described and illustrated in the flowcharts herein. 2B, memory die 104 may include one or more processors 168 individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, stored in memory array 142, or stored external to memory die 104. As another example, the one or more components may include circuits such as, but not limited to, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0021] In addition to or instead of one or more processors 138 (or, more generally, components) in the controller 102 and one or more processors 168 (or, more generally, components) in the memory die 104, the data storage device 100 may include another set of one or more processors (or, more generally, components). Generally, one or more processors (or, more generally, components) in the data storage device 100, wherever they are located and however many there are, may be configured, individually or in combination, to perform various functions, including, but not limited to, the functions described herein and illustrated in the flowcharts. For example, one or more processors (or components) may be in the controller 102, the memory device 104, and / or elsewhere in the data storage device 100. Also, different functions may be performed using different processors (or components) or combinations of processors (or components). Furthermore, means for performing a function may be implemented using a controller that includes one or more components (e.g., the processors or other components described above).

[0022] Returning again to FIG. 2A , flash control layer 132 (referred to herein as flash translation layer (FTL)) handles flash errors and interfaces with the host. In particular, the FTL, which may be an algorithm in firmware, handles the internals of memory management and translates writes from the host into writes to memory 104. The FTL may be needed because memory 104 may have limited endurance, may only be written to multiple pages, and / or may not be written to unless erased as a block. The FTL understands these potential limitations of memory 104, which may be invisible to the host. Thus, the FTL attempts to translate writes from the host into writes to memory 104.

[0023] The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allocated cache memory. In this manner, the FTL translates logical block addresses ("LBA") from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (so that the FTL's data structures can be recovered in the event of a sudden power loss) and wear leveling (so that wear across memory blocks is uniform to prevent excessive wear in any one block that would result in a greater likelihood of failure).

[0024] Referring again to the drawings, FIG. 3 is a block diagram of a host 300 and a data storage device 100 in one embodiment. The host 300 may take any suitable form, including, but not limited to, a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. The host 300 (here, a computing device) in this embodiment comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in the one or more memories 340 configures the one or more processors 330 to perform the operations described herein as being performed by the host 300. Accordingly, actions performed by the host 300 may be referred to herein as being performed by an application (computer-readable program code) executing on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the data storage device's memory 104.

[0025] As mentioned above, one of the main challenges posed by NAND process shrinking and three-dimensional stacking is maintaining process uniformity. In addition, data storage devices may need to support a wide range of operating conditions (such as different program / erase cycles, retention times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variations, the read threshold (RT) used to read a memory page in some data storage devices is not fixed and can vary significantly as a function of physical location and operating conditions, especially for newer, less mature memory nodes.

[0026] Reads using an inaccurate read threshold can lead to a higher bit error rate (BER), which can degrade performance and quality of service (QoS) due to decoding failures, which may require invoking high-latency recovery flows that can cause delays and hiccups in performance. The challenge of maintaining an optimal read threshold can be particularly important for enterprise memory systems with very stringent quality of service requirements, as well as for mobile, internet of things (IoT), and automotive memory systems, where the required range of operating conditions is wide and the frequency of condition changes (e.g., temperature) can be high. This problem is even more difficult during the transition to newer, less mature memory nodes.

[0027] Current solutions for read threshold calibration, such as BER estimation scan (BES) and valley search (VS), are high-latency operations aimed at optimizing the read threshold for a particular word line, which is good for infrequent read recovery flows in the event of data decoding failure, but may not be suitable for frequent operations in the event of frequent read threshold changes. Therefore, to address this issue, flash memory systems can implement a read threshold management scheme that attempts to track read threshold changes in the background via a maintenance process to ensure that the appropriate read threshold is used when the host issues a read command.

[0028] One approach is to track read thresholds for groups of blocks that share the same conditions. More specifically, blocks that are written at approximately the same time and temperature are grouped into time and temperature (TT) groups. Read thresholds are tracked for each time-temperature group, typically taken for several representative word lines from the blocks in the group. When the host performs a read operation, the read threshold associated with the time-temperature group corresponding to the read block is used, and additional adaptation to the read threshold by the specific read word line is performed based on a pre-calibrated word line zoning table.

[0029] Some read threshold management schemes may not adequately track the read threshold under frequently changing conditions and high variation between memory pages. Various solutions to address this issue are possible. For example, U.S. Patent Application No. 17 / 838,481, filed June 13, 2022, which is incorporated herein by reference, describes a read threshold calibration method that applies a machine learning (ML) predictive model, specifically including a system and method for inferring optimal read thresholds from various available information, including time and temperature group information, temperature information, bit error rate (BER) information, program-erase count (PEC) information, and physical page location.

[0030] As another example, U.S. Patent Application Nos. 17 / 899,073, filed August 30, 2022, 18 / 220,363, filed July 11, 2023, and 18 / 242,061, filed September 5, 2023, which are incorporated herein by reference, describe methods that enable implementation of an inference engine for faster and more accurate acquisition of read thresholds. In one embodiment described therein, a binary tree model is used to efficiently store only a subset of relevant correction data. Furthermore, direct reads from memory are not required to perform threshold calibration, making it much faster than BES / VS-based calibration. The unique structure of the binary tree enables a fast, low-area, and low-power solution.

[0031] Furthermore, U.S. Patent Application No. 18 / 658,074, filed May 8, 2024, which is incorporated herein by reference, describes hardware implementations. Hardware implementations may impose severe limitations on the complexity of the implemented predictive models. Therefore, as described in the references of the above-mentioned patent application, efficient predictive model-based ensembles of symmetric trees may be used. However, while symmetric predictive tree models may be capable of describing complex nonlinear functions of input features, they may have the inherent drawback of being discrete (non-continuous). This characteristic of random forest models may limit their predictive accuracy, as they have only a finite number of potential output values. The impact of this limitation on model performance may increase as hardware requirements become more stringent.

[0032] As described above, read threshold selection can be a complex task that may be well suited to machine learning techniques. Therefore, an artificial intelligence-based read threshold (ART) mode can be used to replace legacy read threshold schemes. One implementation of ART is a multi-model inference engine that can infer from multiple different types of models in real time with high accuracy and minimal latency. Other partial implementations may include firmware derivatives of this approach.

[0033] Current approaches for building a prediction module that provides a read threshold include a one-load model. Because RAM allocation on hardware implementing an ART module for read threshold prediction may be limited, there is an inherent lack of RAM space to support all specified conditions and requirements. Furthermore, the dataset collected to train the ART model to provide optimal read levels can sample the feature space in a way that compromises its representation for different conditions. For example, one approach can include collecting databases from different conditions of the data storage device 100 (e.g., beginning of life (BOL)), middle of life (MOL), and end of life (EOL)). The generated model can be a compromise between these conditions (e.g., due to limited model RAM size and a limited focus on the dataset). Furthermore, it may be desirable to optimize the read threshold for all different operating points at once. However, there may be no clear criteria for an optimized operating point (i.e., the same threshold can fit both frequent low bit error rate (BER) cases (e.g., 0-2 sigma) as well as rare high BER cases (e.g., 4-5 sigma)).

[0034] Thus, read threshold prediction models may be limited by the allocated volatile memory (e.g., RAM) size and by the diverse datasets assumed to cover various device conditions and requirements. The performance of models aimed at optimizing read thresholds for certain conditions and / or for certain portions of a cell population (low / median / high sigma) can improve upon the performance achieved by compromise all-in-one models in conventional approaches. Furthermore, it is necessary to find a way to achieve this goal without increasing the RAM size allocated for the models and, consequently, the size and cost of dedicated hardware modules. That is, it may be beneficial to be able to use different read threshold prediction models, each focused on specific use cases, conditions, and requirements, without exceeding the allocated RAM size and cost budget.

[0035] In one embodiment, a multi-model system for flexible read threshold prediction is provided that is adapted to provide the best performance for specific conditions and / or requirements without increasing the amount of dedicated RAM. In this embodiment, multiple flavors of such predictive models are stored (e.g., in memory 104 of data storage device 100 or in a host memory such as a host memory buffer (HMB)), and controller 102 of data storage device 100 selects the model that is most appropriate for the current conditions and requirements. The selection can follow models trained under conditions (i.e., feature ranges / values) similar to the current conditions.

[0036] In one exemplary implementation, multiple predictive models for the read threshold are stored, with each model optimized for different conditions / operating points. The best model can be used depending on the current situation. Also, the model type most similar to the current conditions / operating point can be used as a preliminary step to replace the most appropriate model. (Similar conditions can refer to conditions closer to the current conditions than the conditions under which a given model was trained.) Additional optimizations can be used. For example, a host memory buffer (HMB) can be selectively used to accelerate the loading of such read threshold models. Also, different sized models can be used according to the current BER level and / or firmware requirements (e.g., as a "heroics" decoding step in case of decoding failure). Furthermore, opportunistic trials of different models can be used until improved BER results are seen. This feature can be applied when a predefined BER threshold and / or decoding latency is exceeded. In another example, after a period of time, the controller 102 can opportunistically replace a model to see if a better threshold can be achieved.

[0037] The following paragraphs illustrate an exemplary embodiment. In this example, the controller 102 selects one of the stored condition-specific lumped models. Such lumped models can, for example, follow one or more of the following criteria: P / E count → BOL / MOL / EOL lumped model, a model by time pool index, a model by read / write typical temperature (e.g., different server farms may operate at different base temperatures due to various requirements and limitations), and a model by sigma region (e.g., one model for frequent very low BER cases (e.g., 0 sigma to 50% cases), another model for medium BER cases (e.g., 2 sigma to 2% cases), another model for rare high BER events (e.g., 4 sigma to 0.003% or less samples), and a performance model for a reliability model (e.g., one model is used for all mainstream reads, while the second model is used for the first step of read error handling (REH)).

[0038] Referring again to the drawings, FIGS. 4 and 5 are flowcharts 400, 500 of methods for two exemplary implementations of these embodiments. Referring first to FIG. 4, FIG. 4 is a flowchart 400 for using a multi-condition model as a default. As shown in FIG. 4, the controller 102 starts with a general (e.g., multi-objective) model (410) and tracks performance (420). The default multi-objective model can be trained across multiple conditions / datasets, including, for example, BOL / MOL / EOL, with or without data retention. The model can be tuned, for example, to provide best results in the mid-BER range (e.g., two sigma points on a sigma plot). This can be thought of as an "all-in model" that is a compromise between all conditions and operating points. Performance can be tracked over a predefined period. The controller 102 then determines (430) whether the average bit error rate (BER) is greater than a threshold (TH). (In an alternative embodiment, instead of or in addition to tracking the BER, the average / maximum latency (or another condition indicative of a suboptimal read threshold) can be tracked.) If the average BER is not greater than the threshold, the method loops back to 420. However, if the average BER is greater than the threshold, the controller 102 identifies (440) a model trained under conditions similar to the current conditions (e.g., the most similar model). The controller 102 then fetches (450) another model from memory (here, a host memory buffer, although a different memory, such as memory 104 of the data storage device 100, could be used). Use of the new model should reduce the BER.

[0039] 5, the method starts with a beginning-of-life (BOL) model (510) and counts write / erase (W / E) cycles (520). The controller 102 determines whether the number of W / E cycles is greater than a current condition threshold (TH) (530). If so, the controller 102 fetches the next condition model from memory (540). The models can be updated in a predefined order (e.g., BOL, then MOL, then EOL).

[0040] Identifying the model type that is most similar to the current conditions / operating point can be done in any suitable way. For example, the controller 102 can keep a typical feature count / range for each model as a header (e.g., in a dedicated buffer) and calculate a similarity score between the current relevant features and the headers of all optional models. The controller 102 can then select the model with the highest similarity score. The relevant features can include, but are not limited to, read temperature, P / E cycles, DR quantization, and other physical conditions. For example, the similarity score can be calculated based on the number of program / erase cycles and / or read temperature (e.g., by a factor of 1). * (Current PE-Cycle - PE-Cycle of Model-i) + coefficient 2 * (Current Read-Temp-Model-i's Read-temp)

[0041] The controller 102 can also opportunistically attempt to apply multiple models and select the one that produces the lowest BER for the current data (and conditions). This option does not require maintaining metadata for the model, but may have overhead (and therefore may only be applied as a heroic decoding mode, or at idle times, or during periods of low workload).

[0042] The controller 102 can average the scores generated by the methods described in the above two paragraphs across multiple samples over a predefined period of time and select the best model when that time has passed.

[0043] Figure 6 shows the BER sigma plot distribution of predicted read thresholds when the model is calculated for a specific condition dataset (here, EOL) versus the predictions when the predictive model is adjusted for a general condition dataset (including BOL, MOL, and EOL). The figure shows the optimal BES-based read threshold, the reference, and two ART models for 12 trees. As can be seen from this graph, the ART outperforms the non-machine-trained reference, and using a dedicated model for the current condition provides superior results compared to the comprehensive model.

[0044] There are several advantages associated with these embodiments. For example, using a dedicated predictive model for read thresholds can provide improved thresholds that produce reduced BER without expanding hardware, cost, and computational resources (e.g., firmware overhead). Better read thresholds can translate into improved throughput, quality of service, and power consumption (e.g., shorter decoding duration), which can be very important for most product line storage device operations and can be critical to end-user requirements.

[0045] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0046] Memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity-switching storage element such as an antifuse, a phase-change material, and optionally a steering element such as a diode. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements that include charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0047] Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. As a non-limiting example, a NAND-configured flash memory device (NAND memory) typically includes memory elements connected in series. A NAND memory array may be configured so that the array is made up of multiple strings of memory, where a string is made up of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements may be configured in other ways.

[0048] The semiconductor memory elements located in and / or on the substrate may be arranged in two or three dimensions, such as in a two or three dimensional memory structure.

[0049] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., an xz-direction plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer on or in which a layer of memory elements is formed, or may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0050] The memory elements may be arranged in an ordered array, such as multiple rows and / or columns, in a single memory device level. However, the memory elements may be arranged in an irregular or non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0051] A three-dimensional memory array is one in which memory elements are arranged to occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional (i.e., x, y, and z directions, where the y direction is substantially perpendicular to the major surface of the substrate and the x and z directions are substantially parallel to the major surface of the substrate) structure.

[0052] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements within each column. The columns can be arranged in a two-dimensional configuration, e.g., in the xz plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also make up a three-dimensional memory array.

[0053] As a non-limiting example, in a three-dimensional NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned, in which some NAND strings contain memory elements within a single memory level and other strings contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0054] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers making up each memory device level of the array are typically formed on layers of the memory device level below the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or may have intervening layers between the memory device levels.

[0055] Again, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but the resulting memory array is not a monolithic three-dimensional memory array because the memory device levels are first formed on separate substrates. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0056] Associated circuitry is typically required for operation of and communication with the memory elements. As a non-limiting example, a memory device may have circuitry used to control and drive the memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0057] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described, but rather encompasses all relevant memory structures within the spirit and scope of the present invention as described herein and as understood by those skilled in the art.

[0058] The foregoing detailed description is intended to be understood as an illustration of selected forms that the invention can take, rather than as a definition of the invention. It is only the following claims, including all equivalents, that are intended to define the scope of the invention as claimed. Finally, it should be noted that any aspect of any of the embodiments described herein can be used alone or in combination with each other.

Claims

1. 1. A data storage device comprising: Memory and and one or more processors, said one or more processors individually or in combination: Using a model trained on multiple conditions to generate a readout threshold, tracking parameters resulting from using the read threshold to read the memory; In response to the value of the parameter exceeding a threshold value, generating a new read threshold using a different model trained under conditions similar to the current conditions of the data storage device; The data storage device is configured to read the memory using the new read threshold.

2. The data storage device of claim 1 , wherein the programming parameters include a bit error rate.

3. The data storage device of claim 1 , wherein the programming parameters include program latency, power consumption, failed bit count, syndrome weight values, and / or activation of a high decoding mode.

4. The data storage device of claim 1 , wherein the different model is selected from a plurality of different models, each of the plurality of different models being trained under different conditions.

5. The data storage device of claim 4 , wherein the plurality of different models are stored in the memory of the data storage device.

6. The data storage device of claim 4 , wherein the plurality of different models are stored in a host memory buffer within the host.

7. The data storage device of claim 4 , wherein the different model is selected from the plurality of different models because it has the highest condition similarity score among the plurality of different models.

8. The data storage device of claim 7 , wherein the similarity score is based on a read temperature.

9. The data storage device of claim 7 , wherein the similarity score is based on a number of program / erase cycles and / or a read temperature.

10. The data storage device of claim 7 , wherein the similarity score is based on a data-preserving quantization.

11. The data storage device of claim 1 , wherein the plurality of conditions includes at least two of an early life condition, a mid-life condition, and an end-of-life condition.

12. 10. The data storage device of claim 1, wherein the one or more processors are further configured, individually or in combination, to use different sized models for different values ​​of the parameters and / or to increase the size of the model according to a prior indication of a high bit error rate, a high failed bit count, and / or a program-erase cycle value.

13. The data storage device of claim 1 , wherein the one or more processors are further configured to use other models, individually or in combination, until the value of the parameter does not exceed the threshold.

14. The data storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to use a different model after a period of time.

15. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

16. 1. A method, in a data storage device comprising a memory, comprising: generating a first read threshold using the model trained under the first conditions; Tracking the number of program / erase cycles; in response to the number of program / erase cycles exceeding a threshold for the current condition of the data storage device; Selecting different models trained under different conditions to generate different readout thresholds; reading the memory using the different read thresholds.

17. The method of claim 16 , further comprising selecting the different models in a predefined order.

18. 20. The method of claim 17, wherein the different models in the predefined order include a model trained under early-life conditions, a model trained under mid-life conditions, and a model trained under end-of-life conditions.

19. The method of claim 17 , wherein the memory comprises a three-dimensional memory.

20. 1. A data storage device comprising: Memory and Using a model trained on multiple conditions to generate a readout threshold, generating a new read threshold value using a different model trained under conditions similar to the current conditions of the data storage device in response to a bit error rate or read latency value exceeding a threshold value; means for reading the memory using the new read threshold.

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