Fan-out type wafer level packaging unit
The FOWLP unit addresses high costs and environmental issues by forming conductive lines with metal paste and connecting dies from both sides, achieving lightweight, thin, and compact designs.
Patent Information
- Application Number
- JP2025114383
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-07-19
- Filing Date
- 2025-07-07
- Publication Date
- 2026-01-29
AI Technical Summary
Conventional FOWLP technologies face high manufacturing costs and environmental issues due to chemical plating techniques for conductive lines, and the challenge of electrically connecting dies to both sides of the encapsulation unit without increasing thickness.
A FOWLP unit with a substrate, dielectric layers, conductive pillars, and conductive lines formed by filling metal paste into recesses and polishing, allowing electrical connections through solder pads on both sides of the die area.
Reduces manufacturing costs, improves reliability, and achieves lightweight, thin, and compact design by electrically connecting dies from both sides without increasing thickness, meeting design needs for electronic products.
Smart Images
Figure 2026015245000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a sealing unit, and more particularly to a Fan-Out Wafer Level Packaging (FOWLP) unit. [Background technology]
[0002] Lightweight, thin, compact, highly efficient and reliable packaging technology is the trend of development in the semiconductor industry, among which FOWLP is a conventional packaging technology.
[0003] In the advanced packaging technology FOWLP, the redistribution layer (RDL) is the most important because the conductive lines in the RDL electrically extend and interconnect multiple die pads on the die in the XY plane, allowing for multiple solder pads to be more dispersed around the die, thereby more effectively improving the design space and reliability of each conductive line. However, in the RDL technology used in traditional FOWLP, the conductive lines are manufactured using chemical plating or electroplating techniques. This not only results in relatively higher material and manufacturing costs, but also makes the manufacturing process less environmentally friendly.
[0004] Another problem that needs to be solved is how to enable the die in the FOWLP unit to be electrically connected to the outside world on both sides of the encapsulation unit without increasing the overall thickness, in order to meet the design needs of the entire electronic product to be lighter, thinner, and smaller. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] Special Publication No. 2023-551401 Summary of the Invention [Problem to be solved by the invention]
[0006] A primary object of the present invention is to provide a FOWLP unit, which includes: The package includes a substrate, at least one die, a first dielectric layer, at least one conductive pillar, a second dielectric layer, a plurality of first conductive lines, a first outer protective layer, a third dielectric layer, a plurality of second conductive lines, and a second outer protective layer. The die can be electrically connected to the outside through at least one first solder pad disposed around the die area on the second surface of the die. The die can also be electrically connected to the outside through at least one second solder pad disposed in at least one opening in the second outer protective layer. The first and second conductive lines are fabricated by a technique of first filling a metal paste into a recess and then polishing it to form the conductive lines, thereby effectively solving the high manufacturing costs and environmental problems that often occur when forming conductive lines in conventional fan-out packaging technology. [Means for solving the problem]
[0007] To achieve the above object, the present invention provides a FOWLP unit, which includes a substrate, at least one die, a first dielectric layer, at least one conductive pillar, a second dielectric layer, a plurality of first conductive lines, a first outer protective layer, a third dielectric layer, a plurality of second conductive lines, and a second outer protective layer, wherein the substrate has a first surface and an opposing second surface, and at least one first through-hole penetrating the first surface and the second surface.
[0008] Each of the dies is separated from a single wafer, and each of the dies has a first surface and an opposing second surface, each of the first surfaces is fixed on the second surface of the substrate, each of the second surfaces has a plurality of die pads, and the vertical range of the chip on the second surface is defined as one die area.
[0009] The first dielectric layer is disposed on the second surface of the substrate and encapsulates the dies, and has at least one first recess extending horizontally and at least one second through-hole communicating with a corresponding one of the first through-holes.
[0010] The conductive pillars are formed in the first through holes and the second through holes and are exposed to the outside from the first through holes and the second through holes. The second dielectric layer is formed on the first dielectric layer and has a plurality of second recesses extending horizontally. Each of the first recesses is exposed to the outside from each of the second recesses. Each of the conductive pillars is exposed to the outside from each of the second recesses.
[0011] Each of the first conductive lines is formed by filling a metal paste into each of the first recesses and each of the second recesses, and each of the first conductive lines is electrically connected to each of the die pads and each of the conductive pillars of each of the dies, respectively.
[0012] The first outer protective layer is disposed on the second dielectric layer and each of the first conductive lines, and the first outer protective layer has a plurality of first openings, at least one of which is located around the die area on the second surface of the die, and each of the first conductive lines is exposed to the outside through each of the first openings, and each of the first openings forms a first solder pad.
[0013] The third dielectric layer is disposed on the first surface of the substrate, and has a plurality of third recesses extending horizontally, each of which communicates with one of the first through holes.
[0014] Each of the second conductive lines is formed by filling a metal paste in each of the third recesses, and each of the second conductive lines is electrically connected to each of the conductive pillars.
[0015] The second outer protective layer is disposed on the third dielectric layer, and the second outer protective layer has a plurality of second openings, and each of the second conductive lines is exposed to the outside through each of the second openings, and a second solder pad is formed in each of the second openings.
[0016] The die is electrically connected to the outside via the die pads, the first conductive lines, and the first solder pads around the die area located on the second surface of the die, thereby forming the FOWLP unit.
[0017] The die is electrically connected to the outside via the die pads, the first conductive lines, the conductive pillars, the second conductive lines, and the second solder pads in sequence.
[0018] The manufacturing method of the FOWLP unit includes the following steps:
[0019] Step S1: Provide a substrate, which has a first surface and an opposing second surface.
[0020] Step S2: A plurality of dies separated from at least one wafer are placed on the second surface of the substrate at intervals, each of the dies having a first surface and an opposite second surface, each of the first surfaces being fixed on the second surface of the substrate, each of the second surfaces having a plurality of die pads, and the vertical extent of the chip on the second surface being defined as a die area.
[0021] Step S3: Forming a plurality of first conductive lines on the second surface of each die using a technique of filling the recesses with a metal paste and then polishing it to form conductive lines. First, a first dielectric layer is laid on the second surface of the substrate and on each die. Next, a plurality of first recesses are horizontally formed on the first dielectric layer, a plurality of first through holes penetrating the substrate downward, and a plurality of second through holes penetrating the first dielectric layer downward (see FIG. 4). Furthermore, each die pad of each die can be exposed to the outside through each first recess, and each of the first through holes and each of the second through holes are connected. Next, a conductive pillar is formed in each of the first through holes and each of the second through holes that are connected to each other. Then, a second dielectric layer is laid on the first dielectric layer. Next, a plurality of second recesses are formed horizontally on the second dielectric layer, and a metal paste is filled into each of the first recesses and each of the second recesses until the thickness of the metal paste is higher than the surface of the second dielectric layer. Finally, the metal paste that is higher than the surface of the second dielectric layer is polished so that the surface of the metal paste is flush with the surface of the second dielectric layer, thereby forming a plurality of first conductive lines.
[0022] Step S4: Lay a first outer protective layer on the second dielectric layer.
[0023] Step S5: The first outer protective layer is formed with a plurality of first openings, at least one of which is formed around the die area on the second surface of the die, so that each of the first conductive lines can be exposed to the outside through each of the first openings, and a first solder pad is formed in each of the first openings.
[0024] Step S6: A plurality of second conductive lines are formed on the first surface of the substrate using a technique of filling the recesses with metal paste and then polishing it to form conductive lines. First, a third dielectric layer is laid on the first surface of the substrate. Next, a plurality of third recesses are horizontally formed on the third dielectric layer, and each of the conductive pillars of each of the first through holes can be exposed to the outside through each of the third recesses. Next, metal paste is filled into each of the third recesses, and the thickness of the metal paste is made higher than the surface of the third dielectric layer. Finally, the metal paste that has risen above the surface of the third dielectric layer is polished to make the surface of the metal paste flush with the surface of the third dielectric layer, thereby forming a plurality of second conductive lines.
[0025] Step S7: Lay a second outer protective layer on the third dielectric layer.
[0026] Step S8: The second outer protective layer is formed with a plurality of second openings, each of the second conductive lines can be exposed to the outside through the second opening, and a second solder pad is formed in each of the second openings.
[0027] Step S9: A dividing operation is carried out to divide and form a plurality of FOWLP units.
[0028] In one best embodiment of the present invention, the substrate includes a silicon substrate, a glass substrate or a ceramic substrate.
[0029] In one best embodiment of the present invention, the metal paste forming each of the first conductive lines and each of the second conductive lines includes silver paste, nano-silver paste, copper paste, or nano-copper paste.
[0030] In one best embodiment of the present invention, the first surface of each die is further attached to the substrate using a die attach film (DAF).
[0031] In one best embodiment of the present invention, a solder ball is further provided on each of the first openings, and each of the solder balls is electrically connected to each of the first solder pads in each of the first openings.
[0032] In one best embodiment of the present invention, the fan-out type wafer level packaging unit can be electrically connected and installed on a printed circuit board (PCB) through each of the solder balls.
[0033] In one best embodiment of the present invention, a solder ball is further provided on each of the second openings, and each of the solder balls is electrically connected to each of the second solder pads in each of the second openings.
[0034] In one best embodiment of the present invention, the FOWLP unit further comprises a plurality of electronic components, each of which can be electrically connected and disposed on the FOWLP unit via each of the solder balls. [Effects of the Invention]
[0035] Steps S3 and S6 in the method for fabricating the FOWLP unit of the present invention can be considered the main steps for forming the redistribution layer (RDL) of the FOWLP unit 1. Furthermore, steps S3 and S6 are both precise and easy to implement, which simplifies the process and achieves the specific effects of achieving a certain degree of lightness, thinness, and compactness, even when the conductive lines in the RDL are electrically extended and interconnected in the XY plane. This is particularly advantageous for reducing the thickness of the FOWLP unit, which not only reduces manufacturing costs but also effectively improves the use efficiency and reliability of the FOWLP unit. Furthermore, the conductive lines of the present invention are formed by filling recesses with metal paste and then polishing them to form conductive lines, which effectively solves the problems of high manufacturing costs and environmental issues. Furthermore, by providing each conductive pillar inside the FOWLP unit, each die in the FOWLP unit is electrically connected to the outside from both opposing sides of the FOWLP unit, so that the die in the FOWLP unit can be electrically connected to the outside from both opposing sides of the encapsulation unit without increasing the overall thickness, thereby meeting the design needs of the entire electronic product, such as light weight, thinness, and compactness. [Brief explanation of the drawings]
[0036] [Figure 1] FIG. 1 is a side cross-sectional view of an application example of a FOWLP unit of the present invention. [Figure 2] FIG. 2 is a cross-sectional side view of the substrate and die of the present invention. [Figure 3] 3 is a cross-sectional side view of a first dielectric layer disposed on the substrate of FIG. 2. FIG. [Figure 4] 4 is a side cross-sectional view of forming a first through-hole on the substrate of FIG. 3 and forming a second through-hole on the first dielectric layer. [Figure 5] 5 is a side cross-sectional view showing a state in which conductive pillars are installed in the first through-hole and the second through-hole of FIG. 4. FIG. [Figure 6] 6 is a side cross-sectional view of forming a first recess on the first dielectric layer of FIG. 5. FIG. [Figure 7] FIG. 7 is a side cross-sectional view of a second dielectric layer placed on the first dielectric layer of FIG. 6. [Figure 8] 8 is a side cross-sectional view showing filling of a metal paste into the first recess and the second recess of FIG. 7. FIG. [Figure 9] 9 is a side cross-sectional view showing the metal paste of FIG. 8 being polished to form first conductive lines. [Figure 10] 10 is a side cross-sectional view of a first outer protective layer placed on the first conductive line of FIG. 9. FIG. [Figure 11] 11 is a cross-sectional side view of the placement of a third dielectric layer over the substrate of FIG. 10. FIG. [Figure 12] 12 is a side cross-sectional view of filling a metal paste into the third recess of FIG. 11. FIG. [Figure 13] 13 is a side cross-sectional view showing the metal paste of FIG. 12 being polished to form second conductive wires. FIG. [Figure 14] 14 is a side cross-sectional view of a second outer protective layer placed on the second conductive line of FIG. 13. FIG. [Figure 15] 15 is a side cross-sectional view showing solder balls placed on the first opening and the second opening of FIG. 14, respectively. FIG. [Figure 16] FIG. 16 is a side cross-sectional view showing an electronic component placed on the solder balls of FIG. 15. DETAILED DESCRIPTION OF THE INVENTION [Example]
[0037] Referring to FIG. 1 , the present invention provides a fan-out wafer level packaging (FOWLP) unit 1, which includes a substrate 10, at least one die 20, a first dielectric layer 30, at least one conductive pillar 40, a second dielectric layer 50, a plurality of first conductive lines 60, a first outer protective layer 70, a third dielectric layer 80, a plurality of second conductive lines 90, and a second outer protective layer 100.
[0038] As shown in Fig. 2, the substrate 10 has a first surface 11 and an opposing second surface 12. As shown in Fig. 4, the substrate 10 has at least one first through-hole 13 penetrating the first surface 11 and the second surface 12. The substrate 10 may include a silicon substrate, a glass substrate, or a ceramic substrate.
[0039] As shown in FIG. 2, each die 20 is separated from a single wafer, and each die 20 has a first surface 21 and an opposing second surface 22. The first surface 21 of each die 20 is fixed on the second surface 12 of the substrate 10, and each die 20 has a plurality of die pads 23 on the second surface 22. The vertical extent of the chip on the second surface 22 is defined as a die area 1a.
[0040] The first dielectric layer 30 is disposed on the second surface 22 of the substrate 10 and encapsulates the dies 20. The first dielectric layer 30 has at least one first recess 31 (see FIG. 6) and at least one second through hole 32 (see FIG. 4) extending horizontally. As shown in FIG. 4, each of the second through holes 32 communicates with a corresponding one of the first through holes 13. The first through holes 13 and the second through holes 32 are further formed using silicon through-hole technology, which simplifies the manufacturing process and reduces the overall thickness of the packaging.
[0041] As shown in FIGS. 5 and 6, the conductive pillars 40 are formed in the first through holes 13 and the second through holes 32, and are exposed to the outside from the first through holes 13 and the second through holes 32.
[0042] 7, the second dielectric layer 50 is provided on the first dielectric layer 30, and the second dielectric layer 50 has a plurality of second recesses 51 extending horizontally. As shown in FIG. 7, each of the first recesses 31 is exposed to the outside through each of the second recesses 51. Each of the conductive pillars 40 is exposed to the outside through each of the second recesses 51.
[0043] As shown in FIG. 7, each of the first conductive lines 60 is formed by filling a metal paste 60a into each of the first recesses 31 and each of the second recesses 51, and each of the first conductive lines 60 is electrically connected to each of the die pads 23 and each of the conductive pillars 40 of each of the dies 20, respectively.
[0044] 10 , the first outer protective layer 70 is disposed on the second dielectric layer 50 and the first conductive lines 60, and the first outer protective layer 70 has a plurality of first openings 71, at least one of which is located around the die area 1a on the second surface 22 of the die 20. Each of the first conductive lines 60 is exposed to the outside through each of the first openings 71, and each of the first openings 71 forms a first solder pad 61.
[0045] 11 , the third dielectric layer 80 is disposed on the first surface of the substrate 10, and has a plurality of third recesses 81 extending horizontally. Each of the third recesses 81 communicates with each of the first through holes 13.
[0046] As shown in FIG. 13, each of the second conductive lines 90 is formed by filling a metal paste 90 a in each of the third recesses 81 , and each of the second conductive lines 90 is electrically connected to each of the conductive pillars 40 .
[0047] 14, the second outer protective layer 100 is disposed on the third dielectric layer 80, and the second outer protective layer 100 has a plurality of second openings 101. Each of the second conductive lines 90 is exposed to the outside through each of the second openings 101, and a second solder pad 91 is formed in each of the second openings 101.
[0048] 15 , the die 20 is electrically connected to the outside via the die pads 23, the first conductive lines 60, and the first solder pads 61 around the die area 1a located on the second surface 22 of the die 20, thereby forming the FOWLP unit 1. Thus, the die 20 is electrically connected to the outside via the die pads 23, the first conductive lines 60, the conductive pillars 40, the second conductive lines 90, and the second solder pads 61, respectively.
[0049] The manufacturing method of the FOWLP unit 1 includes the following steps:
[0050] Step S1: As shown in FIG. 2, a substrate 10 is provided, and the substrate 10 has a first surface 11 and an opposing second surface 12.
[0051] Step S2: As shown in Figure 2, a plurality of dies 20 separated from at least one wafer are placed at intervals on the second surface of the substrate 10. Each die 20 has a first surface 21 and an opposing second surface 22, the first surface 21 of each die 20 is fixed on the second surface 12 of the substrate 10, and the second surface 22 of each die 20 has a plurality of die pads 23, and the vertical extent of the chip on the second surface 22 is defined as a die area 1a.
[0052] Step S3: A plurality of first conductive lines 60 are formed on the second surface 22 of each die 20 using a technique of filling the recesses with a metal paste and then polishing it to form conductive lines. As shown in FIG. 3, a first dielectric layer 30 is first laid on the second surface 12 of the substrate 10 and on each die 20. Next, a plurality of first recesses 31 (see FIG. 6) are formed horizontally on the first dielectric layer 30, as well as first through holes 13 that penetrate the substrate 10 downward and a plurality of second through holes 32 (see FIG. 4) that penetrate the first dielectric layer 30 downward. Furthermore, each die pad 23 of each die 20 can be exposed to the outside through each first recess 31 (see FIG. 6), and each first through hole 13 and each second through hole 32 are connected (see FIG. 4). 5, a conductive pillar 40 is first formed in each of the first through holes 13 and each of the second through holes 32 that communicate with each other. Then, as shown in FIG. 7, a second dielectric layer 50 is laid on the first dielectric layer 30. Next, as shown in FIG. 7, a plurality of second recesses 51 are formed horizontally on the second dielectric layer 50. Then, as shown in FIG. 8, a metal paste 60a is filled into each of the first recesses 31 and each of the second recesses 51, and the thickness of the metal paste 60a is made higher than the surface of the second dielectric layer 50. Finally, as shown in FIG. 9, the metal paste 60a that is higher than the surface of the second dielectric layer 50 is polished so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50, thereby forming a plurality of first conductive lines 60.
[0053] Step S4: As shown in FIG. 10, a first outer protective layer 70 is laid on the second dielectric layer 50.
[0054] 10 , the first outer protective layer 70 is formed with a plurality of first openings 71, at least one of which is formed around the die area 1 a on the second surface 22 of the die 20, so that each of the first conductive lines 60 can be exposed to the outside through each of the first openings 71, and each of the first openings 71 has a first solder pad 61 formed therein.
[0055] Step S6: A plurality of second conductive lines 90 are formed on the first surface 11 of the substrate 10 using a technique of filling the recesses with metal paste and then polishing it to form conductive lines. First, as shown in FIG. 11 , a third dielectric layer 80 is laid on the first surface 11 of the substrate 10. Next, as shown in FIG. 11 , a plurality of third recesses 81 are formed horizontally on the third dielectric layer 80, and the conductive pillars 40 of each first through hole 13 can be exposed to the outside through each of the third recesses 81. Next, as shown in FIG. 12 , a metal paste 90a is filled into each of the third recesses 81, and the thickness of the metal paste 90a is made higher than the surface of the third dielectric layer 80. Finally, as shown in FIG. 13 , the metal paste 90a that is higher than the surface of the third dielectric layer 80 is polished so that the surface of the metal paste 90a is flush with the surface of the third dielectric layer 80, thereby forming a plurality of second conductive lines 90.
[0056] Step S7: As shown in FIG. 14, a second outer protective layer 100 is laid on the third dielectric layer 80.
[0057] Step S8: As shown in FIG. 14, the second outer protective layer 100 has a plurality of second openings 101 formed therein, through which the second conductive lines 90 can be exposed, and a second solder pad 91 is formed in each of the second openings 101.
[0058] Step S9: As shown in FIG. 1, a dividing operation is carried out to divide and form a plurality of FOWLP units 1.
[0059] 9 and 13, the metal paste 60a, 90a constituting each of the first conductive wires 60 and each of the second conductive wires 90 includes silver paste, nano silver paste, copper paste, or nano copper paste. The nano silver paste material has properties such as low cost, high conductivity, and low-temperature sintering.
[0060] As shown in FIG. 2, the first surface 21 of each die 20 is further attached to the substrate 10 using a die attach film (DAF) 110 .
[0061] Referring to FIG. 15, a solder ball 120 is further provided on each of the first openings 71 , and each of the solder balls 120 is electrically connected to each of the first solder pads 61 in each of the first openings 71 .
[0062] As shown in FIG. 1, the FOWLP unit 1 can be electrically connected and installed on a printed circuit board (PCB) 2 via the solder balls 120, which allows for a variety of product applications.
[0063] Referring to FIG. 15, a solder ball 120 is further provided on each of the second openings 101 , and each of the solder balls 120 is electrically connected to each of the second solder pads 91 in each of the second openings 101 .
[0064] Referring to Figures 1 and 16, the FOWLP unit 1 further includes a plurality of electronic components 3, each of which can be electrically connected and installed on the FOWLP unit 1 via each of the solder balls 120.
[0065] Comparing the FOWLP unit 1 of the present invention with the conventional FOWLP unit technology, it has the following advantages:
[0066] (1) Steps S3 and S6 in the manufacturing method of the FOWLP unit 1 of the present invention can be considered as the main steps for forming the redistribution layer (RDL) of the FOWLP unit 1. Because steps S3 and S6 are both easy to perform precisely, the process can be simplified. Even when the conductive lines in the RDL are electrically extended and interconnected in the XY plane, the specific effects of lightness, thinness, and compactness can be achieved to a certain extent. This is particularly advantageous for reducing the thickness of the FOWLP unit 1. Therefore, the present invention not only reduces manufacturing costs but also effectively improves the usage efficiency and reliability of the FOWLP unit 1.
[0067] (2) The present invention utilizes a technique in which the first conductive wires 60 and the second conductive wires 90 are formed by filling recesses with a metal paste and then polishing the metal paste to form conductive wires. This effectively solves the problems of higher manufacturing costs and environmental issues that tend to arise when manufacturing conductive wires in the conventional FOWLP unit 1 technology.
[0068] (3) The FOWLP unit 1 of the present invention has the conductive pillars 40 inside, so that the dies 20 in the FOWLP unit 1 are electrically connected to the outside from both opposing sides of the FOWLP unit 1. This allows the dies in the FOWLP unit 1 to be electrically connected to the outside from both opposing sides of the encapsulation unit without increasing the overall thickness, thereby satisfying the design needs of the entire electronic product, such as light weight, thinness, and compactness. [Explanation of symbols]
[0069] 1 Fan-out type wafer level packaging unit 1a Die Area 10 Substrate 11 Page 1 12 Side 2 13 First through hole 20 Die 21 Page 1 22 Side 2 23 Die pad 30 First dielectric layer 31 First Recess 32 Second through hole 40 Conductive Pillar 50 Second dielectric layer 51 Second Recess 60 First conductive wire 60a metal paste 61 First solder pad 70 1st outer protective layer 71 First Opening 80 Third dielectric layer 81 Third Recess 90 Second conductive wire 91 Second solder pad 100 Second outer protective layer 101 Second Opening 110 Die attach film 120 solder balls 2 Printed circuit board 3 Electronic original
Claims
1. a substrate, at least one die, a first dielectric layer, at least one conductive pillar, a second dielectric layer, a plurality of first conductive lines, a first outer protective layer, a third dielectric layer, a plurality of second conductive lines, and a second outer protective layer; the substrate has a first surface and an opposing second surface, and the substrate has at least one first through-hole penetrating the first surface and the second surface; Each die is separated from a single wafer, each die has a first surface and an opposing second surface, the first surface of each die is fixed on the second surface of the substrate, each die has a plurality of die pads on the second surface, and a vertical range of a chip on the second surface is defined as one die area; The first dielectric layer is disposed on the second surface of the substrate and encapsulates the dies, the first dielectric layer having at least one first recess extending horizontally and at least one second through hole, each second through hole communicating with a corresponding one of the first through holes; The conductive pillars are formed in the first through holes and the second through holes, and are exposed to the outside from the first through holes and the second through holes, the second dielectric layer is provided on the first dielectric layer, the second dielectric layer has a plurality of second recesses extending horizontally, each of the first recesses is exposed to the outside from each of the second recesses, and each of the conductive pillars is exposed to the outside from each of the second recesses; each of the first conductive lines is formed by filling a metal paste into each of the first recesses and each of the second recesses, and each of the first conductive lines is electrically connected to each of the die pads and each of the conductive pillars of each of the dies; the first outer protective layer is disposed on the second dielectric layer and each of the first conductive lines, the first outer protective layer having a plurality of first openings, at least one of which is located around the die area on the second surface of the die, each of the first conductive lines being exposed to the outside through each of the first openings, and each of the first openings forming a first solder pad; the third dielectric layer is disposed on the first surface of the substrate, and the third dielectric layer has a plurality of third recesses extending horizontally, each of the third recesses communicating with a corresponding one of the first through holes; Each of the second conductive lines is formed by filling a metal paste into each of the third recesses, and each of the second conductive lines is electrically connected to each of the conductive pillars; and the second outer protective layer is disposed on the third dielectric layer, the second outer protective layer has a plurality of second openings, each of the second conductive lines is exposed to the outside through each of the second openings, and a second solder pad is formed in each of the second openings; the die is electrically connected to the outside via the die pads, the first conductive lines, and the first solder pads around the die area located on the second surface of the die, thereby forming the FOWLP unit; the die is electrically connected to the outside via each of the die pads, each of the first conductive lines, each of the conductive pillars, each of the second conductive lines, and each of the second solder pads; The method for manufacturing the FOWLP unit includes the following steps: Step S1: Providing a substrate, the substrate having a first surface and an opposing second surface; Step S2: Place a plurality of dies separated from at least one wafer on the second surface of the substrate at intervals, each die having a first surface and an opposite second surface, the first surface of each die being fixed on the second surface of the substrate, each die having a plurality of die pads on the second surface, and defining a vertical range of the chip on the second surface as a die area; Step S3: forming a plurality of first conductive lines on the second surface of each of the dies by filling a metal paste into the recesses and then polishing it to form conductive lines; first laying a first dielectric layer on the second surface of the substrate and on each of the dies; then forming a plurality of first recesses horizontally on the first dielectric layer, first through holes downwardly penetrating the substrate, and a plurality of second through holes downwardly penetrating the first dielectric layer; furthermore, each of the die pads of each of the dies can be exposed to the outside through each of the first recesses, and each of the first through holes and each of the second through holes are connected; and First, a conductive pillar is formed in each of the first through holes and each of the second through holes that are connected to each other, then a second dielectric layer is laid on the first dielectric layer, then a plurality of second recesses are formed horizontally on the second dielectric layer, then a metal paste is filled into each of the first recesses and each of the second recesses, and the thickness of the metal paste is made higher than the surface of the second dielectric layer, finally, the metal paste that is higher than the surface of the second dielectric layer is polished so that the surface of the metal paste is flush with the surface of the second dielectric layer, thereby forming a plurality of first conductive lines; Step S4: Laying a first outer protective layer on the second dielectric layer; Step S5: forming a plurality of first openings in the first outer protective layer, at least one of which is formed around the die area on the second surface 22 of the die, so that each of the first conductive lines can be exposed to the outside through each of the first openings, and forming one first solder pad in each of the first openings; Step S6: forming a plurality of second conductive lines on the first surface of the substrate using a technique of filling the recesses with metal paste and then polishing it to form conductive lines, by first laying a third dielectric layer on the first surface of the substrate, then forming a plurality of third recesses horizontally on the third dielectric layer, and allowing the conductive pillars of the first through holes to be exposed to the outside through the third recesses, subsequently filling the third recesses with metal paste, and making the thickness of the metal paste higher than the surface of the third dielectric layer, finally polishing the metal paste that has become higher than the surface of the third dielectric layer, so that the surface of the metal paste is flush with the surface of the third dielectric layer, thereby forming a plurality of second conductive lines; Step S7: laying a second outer protective layer on the third dielectric layer; Step S8: forming a plurality of second openings in the second outer protective layer, each of the second conductive lines being exposed to the outside through the second openings, and forming a second solder pad in each of the second openings; and Step S9: A dividing operation is performed to divide and form a plurality of FOWLP units.
2. 2. The FOWLP unit according to claim 1, wherein the substrate comprises a silicon substrate, a glass substrate, or a ceramic substrate.
3. 2. The FOWLP unit according to claim 1, wherein the metal paste constituting each of the first conductive lines comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.
4. 2. The fan-type wafer-level packaging unit according to claim 1, wherein the metal paste constituting each of the second conductive lines comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.
5. 2. The FOWLP unit according to claim 1, wherein the first surface of each die is further attached to the substrate 10 using a die attach film (DAF).
6. 2. The FOWLP unit according to claim 1, further comprising a solder ball disposed above each of the first openings, each of the solder balls electrically connecting with each of the first solder pads in each of the first openings.
7. 7. The FOWLP unit according to claim 6, wherein the FOWLP unit can be electrically connected and installed on a printed circuit board (PCB) via each of the solder balls.
8. 2. The FOWLP unit according to claim 1, further comprising a solder ball disposed above each of the second openings, each of the solder balls electrically connecting with each of the second solder pads in each of the second openings.
9. 9. The FOWLP unit according to claim 8, further comprising a plurality of electronic components, each of which can be electrically connected and installed on the FOWLP unit via each of the solder balls.
Citation Information
Patent Citations
Low-Power Optical Input / Output Chiplets (TeraPHYe) for Ethernet Switches
JP2023551401A