Semiconductor device

Abstract

As the definition of a display device is increased, the number of pixels, the number of gate lines, and the number of signal lines are increased. When the number of gate lines and signal lines is increased, it is difficult to mount an IC chip including a driver circuit for driving the gate lines and the signal lines by bonding or the like, which causes a problem of an increase in manufacturing cost.SOLUTION: A pixel portion and a driver circuit for driving the pixel portion are provided over one substrate, and at least part of the driver circuit is formed using a thin film transistor sandwiched between gate electrodes. Manufacturing cost is reduced by providing a pixel portion and a driver circuit over the same substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are , amorphous silicon, and polycrystalline silicon. Thin film transistors using silicon have low field effect mobility, but are suitable for enlarging the area of ​​glass substrates. On the other hand, thin film transistors using polycrystalline silicon have a field effect mobility of Although it is expensive, it requires a crystallization process such as laser annealing, which is necessary for enlarging the area of ​​glass substrates. It has the characteristic that it does not necessarily adapt.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-G Thin film transistors were fabricated using a-Zn-O oxide semiconductors and used as switches for image display devices. Patent Documents 1 and 2 disclose techniques used in chip elements and the like. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-096055 Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors with a channel formation region in an oxide semiconductor are made of amorphous silicon. The oxide semiconductor film has a higher field effect mobility than the thin film transistors used in the previous study. Film formation is possible at temperatures below 300°C using methods such as sputtering, and polycrystalline silicon The manufacturing process is simpler than that of thin film transistors using SiO2.

[0006] Using such oxide semiconductors, thin film transistors can be formed on glass substrates, plastic substrates, etc. and displays such as liquid crystal displays, electroluminescent displays, or electronic paper. It is expected to be applied to display devices.

[0007] Furthermore, when the display area of ​​the display device is enlarged, the number of pixels increases, and the number of gate lines and signal lines also increases. In addition, as display devices become more highly precise, the number of pixels increases, and the number of gate lines and signal As the number of gate lines and signal lines increases, the number of drivers required to drive them also increases. It has become difficult to mount IC chips with operating circuits by bonding, etc., and manufacturing costs have risen. The number of cases increases.

[0008] Therefore, a thin film transistor using an oxide semiconductor is used for at least a part of the driving circuit that drives the pixel portion. One object is to reduce manufacturing costs by using transistors.

[0009] At least a part of the driving circuit that drives the pixel section is made of a thin film transistor that uses an oxide semiconductor. When using a thin film transistor, the thin film transistor must have high dynamic characteristics (on-state characteristics) and frequency characteristics (f The thin film transistor with high dynamic characteristics (ON characteristics) is required. It is another object of the present invention to provide a driver circuit that can be driven at high speed. [Means for solving the problem]

[0010] Gate electrodes are provided above and below the oxide semiconductor layer, improving the on-state characteristics and reliability of the thin film transistor. In addition, a gate electrode provided below the oxide semiconductor layer and a gate insulating film formed on the oxide semiconductor layer A source electrode layer or a drain electrode layer is formed between the source electrode layer and the drain electrode layer. At least a part of the drain electrode layer is provided with low-resistance oxide semiconductor layers above and below the source region or drain region. The source electrode layer and the drain electrode layer are formed as first electrodes on the upper and lower sides. the source region or the first drain region, and the second source region or the second drain region It is a sandwiched structure.

[0011] In addition, the threshold voltage can be controlled by controlling the gate voltage applied to the upper and lower gate electrodes. The upper and lower gate electrodes may be electrically connected to each other to have the same potential. The gate electrodes may be connected to separate wirings to have different potentials. For example, the threshold voltage may be set to zero. Alternatively, it can be made closer to zero, reducing the drive voltage and thereby reducing power consumption. In addition, the threshold voltage can be set to a positive value to function as an enhancement type transistor. In addition, the threshold voltage can be set negative to function as a depletion-type transistor. It can also be done as follows.

[0012] For example, a combination of enhancement and depletion type transistors An inverter circuit (hereinafter referred to as an EDMOS circuit) can be configured using this and used in a drive circuit. The drive circuit has at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above EDMOS circuit. It is preferable to use a thin film transistor that can pass a large amount of ON current for the layer. A recessed type transistor or a thin film transistor having gate electrodes above and below an oxide semiconductor layer A transistor is used.

[0013] Fabricating thin-film transistors with different structures on the same substrate without significantly increasing the number of processes For example, a drive circuit for high-speed operation can be provided with gate electrodes above and below the oxide semiconductor layer. The EDMOS circuit is constructed using thin film transistors with electrodes, and the pixel section is made of oxide semiconductor. A thin film transistor having a gate electrode only below the body layer may also be used.

[0014] If the threshold voltage of the n-channel TFT is positive, it is called an enhancement type transistor. When the threshold voltage of the n-channel TFT is negative, it is called a depletion-type transistor. This definition will be followed throughout the specification.

[0015] In addition, the material of the gate electrode provided above the oxide semiconductor layer is not particularly limited as long as it is a conductive film. Not specified, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), W, Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scandium The element selected from the group consisting of Sc, Cr, and Cr, or an alloy containing the above-mentioned elements as components, is used. The gate electrode is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. Cut.

[0016] In addition, the gate electrode provided above the oxide semiconductor layer is made of the same material as the pixel electrode (transparent For example, in the case of a transmission type display device, a transparent conductive film can be used. In the same process as the process of forming the pixel electrode electrically connected to the thin film transistor, The gate electrode can be formed above the semiconductor layer. Without increasing the number of gate electrodes, a thin-film transistor with gate electrodes above and below the oxide semiconductor layer can be formed. It can be achieved.

[0017] In addition, by providing a gate electrode above the oxide semiconductor layer, the signal In the bias-thermal stress test (hereinafter referred to as BT test) to check the reliability, The amount of change in the threshold voltage of the thin film transistor before and after the test can be reduced. That is, by providing a gate electrode above the oxide semiconductor layer, reliability can be improved. can.

[0018] In addition, an ohmic contact is required between the source electrode and the oxide semiconductor layer. It is desirable to reduce the contact resistance as much as possible. Ohmic contact with the conductor layer is required, and the contact resistance must be as low as possible. Therefore, it is desirable to reduce the amount of the gate insulating layer between the source electrode and the drain electrode, and between the gate insulating layer and the drain electrode. The oxide semiconductor layer is electrically connected to the source electrode and the drain electrode. By intentionally providing high concentration source and drain regions, ohmic contact is achieved. In this specification, the contacts function as source and drain regions. The low-resistance oxide semiconductor layer has n-type conductivity, + Also called a layer.

[0019] The invention disclosed in this specification has a configuration including a first gate electrode on an insulating surface; a first insulating layer above the first insulating layer; and a first source region or a first drain region above the first insulating layer. a source electrode or a drain electrode above the first source region or the first drain region; a second source region or a second drain region above the source electrode and the drain electrode; an oxide semiconductor layer over the second source region or the second drain region; a second insulating layer and a second gate electrode above the second insulating layer, and the oxide semiconductor layer is a first insulating layer formed on the first gate electrode and overlapping the first gate electrode; The first gate electrode is disposed between the source electrode and the drain electrode, and the second gate electrode is made of an oxide semiconductor. The semiconductor device is formed by overlying the first gate electrode and the second gate electrode.

[0020] The above configuration solves at least one of the above problems.

[0021] In the above structure, the width of the second gate electrode is wider than the width of the first gate electrode. In this way, a voltage can be applied to the entire oxide semiconductor layer from the second gate electrode.

[0022] Alternatively, in the above configuration, the width of the first gate electrode is narrower than the width of the second gate electrode. By doing so, the area overlapping with the source electrode or drain electrode is reduced, thereby reducing the parasitic capacitance. Furthermore, the width of the second gate electrode can be set to be equal to or smaller than the width between the source electrode and the drain electrode. By making the gap narrower than the gap, the parasitic capacitance is reduced by not overlapping with the source or drain electrodes. The amount may be further reduced.

[0023] The manufacturing method of the above structure is also characterized by the fact that the first gate electrode is formed on an insulating surface. a first insulating layer on the first gate electrode; a first insulating layer on the first insulating layer; forming a first source region or a first drain region, A source electrode or a drain electrode is formed on the gate region, and a A second source region or a second drain region is formed, and the first insulating layer, the second source region, After performing a plasma treatment on the second source region and the second drain region, forming an oxide semiconductor layer on the insulating region; forming a second insulating layer covering the oxide semiconductor layer; The method for manufacturing a semiconductor device includes forming a second gate electrode on the insulating layer. In this case, the second gate electrode is formed using the same material and the same mask as the pixel electrode. This allows the fabrication to be carried out without significantly increasing the number of steps.

[0024] In addition, another aspect of the present invention has a pixel section and a driving circuit, and the pixel section has at least a first oxide a first thin film transistor having an oxide semiconductor layer, and a driving circuit having at least a second oxide semiconductor layer; a second thin film transistor having a compound semiconductor layer and a third thin film transistor having a third oxide semiconductor layer; a third thin film transistor; and an EDMOS circuit having a third oxide a first gate electrode below the oxide semiconductor layer; and a second gate electrode above the third oxide semiconductor layer. and an electrode, and source regions are provided above and below at least a part of the third oxide semiconductor layer. A second gate electrode is disposed between the source electrode and the drain electrode having drain regions above and below it. The gate electrode is a semiconductor device that overlaps with the third oxide semiconductor layer and the first gate electrode.

[0025] In the above structure, the first thin film transistor in the pixel portion is electrically connected to the pixel electrode, By using the same material for the electrode as for the second gate electrode of the drive circuit, the number of processes can be reduced. It can be made.

[0026] In the above structure, the first thin film transistor in the pixel portion is electrically connected to the pixel electrode, The electrode is made of a material different from that of the second gate electrode of the driving circuit. For example, the pixel electrode is made of a transparent conductive film. By using an aluminum film as the second gate electrode, Resistance can be reduced.

[0027] In the above configuration, by setting the first gate electrode and the second gate electrode to the same potential, Since gate voltage can be applied from above and below the oxide semiconductor layer, the current The current that can be supplied can be increased.

[0028] In the above structure, the first gate electrode and the second gate electrode are set to different potentials. For example, by setting the threshold voltage to zero or close to zero and reducing the drive voltage, power consumption can be reduced. It is possible to reduce the force.

[0029] The third oxide semiconductor layer of the driver circuit overlaps with the first gate electrode via the first insulating layer. and overlaps with the second gate electrode via the second insulating layer, forming a so-called dual gate structure. It is made of

[0030] In addition to liquid crystal display devices, semiconductor devices having driver circuits include light emitting devices using light emitting elements. Examples include optical display devices and display devices that use electrophoretic display elements and are also called electronic paper. .

[0031] In this specification, the term "display device" refers to an image display device, a light-emitting device, or a light It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0032] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel In the element part, the gate electrode of a thin film transistor and the source wiring of another transistor, The gate electrode has a portion for electrically connecting the gate electrode or drain wiring.

[0033] In addition, thin film transistors are easily damaged by static electricity, so the gate line or source It is preferable to provide a protection circuit for protecting the driver circuit on the same substrate as the line. is preferably configured using a nonlinear element using an oxide semiconductor.

[0034] The oxide semiconductor used in this specification is InMO3(ZnO) m Thin (m>0) A thin film is formed, and a thin film transistor is fabricated using the thin film as the semiconductor layer. , Ga, Fe, Ni, Mn, and Co. For example, M can be Ga, or it can be Ga and Ni or Ga and Fe, etc. In addition, in the oxide semiconductor, the metal element M may be contained. In addition to the metal elements contained in the alloy, Fe, Ni and other transition metal elements, or the transition metal elements, may be contained as impurity elements. In this specification, this thin film is called In-Ga- It is also called a Zn-O based non-single crystal film.

[0035] In-Ga-Zn-O based non-single crystal film is formed by sputtering, and then heated at 200 to 500°C. Typically, heating was carried out at 300 to 400°C for 10 to 100 minutes. The crystalline structure of the a-Zn-O non-single crystal film is amorphous, as observed in the XRD analysis. do.

[0036] Oxide semiconductors, such as In-Ga-Zn-O non-single crystal films, have an energy gap ( Since the oxide semiconductor layer has a wide Eg, even if two gate electrodes are provided above and below the oxide semiconductor layer, The increase in current can be suppressed.

[0037] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, in this specification, specific names are not used as matters for identifying the invention. This does not indicate [Effects of the Invention]

[0038] Peripheral circuits such as gate line driver circuits or source line driver circuits, or pixel areas, are divided into two parts, one above the other. By forming a thin film transistor using an oxide semiconductor between the gate electrodes, Reduce manufacturing costs.

[0039] In the above-mentioned thin film transistor, a solenoid is disposed above and below the source electrode or the drain electrode. A low-resistance oxide semiconductor layer functioning as a source region or a drain region is formed. Therefore, the area where the side surface of the source electrode or drain electrode comes into contact with the oxide semiconductor layer is reduced. This makes it possible to increase the on-current of the thin film transistor. Between the source electrode and the drain electrode and the gate insulating layer, a layer having a higher carrier concentration than the oxide semiconductor layer is formed. By intentionally providing high source and drain regions, ohmic contacts can be achieved. A t can be formed. [Brief explanation of the drawings]

[0040] [Figure 1] 1A is a cross-sectional view showing an example of the display device of the first embodiment; FIG. 1B is a cross-sectional view showing another example of the display device of the first embodiment; FIG. 1C is a cross-sectional view showing another example of the display device of the first embodiment. [Figure 2] 1A is a cross-sectional view of a semiconductor device according to a second embodiment, FIG. 1B is an equivalent circuit diagram, and FIG. 1C is a top view. [Figure 3] FIG. 10 is a block diagram illustrating the entire display device of Embodiment 3. [Figure 4] 10A and 10B illustrate an arrangement of wirings, input terminals, and the like in a display device according to Embodiment 3. [Figure 5] FIG. 2 is a block diagram illustrating a configuration of a shift register circuit. [Figure 6] FIG. 1 is a diagram showing an example of a flip-flop circuit. [Figure 7] FIG. 1 is a diagram showing a layout diagram (top view) of a flip-flop circuit. [Figure 8] FIG. 4 is a timing chart for explaining the operation of the shift register circuit. [Figure 9] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 10] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 11] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 12] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 13] 10A to 10C illustrate a manufacturing method of a semiconductor device of Embodiment 4. [Figure 14]10A to 10C illustrate a semiconductor device according to Embodiment 4. [Figure 15] 10A to 10C illustrate a semiconductor device according to Embodiment 4. [Figure 16] 10A to 10C illustrate a semiconductor device according to Embodiment 4. [Figure 17] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment. [Figure 18] FIG. 10 illustrates a pixel equivalent circuit of the semiconductor device of Embodiment 6. [Figure 19] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a sixth embodiment. [Figure 20] 10A and 10B are a top view and a cross-sectional view illustrating a semiconductor device of Embodiment 6. [Figure 21] 13A and 13B are a top view and a cross-sectional view illustrating a semiconductor device of Embodiment 7. [Figure 22] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment. [Figure 23] FIG. 1 is an external view showing an example of an electronic device. [Figure 24] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 25] FIG. 1 is an external view showing an example of a mobile phone. DETAILED DESCRIPTION OF THE INVENTION

[0041] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0042] (Embodiment 1) FIG. 1A shows a first thin film transistor 480 used in a driver circuit and a second thin film transistor 480 used in a pixel portion. 1A shows an example in which a thin film transistor 170 is provided over the same substrate. 1 is an example of a cross-sectional view of the

[0043] The pixel section and the driver circuit are formed on the same substrate, and the pixel section is arranged in a matrix. The pixel electrode is formed using the second thin film transistor 170, which is an enhancement type transistor. The voltage applied to the second thin film transistor 110 is turned on and off. The second thin film transistor 170 uses the oxide semiconductor layer 103. At a gate voltage of ±20V, the on-off ratio is 10 9 Contrast displayed because Furthermore, the low leakage current allows for low power consumption operation. The on-off ratio is the ratio of the off current to the on current (I ON / I OFF ) and The larger the value, the better the switching characteristics, which contributes to improving the contrast of the display. The on-state current is the current between the source electrode and the drain electrode when the transistor is on. The off-state current is the current that flows through the source when the transistor is off. For example, in the case of an n-type transistor, the current that flows between the gate and drain electrodes When the gate voltage is lower than the threshold voltage of the transistor, the In this way, in order to achieve high contrast and low power consumption, For this purpose, it is preferable to use an enhancement type transistor in the pixel portion.

[0044] In the driver circuit, a first gate electrode 401 and an oxide semiconductor layer 405 are provided below the oxide semiconductor layer 405. A thin film transistor 430 having a second gate electrode 470 above the semiconductor layer 405 is formed. At least one second gate electrode 470 is used. This second gate electrode 470 can also be called a back gate electrode. By forming a gate electrode, a via hole is formed to check the reliability of thin film transistors. In the thermal stress test (hereinafter referred to as BT test), the thin film transistor The amount of change in the threshold voltage of the transistor can be reduced.

[0045] The structure of the thin film transistor 430 will be described with reference to FIG. A first gate electrode 401 provided on a substrate 400 is covered with a first gate insulating layer 403. On the first gate insulating layer 403 overlapping the first gate electrode 401, + layer 408a and n + Layer 408b is provided. + Layers 408a and n + On layer 408b: A first wiring 409 or a second wiring 410 is provided. On the first wiring 409 or the second wiring 410 which functions as + Layers 406a and n + layer 40 6b and n + Layers 406a and n + On the layer 406b, an oxide semiconductor layer The oxide semiconductor layer 405 is covered with a second gate insulating layer 412. In addition, a second gate electrode 470 is provided on the second gate insulating layer 412 .

[0046] In addition, n + Layers 408a and n + The layer 408b has at least a portion of its side surface made of an oxide semiconductor. In contact with the layer 405. + Layers 406a and n + Layer 406b has at least one At least part of the surface and at least part of the side surface of the first insulating film 401 are in contact with the oxide semiconductor layer 405. Above and below the first wiring 409 and the second wiring 410 are n+ Since each layer is provided, the first distribution The area where the side surfaces of the wire 409 and the second wiring 410 contact the oxide semiconductor layer 405 is reduced. It is possible.

[0047] n + The layer is an oxide semiconductor layer having a lower resistance than the oxide semiconductor layer, and The first wiring 409 functions as a source electrode layer, and the second wiring If the line 410 acts as a drain electrode layer, n + Layers 408a and n + Layer 406a is the 1 and 2, which serve as source regions, and + Layers 408b and n + Layer 406b is the first and The thin film transistor has multiple source regions, multiple drain regions, and By providing a source or drain region, the transistor The on-current of the transistor can be increased.

[0048] The first gate electrode 401 and the second gate electrode 470 are electrically connected to each other to have the same potential. When the potentials are the same, gate voltages can be applied from above and below the oxide semiconductor layer. Therefore, the current flowing in the ON state can be increased.

[0049] Also, a control signal line for shifting the threshold voltage to the negative side is connected to the first gate electrode 401. , or the second gate electrode 470. The TFT may be a cushion type TFT.

[0050] A control signal line for shifting the threshold voltage to the positive side is connected to the first gate electrode 401, Alternatively, the enhancement layer 440 may be electrically connected to either of the second gate electrodes 470. The TFT may be a stimulant type TFT.

[0051] The combination of two thin film transistors used in the driving circuit is not particularly limited. A thin film transistor with a gate electrode is used as a depletion type TFT, and two gates A thin film transistor having a gate electrode may be used as an enhancement type TFT. In this case, the gate electrodes are arranged above and below the oxide semiconductor layer as thin film transistors in the pixel section. The structure shall have each of these.

[0052] In addition, as a thin film transistor in a pixel portion, a gate electrode is provided above and below the oxide semiconductor layer. The gate electrode is made of oxide semiconductor as an enhancement type TFT of the driving circuit. The gate electrode is a depletion-type TFT for the drive circuit. A structure in which electrodes are provided above and below the oxide semiconductor layer may be used. A control signal line for controlling the value voltage is electrically connected to either the upper or lower gate electrode. The gate electrode connected thereto controls the threshold voltage.

[0053] In FIG. 1A, the second gate electrode 470 is the same as the pixel electrode 110 of the pixel portion. For example, in the case of a transmission type liquid crystal display device, the number of processes is reduced by using a transparent conductive film. The width of the second gate electrode 470 is, but not limited to, the same as that of the first gate electrode 40. 1 and is wider than the width of the oxide semiconductor layer, but is not particularly limited. do not have.

[0054] FIG. 1B shows an example in which the material and width of the second gate electrode are different from those in FIG. 1A. (B) shows a second thin film transistor 170 connected to an organic or inorganic light emitting element. This is an example of a display device provided in the element part.

[0055] In FIG. 1B, an electrode functioning as a second gate electrode of the thin film transistor 432 The material of 471 is metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (N d), scandium (Sc), or an alloy containing the above elements) The width of the electrode 471 in cross section is narrower than that of the second gate electrode 470 in FIG. The width of the electrode 471 is narrower than that of the oxide semiconductor layer 405. Therefore, the second gate electrode 471 is connected to the first wiring 409, the second wiring 410 and the second gate electrode 472. The overlapping area via the insulating layer 412 can be reduced, and the parasitic capacitance can be reduced. Cut.

[0056] The light-emitting element has at least a first electrode 472, a light-emitting layer 475, and a second electrode 474. In FIG. 1B, the electrode 471 is made of the same material as the first electrode 472 of the pixel portion, for example, The number of steps is reduced by using aluminum or the like, but there is no particular limitation. In B), the insulating layer 473 serves as a partition wall for insulating the first electrodes of adjacent pixels. It works like this.

[0057] FIG. 1C shows an example in which the material and width of the second gate electrode are different from those in FIG. 1A. In (C), the electrode 47 functions as the second gate electrode of the thin film transistor 433. The material of 6 is metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd) , scandium (Sc), or an alloy containing the above elements) The width of the second gate electrode in cross section is narrower than that in FIG. 1(B). By narrowing the width of the first wiring 409, the second wiring 410 and the second gate insulating layer This allows for no overlapping via 412, further reducing the parasitic capacitance. The width of the electrode 476 shown in FIG. 1C is set to be smaller than the distance between the first wiring 409 and the second wiring 410. When forming the electrode 476 with such a narrow width, wet etching or the like is used. It is preferable to use a resist mask so that both ends of the electrode 476 are positioned inside the end of the resist mask. However, in FIG. 1C, a metal material different from that of the pixel electrode 110 is used, The photolithography process for forming electrode 476 is increased by one, and the number of masks is also increased by one. This will be done.

[0058] Gate line driving circuit or source line driving circuit used in liquid crystal display devices, light emitting display devices, and electronic paper The oxide sandwiched between two gate electrodes on the top and bottom of the peripheral circuit or pixel section Using thin-film transistors made of semiconductors, high-speed operation and low power consumption can be achieved. In addition, both the pixel section and the driver circuit can be formed on the same substrate without significantly increasing the number of processes. By providing various circuits other than the pixel portion on the same substrate, the display The manufacturing cost of the device can be reduced.

[0059] In addition, a source region or a drain region may be provided above or below the source electrode or the drain electrode. This allows for good connection between the source electrode or drain electrode, which is a metal layer, and the oxide semiconductor layer. As a junction, it has thermally stable operation compared to a Schottky junction. The source side supplies carriers to the transistor, while the drain side absorbs carriers from the channel. This creates a resistance component at the interface with the source electrode (or drain electrode). It is important to provide a source region or a drain region in order to suppress the Resistive oxide semiconductor layer (n + By providing a layer, good mobility can be achieved even at high drain voltages. It can be retained.

[0060] (Embodiment 2) In the first embodiment, one thin film transistor is described as the thin film transistor of the drive circuit. However, here, two n-channel thin film transistors are used to form the inverter circuit of the driver circuit. The thin film transistor shown in FIG. Since the thin film transistor 430 is the same as that shown in FIG. 1(A) of the first embodiment, the same parts are used. The explanation will be given using symbols.

[0061] The driver circuit for driving the pixel section is composed of an inverter circuit, a capacitor, a resistor, etc. When two n-channel TFTs are combined to form an inverter circuit, When forming a combination of a ment type transistor and a depletion type transistor ( EDMOS circuit) and enhancement-type TFTs (hereinafter referred to as , called EEMOS circuits).

[0062] The cross-sectional structure of the inverter circuit of the driver circuit is shown in Figure 2(A). The first thin film transistor 430 and the second thin film transistor 431 are bottom gate thin film transistors. This is an example of a thin film transistor in which wiring is provided under the semiconductor layer.

[0063] In FIG. 2A, a first gate electrode 401 and a gate electrode 402 are provided on a substrate 400. The first gate electrode 401 and the gate electrode 402 are made of molybdenum, titanium, chromium, or the like. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a laminated layer using a material or an alloy material containing these as the main component. do.

[0064] For example, the two-layer laminate structure of the first gate electrode 401 and the gate electrode 402 may be Al. Two-layer laminate structure with a molybdenum layer on a aluminum layer, or a molybdenum layer on a copper layer or a titanium nitride or tantalum nitride layer on a copper layer. Preferably, the titanium nitride layer and the molybdenum layer are laminated together to form a two-layer structure. The laminated structure is composed of a tungsten layer or a tungsten nitride layer and a layer of aluminum and silicon. A titanium nitride layer or titanium layer is laminated on an alloy of aluminum and titanium or an alloy of aluminum and titanium. It is preferable to use a laminate in this manner.

[0065] Also, on the first gate insulating layer 403 covering the first gate electrode 401 and the gate electrode 402 On one side, a first wiring 409, a second wiring 410, and a third wiring 411 are provided. The first gate insulating layer 403 and the first wiring 409, the first gate insulating layer 403 and the second wiring 410, the first Between the gate insulating layer 403 and the third wiring 411, n + layers 420, 421, 42 The second wiring 410 is connected to a contact hole formed in the first gate insulating layer 403. It is connected to the gate electrode 402 via a gate electrode 404 .

[0066] An oxide semiconductor layer 405 is provided above the first wiring 409 and the second wiring 410. , the first wiring 409 and the oxide semiconductor layer 405, and the second wiring 410 and the oxide semiconductor layer 405 Between + Layers 423 and 424 are provided. The second oxide semiconductor layer 407 is provided above the third wiring 411. Between the third wiring 411 and the oxide semiconductor layer 407, and between the third wiring 411 and the oxide semiconductor layer 407, + Layers 425 and 426 are provided respectively.

[0067] In addition, n + The layers 420 to 426 are different from the oxide semiconductor layer 405 and the oxide semiconductor layer 407 in that The wiring is an oxide semiconductor layer having low resistance and functions as a source region or a drain region. and the oxide semiconductor layer + By using a structure with layers, compared to a Schottky junction, It also provides thermally stable operation.

[0068] The thin film transistor 430 includes a first gate electrode 401 and a first gate insulating layer 403. The first wiring 409 is formed by a first gate electrode 401 and an oxide semiconductor layer 405 overlapping the first gate electrode 401. This power supply line is a power supply line to which a negative voltage VDL is applied (negative power supply line). It may also be a power supply line (ground power supply line).

[0069] The second thin film transistor 431 includes a gate electrode 402 and a first gate insulating layer 40 a second oxide semiconductor layer 407 overlapping the gate electrode 402 via a third wiring 4 Reference numeral 11 denotes a power supply line (positive power supply line) to which a positive voltage VDH is applied.

[0070] FIG. 2C shows a top view of the inverter circuit of the driver circuit. The cross section taken along line Z1-Z2 corresponds to FIG. 2(A).

[0071] The equivalent circuit of the EDMOS circuit is shown in Figure 2(B). 2(B), and the thin film transistor 430 is an enhancement type n-channel transistor. The second thin film transistor 431 is a depletion type n-channel transistor. This is an example of a star.

[0072] In order to make the thin film transistor 430 an enhancement type n-channel transistor, In this embodiment, a second gate insulating layer 412 and a second gate insulating layer 413 are formed over the oxide semiconductor layer 405. A second gate electrode 470 is provided on the gate insulating layer 412, and a voltage is applied to the second gate electrode 470. The threshold voltage of the thin film transistor 430 is controlled by the applied voltage.

[0073] The second gate insulating layer 412 also serves as a protective layer covering the second oxide semiconductor layer 407. It works.

[0074] 2A and 2C, the second wiring 410 is connected to the first gate insulating layer 403. 4 shows an example in which the gate electrode 402 is directly connected to the contact hole 404 formed in the However, this is not particularly limited, and a connecting electrode may be separately provided to connect the second wiring 410 and the gate electrode 402. They may also be electrically connected.

[0075] This embodiment mode can be freely combined with Embodiment Mode 1.

[0076] (Embodiment 3) In this embodiment, a display device will be described with reference to block diagrams and the like.

[0077] FIG. 3(A) shows an example of a block diagram of an active matrix liquid crystal display device. The liquid crystal display device shown in A) has a pixel section 300 having a plurality of pixels each having a display element on a substrate 300. 01, a scanning line driving circuit 302 that controls the scanning lines connected to the gate electrodes of the pixels, and a selection and a signal line driver circuit 303 that controls input of a video signal to the selected pixel.

[0078] FIG. 3(B) shows an example of a block diagram of an active matrix light-emitting display device. The light-emitting display device shown in B) has a pixel section 3 having a plurality of pixels each having a display element on a substrate 310. 11, and a first scanning line driving circuit 312 that controls the scanning lines connected to the gate electrodes of the pixels. and a second scanning line driver circuit 313, and a signal generator for controlling the input of a video signal to a selected pixel. A signal line driving circuit 314 is provided. Each pixel has a switching TFT (Thin Film Transistor). lm Transistor (hereafter referred to as TFT) and a current control TFT. In this case, in the light-emitting display device shown in FIG. 3B, The signal input to the first scanning line connected to the first scanning line is generated by the first scanning line driving circuit 312, and is controlled by a current. The signal input to the second scanning line connected to the gate electrode of the control TFT is the second scanning line driving signal. The signal input to the first scanning line and the signal input to the second scanning line are generated by the circuit 313. The signal to be output may be generated by a single scanning line driver circuit. The number of TFTs in a switching element is used to control the operation of the switching element. In this case, the plurality of first scanning lines may be provided for each pixel. The signals input to the scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of scanning lines. A driving circuit may be provided to generate each of these.

[0079] Here, the scanning line driver circuit 302, the first scanning line driver circuit 312, the second scanning line driver circuit 313, The embodiment in which the signal line driver circuits 303 and 314 are fabricated in the display device has been shown. , the scanning line driving circuit 302, the first scanning line driving circuit 312, or the second scanning line driving circuit 3 A part of the signal line driver circuits 303 and 31 may be implemented as a semiconductor device such as an IC. A part of 4 may be implemented as a semiconductor device such as an IC.

[0080] FIG. 4 shows a signal input terminal 322, a scanning line 323, a signal line 324, a non-line 1 is a diagram illustrating the positional relationship between a protection circuit including a semiconductor device and a pixel portion. On the substrate 320, scanning lines 323 and signal lines 324 are arranged to cross each other, forming a pixel section 327. The pixel portion 327 corresponds to the pixel portion 301 and the pixel portion 311 shown in FIG.

[0081] The pixel section 301 is connected to a signal line driving circuit 303 and includes a plurality of signal lines S arranged in a column direction. 1 to Sm (not shown) are connected to the signal line driving circuit 303, and the scanning line driving circuit 302 A plurality of scanning lines G1 to Gn (not shown) are arranged extending in the row direction from the The matrix is ​​connected to the driving circuit 302 and corresponds to the signal lines S1 to Sm and the scanning lines G1 to Gn. The pixel array has a plurality of pixels (not shown) arranged in a grid pattern. Each pixel is connected to a signal line Sj( signal lines S1 to Sm), scanning lines Gi (any one of scanning lines G1 to Gn) ) is connected.

[0082] The pixel section 327 is configured by arranging a plurality of pixels 328 in a matrix. 323 and the signal line 324, a pixel TFT 329, a storage capacitor 330, and a pixel It is configured to include an electrode 331 .

[0083] In the pixel configuration shown here, in the storage capacitor section 330, one electrode and the pixel TFT 329 The pixel electrode 3 is connected to the capacitance line 332, and the other electrode is connected to the capacitance line 332. 31 drives display elements (liquid crystal elements, light emitting elements, contrast media (electronic ink), etc.) The other electrodes of these display elements are connected to a common terminal 333. There are.

[0084] The protection circuit is disposed between the pixel section 327 and the signal line input terminal 322. The protection circuit is disposed between the scan line driver circuit and the pixel section 327. The scanning line 323, the signal line 324 and the capacitance bus line 337 are electrically connected to the sensor by static electricity or the like. A voltage is applied to the pixel TFT 329 so that it is not destroyed. The protection circuit is configured to release the electric charge to the common wiring when a surge voltage is applied. It is being done.

[0085] In this embodiment, a protection circuit 334 is provided on the scanning line 323 side, and a protection circuit 335 is provided on the signal line 324 side. 1 shows an example in which a protection circuit 336 is provided on a capacitive bus line 337. The installation position is not limited to this. In addition, the scanning line driving circuit is not implemented as a semiconductor device such as an IC. In this case, the protection circuit 334 does not need to be provided on the scanning line 323 side.

[0086] By using the TFTs shown in the first embodiment or the second embodiment in each of these circuits, The advantages are as follows:

[0087] The drive circuit is roughly divided into a logic circuit section and a switch section or buffer section. The TFT to be provided should preferably have a configuration that allows control of the threshold voltage. Alternatively, it is preferable that the TFT provided in the buffer section has a large on-state current. By providing a driver circuit having the TFT shown in Embodiment 2, the TFT provided in the logic circuit portion can be The threshold voltage of the FT can be controlled, and the on / off voltage of the TFT provided in the switch section or buffer section can be controlled. Furthermore, the area occupied by the drive circuit is reduced, allowing for a narrow frame. It also contributes to edge formation.

[0088] The shift register circuit that constitutes the scanning line driving circuit will be described below.

[0089] The shift register circuit shown in FIG. 5 has a plurality of flip-flop circuits 351 and a control signal line 352, control signal line 353, control signal line 354, control signal line 355, control signal line 356, and a reset line 357.

[0090] As shown in the shift register circuit of FIG. 5, in the flip-flop circuit 351, the input of the first stage A start pulse SSP is input to the terminal IN via the control signal line 352, and the following stages The input terminal IN is connected to the output signal terminal S of the previous stage flip-flop circuit 351. OUT is connected Also, the reset terminal RES of the Nth stage (N is a natural number) is Flip-flop circuit output signal terminal S out and reset wire 357. The clock terminal CLK of the Nth stage flip-flop circuit 351 is connected to a control signal line 353. Assuming that the first clock signal CLK1 is input via The clock terminal CLK of the flip-flop circuit 351 is connected to the second control signal line 354. The clock signal CLK2 is input to the (N+2)th stage flip-flop circuit 3 The clock terminal CLK of 51 receives the third clock signal CLK via a control signal line 355. 3 is input to the clock terminal C of the (N+3)th flip-flop circuit 351. A fourth clock signal CLK4 is input to LK via a control signal line 356. The clock terminal CLK of the (N+4)th flip-flop circuit 351 receives the control signal A first clock signal CLK1 is input via a line 353. In addition, the Nth stage flip The flop circuit 351 has a gate output terminal G out Therefore, the Nth stage of the flip-flop circuit Output SRoutN.

[0091] Although the connection between the flip-flop circuit 351 and the power supply and power supply line is not shown, The flip-flop circuit 351 is supplied with a power supply potential Vdd and a power supply potential GND via power supply lines. are being provided.

[0092] The power supply potential described in this specification corresponds to the potential difference when the reference potential is 0V. Therefore, the power supply potential is also called the power supply voltage, and the power supply voltage is also called the power supply potential. be.

[0093] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, those that are connected electrically are also included. Electrically connected means that there is an object between A and B that has some electrical effect. This represents the case where A and B are roughly the same node via the object. A and B are connected via a switching element such as a TFT, and the switching element When A and B are connected via a resistor, the potential of A and B becomes approximately the same. The potential difference across the resistor element is small enough not to affect the operation of the circuit including A and B. When considering circuit operation, A and B can be regarded as the same node. This indicates a situation where there is no support.

[0094] Next, FIG. 6 shows the flip-flop circuit 351 included in the shift register circuit shown in FIG. The flip-flop circuit 351 shown in FIG. 6 includes a logic circuit portion 361 and a switch The logic circuit section 361 has TFTs 363 to 368. The switch section 362 also includes TFTs 369 to 372. The path section is a circuit that outputs a signal to the switch section, which is a subsequent circuit, in response to a signal input from the outside. The switch section is a circuit for switching between the inputs from the outside and the control circuit section. The TFTs that act as switches are switched on or off depending on the signal received, and the size of the TFTs is changed. It is a circuit for outputting a current according to the size and structure.

[0095] In the flip-flop circuit 351, the input terminal in is the gate terminal of the TFT 364, and The reset terminal RES is connected to the gate terminal of the TFT363. The clock terminal CLK is connected to the first terminal of the TFT369 and the The power supply line to which the power supply potential Vdd is supplied is connected to the first terminal of TFT3 64, and the gate terminal and second terminal of the TFT 366. The power supply line to which the potential GND is supplied is connected to the second terminal of the TFT363, the second terminal of the TFT365, The second terminal of the TFT367, the second terminal of the TFT368, the second terminal of the TFT370, and the TF It is connected to the second terminal of TFT372. It is also connected to the first terminal of TFT363 and the second terminal of TFT364. 2nd terminal, 1st terminal of TFT365, gate terminal of TFT368, gate of TFT369 The first terminal of the TFT 366 and the gate terminal of the TFT 371 are connected to each other. Terminal 1 is the gate terminal of TFT365, the first terminal of TFT367, and the first terminal of TFT368. The gate terminal of the TFT 370 and the gate terminal of the TFT 372 are connected to each other. , gate output terminal G out is connected to the second terminal of the TFT369 and the first terminal of the TFT370. Connected to output signal terminal S out is the second terminal of TFT371 and TFT372 is connected to the first terminal of the

[0096] In this example, the TFTs 363 to 372 are all N-type TFTs. We will explain the following.

[0097] A TFT has at least three terminals including a gate, a drain, and a source. The element has a channel forming region between a drain region and a source region, and the drain region A current can flow through the channel forming region and the source region. The drain may be switched depending on the TFT structure and operating conditions, so it is difficult to know which is the source. It is difficult to identify which is the source and which is the drain. The regions that function as the source and drain are not called the source or drain, but are called, for example, are sometimes written as the first terminal and the second terminal. In this case, The terminal is referred to as a gate terminal.

[0098] Next, an example of a layout diagram of the flip-flop circuit 351 shown in FIG. 6 is shown in FIG.

[0099] The flip-flop circuit of FIG. 7 includes a power supply line 381 to which a power supply potential Vdd is supplied, a reset line 382, control signal line 353, control signal line 354, control signal line 355, control signal line 356, a control signal line 383, a power supply line 384 to which a power supply potential GND is supplied, a logic circuit unit 361, and The logic circuit section 361 includes a switch section 362. The logic circuit section 361 includes TFTs 363 to 368. The switch section 362 has TFTs 369 to 372. 7, the gate output terminal G out Wiring connected to output signal terminal S out connected to The wiring is also shown.

[0100] In FIG. 7, a semiconductor layer 385, a first wiring layer 386, a second wiring layer 387, a third wiring layer The first wiring layer 386 is made of a gate electrode. The second wiring layer 387 is formed from a layer that forms a source electrode of the TFT. The third wiring layer 388 is formed from a layer that forms a pixel electrode in the pixel area. However, the present invention is not limited to this, and may be formed, for example, by using a layer that forms the third wiring layer 3 The wiring layer 88 may be formed as a separate wiring layer from the layer in which the pixel electrodes are formed.

[0101] The connections between the circuit elements in FIG. 7 are as explained in FIG. 6. , the first clock signal is input to the flip-flop circuit. Connections to signal lines 354 to 356 are not shown.

[0102] In the layout diagram of the flip-flop circuit in FIG. 7, the TFTs included in the logic circuit portion 361 By controlling the threshold voltage of the TFT 366 or the TFT 367, the EDMOS circuit 373 is constructed. Typically, TFT366 is a depletion type, and TFT367 is a The switch section 362 is configured with an enhancement type EDMOS circuit 373. The TFT369 to TFT372 are dual gate type TFTs or depletion type TFTs. In FIG. 6, the TFT 366 and the TFT The T367 is an EDMOS circuit shown in Figure 2. The connection position is different.

[0103] TFT366 or TFT367 is formed as a dual gate type TFT, and a back gate voltage By controlling the potential of the electrodes, it is possible to produce a depletion-type TFT or an enhancement-type TFT. It can be FT.

[0104] In FIG. 7, the control gate electrode is connected to the back gate electrode for controlling the threshold voltage of the TFT366. A control signal line 390 is provided separately to make the TFT 366 a depletion type. The potential of the back gate electrode is the power supply potential V applied to the gate electrode. This is a different potential from the power supply line 381 to which dd is supplied.

[0105] In FIG. 7, TFTs 369 to 372 are dual-gate TFTs, and In this example, the back gate electrode and the gate electrode are at the same potential. The power supply potential Vdd applied to the power supply line is the same potential as that of the power supply line.

[0106] In this way, the TFTs arranged in the pixel section and the driver circuit of the display device are formed by using an oxide semiconductor layer. The device can be formed using only n-channel TFTs.

[0107] In addition, the TFT 366 in the logic circuit section 361 flows a current according to the power supply potential Vdd. The TFT366 is a dual-gate TFT or a depletion-type TFT. By increasing the current flowing through the TFT, the TFT size can be reduced without degrading performance. It is possible to standardize the process.

[0108] In addition, in the TFT that constitutes the switch section 362, the amount of current flowing through the TFT is increased, And because it can be switched on and off quickly, it can be used without compromising performance. Therefore, the area occupied by the TFT can be reduced. It is also possible to reduce the area in which the TFTs 369 to 369 are disposed in the switch section 362. As shown in the figure, the FT 372 is formed by connecting a semiconductor layer 385 to a first wiring layer 386 and a third wiring layer 387. The layout is such that the two electrodes 88 sandwich the two electrodes, forming a dual gate TFT.

[0109] 7, the dual gate type TFT has a semiconductor layer 385 connected to a first wiring layer 386, The third wiring layer 386 is connected to the first wiring layer 386 through a contact hole 389 and has the same potential. Although an example in which the wiring layer 388 is sandwiched between the wiring layer 388 and the wiring layer 388 has been shown, the present invention is not limited to this configuration. For example, a control signal line is provided separately for the third wiring layer 388, and the potential of the third wiring layer 388 is It may be configured to be controlled independently from the first wiring layer 386.

[0110] In the layout diagram of the flip-flop circuit shown in FIG. The shape of the channel forming region of T372 may be U-shaped (or horseshoe-shaped). In Figure 7, the size of each TFT is set to be equal, but the output varies depending on the size of the load in the subsequent stage. Signal terminal S out or gate output terminal G out The size of each TFT connected to the You can change it.

[0111] Next, using the timing chart shown in Figure 8, the operation of the shift register circuit shown in Figure 5 will be explained. FIG. 8 shows the control signal lines 352 to 356 shown in FIG. The start pulse SSP, the first clock signal CLK1 to the fourth clock signal CLK2 are supplied. signal CLK4, and the output signal terminal S of the first to fifth stage flip-flop circuits out from The output signals Sout1 to Sout5 are shown. The reference numerals given to the elements in FIG. 7 are used.

[0112] 8. Note that FIG. 8 shows the case where each of the TFTs in the flip-flop circuit is an N-type TFT. 1 is a timing chart showing the first clock signal CLK1 and the fourth clock signal C As shown in the figure, LK4 is configured to be shifted by 1 / 4 wavelength (one section divided by dotted lines). It has become.

[0113] First, during the period T1, a start pulse SSP is input to the first stage flip-flop circuit. When the signal is input at H level, the logic circuit section 361 turns on the TFTs 369 and 371 of the switch section. At this time, the first clock signal C Since LK1 is at L level, Sout1 is at L level.

[0114] During the period T1, the flip-flop circuits from the second stage onwards receive a signal at the IN terminal. Since no signal is input, the L level is output without operation. The explanation will be given assuming that each flip-flop circuit of the register circuit outputs an L level. .

[0115] Next, in the period T2, in the first stage flip-flop circuit, the logic The circuit unit 361 controls the switch unit 362. In the period T2, the first clock signal CL Since K1 is at H level, Sout1 is at H level. In the flip-flop circuit, Sout1 is input to the IN terminal at a H level, and the logic circuit section 361 turns on TFT369 and TFT371 of the switch section, and TFT370 and TFT At this time, the second clock signal CLK2 is at the L level, so ut2 is at L level.

[0116] During the period T2, the flip-flop circuits from the third stage onwards receive a signal at the IN terminal. Since no signal is input, the L level is output without operating.

[0117] Next, during the period T3, the first stage flip-flop circuit maintains the state of the period T2. The logic circuit unit 361 controls the switch unit 362 so that The first clock signal CLK1 is at H level, and Sout1 is at H level. During the period T3, in the second stage flip-flop circuit, the logic circuit unit 3 61 controls the switch unit 362. During the period T3, the second clock signal CLK2 is H Since the third flip-flop in the period T3 is at the H level, Sout2 is at the H level. In the drop circuit, Sout2 is input to the IN terminal at H level, and the logic circuit unit 361 switches The TFTs 369 and 371 in the switch section are turned on, and the TFTs 370 and 372 are turned off. At this time, the third clock signal CLK3 is at the L level, and therefore Sout3 is at the L level. .

[0118] During the period T3, the flip-flop circuits from the fourth stage onwards receive a signal at the IN terminal. Since no signal is input, the L level is output without operating.

[0119] Next, during the period T4, the first stage flip-flop circuit maintains the state of the period T3. The logic circuit unit 361 controls the switch unit 362 so that Therefore, the first clock signal CLK1 is at L level, and Sout1 is at L level. During the period T4, the second stage flip-flop circuit is set to maintain the state of the period T3. The logic circuit unit 361 controls the switch unit 362 in this manner. The second clock signal CLK2 is at H level, and Sout2 is at H level. During the period T4, in the third stage flip-flop circuit, the logic circuit section 3 61 controls the switch unit 362. During the period T4, the third clock signal CLK3 is H Since the fourth flip-flop in the period T4 is at the H level, Sout3 is at the H level. In the drop circuit, Sout3 is input to the IN terminal at H level, and the logic circuit unit 361 switches The TFTs 369 and 371 of the switch 362 are turned on, and the TFTs 370 and 372 are turned on. At this time, the fourth clock signal CLK4 is at the L level, so Sout 4 is L level.

[0120] During the period T4, the flip-flop circuits from the fifth stage onwards receive a signal at the IN terminal. Since no signal is input, the L level is output without operating.

[0121] Next, during the period T5, the second stage flip-flop circuit maintains the state of the period T3. The logic circuit unit 361 controls the switch unit 362 so that Therefore, the second clock signal CLK2 is at L level, and Sout2 is at L level. During the period T5, the third stage flip-flop circuit is set to maintain the state of the period T4. The logic circuit unit 361 controls the switch unit 362 in this manner. The third clock signal CLK3 is at H level, and Sout3 is at H level. During the period T5, the fourth-stage flip-flop circuit is connected to the logic circuit unit 36 ​​in the same manner as during the period T4. 1 controls the switch unit 362. During the period T5, the fourth clock signal CLK4 is at the H level. Since this is a bell, Sout4 is at H level. The wiring relationship is the same as that of the first to fourth flip-flop circuits. The timing of the signal is similar, so the explanation will be omitted.

[0122] As shown in the shift register circuit of Figure 5, Sout4 is the first stage flip-flop circuit During the period T5, Sout4 becomes H level, and this signal The reset signal is input to the reset terminal RES of the first flip-flop circuit. By this, the TFTs 369 and 371 of the switch section 362 are turned off, and the TFT 37 0 and TFT372 are turned on. Then, Sout1 of the first stage flip-flop circuit is , the L level is output until the next start pulse SSP is input.

[0123] By the operation explained above, even in the second and subsequent flip-flop circuits, The logic circuit is reset based on the reset signal output from the Soup circuit. As shown in t1 to Sout5, a signal with a waveform shifted by 1 / 4 wavelength of the clock signal is The shift register circuit may be configured to output a signal.

[0124] In addition, as a flip-flop circuit, enhancement type and depletion type are used in the logic circuit section. The switch section is equipped with a dual-gate TFT and an EDMOS TFT. By adopting this configuration, the amount of current flowing through the TFTs that constitute the logic circuit section 361 can be increased. It is possible to reduce the area occupied by the TFT and the amount of light generated by the TFT without degrading the performance. The area occupied by the circuitry configured can be reduced. In the case of TFTs, the amount of current flowing through the TFT is increased, and the switching between on and off is performed quickly. Therefore, the area occupied by the TFT and the size of the TFT can be reduced without deteriorating the performance. Therefore, the area occupied by the circuit configured by the above can be reduced. This allows for greater speed, miniaturization, and higher performance.

[0125] Furthermore, a latch circuit, a level shifter circuit, etc. can be provided in the signal line driver circuit shown in FIG. A buffer section is provided at the final stage of sending signals from the signal line driver circuit to the pixel section, and the amplified signals is sent from the signal line driver circuit to the pixel section. For this reason, the buffer section is provided with a TFT with a large on-current. Typically, a dual gate TFT or a depletion type TFT is provided. Therefore, it is possible to reduce the area of ​​the TFT, and the area occupied by the signal line driving circuit can be reduced. Therefore, it is possible to achieve a display device with a narrower frame, smaller size, and higher performance. The shift register, which is part of the signal line driver circuit, is required to operate at high speed. It is preferable to mount the display device using the above.

[0126] This embodiment mode can be freely combined with Embodiment Mode 1 or 2. Cut.

[0127] (Fourth embodiment) In this embodiment, a display device including the second thin film transistor 170 described in Embodiment 1 The manufacturing process will be described with reference to FIGS.

[0128] In FIG. 9(A), a substrate 100 having light-transmitting properties is made of Corning 7059 glass or 1 Barium borosilicate glass, such as 737 glass, and aluminoborosilicate glass Any glass substrate can be used.

[0129] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary portions are removed by etching to form wiring and electrodes (gate A gate wiring including a gate electrode 101, a capacitance wiring 108, and a first terminal 121 are formed. At this time, etching is performed so that at least the end of the gate electrode 101 is tapered. The cross-sectional view at this stage is shown in Figure 9(A). The top view at this stage is shown in Figure 11. When the spin coating method is used to form the resist mask, the resist film To improve uniformity, a large amount of resist material and developer are used, and the excess material is removed. In particular, when the substrate becomes larger, the film formation method using the spin coating method requires a large substrate. The mechanism for rotating the plate is large-scale, and there is a large amount of loss of liquid material and waste liquid, which is a problem in mass production. Furthermore, when a rectangular substrate is spin-coated, circular irregularities occur around the axis of rotation. Therefore, droplet ejection methods such as inkjet printing and screen printing methods are used. A resist material film is selectively formed using the above, and then exposed to light to form a resist mask. By selectively forming a resist material film, it is possible to prevent the use of the resist material. This reduces the amount of material required, resulting in significant cost reductions. It can also handle large area boards such as 100mm x 1250mm and 1150mm x 1300mm. Cut.

[0130] The gate wiring including the gate electrode 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are It is desirable to form it from a low-resistance conductive material such as aluminum (Al) or copper (Cu), Aluminum alone has problems such as poor heat resistance and susceptibility to corrosion, so it is used as a heat-resistant conductive material. The heat-resistant conductive material is titanium (Ti), tantalum (Ta), , tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), an element selected from the group consisting of indium (Sc), or an alloy containing the above elements, or It is formed from an alloy film of a combination of elements or a nitride containing the above-mentioned elements as components.

[0131] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode 101. The film thickness of 2 is 50 to 400 nm, and is formed by sputtering or the like. When priority is given to the thickness, it is preferable that the gate insulating layer 102 is thick.

[0132] For example, a silicon oxide film is used as the gate insulating layer 102 by sputtering, and the thickness is 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. Silicon oxide nitride film, silicon nitride film, aluminum oxide film, aluminum nitride film, Other insulating films such as aluminum film, aluminum oxide nitride film, and tantalum oxide film are used, and these materials The gate insulating layer 102 may be formed as a single layer or a stacked layer structure of the material. When a silicon oxynitride film or a silicon nitride film is used, impurities from the glass substrate For example, sodium or the like is prevented from diffusing and penetrating into the oxide semiconductor to be formed later. It is possible.

[0133] Next, a second photolithography step is performed to form a resist mask and etch the By removing unnecessary parts, wiring made of the same material as the gate electrode and contact holes reaching the electrode are formed. This contact hole is provided for direct connection with a conductive film to be formed later. For example, in the driving circuit section, the gate electrode and the source electrode or the drain electrode are in direct contact with each other. When forming a thin film transistor that is electrically connected to the gate wiring of the terminal part, A contact hole is formed. Here, a second photolithography step is performed to Although an example of forming a contact hole for direct connection with a conductive film to be formed later has been shown, The gate electrode may be formed in the same process as the contact hole for connection to the pixel electrode later. A contact hole reaching the layer may be formed, and electrical connection may be made using the same material as the pixel electrode. If the electrical connection is made with the same material as the pixel electrode, the number of masks can be reduced by one. Cut.

[0134] Next, a first n + In this embodiment, the film (In-Ga-Zn- O-based non-single crystal film) is formed by sputtering. + The film is In2O3:Ga2O3:ZnO The film formation conditions were a pressure of 0.4 Pa and a power of 50 The sputtering was performed at 0 W, the deposition temperature was room temperature, and argon gas flow rate was 40 sccm. A target of In2O3:Ga2O3:ZnO=1:1:1 was intentionally used. Despite the fact that the In-Ga-Z film contains crystal grains of 1 nm to 10 nm in size immediately after deposition, In some cases, a non-single crystal film of nO may be formed. 0.1Pa~2.0Pa), power (250W~3000W: 8 inch diameter), temperature (room temperature~1 00℃), and by appropriately adjusting the film formation conditions of reactive sputtering, it is possible to detect the presence or absence of crystal grains and The density and diameter of the first n can be adjusted in the range of 1 nm to 10 nm. + The thickness of the film is set to 5 nm to 20 nm. Of course, if the film contains crystal grains, the contained crystal grains The size of the crystal grains does not exceed the thickness of the film. + The film thickness is , 5nm.

[0135] Next, the first n+ A conductive film made of a metal material is formed on the film by sputtering or vacuum deposition. Here, the structure is a three-layer structure consisting of a Ti film, an aluminum film containing Nd, and a Ti film. The elements are selected from Al, Cr, Ta, Ti, Mo, and W, or a mixture of the elements mentioned above. The conductive film may be an alloy film containing the above elements or an alloy film combining the above elements. A two-layer structure may be used, and a titanium film may be stacked on an aluminum film. Alternatively, a single layer structure of an aluminum film containing silicon or a single layer structure of a titanium film may be used.

[0136] Next, a second n + Film (In this embodiment, In-Ga-Zn-O system non-single crystal film ) is deposited by sputtering. + The membrane is the first + Using the same deposition conditions as the film It can be formed. + The film has crystal grains of 1 nm to 10 nm in size immediately after deposition. The second n + The film thickness is 5 In this embodiment, the second n + The film thickness is set to 5 nm.

[0137] Gate insulating layer 102, first n + film, conductive film, and second n + The film is made by sputtering. By appropriately switching the gas introduced into the beam or the target to be installed, the beam can be exposed to the atmosphere. When continuous film formation is performed without exposure to the atmosphere, impurities are easily removed. When continuous film formation is performed without exposure to the atmosphere, a multi-chamber It is preferable to use a manufacturing device of this type.

[0138] In this embodiment, the conductive film is made of In-Ga-Zn-O based non-single crystal films on the top and bottom. The first and second n + In this case, the In-Ga-Zn-O non-single layer is sandwiched between the layers. The crystalline film can function as a barrier metal, so the conductive film can be made as a single layer of aluminum film. By using a single aluminum film as the conductive film, it is possible to form a chamber This allows for only one type of target to be installed in the target chamber, thereby reducing costs.

[0139] Next, a third photolithography process is performed to form a resist mask and then etching is performed. The unnecessary portions are removed to form the first source region 106a and the first drain region 106b. The source electrode layer 105a and the drain electrode layer 105b, the second n + n consisting of membrane + layer 141 The etching method used here is wet etching or dry etching. Here, wet etching is performed using ITO07N (manufactured by Kanto Chemical Co., Ltd.). By Ching, n + After forming the layers 141a and 141b, an etchant for the Ti film is added. Ammonia peroxide:ammonia:water = 5:2:2 was used to measure the amount of aluminum containing neodymium. The etching of the aluminum film is carried out using a mixture of phosphoric acid, acetic acid, and nitric acid. This wet etching process creates a conductive film consisting of a Ti film, an Al-Nd film, and a Ti film stacked in sequence. The film is etched to form the source electrode layer 105a and the drain electrode layer 105b. After that, using the same resist mask, wet etching was performed using ITO07N (Kanto Chemical Co., Ltd.) By this etching, a first source region 106a and a first drain region 106b are formed. The cross-sectional view at this stage is shown in Figure 9(B). The top view at this stage corresponds to Figure 12. .

[0140] In the terminal portion, the connection electrode 120 is connected to the gate insulating layer through a contact hole formed in the gate insulating layer. The second n-type terminal 121 is directly connected to the first terminal 121 of the terminal portion. + film consisting of n + The layer 145 remains. Also, the layer 145 exists under the connection electrode 120 and is connected to the first terminal The first n overlapping with child 121 + n consisting of membrane + The layer 143 remains on the second terminal 122. is the second n + n consisting of membrane + Layer 144 remains, and below second terminal 122 is the first n + n consisting of membrane + The layer 142 remains. Although not shown here, the above-mentioned process The same process is used to connect the source wiring or drain wiring and gate voltage of the thin film transistor of the driving circuit. In the capacitance section, the first and second electrodes are directly connected to the capacitance wiring 108. n + The membrane is removed.

[0141] Next, after removing the resist mask, a plasma is used to remove any dust or other particles adhering to the surface. It is preferable to perform the treatment. A cross section at this stage is shown in Figure 9(C). Reverse sputtering is performed by introducing gas and generating plasma using an RF power source. The gate insulating layer is subjected to a plasma treatment.

[0142] A second n-type semiconductor layer is formed on the source electrode layer 105a and the drain electrode layer 105b. + Membrane n + layer 14 1a and 141b are provided, plasma damage is reduced. + Membrane n + Since the layers 141a and 141b are provided, the source electrode layers 105a and This can prevent an increase in wiring resistance due to oxidation of the drain electrode layer 105b.

[0143] Next, after plasma treatment, an oxide semiconductor film is formed. By forming the oxide semiconductor film without using a gate insulating layer, dust or the like can be prevented from being generated at the interface between the gate insulating layer and the oxide semiconductor film. Here, an 8-inch diameter In (indium), Ga ( Oxide semiconductor target containing gallium and zinc (In2O3:Ga2O3 ZnO=1:1:1), the distance between the substrate and the target was 170 mm, and the pressure was 0 The film is formed under argon or oxygen atmosphere at 0.4 Pa and a direct current (DC) power supply of 0.5 kW. The use of a pulsed direct current (DC) power supply is preferred because it reduces dust and makes the film thickness distribution uniform. The thickness of the oxide semiconductor film is set to 5 nm to 200 nm. The thickness of the conductor film is set to 100 nm.

[0144] Next, a fourth photolithography step is performed to form a resist mask and then to perform etching. The oxide semiconductor layer 103 is formed by removing unnecessary portions. Unnecessary parts were removed by wet etching using a SiO2 film (manufactured by Tokamak Co., Ltd.) to form the oxide semiconductor layer. 103. Note that the first n + Membrane, second n + The oxide semiconductor film and the oxide semiconductor film are formed on the same etched surface. To use the chant, the etching here will + A part of the membrane and a second n + film The remaining second n-type semiconductor layer is covered with the oxide semiconductor film. + The membrane is This forms a first source region 146a and a second drain region 146b. The etching is not limited to wet etching, but dry etching may also be used. Remove the gyst mask.

[0145] In the fourth photolithography step, the source electrode layer or the drain electrode layer The second terminals made of the same material as 105a and 105b are left in the terminal portion. 2 is a source wiring (a source wiring including source electrode layers or drain electrode layers 105a and 105b). ) is electrically connected to

[0146] Next, it is preferable to carry out a heat treatment at 200°C to 600°C, typically 300°C to 500°C. For example, place it in a furnace and heat treat it at 350°C for 1 hour in a nitrogen or air atmosphere. Through the above steps, a thin film transistor 1 having the oxide semiconductor layer 103 as a channel formation region is formed. The cross section at this stage is shown in Figure 10(A). The cross-sectional view corresponds to FIG. 13. Note that the timing of the heat treatment is after the formation of the oxide semiconductor film. There are no particular limitations on the method, and it may be performed after forming the protective insulating film, for example.

[0147] Furthermore, the exposed surface of the oxide semiconductor layer 103 may be subjected to oxygen radical treatment. By performing oxygen radical treatment, the thin film transistor can be made normally off. In addition, by performing radical treatment, the oxide semiconductor layer 103 can be etched. The damage can be repaired. Radical treatment involves O2, N2O, preferably oxygen. It is preferable to carry out the process in an atmosphere of N2, He, or Ar. The radical treatment may be carried out in an atmosphere containing a fluorine atom. stomach.

[0148] Next, a protective insulating layer 107 is formed to cover the second thin film transistor 170. 107 is a silicon nitride film, a silicon oxide film, a silicon oxynitride film, etc. obtained by sputtering. Silicon film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, aluminum oxide film A single layer of a thin film such as a tantalum film or a laminate of these films can be used. In the transistor, the protective insulating layer 107 functions as a second gate insulating layer. The second gate electrode is formed on the protective insulating layer 107. The thickness of the protective insulating layer 107 is set to 50 to 400 nm. When priority is given to the yield of thin film transistors, the thicker the protective insulating layer 107, the better. It is preferable that the protective insulating layer 107 is a silicon oxynitride film or a silicon nitride film. When a film or the like is used, impurities that may adhere for some reason after the protective insulating layer 107 is formed, such as It is possible to block sodium and the like from diffusing and entering the oxide semiconductor.

[0149] Next, a fifth photolithography step is performed to form a resist mask, and a protective insulating layer 1 A contact hole 125 reaching the drain electrode layer 105b is formed by etching in step 07. In addition, the etching here forms a contact hole 122 that reaches the second terminal 122. 7. A contact hole 126 reaching the connection electrode 120 is also formed. Shown in Figure 10(B).

[0150] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with a hydrochloric acid solution. However, etching of ITO in particular Residues tend to be generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0151] Next, a sixth photolithography step is performed to form a resist mask and then to perform etching. The unnecessary portions are removed to form the pixel electrode 110 in the pixel portion. In the etching process, the same material as the pixel electrode 110 is used in part of the drive circuit. Using this, an electrode layer (back gate electrode) for controlling the threshold voltage is formed on the oxide semiconductor layer. Note that the thin film transistor having a back gate electrode is the same as that shown in FIG. Since this is an illustration, detailed description will be omitted here.

[0152] In this sixth photolithography step, the gate insulating layer 10 in the capacitance section is 2 and the protective insulating layer 107 as dielectrics, the capacitor wiring 108 and the pixel electrode 110 form a storage capacitor. In this case, the gate insulating layer 102 and the protective insulating layer 107 are used as dielectrics. In the example shown, the storage capacitor is formed by the capacitor wiring 108 and the pixel electrode 110, but this is not particularly limited. An electrode made of the same material as the source electrode or drain electrode is provided above the capacitance wiring. The electrode, the capacitance wiring, and the gate insulating layer 102 between them are configured as a dielectric. A storage capacitor may be formed and its electrode may be electrically connected to the pixel electrode.

[0153] In the sixth photolithography step, the first terminal and the second terminal are formed by resist. The transparent conductive films 128 and 129 formed on the terminal portions are left covered with a mask. 8 and 129 are electrodes or wiring used for connection with the FPC. The transparent conductive film 128 formed on the connected connection electrode 120 is connected to the input terminal of the gate wiring. The transparent conductive film 1 formed on the second terminal 122 serves as a terminal electrode for connection. Reference numeral 29 denotes a connection terminal electrode that functions as an input terminal for the source wiring.

[0154] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The top view at this stage corresponds to Figure 14.

[0155] 15(A1) and 15(A2) are top views of the gate wiring terminal portion at this stage. The cross-sectional views are shown in Fig. 15(A1) and Fig. 15(A2) along the line C1-C2. In FIG. 15(A1), a transparent insulating film formed on the protective insulating film 154 The conductive film 155 is a terminal electrode for connection that functions as an input terminal. ), the terminal portion includes a first terminal 151 made of the same material as the gate wiring, and a source The connection electrode 153, which is made of the same material as the source wiring, is connected to the gate insulating layer 152 and the first source wiring. formed of the same material as the region + The layers 160 are overlapped and electrically connected. The electrode 153 and the transparent conductive film 155 are connected to each other through a contact hole provided in the protective insulating film 154. The wires are directly connected to each other to provide electrical continuity.

[0156] 15(B1) and 15(B2) are a top view and a cross-sectional view of a source wiring terminal portion. Also, FIG. 15(B1) is taken along the line D1-D2 in FIG. 15(B2). In FIG. 15(B1), a transparent conductive film formed on the protective insulating film 154 is The conductive film 155 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, an electrode 156 made of the same material as the gate wiring is connected to the source wiring. Below the second terminal 150 to which it is electrically connected, + through the layer 161 and the gate insulating layer 152. The electrode 156 is not electrically connected to the second terminal 150. If the second terminal 150 is set to a different potential, such as floating, GND, or 0V, It is possible to form a capacitance for noise countermeasures or static electricity countermeasures. The second terminal 150 is electrically connected to the transparent conductive film 155 via the protective insulating film 154. There are.

[0157] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0158] In this way, six photolithography processes were carried out using six photomasks to create the bottom a second thin film transistor 170, which is a gate-type n-channel thin film transistor; Then, these are arranged in a matrix corresponding to each pixel. To fabricate an active matrix display device by arranging the electrodes to form a pixel portion. For convenience, in this specification, such a substrate is referred to as an active matrix. This is called a risk board.

[0159] In addition, when the same material as the pixel electrode is used to electrically connect to the gate line, The third photolithography step can be omitted, reducing the number of photolithography steps to five. Using five photomasks, a bottom-gate n-channel thin-film transistor was fabricated. A second thin film transistor, which is a storage capacitor, can be added.

[0160] In addition, as shown in FIG. 1(C), when the material of the second gate electrode is different from the material of the pixel electrode, In this case, one photolithography step is added, and one photomask is added.

[0161] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0162] The pixel configuration is not limited to that shown in FIG. 14, and an example of a top view different from that shown in FIG. 14 is shown in FIG. In the case of 16, no capacitance wiring is provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel, the protective insulating film, and the gate In this example, a storage capacitor is formed by stacking the capacitor wiring and the capacitor wiring The third terminal connected to the terminal 3 can be omitted. The same reference numerals will be used for the explanation.

[0163] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0164] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0165] In addition, the vertical period can be increased by 1.5 or 2 times to improve the video characteristics. A driving technique called double speed driving may also be used.

[0166] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0167] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0168] The n-channel transistor obtained in this embodiment is an In-Ga-Zn-O based non-single crystal The crystal film is used in the channel formation region and has good dynamic characteristics, so these driving technologies They can be combined.

[0169] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example, GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0170] The gate line driver circuit or source line driver circuit is formed by thin film transistors using oxide semiconductors. By forming a thin film transistor using a driving circuit, the manufacturing cost can be reduced. By directly connecting the gate electrode and the source wiring or the drain wiring, a contact hole is formed. Therefore, it is possible to provide a display device in which the number of driving circuits can be reduced and the area occupied by the driving circuits can be reduced.

[0171] Therefore, this embodiment makes it possible to provide a display device with excellent electrical characteristics at low cost. do.

[0172] This embodiment mode can be freely combined with embodiment mode 1, embodiment mode 2, or embodiment mode 3. It can be adjusted.

[0173] (Embodiment 5) In this embodiment mode, an example of an electronic paper will be shown as a semiconductor device.

[0174] FIG. 17 shows an active matrix type electronic device as an example of a semiconductor device different from a liquid crystal display device. The thin film transistor 581 used in the pixel portion of the semiconductor device is It can be fabricated in the same manner as the thin film transistor of the pixel portion shown in Form 4, and the In-Ga-Zn-O based non- The thin film transistor includes a single crystal film as a semiconductor layer. As shown in the figure, the pixel section and the driver circuit can be fabricated on the same substrate, reducing the manufacturing cost. Paper can be realized.

[0175] The electronic paper in Figure 17 is an example of a display device that uses the twisting ball display method. The ball display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of the spherical particles that are generated.

[0176] The thin film transistor 581 is a thin film transistor with a bottom gate structure, and the source electrode layer The drain electrode layer is formed on the first electrode layer 587 and the insulating layers 583, 584, and 585. The first electrode layer 587 and the second electrode layer 588 are in contact with each other at the opening and are electrically connected. The liquid-filled container has a black area 590a and a white area 590b between them. A spherical particle 589 containing a particle 594 is provided between a pair of substrates 580 and 596, The spherical particle 589 is filled with a filler 595 such as a resin (see FIG. 17).

[0177] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, and is called electronic paper. Dynamic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied, the image once displayed can be retained. From the radio wave source to the semiconductor device with display function (simply display device, or semiconductor with display device) Even if the device (also called a camera) is moved away, the displayed image can be saved. do.

[0178] By the above process, electronic paper can be manufactured as a semiconductor device with reduced manufacturing costs. can be done.

[0179] This embodiment may be appropriately combined with the configuration described in the first or second embodiment. It is possible to implement.

[0180] (Sixth embodiment) In this embodiment mode, a light-emitting display device is shown as an example of a semiconductor device. Here, a light-emitting element that uses electroluminescence is used as the element. Light-emitting devices that utilize electroluminescence are either organic or inorganic compounds that emit light. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. It's been discovered.

[0181] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0182] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0183] FIG. 18 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0184] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The n-type semiconductor uses an oxide semiconductor layer (In-Ga-Zn-O based non-single crystal film) in the channel formation region. 1 shows an example in which two channel-type transistors are used in one pixel.

[0185] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408 .

[0186] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0187] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0188] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0189] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By using the same pixel configuration as in FIG. 18, it is possible to use the same pixel configuration as in FIG.

[0190] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0191] Note that the pixel configuration shown in Fig. 18 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0192] Next, the structure of the light emitting element will be explained with reference to FIGS. 19(A), 19(B), and 19(C). Here, the case where the driving TFT is the thin film transistor 170 shown in FIG. 1(B) is taken as an example. The cross-sectional structure of the pixel will be described with reference to FIGS. 19(A), 19(B), and 19(C). The TFTs 7001, 7011, and 7021 are driver TFTs used in the semiconductor device , which can be manufactured in the same manner as the thin film transistor 170 shown in Embodiment 1. The thin film transistor has excellent electrical characteristics and includes a non-single-crystal film as a semiconductor layer.

[0193] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure in which light is emitted from the side surface. The present invention can also be applied to a light emitting element with an injection structure.

[0194] A light emitting element with a top emission structure will be described with reference to FIG.

[0195] In FIG. 19(A), the driving TFT TFT7001 is a thin film transistor shown in FIG. 1(B). When the light emitted from the light emitting element 7002 exits to the anode 7005 side, 19A shows a cross-sectional view of a pixel. In FIG. 19A, a cathode 7003 of a light-emitting element 7002 and a driving TF The TFT 7001 is electrically connected to a cathode 7003, and a light-emitting layer 7004 is formed on the cathode 7003. The cathode 7003 has a small work function and reflects light. Various materials can be used as long as they are conductive films that reflect light. For example, Ca, Al, CaF, The light-emitting layer 7004 is preferably made of MgAg, AlLi, or the like. It may be configured as a single layer or as a laminate of multiple layers. In this case, an electron injection layer, an electron transport layer, an emitting layer, a hole transport layer, and a hole The anode 7005 is a light-transmitting layer. The insulating film is formed using a light-transmitting conductive material, for example, an indium-ion conductive material containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, titanium oxide, indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. Alternatively, a conductive film having a conductive property may be used.

[0196] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 19(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0197] Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is the cathode 7003. It is preferable to form them from the same material because this simplifies the process.

[0198] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. 011 is the thin film transistor 170 shown in FIG. 1A, and the light emitted from the light-emitting element 7012 19(B) shows a cross-sectional view of a pixel when light emitted from the driving A light-emitting element is formed on a light-transmitting conductive film 7017 electrically connected to the active TFT 7011. A cathode 7013 is formed on the cathode 7012, and a light-emitting layer 7014 and an anode 70 are formed on the cathode 7013. In addition, when the anode 7015 is transparent, a transparent insulating film 15 is formed on the anode 7015 so as to cover the anode. As shown in FIG. 7, a shielding film 7016 for reflecting or blocking light may be formed. 13, as in the case of FIG. 19(A), various conductive materials with small work functions can be used. However, the film thickness should be such that light can be transmitted (preferably 5 nm to 3 For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013. The light-emitting layer 7014 can be formed as a single layer, as in FIG. The anode may be formed of a single layer or a plurality of layers stacked together. 7015 does not need to transmit light, but as in FIG. 19(A), it is a conductive material having light-transmitting properties. The shielding film 7016 can be formed using a material such as a metal that reflects light. For example, a resin containing a black pigment can be used. You can also be there.

[0199] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 19B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0200] Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is the cathode 7013. It is preferable to form them from the same material because this simplifies the process.

[0201] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 is formed using a light-transmitting conductive material, similar to FIG. 19(A). It is possible.

[0202] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 19C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0203] Note that the second gate electrode provided over the oxide semiconductor layer in the driver circuit is a conductive film 7027 It is preferable to form the gate electrode from the same material as the gate electrode because this simplifies the process. The second gate electrode provided on the compound semiconductor layer is made of the same material as the conductive film 7027 and the cathode 7023. By using this method to stack the layers, the process can be simplified and the wiring resistance can be reduced. This can be preferably reduced.

[0204] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0205] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light emitting element is electrically connected has been shown, it is possible to prevent a current from flowing between the driving TFT and the light emitting element. A control TFT may be connected.

[0206] Note that the semiconductor device described in this embodiment mode has the same structure as that shown in FIGS. The present invention is not limited to the above-described configuration, and various modifications based on the disclosed technical idea are possible. do.

[0207] Next, the upper surface and the lower surface of a light-emitting display panel (also referred to as a light-emitting panel), which corresponds to one mode of a semiconductor device, The cross section will be explained using Figures 20(A) and 20(B). Figure 20(A) shows the first The thin film transistor and the light emitting element formed on the substrate are sandwiched between the second substrate and the substrate by a sealing material. 20(B) is a top view of the panel sealed by the HI in FIG. 20(A). This corresponds to a cross-sectional view.

[0208] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0209] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 20B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0210] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O based non-single crystal films as semiconductor layers. The highly reliable thin film transistor described in Embodiment 1 can be applied. In addition, the thin film transistor 4509 is a thin film transistor having a semiconductor layer as shown in Embodiment 1 and FIG. The gate electrodes are located above and below the gate electrode.

[0211] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0212] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0213] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0214] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0215] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0216] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film.

[0217] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0218] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 must be light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0219] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used.

[0220] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0221] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A single crystal semiconductor substrate or a polycrystalline semiconductor film is formed on an insulating substrate. Alternatively, the signal line driver circuit may be implemented as a drive circuit formed by a thin film. Alternatively, only a part of the scanning line driver circuit or only a part of the scanning line driver circuit may be separately formed and mounted. This embodiment is not limited to the configurations of FIGS. 20(A) and 20(B).

[0222] Through the above steps, a light-emitting display device (display panel) can be manufactured at reduced manufacturing costs. can.

[0223] This embodiment may be appropriately combined with the configuration described in the first or second embodiment. It is possible to implement.

[0224] (Embodiment 7) In this embodiment mode, a top view and a cross section of a liquid crystal display panel, which corresponds to one mode of a semiconductor device, are shown. This will be explained using Figures 21(A1), 21(A2), and 21(B). 21A2 shows the In-G film shown in Embodiment 1 formed on the first substrate 4001. Thin film transistors 4010 and 4011 containing a-Zn-O based non-single crystal film as a semiconductor layer, The liquid crystal element 4013 is sealed between the second substrate 4006 and the liquid crystal element 4013 by a sealant 4005. 21(A1) and 21(A2). This corresponds to the cross-sectional view in

[0225] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0226] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 21(A2) shows This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0227] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 21B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4022 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0228] The thin film transistors 4010 and 4011 are made of an In-Ga-Zn-O based non-single crystal film as a semiconductor layer. The thin film transistor described in Embodiment 1 can be applied. The transistor 4011 is a thin film transistor having a back gate electrode shown in FIG. 2(A) of the second embodiment. It is equivalent to a transistor.

[0229] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0230] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0231] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0232] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs to It is optically isotropic, requiring no alignment treatment, and has little viewing angle dependency. stomach.

[0233] Although this embodiment is an example of a transmissive liquid crystal display device, a transflective liquid crystal display device may also be used. It can also be applied to a liquid crystal display device.

[0234] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0235] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the thin film transistor obtained in the first embodiment, a protective film or The insulating layer 4020 and the insulating layer 4021 are covered with insulating layers that function as planarizing insulating films. The protective film also prevents contamination by organic matter, metals, water vapor, and other polluting impurities floating in the air. The protective film is formed by sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitride A single layer or multilayer of an aluminum film, an aluminum oxynitride film, or an aluminum nitride oxide film In this embodiment, an example in which the protective film is formed by sputtering is shown. The method is not limited to this and may be a PCVD method or other various methods. This protective film functions as a second gate insulating layer, and a back gate is formed on the second gate insulating layer. The thin film transistor includes a

[0236] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping

[0237] In addition, an insulating layer is formed as the second layer of the protective film. Then, a silicon nitride film is formed by sputtering. When a silicon nitride film is used as a protective film, Prevents ions such as thorium from penetrating into the semiconductor region and changing the electrical characteristics of the TFT. It can be controlled.

[0238] After forming the protective film, the semiconductor layer may be annealed (at 300°C to 400°C). In addition, the back gate is formed after the protective film is formed.

[0239] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0240] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0241] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, The semiconductor layer may be annealed (at 300°C to 400°C) at the same time as the step of annealing. By combining the firing process of the edge layer 4021 with the annealing of the semiconductor layer, semiconductor devices can be efficiently manufactured. It becomes possible to do this.

[0242] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0243] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0244] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0245] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0246] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 40 The source electrode layer and the drain electrode layer 11 are formed of the same conductive film.

[0247] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0248] In addition, in FIG. 21(A1) and FIG. 21(A2), a signal line driver circuit 4003 is separately formed. 10, an example in which the first substrate 4001 is mounted is shown, but this embodiment is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or Alternatively, only a part of the scanning line driving circuit may be separately formed and mounted.

[0249] FIG. 22 shows a liquid crystal display module constructed as a semiconductor device using a TFT substrate 2600. An example is shown.

[0250] FIG. 22 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0251] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic) ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid Crystal Crystal mode, AFLC (AntiFerroelectric Liquid Crystal) can be used.

[0252] By the above steps, a liquid crystal display panel can be manufactured as a semiconductor device at reduced manufacturing costs. This can be done.

[0253] This embodiment is applicable to the configuration described in the first, second, or third embodiment. It is possible to carry out any combination of these.

[0254] (Embodiment 8) The semiconductor device according to the disclosed invention can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), Examples include large game machines such as small game machines, mobile information terminals, sound reproduction devices, and pachinko machines. can be.

[0255] 23A shows an example of a mobile information terminal device 9200. The 00 has a built-in computer and is capable of performing various data processing. Such portable information terminal devices 9200 include PDAs (Personal Digital Assistants) Assistance).

[0256] The mobile information terminal device 9200 is composed of two housings, a housing 9201 and a housing 9203. The housing 9201 and the housing 9203 are foldably connected to each other at a connecting portion 9207. A display unit 9202 is incorporated in a housing 9201, and a keyboard 9203 is incorporated in a housing 9203. Of course, the configuration of the mobile information terminal device 9200 is not limited to the above. It is sufficient that the thin film transistor has a back gate electrode. The drive circuit and other auxiliary equipment can be mounted on the same board. By forming a pixel section, manufacturing costs are reduced and thin film transistors with high electrical properties can be used. It is possible to realize a portable information terminal device having such a function.

[0257] FIG. 23B shows an example of a digital video camera 9500. The META 9500 has a display unit 9503 built into a housing 9501, and various operation units are also installed. The configuration of the digital video camera 9500 is not particularly limited, and at least It is sufficient that the device has a thin film transistor having a back gate electrode, and other auxiliary equipment The driving circuit and the pixel section are formed on the same substrate. This reduces manufacturing costs and allows for the development of digital video devices with thin film transistors with excellent electrical properties. This makes it possible to realize a video camera.

[0258] FIG. 23C shows an example of a mobile phone 9100. The mobile phone 9100 has a housing It consists of two housings, 9102 and housing 9101, and is foldable by connecting part 9103. The display unit 9104 is incorporated in the housing 9102. The body 9101 is provided with operation keys 9106. The mobile phone 9100 has the following configuration: There is no particular limitation, but the configuration includes at least a thin film transistor having a back gate electrode. Other auxiliary equipment may be provided as appropriate. By forming the operating circuit and pixel section, manufacturing costs are reduced, and thin film transistors with high electrical properties are used. It is possible to realize a mobile phone having a register.

[0259] FIG. 23(D) shows an example of a portable computer 9300. The electronic device 300 includes a housing 9301 and a housing 9302 that are connected so as to be openable and closable. The display unit 9303 is incorporated in the housing 9302, and the housing 9302 is equipped with a keyboard 9304 and the like. The configuration of the computer 9300 is not particularly limited, and at least the back gate electrode Any configuration is possible as long as it includes a thin film transistor having the above structure, and other auxiliary equipment is appropriately provided. By forming the driver circuit and the pixel portion on the same substrate, the manufacturing cost can be reduced. This makes it possible to realize a computer having thin film transistors with reduced noise and high electrical properties.

[0260] FIG. 24(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0261] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0262] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0263] FIG. 24B shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0264] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0265] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0266] FIG. 25(A) shows an example of a mobile phone 1000 different from the mobile phone of FIG. 23(C). The mobile phone 1000 includes a display unit 1002 built into a housing 1001, an operation unit 1003, a display unit 1004, a display unit 1005, a display unit 1006, a display unit 1007, a display unit 1008, a display unit 1009, a display unit 1010, a display unit 1011, a display unit 1012, a display unit 1013, a operation button 1003, external connection port 1004, speaker 1005, microphone 1006, etc. It is prepared.

[0267] The mobile phone 1000 shown in FIG. 25A displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or sending an email can be performed using the display unit 1. This can be done by touching 002 with a finger or the like.

[0268] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0269] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0270] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0271] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0272] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0273] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0274] FIG. 25B is also an example of a mobile phone. The mobile phone in FIG. 25B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can be used independently. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry. [Explanation of symbols]

[0275] 100 boards 101 gate electrode 102 Gate insulating layer 103 Oxide semiconductor layer 105a Source electrode layer 105b drain electrode layer 106a Source Region 106b Drain region 107 Protective insulation layer 108 Capacitance wiring 110 pixel electrode 112 Scanning line driving circuit 120 connecting electrode 121 terminal 122 terminals 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Transparent conductive film 129 Transparent conductive film 141a n + layer 141b n + layer 146a Source Region 146b Drain region 142 n+ layer 143 n+ layer 144 n+ layer 145 n+ layer 150 terminals 151 terminals 152 Gate insulating layer 153 Connecting electrode 154 Protective insulating film 155 Transparent conductive film 156 Electrode 170 Thin-Film Transistor 300 boards 301 Pixel section 302 Scanning line driving circuit 303 Signal line driver circuit 310 Substrate 311 Pixel section 312 Scanning line driving circuit 313 Scanning line driving circuit 314 Signal line driver circuit 320 board 322 signal line input terminal 323 scan lines 324 signal line 327 Pixel section 328 pixels 329 pixel TFT 330 Holding capacity section 331 Pixel electrode 332 Capacitance Line 333 Common terminal 334 Protection circuit 335 Protection circuit 336 Protection circuit 337 capacity bus line 351 Flip-Flop Circuit 352 Control signal line 353 Control Signal Line 354 Control signal line 355 Control signal line 356 Control Signal Line 357 Reset Line 361 Logic Circuit Section 362 Switch section 363 TFT 364 TFT 365 TFT 366 TFT 367 TFT 368 TFT 369 TFT 370 TFT 371 TFT 372 TFT 373 EDMOS Circuit 381 Power line 382 Reset Line 383 Control Signal Line 384 Power line 385 Semiconductor Layer 386 wiring layer 387 Wiring layer 388 wiring layer 389 Contact Hole 390 Control Signal Line 400 boards 401 Gate electrode 402 gate electrode 403 Gate insulating layer 404 Contact Hole 405 Oxide semiconductor layer 406a n+ layer 406b n+ layer 408a n+ layer 408b n+ layer 407 Oxide semiconductor layer 409 Wiring 410 Wiring 411 Wiring 412 Gate insulating layer 420 n+ layer 423 n+ layer 425 n+ layer 430 Thin Film Transistor 431 Thin-film transistor 432 Thin-film transistor 433 Thin-Film Transistor 470 gate electrode 471 Electrode 471 Gate electrode 472 Electrode 473 Insulating Layer 474 Electrode 475 luminescent layer 476 Electrode 480 Thin Film Transistors 581 Thin-film transistor 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 1000 mobile phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4020 Insulation layer (insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4518a FPC 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Bulkhead 6400 pixels 6401 Switching transistor 6402 Drive transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light-emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7011 Driving TFT 7012 Light-emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7021 Driving TFT 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9100 Mobile Phone 9101 Housing 9102 Housing 9103 Connection section 9104 Display section 9106 Operation key 9200 Portable information terminal equipment 9201 Case 9202 Display section 9203 Housing 9205 keyboard 9207 Connection section 9300 Computer 9301 Housing 9302 Housing 9303 Display section 9304 Keyboard 9400 Communication Equipment 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9500 Digital Video Camera 9501 Housing 9503 Display section 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section

Claims

1. The semiconductor device includes first to eighth transistors and first to sixth wirings, one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the third transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the fifth wiring; a gate electrode of the fifth transistor is always electrically connected to the fifth wiring; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the sixth transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the seventh transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the eighth transistor is always electrically connected to the sixth wiring; a first conductive film having a function as a gate electrode of the third transistor and a function as a gate electrode of the sixth transistor intersects with a second conductive film having a function as one of a source electrode or a drain electrode of the third transistor, a function as one of a source electrode or a drain electrode of the fourth transistor, and a function as one of a source electrode or a drain electrode of the eighth transistor; Semiconductor device.

2. The semiconductor device includes first to eighth transistors and first to sixth wirings, one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the third transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the fifth wiring; a gate electrode of the fifth transistor is always electrically connected to the fifth wiring; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the sixth transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the seventh transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the eighth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a signal, the second wiring has a function of transmitting a clock signal; the third wiring has a function of transmitting a power supply potential; a first conductive film having a function as a gate electrode of the third transistor and a function as a gate electrode of the sixth transistor intersects with a second conductive film having a function as one of a source electrode or a drain electrode of the third transistor, a function as one of a source electrode or a drain electrode of the fourth transistor, and a function as one of a source electrode or a drain electrode of the eighth transistor; Semiconductor device.

3. The semiconductor device includes first to eighth transistors and first to sixth wirings, one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the third transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the fifth wiring; a gate electrode of the fifth transistor is always electrically connected to the fifth wiring; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the sixth transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the seventh transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the eighth transistor is always electrically connected to the sixth wiring; a first conductive film having a function as a gate electrode of the third transistor and a function as a gate electrode of the sixth transistor intersects with a second conductive film having a function as one of a source electrode or a drain electrode of the third transistor, a function as one of a source electrode or a drain electrode of the fourth transistor, and a function as one of a source electrode or a drain electrode of the eighth transistor; the third conductive film having a function as a gate electrode of the fourth transistor intersects with the fourth conductive film having a function as the third wiring; Semiconductor device.

4. The semiconductor device includes first to eighth transistors and first to sixth wirings, one of a source electrode and a drain electrode of the first transistor is always electrically connected to the first wiring; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to the second wiring; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the first wiring; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; a gate electrode of the third transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the fourth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; one of a source electrode and a drain electrode of the fifth transistor is always electrically connected to a gate electrode of the second transistor; the other of the source electrode and the drain electrode of the fifth transistor is always electrically connected to the fifth wiring; a gate electrode of the fifth transistor is always electrically connected to the fifth wiring; one of a source electrode and a drain electrode of the sixth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the sixth transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the sixth transistor is always electrically connected to the fourth wiring; one of a source electrode and a drain electrode of the seventh transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the seventh transistor is always electrically connected to the gate electrode of the second transistor; a gate electrode of the seventh transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the eighth transistor is always electrically connected to the third wiring; the other of the source electrode and the drain electrode of the eighth transistor is always electrically connected to the gate electrode of the first transistor; a gate electrode of the eighth transistor is always electrically connected to the sixth wiring; the first wiring has a function of outputting a signal, the second wiring has a function of transmitting a clock signal; the third wiring has a function of transmitting a power supply potential; a first conductive film having a function as a gate electrode of the third transistor and a function as a gate electrode of the sixth transistor intersects with a second conductive film having a function as one of a source electrode or a drain electrode of the third transistor, a function as one of a source electrode or a drain electrode of the fourth transistor, and a function as one of a source electrode or a drain electrode of the eighth transistor; the third conductive film having a function as a gate electrode of the fourth transistor intersects with the fourth conductive film having a function as the third wiring; Semiconductor device.

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