Semiconductor device

Abstract

To provide a semiconductor device and a bonding method for improving reliability.SOLUTION: The semiconductor device includes a semiconductor device 11 including a device main surface 11a, a device back surface 11b, and a first region disposed on the device main surface side and separated from each other in the Z direction, an electrode member 31A electrically connected to the first region and disposed on the device back surface, a first conductive member 22A bonded to the semiconductor device, and a first bonding portion 511 bonded to the electrode member, the first joint part is partially welded and joined to the electrode member, the electrode member is a metal plate, the semiconductor device further includes a resin member 7 covering at least a part of the semiconductor element, the electrode member, the first joint part 511, and the first conductive member, and an upper surface of a welding mark 8 formed by welding and joining has irregularities and is in contact with the resin member. With such a configuration, the reliability of the semiconductor device can be improved.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Various configurations have been proposed for semiconductor devices. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a semiconductor element, a lead frame, and a strap (conductive metal plate). The semiconductor element includes a source electrode and is mounted on a part of the lead frame. The strap is ultrasonically connected to the source electrode of the semiconductor element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-310609 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, the strap is ultrasonically connected to the source electrode of the semiconductor element to establish electrical continuity between the strap and the source electrode. In this ultrasonic connection, ultrasonic vibrations are applied while the strap is pressed against the source electrode, which can damage the semiconductor element due to the pressure and vibrations. This raises concerns about a decrease in the reliability of the semiconductor device.

[0005] The present disclosure has been made in view of the above-mentioned problems, and has an object to provide a semiconductor device and a bonding method that are improved in reliability. [Means for solving the problem]

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises a semiconductor element having an element main surface and an element back surface spaced apart from each other in a first direction and a first region arranged on the element main surface side, an electrode member that is conductive to the first region and is arranged on the element main surface, a first conductive member that faces the element back surface and is joined to the semiconductor element, a second conductive member that is arranged at a distance from the first conductive member, and a connecting member that conducts electricity between the electrode member and the second conductive member, and the connecting member is joined to the electrode member by laser welding.

[0007] A bonding method provided by a second aspect of the present disclosure is a bonding method for bonding a conductive connecting member to a semiconductor element having an element main surface and an element back surface spaced apart from each other in a first direction, wherein the semiconductor element includes a first region arranged on the element main surface side, and the bonding method includes a first step of placing a conductive member on the element main surface and conducting the conductive member to the first region, and a second step of overlapping the connecting member on the conductive member and laser welding the connecting member and the conductive member in the region where the connecting member and the conductive member overlap as viewed in the first direction, wherein a first laser beam and a second laser beam having different wavelengths are used in the laser welding. [Effects of the Invention]

[0008] According to the semiconductor device and bonding method of the present disclosure, reliability can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a perspective view of the embodiment shown in FIG. 1 with the resin member omitted. [Figure 3] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 4] 4 is a diagram showing the resin member in the plan view shown in FIG. 3 by using imaginary lines. [Figure 5] FIG. 4 is a partially enlarged view of a part of FIG. 3. [Figure 6] FIG. 1 is a front view showing a semiconductor device according to a first embodiment. [Figure 7] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 8] 1 is a side view (left side view) showing a semiconductor device according to a first embodiment. [Figure 9] 1 is a side view (right side view) showing a semiconductor device according to a first embodiment. [Figure 10] FIG. 5 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 10 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a partially enlarged view of a part of FIG. [Figure 13] FIG. 2 is a schematic plan view showing an example of a welding mark. [Figure 14] FIG. 2 is a cross-sectional view showing an example of a welding mark. [Figure 15] FIG. 1 is a schematic diagram showing an example of a laser irradiation device. [Figure 16] 4 is a timing chart showing output waveforms of two laser beams. [Figure 17] FIG. 10 is a perspective view showing a semiconductor device according to a second embodiment. [Figure 18] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment. [Figure 19] FIG. 19 is a partially enlarged view of a part of FIG. 18. [Figure 20] FIG. 10 is a front view showing a semiconductor device according to a third embodiment. [Figure 21] FIG. 19 is a cross-sectional view taken along line XXI-XXI in FIG. 18. [Figure 22] FIG. 22 is a partially enlarged view of a part of FIG. 21. [Figure 23] FIG. 10 is a perspective view showing a semiconductor device according to a fourth embodiment. [Figure 24] FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The semiconductor device and bonding method of the present disclosure will be described below with reference to the drawings.

[0011] 1 to 12 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of the first embodiment includes a plurality of semiconductor chips 10, a support substrate 20, a plurality of metal plates 31, a plurality of terminals 40, an insulating plate 49, a plurality of lead members 5, a plurality of wire members 6, and a plurality of resin members 7. The plurality of terminals 40 include input terminals 41 and 42, an output terminal 43, a pair of gate terminals 44A and 44B, a pair of detection terminals 45A and 45B, a plurality of dummy terminals 46, and a pair of side terminals 47A and 47B.

[0012] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a perspective view of FIG. 1 with the resin member 7 omitted. FIG. 3 is a plan view showing the semiconductor device A1. FIG. 4 is a view in which the resin member 7 is indicated by an imaginary line (two-dot chain line) in the plan view of FIG. 3. FIG. 5 is a partially enlarged view of a part of FIG. 4. FIG. 6 is a front view showing the semiconductor device A1. FIG. 7 is a bottom view showing the semiconductor device A1. FIG. 8 is a side view (left side view) showing the semiconductor device A1. FIG. 9 is a side view (right side view) showing the semiconductor device A1. FIG. 10 is a cross-sectional view taken along line XX in FIG. 4. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 4. FIG. 12 is a partially enlarged view of a part of FIG. 11.

[0013] For ease of explanation, in Figures 1 to 12, three mutually orthogonal directions are defined as the x-direction, y-direction, and z-direction. The x-direction is the left-right direction in the plan view of the semiconductor device A1 (see Figures 3 and 4). The y-direction is the up-down direction in the plan view of the semiconductor device A1 (see Figures 3 and 4). The z-direction is the thickness direction of the semiconductor device A1. One of the x-directions is the x1-direction, and the other of the x-directions is the x2-direction. Similarly, one of the y-directions is the y1-direction, the other of the y-directions is the y2-direction, one of the z-directions is the z1-direction, and the other of the z-directions is the z2-direction. The z1-direction may also be referred to as the bottom, and the z2-direction as the top. Furthermore, the dimension in the z-direction may also be referred to as the "thickness." The z-direction corresponds to the "first direction" described in the claims.

[0014] Each of the multiple semiconductor chips 10 is the functional center of the semiconductor device A1. When viewed in the z direction (hereinafter also referred to as "plan view"), each semiconductor chip 10 has a rectangular shape. Note that the plan view shape of each semiconductor chip 10 is an example. Each semiconductor chip 10 includes a semiconductor element 11, element electrodes 12, and an insulating film 13.

[0015] Each semiconductor element 11 is configured using a semiconductor material mainly made of, for example, SiC (silicon carbide). The semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. In the present disclosure, a case where the semiconductor element 11 is a MOSFET (metal-oxide-semiconductor field-effect transistor) will be described as an example. The semiconductor element 11 is not limited to a MOSFET, and may be a field-effect transistor including a MISFET (metal-insulator-semiconductor FET), or a bipolar transistor such as an IGBT (insulated gate bipolar transistor). The semiconductor elements 11 may be, for example, an IC chip such as a transistor or LSI, a diode, or a capacitor. The plurality of semiconductor elements 11 are, for example, each of n-channel MOSFETs, and are all the same element. Note that each semiconductor element 11 may also be a p-channel MOSFET. The thickness of each semiconductor element 11 is, for example, approximately 50 to 370 μm.

[0016] Each semiconductor element 11 has an element principal surface 11a and an element rear surface 11b. In each semiconductor element 11, the element principal surface 11a and the element rear surface 11b are spaced apart in the z direction. The element principal surface 11a is the top surface of the semiconductor element 11 and faces the z2 direction. The element rear surface 11b is the bottom surface of the semiconductor element 11 and faces the z1 direction.

[0017] Each semiconductor element 11 includes a first region 111, a second region 112, and a third region 113. In each semiconductor element 11, the first region 111 and the second region 112 are both semiconductor regions located on the element main surface 11a side in the z direction. The third region 113 is a semiconductor region located on the element back surface 11b side in the z direction. In a semiconductor element 11 that is a MOSFET, for example, the first region 111 is a source region, the second region 112 is a gate region, and the third region 113 is a drain region. Note that the first region 111 may be the drain region, and the third region 113 may be the source region. Alternatively, the third region 113 may be located on the element main surface 11a side.

[0018] Each of the device electrodes 12 is an electrode pad on each of the semiconductor chips 10, and functions as a terminal on each of the semiconductor chips 10. Each of the device electrodes 12 includes a first electrode layer 121, a second electrode layer 122, and a third electrode layer 123.

[0019] Each first electrode layer 121 is exposed from the element main surface 11a of each semiconductor element 11. Each first electrode layer 121 is in ohmic contact with each first region 111. Each first electrode layer 121 is a source electrode of each semiconductor chip 10, and a source current flows through it. Each first electrode layer 121 may be divided into multiple regions.

[0020] Each second electrode layer 122 is exposed from the element main surface 11a of each semiconductor element 11. Each second electrode layer 122 is in ohmic contact with each second region 112. Each second electrode layer 122 is a gate electrode of each semiconductor chip 10, and a gate voltage for driving each semiconductor element 11 is applied to each second electrode layer 122.

[0021] In a plan view, the first electrode layer 121 is larger than the second electrode layer 122. When viewed in both the x direction and the y direction, the first electrode layer 121 and the second electrode layer 122 overlap each other.

[0022] Each third electrode layer 123 is exposed from the element back surface 11b of each semiconductor element 11. Each third electrode layer 123 is in ohmic contact with each third region 113. Each third electrode layer 123 is formed over the entire surface of each element back surface 11b. Each third electrode layer 123 is a drain electrode of each semiconductor chip 10, and a drain current flows through it.

[0023] As shown in FIGS. 5 and 12, each insulating film 13 is formed on the element principal surface 11a. Each insulating film 13 has electrical insulation properties. Each insulating film 13 is formed between the first electrode layer 121 and the second electrode layer 122 to insulate them. If the first electrode layer 121 is divided into multiple regions, the insulating film 13 is also formed between these regions to insulate each region from each other. The insulating film 13 is formed by laminating, for example, a SiO2 (silicon dioxide) layer, a SiN4 (silicon nitride) layer, and a polybenzoxazole layer in this order from the element principal surface 11a. A polyimide layer may be used instead of the polybenzoxazole layer.

[0024] The multiple semiconductor chips 10 include multiple semiconductor chips 10A and multiple semiconductor chips 10B. The semiconductor device A1 configures, for example, a half-bridge switching circuit, with the multiple semiconductor chips 10A configuring an upper arm circuit in the switching circuit and the multiple semiconductor chips 10B configuring a lower arm circuit in the switching circuit. As shown in FIGS. 2 and 4, the semiconductor device A1 includes four semiconductor chips 10A and four semiconductor chips 10B. The number of semiconductor chips 10 is not limited to this configuration and can be freely set depending on the performance required of the semiconductor device A1.

[0025] As shown in FIGS. 2, 4, 5, 11, and 12, each of the multiple semiconductor chips 10A is mounted on a support substrate 20 (a conductive substrate 22A described later). The multiple semiconductor chips 10A are aligned in the y direction and spaced apart from one another. When each semiconductor chip 10A is mounted on the conductive substrate 22A, the back surface 11b of the device faces the conductive substrate 22A. As shown in FIGS. 11 and 12, each semiconductor chip 10A is bonded to the support substrate 20 (conductive substrate 22A) via a conductive bonding material 100A. This allows the third electrode layer 123 of each semiconductor chip 10A to be electrically connected to the support substrate 20 (conductive substrate 22A) via the conductive bonding material 100A. The conductive bonding material 100A is made of a sintered metal such as Ag or Cu. The conductive bonding material 100A is not limited to a sintered metal and may be Ag paste, solder, or the like.

[0026] As shown in FIGS. 2, 4, 5, and 10, each of the multiple semiconductor chips 10B is mounted on a support substrate 20 (a conductive substrate 22B described later). The multiple semiconductor chips 10B are aligned in the y direction and spaced apart from one another. When each semiconductor chip 10B is mounted on the conductive substrate 22B, the back surface 11b of the element faces the conductive substrate 22B. As shown in FIG. 10, each semiconductor chip 10B is bonded to the support substrate 20 (conductive substrate 22B) via a conductive bonding material 100B. The third electrode layer 123 of each semiconductor chip 10B is electrically connected to the support substrate 20 (conductive substrate 22B) via the conductive bonding material 100B. The conductive bonding material 100B is made of the same material as the conductive bonding material 100A. The conductive bonding materials 100A and 100B may be collectively referred to as the conductive bonding material 100. The multiple semiconductor chips 10A and the multiple semiconductor chips 10B are alternately arranged when viewed in the x direction. Each semiconductor chip 10A and each semiconductor chip 10B may be arranged to overlap each other when viewed in the x direction.

[0027] The support substrate 20 is a member that supports a plurality of semiconductor chips 10. The support substrate 20 includes an insulating substrate 21, a plurality of conductive substrates 22, a pair of insulating layers 23A and 23B, a pair of gate layers 24A and 24B, a pair of detection layers 25A and 25B, and a plurality of block materials 29.

[0028] As shown in FIGS. 2, 4, 10, and 11, insulating substrate 21 has a plurality of conductive substrates 22 arranged thereon. Insulating substrate 21 has electrical insulation properties. The insulating substrate 21 is made of, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al2O3 (aluminum oxide). As shown in FIG. 4, insulating substrate 21 has, for example, a rectangular shape in plan view. Insulating substrate 21 has the shape of a single flat plate. In this embodiment, insulating substrate 21 corresponds to the "insulating member" recited in the claims.

[0029] As shown in FIGS. 10 and 11 , the insulating substrate 21 has a main surface 211 and a back surface 212. The main surface 211 and the back surface 212 are spaced apart in the z direction. The main surface 211 faces the z2 direction, and the back surface 212 faces the z1 direction. A plurality of conductive substrates 22 are arranged on the main surface 211. A heat sink (not shown) or the like can be connected to the back surface 212. The main surface 211, along with the plurality of conductive substrates 22 and the plurality of semiconductor chips 10, is covered by a resin member 7, and the back surface 212 is exposed from the resin member 7. Note that the configuration of the insulating substrate 21 is not limited to that described above, and the insulating substrate 21 may be provided individually for each of the plurality of conductive substrates 22. In this embodiment, the main surface 211 corresponds to the "main surface of an insulating member" recited in the claims.

[0030] Each of the plurality of conductive substrates 22 is a plate-shaped member having electrical conductivity. The constituent material of each conductive substrate 22 is copper or a copper alloy. That is, each conductive substrate 22 is a copper substrate. Alternatively, each conductive substrate 22 may be a composite substrate having a graphite substrate and copper material formed on both sides of the graphite substrate in the z direction. The surface of each conductive substrate 22 may be covered with silver plating. The plurality of conductive substrates 22, together with the plurality of terminals 40, form conduction paths to the plurality of semiconductor chips 10. The plurality of conductive substrates 22 are spaced apart from one another and are each disposed on the main surface 211 of the insulating substrate 21.

[0031] The multiple conductive substrates 22 include a conductive substrate 22A and a conductive substrate 22B. As shown in Figures 2, 4, 10, and 11, the conductive substrates 22A and 22B are spaced apart from each other in the x-direction and are arranged side by side on the main surface 211 of the insulating substrate 21. As shown in Figure 4, both the conductive substrates 22A and 22B have a rectangular shape in a plan view.

[0032] As shown in FIGS. 10 and 11, conductive substrate 22A is bonded to main surface 211 of insulating substrate 21 via bonding material 220A. Bonding material 220A may be a conductive material such as silver paste, solder, or a sintered metal material, or may be an insulating material. As shown in FIGS. 4, 10, and 11, conductive substrate 22A is located in the x2 direction relative to conductive substrate 22B. As shown in FIGS. 10 and 11, conductive substrate 22A has main surface 221A facing the z2 direction, and multiple semiconductor chips 10A are mounted on main surface 221A.

[0033] As shown in FIGS. 10 and 11, the conductive substrate 22B is bonded to the main surface 211 of the insulating substrate 21 via a bonding material 220B. The bonding material 220B may be, for example, a conductive material such as silver paste, solder, or sintered metal, or an insulating material. As shown in FIGS. 10 and 11, the conductive substrate 22B has a main surface 221B facing the z2 direction, and multiple semiconductor chips 10B are mounted on the main surface 221B. One ends of multiple lead members 5 (first leads 51, described later) are bonded to the main surface 221B, respectively.

[0034] The pair of insulating layers 23A, 23B have electrical insulation properties and are made of, for example, glass epoxy resin. As shown in FIGS. 2 and 4, the pair of insulating layers 23A, 23B are each strip-shaped and extend in the y direction. As shown in FIGS. 10 and 11, the insulating layer 23A is bonded to the main surface 221A of the conductive substrate 22A. The insulating layer 23A is located further in the x2 direction than the multiple semiconductor chips 10A. As shown in FIGS. 10 and 11, the insulating layer 23B is bonded to the main surface 221B of the conductive substrate 22B. The insulating layer 23B is located further in the x1 direction than the semiconductor chips 10B.

[0035] The pair of gate layers 24A, 24B are conductive and are made of, for example, copper or a copper alloy. As shown in FIGS. 2 and 4, the pair of gate layers 24A, 24B are each strip-shaped extending in the y direction. As shown in FIGS. 10 and 11, the gate layer 24A is disposed on the insulating layer 23A. The gate layer 24A is electrically connected to the second electrode layer 122 (gate electrode) of each semiconductor chip 10A via a wire member 6 (a gate wire 61 described later). The gate layer 24B is disposed on the insulating layer 23B as shown in FIGS. 10 and 11. The gate layer 24B is electrically connected to the second electrode layer 122 (gate electrode) of each semiconductor chip 10B via a wire member 6 (a gate wire 61 described later).

[0036] The pair of detection layers 25A, 25B are conductive and made of, for example, copper or a copper alloy. As shown in FIGS. 2 and 4, each of the pair of detection layers 25A, 25B has a strip shape extending in the y direction. As shown in FIGS. 10 and 11, the detection layer 25A is disposed on the insulating layer 23A together with the gate layer 24A. In a plan view, the detection layer 25A is located adjacent to the gate layer 24A on the insulating layer 23A and spaced apart from the gate layer 24A. In the x direction, the detection layer 25A is disposed closer to the semiconductor chips 10A than the gate layer 24A. Therefore, the detection layer 25A is located on the x1-direction side relative to the gate layer 24A. The gate layer 24A and the detection layer 25A may be disposed in the opposite direction in the x direction. The detection layer 25A is electrically connected to the first electrode layer 121 (source electrode) of each semiconductor chip 10A via a wire member 6 (a detection wire 62, described later). As shown in FIGS. 10 and 11, the detection layer 25B is disposed on the insulating layer 23B together with the gate layer 24B. In a plan view, the detection layer 25B is located next to the gate layer 24B on the insulating layer 23B and is spaced apart from the gate layer 24B. The detection layer 25B is disposed closer to the semiconductor chips 10B than the gate layer 24B. Therefore, the detection layer 25B is located on the x2 direction side of the gate layer 24B. Note that the arrangement of the gate layer 24B and the detection layer 25B in the x direction may be reversed. The detection layer 25B is electrically connected to the first electrode layer 121 (source electrode) of each semiconductor chip 10B via a wire member 6 (a detection wire 62 described later).

[0037] As shown in FIGS. 2 and 10 , the plurality of blocks 29 are interposed between a portion of the input terminal 42 and the conductive substrate 22A. Each block 29 is a spacer that fills the gap in the z direction between the input terminal 42 (extension 421b, described later) and the conductive substrate 22A. Each block 29 has electrical insulation properties and is made of, for example, ceramic. Each block 29 has, for example, a rectangular columnar shape in plan view. The shape of each block 29 is not limited and may be circular or polygonal in plan view. Each block 29 is bonded to the main surface 221A of the conductive substrate 22A by a bonding material (not shown), and the input terminal 42 (extension 421b) is bonded to the block 29 by a bonding material (not shown).

[0038] The plurality of metal plates 31 are respectively interposed between each semiconductor chip 10 and each lead member 5. Each metal plate 31 is rectangular in plan view. Each metal plate 31 is smaller than each semiconductor chip 10 in plan view and overlaps each semiconductor chip 10. The z-direction dimension of each metal plate 31 is smaller than the z-direction dimension of the semiconductor element 11. The z-direction dimension of each metal plate 31 is, for example, approximately 0.03 to 0.2 mm. Each metal plate 31 is made of a metal containing, for example, copper. A portion of each lead member 5 is welded to each metal plate 31. The first electrode layer 121 of each semiconductor chip 10 and each lead member 5 are electrically connected via each metal plate 31.

[0039] The multiple metal plates 31 include multiple metal plates 31A and multiple metal plates 31B. Each metal plate 31A is disposed on a corresponding semiconductor chip 10A. Each metal plate 31A is conductively bonded to the first electrode layer 121 of the corresponding semiconductor chip 10A via a conductive bonding material 310A. Each metal plate 31B is disposed on a corresponding semiconductor chip 10B. Each metal plate 31B is conductively bonded to the first electrode layer 121 of the corresponding semiconductor chip 10B via a conductive bonding material 310B. The conductive bonding materials 310A and 310B are both made of a material such as sintered metal. Note that the material is not limited to sintered metal and may be Ag paste, solder, or the like. The conductive bonding materials 310A and 310B may be collectively referred to as conductive bonding material 310.

[0040] 12, each metal plate 31 has a main surface 311 and a back surface 312. The main surface 311 and the back surface 312 are spaced apart in the z direction. The main surface 311 faces the z2 direction, and the back surface 312 faces the z1 direction. The main surface 311 contacts a part of the lead member 5 (first bonding portions 511, 521, which will be described later). The back surface 312 contacts the conductive bonding material 310 and faces each semiconductor chip 10.

[0041] The two input terminals 41 and 42 are each a metal plate-shaped member. The metal is, for example, copper or a copper alloy. The dimension of each of the two input terminals 41 and 42 in the z direction is, for example, approximately 0.8 mm. As shown in FIGS. 4 and 6, the two input terminals 41 and 42 are both located toward the x2 direction in the semiconductor device A1. A power supply voltage, for example, is applied between the two input terminals 41 and 42. The power supply voltage may be applied to the input terminals 41 and 42 directly from a power supply (not shown), or may be applied via a bus bar (not shown) connected to sandwich the input terminals 41 and 42. A snubber circuit or the like may also be connected in parallel. The input terminal 41 is a positive terminal (P terminal), and the input terminal 42 is a negative terminal (N terminal). The input terminal 42 is spaced apart from both the input terminal 41 and the conductive substrate 22A in the z direction.

[0042] As shown in FIGS. 4 and 10, the input terminal 41 has a pad portion 411 and a terminal portion 412.

[0043] The pad portion 411 is a portion of the input terminal 41 that is covered with the resin member 7. The end of the pad portion 411 on the x1 direction side is comb-shaped and includes a plurality of comb-tooth portions 411a. The pad portion 411 may be rectangular in plan view without including the plurality of comb-tooth portions 411a. Each of the plurality of comb-tooth portions 411a is conductively joined to the main surface 221A of the conductive substrate 22A. The method for joining each comb-tooth portion 411a to the conductive substrate 22A is not particularly limited, and may be, for example, welding using a laser beam (hereinafter referred to as "laser welding"), ultrasonic bonding, or bonding using a conductive bonding material.

[0044] Terminal portion 412 is a portion of input terminal 41 that is exposed from resin member 7. As shown in Fig. 4, Fig. 6, and Fig. 10, terminal portion 412 extends in the x2 direction from resin member 7 in plan view. Note that the surface of terminal portion 412 may be plated with silver, for example.

[0045] As shown in FIGS. 4 and 10, the input terminal 42 has a pad portion 421 and a terminal portion 422.

[0046] The pad portion 421 is a portion of the input terminal 42 that is covered with the resin member 7. The pad portion 421 includes a connecting portion 421a and multiple extending portions 421b. The connecting portion 421a is strip-shaped and extends in the y direction. The connecting portion 421a is connected to the terminal portion 422. The multiple extending portions 421b are strip-shaped and extend from the connecting portion 421a in the x1 direction. The multiple extending portions 421b are aligned in the y direction and spaced apart from each other in a plan view. A tip portion of each extending portion 421b overlaps a corresponding block material 29 in a plan view. The tip portion is joined to the corresponding block material 29 by a joining material (not shown). The tip portion is an edge portion of the extending portion 421b on the x1 direction side, opposite the side connected to the connecting portion 421a in the x direction. The joining of each extension 421b and each block 29 is not limited to joining using a joining material, but may be laser welding, ultrasonic joining, or the like.

[0047] The terminal portion 422 is a portion of the input terminal 42 that is exposed from the resin member 7. As shown in FIGS. 4, 6, and 10, the terminal portion 422 extends in the x2 direction from the resin member 7 in a plan view. The terminal portion 422 has a rectangular shape in a plan view. As shown in FIG. 4, the terminal portion 422 overlaps the terminal portion 412 of the input terminal 41 in a plan view. The terminal portion 422 is spaced apart from the terminal portion 412 in the z2 direction. The shape of the terminal portion 422 is the same as the shape of the terminal portion 412. The surface of the terminal portion 422 may be silver-plated, for example.

[0048] The output terminal 43 is a metal plate-shaped member. The metal is, for example, copper or a copper alloy. As shown in FIGS. 2, 4, 6, 10, and 11, the output terminal 43 is located closer to the x1 direction in the semiconductor device A1. In other words, the output terminal 43 is located on the opposite side of the input terminals 41 and 42 in the x direction. The AC power (voltage) converted by the multiple semiconductor chips 10 is output from the output terminal 43.

[0049] As shown in FIGS. 4 and 10, the output terminal 43 includes a pad portion 431 and a terminal portion 432.

[0050] The pad portion 431 is a portion of the output terminal 43 that is covered with the resin member 7. A portion of the pad portion 431 on the x2 direction side is comb-shaped and includes a plurality of comb tooth portions 431a. Note that the pad portion 431 may be rectangular in plan view without including the plurality of comb tooth portions 431a. Each of the plurality of comb tooth portions 431a is conductively joined to the main surface 221B of the conductive substrate 22B. The method of joining each comb tooth portion 431a to the conductive substrate 22B is the same as the method of joining each comb tooth portion 411a to the conductive substrate 22A.

[0051] The terminal portion 432 is a portion of the output terminal 43 that is exposed from the resin member 7. As shown in Figures 2, 3, 4, 6, 7, 10 and 11, the terminal portion 432 extends from the resin member 7 in the x1 direction. Note that the surface of the terminal portion 432 may be plated with silver, for example.

[0052] 1 to 7, a pair of gate terminals 44A, 44B are located adjacent to each conductive substrate 22A, 22B in the y direction. A gate voltage for driving the plurality of semiconductor chips 10A is applied to the gate terminal 44A. A gate voltage for driving the plurality of semiconductor chips 10B is applied to the gate terminal 44B.

[0053] As shown in FIGS. 4 and 5, each of the pair of gate terminals 44A, 44B has a pad portion 441 and a terminal portion 442. In each of the gate terminals 44A, 44B, the pad portion 441 is covered with a resin member 7. As a result, each of the gate terminals 44A, 44B is supported by the resin member 7. The surface of the pad portion 441 may be plated with silver, for example. The terminal portion 442 is connected to the pad portion 441 and is exposed from the resin member 7. The terminal portion 442 is L-shaped when viewed in the x direction.

[0054] 1 to 7, the pair of detection terminals 45A, 45B are located adjacent to the pair of gate terminals 44A, 44B in the x direction. The detection terminal 45A detects the voltage (voltage corresponding to the source current) applied to the first electrode layer 121 of each semiconductor element 11 of the multiple semiconductor chips 10A. The detection terminal 45B detects the voltage (voltage corresponding to the source current) applied to the first electrode layer 121 of each semiconductor element 11 of the multiple semiconductor chips 10B.

[0055] As shown in FIGS. 4 and 5, each of the pair of detection terminals 45A, 45B has a pad portion 451 and a terminal portion 452. In each of the detection terminals 45A, 45B, the pad portion 451 is covered with a resin member 7. As a result, each of the detection terminals 45A, 45B is supported by the resin member 7. The surface of the pad portion 451 may be plated with silver, for example. The terminal portion 452 is connected to the pad portion 451 and is exposed from the resin member 7. The terminal portion 452 is L-shaped when viewed in the x direction.

[0056] As shown in FIGS. 1 to 7, the multiple dummy terminals 46 are located on the opposite side of the pair of gate terminals 44A, 44B with respect to the pair of detection terminals 45A, 45B in the x direction. In this embodiment, there are six dummy terminals 46. Three of the dummy terminals 46 are located on one side of the x direction (x2 direction). The remaining three dummy terminals 46 are located on the other side of the x direction (x1 direction). The multiple dummy terminals 46 are not limited to the configuration described above. Also, a configuration without multiple dummy terminals 46 is also possible.

[0057] As shown in FIGS. 4 and 5 , each of the multiple dummy terminals 46 has a pad portion 461 and a terminal portion 462. In each dummy terminal 46, the pad portion 461 is covered with the resin member 7. As a result, the multiple dummy terminals 46 are supported by the resin member 7. The surface of the pad portion 461 may be silver-plated, for example. The terminal portion 462 is connected to the pad portion 461 and is exposed from the resin member 7. The terminal portion 462 is L-shaped when viewed in the x-direction. The shape of the terminal portion 462 is the same as the shape of each terminal portion 442 of the pair of gate terminals 44A, 44B and the shape of each terminal portion 452 of the pair of detection terminals 45A, 45B.

[0058] As shown in FIG. 4 , the pair of side terminals 47A, 47B are edge portions of the resin member 7 on the y1-direction side in plan view and overlap with respective edge portions of the resin member 7 in the x direction. The side terminal 47A is bonded to the conductive substrate 22A and is covered by the resin member 7 except for an end face facing the x2 direction. The side terminal 47B is bonded to the conductive substrate 22B and is covered by the resin member 7 except for an end face facing the x1 direction. In this embodiment, the entire side terminals 47A, 47B overlap with the resin member 7 in plan view. The side terminals 47A, 47B are bonded to the conductive substrates 22A, 22B, respectively, by laser welding using a laser beam. Note that the bonding between the side terminal 47A and the conductive substrate 22A and the bonding between the side terminal 47B and the conductive substrate 22B may be performed by ultrasonic bonding or by using a conductive bonding material instead of laser welding. Each of the side terminals 47A, 47B is partially bent in a plan view, and partially bent in the z direction. The configuration of each of the side terminals 47A, 47B is not limited to this, and for example, each of the side terminals 47A, 47B may extend to protrude from the resin member 7 in a plan view. Furthermore, the semiconductor device A1 may not include each of the side terminals 47A, 47B.

[0059] 1 to 7, the pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, and the plurality of dummy terminals 46 are arranged along the x direction in a plan view. In the semiconductor device A1, the pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, the plurality of dummy terminals 46, and the pair of side terminals 47A, 47B are all formed from the same lead frame.

[0060] The insulating plate 49 has electrical insulation properties and is made of, for example, insulating paper. A portion of the insulating plate 49 is flat and is sandwiched in the z direction between the terminal portion 412 of the input terminal 41 and the terminal portion 422 of the input terminal 42, as shown in FIGS. 4, 6, 9, 10, and 11. In a plan view, the entire input terminal 41 overlaps the insulating plate 49. In addition, in a plan view, a portion of the pad portion 421 and the entire terminal portion 422 of the input terminal 42 overlap the insulating plate 49. The two input terminals 41 and 42 are insulated from each other by the insulating plate 49. A portion of the insulating plate 49 (the portion on the x1 direction side) is covered with the resin member 7.

[0061] 4 and 10, insulating plate 49 has an intervening portion 491 and an extending portion 492. Intervening portion 491 is interposed in the z direction between terminal portion 412 of input terminal 41 and terminal portion 422 of input terminal 42. Intervening portion 491 is entirely sandwiched between terminal portion 412 and terminal portion 422. Extended portion 492 extends from intervening portion 491 in the x2 direction further than terminal portion 412 and terminal portion 422.

[0062] Each of the plurality of lead members 5 is electrically conductive. The constituent material of each lead member 5 is, for example, a metal containing copper. Each lead member 5 is joined to the semiconductor chip 10 (first electrode layer 121) via each metal plate 31. Each lead member 5 can be formed by bending a strip-shaped metal plate having a thickness of, for example, about 0.05 to 0.2 mm. As shown in FIGS. 2, 4, 5, 10, and 11, the plurality of lead members 5 include a plurality of first leads 51 and a plurality of second leads 52.

[0063] 2, 4, 5, and 11, each of the plurality of first leads 51 connects a corresponding semiconductor chip 10A to the conductive substrate 22B. Each first lead 51 includes a first bonding portion 511, a second bonding portion 512, and a connecting portion 513.

[0064] The first bonding portion 511 is bonded to a metal plate 31A that is bonded to the first electrode layer 121 of the semiconductor chip 10A. The first bonding portion 511 is bonded to the metal plate 31A by laser welding. The first bonding portion 511 is electrically connected to the first electrode layer 121 of the semiconductor chip 10A via the metal plate 31A. A plurality of welding marks 8 are formed in the first bonding portion 511 in a planar view. The plurality of welding marks 8 formed in the first bonding portion 511 are arranged in a matrix in a planar view.

[0065] The second bonding portion 512 is bonded to the conductive substrate 22B. The second bonding portion 512 is bonded to the conductive substrate 22B by laser welding. The laser welding method is the same as that used for the first bonding portion 511. A plurality of welding marks 8 are formed in the second bonding portion 512 in a plan view. The plurality of welding marks 8 formed in the second bonding portion 512 are arranged in a matrix pattern in a plan view. Note that the second bonding portion 512 and the conductive substrate 22B may be bonded not by laser welding but by, for example, a conductive bonding material such as silver paste or solder, or by ultrasonic bonding.

[0066] The connecting portion 513 is a portion that connects the first bonding portion 511 and the second bonding portion 512. A portion of the connecting portion 513 is bent in the z direction. The bending of the connecting portion 513 changes the position of the first bonding portion 511 and the position of the second bonding portion 512 in the z direction.

[0067] In this embodiment, the first lead 51 corresponds to the "connection member" in the claims. In this case, the semiconductor element 11 of the semiconductor chip 10A corresponds to the "semiconductor element" in the claims, the metal plate 31A corresponds to the "electrode member" in the claims, the conductive substrate 22A corresponds to the "first conductive member" in the claims, and the conductive substrate 22B corresponds to the "second conductive member" in the claims.

[0068] 2, 4, 5, and 10, each of the plurality of second leads 52 connects the semiconductor chip 10B to the input terminal 42. Each second lead 52 includes a first joint portion 521, a second joint portion 522, and a connecting portion 523.

[0069] The first bonding portion 521 is bonded to a metal plate 31 bonded to the first electrode layer 121 of the semiconductor chip 10B. The first bonding portion 521 is electrically connected to the first electrode layer 121 of the semiconductor chip 10B via the metal plate 31. A plurality of welding marks 8 are formed in the first bonding portion 521 in a planar view. The plurality of welding marks 8 formed in the first bonding portion 521 are arranged in a matrix in a planar view.

[0070] The second joint portion 522 is joined to the extending portion 421b of the input terminal 42. The second joint portion 522 is joined to the extending portion 421b by laser welding. The laser welding method is the same as that used for the first joint portion 511. A plurality of weld marks 8 are formed in the second joint portion 522 in a plan view. The plurality of weld marks 8 formed in the second joint portion 522 are arranged in a matrix pattern in a plan view. Note that the second joint portion 522 and the extending portion 421b (input terminal 42) may not be joined by laser welding, but may instead be joined by a conductive joining material such as silver paste or solder, or by ultrasonic joining.

[0071] The connecting portion 523 is a portion that connects the first joint portion 521 and the second joint portion 522. A portion of the connecting portion 523 is bent in the z direction. The bending of the connecting portion 523 changes the position of the first joint portion 521 and the position of the second joint portion 522 in the z direction.

[0072] In this embodiment, the second lead 52 also corresponds to the "connection member" in the claims. In this case, the semiconductor element 11 of the semiconductor chip 10B corresponds to the "semiconductor element" in the claims, the metal plate 31B corresponds to the "electrode member" in the claims, the conductive substrate 22B corresponds to the "first conductive member" in the claims, and the input terminal 42 corresponds to the "second conductive member" in the claims.

[0073] Each of the plurality of wire members 6 is a so-called bonding wire. Each wire member 6 is electrically conductive and is made of, for example, aluminum, gold, or copper. As shown in FIGS. 4 and 5 , the plurality of wire members 6 include a plurality of gate wires 61, a plurality of detection wires 62, a pair of first connecting wires 63, and a pair of second connecting wires 64.

[0074] 4 and 5, one end of each of the plurality of gate wires 61 is joined to the second electrode layer 122 (gate electrode) of each semiconductor chip 10, and the other end is joined to one of the pair of gate layers 24A, 24B. Among the plurality of gate wires 61, there are those that connect the second electrode layer 122 and gate layer 24A of each semiconductor chip 10A electrically, and those that connect the second electrode layer 122 and gate layer 24B of each semiconductor chip 10B electrically.

[0075] 4 and 5, one end of each of the plurality of detection wires 62 is joined to the first electrode layer 121 (source electrode) of each semiconductor chip 10, and the other end is joined to one of the pair of detection layers 25A, 25B. The plurality of detection wires 62 include those that connect the first electrode layer 121 of each semiconductor chip 10A to the detection layer 25A, and those that connect the first electrode layer 121 of each semiconductor chip 10B to the detection layer 25B.

[0076] 4 and 5, one of the pair of first connecting wires 63 connects the gate layer 24A and the gate terminal 44A, and the other connects the gate layer 24B and the gate terminal 44B. One of the first connecting wires 63 has one end joined to the gate layer 24A and the other end joined to the pad portion 441 of the gate terminal 44A, providing electrical continuity therebetween. The other first connecting wire 63 has one end joined to the gate layer 24B and the other end joined to the pad portion 441 of the gate terminal 44B, providing electrical continuity therebetween.

[0077] 4 and 5, one of the pair of second connecting wires 64 connects the detection layer 25A and the detection terminal 45A, and the other connects the detection layer 25B and the detection terminal 45B. One second connecting wire 64 has one end joined to the detection layer 25A and the other end joined to the pad portion 451 of the detection terminal 45A, providing electrical continuity therebetween. The other second connecting wire 64 has one end joined to the detection layer 25B and the other end joined to the pad portion 451 of the detection terminal 45B, providing electrical continuity therebetween.

[0078] The resin member 7 is a semiconductor encapsulant in the semiconductor device A1. As shown in FIGS. 1 to 4 and 6 to 11, the resin member 7 covers the multiple semiconductor chips 10, the support substrate 20 (excluding the back surface 212 of the insulating substrate 21), the multiple metal plates 31, a portion of each of the multiple terminals 40, a portion of the insulating plate 49, the multiple lead members 5, and the multiple wire members 6. The resin member 7 is made of, for example, epoxy resin. As shown in FIGS. 1 to 4 and 6 to 11, the resin member 7 has a resin main surface 71, a resin back surface 72, and multiple resin side surfaces 731 to 734.

[0079] The resin main surface 71 and the resin back surface 72 are spaced apart in the z direction. The resin main surface 71 is the upper surface of the resin member 7 and faces the z2 direction. The resin back surface 72 is the lower surface of the resin member 7 and faces the z1 direction. As shown in FIG. 7 , the resin back surface 72 has a frame shape surrounding the back surface 212 of the insulating substrate 21 in a plan view. Each of the multiple resin side surfaces 731 to 734 is connected to both the resin main surface 71 and the resin back surface 72 and is sandwiched between them. The two resin side surfaces 731, 732 are spaced apart in the x direction. The resin side surface 731 faces the x1 direction, and the resin side surface 732 faces the x2 direction. The two resin side surfaces 733, 734 are spaced apart in the y direction. The resin side surface 733 faces the y1 direction, and the resin side surface 734 faces the y2 direction.

[0080] 1, 6, and 7, the resin member 7 includes a plurality of recesses 75 each recessed in the z direction from the resin back surface 72. Note that the plurality of recesses 75 does not necessarily have to be formed. Each of the plurality of recesses 75 extends in the y direction and is connected from the edge of the resin back surface 72 in the y1 direction to the edge of the resin back surface 72 in the y2 direction in a plan view. In the semiconductor device A1, the plurality of recesses 75 are formed in groups of three on either side of the back surface 212 of the insulating substrate 21 in the x direction, as shown in FIG.

[0081] Each welding mark 8 is formed by laser welding, which will be described later. Fig. 13 is a schematic plan view showing the welding mark 8. Fig. 14 is a schematic cross-sectional view showing the welding mark 8. Note that Fig. 14 shows the welding mark 8 formed in the joint portion between the first joint portion 511 of the first lead 51 and the metal plate 31, but welding marks 8 formed in other portions also have the following characteristics.

[0082] As shown in FIG. 13 , the weld mark 8 has a circular shape in a plan view. The upper surface 81 of the weld mark 8 facing the z2 direction has a ripple-like pattern. As shown in FIG. 14 , multiple peaks 811 and multiple valleys 812 are formed concentrically and alternately on the upper surface 81 of the weld mark 8. Note that FIG. 13 shows a case where the outer periphery 813 of the weld mark 8 and the ripple pattern (peaks 811 and valleys 812) are perfectly circular, but some distortion or bending due to laser welding may occur. As shown in FIG. 14 , the center of the weld mark 8 in a plan view is the peak 811, which protrudes in the z2 direction. The edge (lower end 82) of the weld mark 8 in the z1 direction overlaps the metal plate 31 when viewed in a direction perpendicular to the z direction. Therefore, the lower end 82 is located between the main surface 311 and the back surface 312 in the z direction.

[0083] Next, a method of joining each lead member 5 to each semiconductor chip 10 using laser welding will be described. In the semiconductor device A1, this joining method is used when joining the first lead 51 to the semiconductor chip 10A and when joining the second lead 52 to the semiconductor chip 10B. It is also used when joining the first lead 51 to the conductive substrate 22B and when joining the second lead 52 to the input terminal 42.

[0084] First, each metal plate 31 is bonded onto each semiconductor chip 10. In bonding the metal plate 31, each metal plate 31 is bonded to the first electrode layer 121 of each semiconductor chip 10 using a conductive bonding material 310. The conductive bonding material 310 may be applied to the first electrode layer 121 of each semiconductor chip 10, or may be laminated onto each metal plate 31. Bonding of each metal plate 31 may be performed before or after mounting each semiconductor chip 10 on each conductive substrate 22. By the process of bonding each metal plate 31, each metal plate 31 is electrically connected to the first region 111 of the semiconductor element 11 of each semiconductor chip 10. Furthermore, since the first electrode layer 121 is formed on the element main surface 11a of the semiconductor element 11, each metal plate 31 is disposed on the element main surface 11a.

[0085] Next, each lead member 5 is bonded to each metal plate 31. In this bonding, first, each lead member 5 is placed on each metal plate 31. Then, in the area where each lead member 5 and each metal plate 31 overlap in a plan view, each lead member 5 and each metal plate 31 are bonded by laser welding. In this way, each lead member 5 and each metal plate 31 are welded and bonded to each metal plate 31.

[0086] By going through the first and second steps described above, each lead member 5 is bonded to the first electrode layer 121 of each semiconductor chip 10 via each metal plate 31.

[0087] Next, laser welding according to this embodiment will be described. The laser welding is performed using, for example, the following laser irradiation device LD (see FIG. 15). The laser welding is spot welding.

[0088] Fig. 15 shows an example of the laser irradiation device LD. As shown in Fig. 15, the laser irradiation device LD includes laser oscillators 91A and 91B, optical fibers 92A and 92B, a dichroic mirror 93, a condenser lens 94, an optical fiber 95, a collimation lens 96, and a condenser lens 97.

[0089] Both laser oscillators 91A and 91B generate laser light. The laser oscillator 91A oscillates a first laser light. The first laser light is a green laser with a wavelength of about 532 nm. The laser oscillator 91B oscillates a second laser light. The second laser light is an infrared laser with a wavelength of about 1064 nm. When the wavelength of the second laser light is the fundamental wavelength, the wavelength of the first laser light is half the wavelength of the second laser light. The first laser light is multimode and has a beam propagation ratio M 2 is, for example, about 1.6 to 3.5. The laser light of 2 is multimode and has a beam propagation ratio M 2 For example, it is about 2.4 to 6.0 is.

[0090] The optical fiber 92A transmits the first laser light oscillated from the laser oscillator 91A. The first laser light transmitted by the optical fiber 92A is emitted to the dichroic mirror 93. The optical fiber 92B transmits the second laser light oscillated from the laser oscillator 91B. The second laser light transmitted by the optical fiber 92B is emitted to the dichroic mirror 93.

[0091] The dichroic mirror 93 is, for example, a mirror that transmits light in a specific wavelength range and reflects the remaining wavelength range. The dichroic mirror 93 reflects the first laser light and transmits the second laser light. Note that the dichroic mirror 93 may be configured to transmit the first laser light and reflect the second laser light.

[0092] The condenser lens 94 is a lens that condenses each laser beam incident from the dichroic mirror 93. The optical fiber 95 transmits the laser beam incident from the condenser lens 94. Each laser beam transmitted by the optical fiber 95 is emitted to the collimation lens 96. The collimation lens 96 is a lens that collimates (converts into parallel light) each laser beam incident from the optical fiber 95. The condenser lens 97 is a lens that condenses each laser beam incident from the collimation lens 96. Each laser beam condensed by the condenser lens 97 is irradiated onto an irradiation target 99.

[0093] The laser irradiation device LD is adjusted so that the focal point of the first laser light substantially coincides with the surface 99a of the irradiation target 99. The focal point of the second laser light is located slightly inside the irradiation target 99 from the surface 99a. The irradiation target 99 in this embodiment is a portion of the first lead 51 overlapping with the metal plate 31A, a portion of the first lead 51 overlapping with the conductive substrate 22B, a portion of the second lead 52 overlapping with the metal plate 31B, and a portion of the second lead 52 overlapping with the input terminal 42. The beam diameter of the first laser light is, for example, approximately 0.15 to 0.25 mm, and the beam diameter of the second laser light is, for example, approximately 0.4 to 0.8 mm.

[0094] In the laser welding of this embodiment, the laser irradiation device LD is adjusted so that the first laser beam and the second laser beam have the output waveforms shown in FIG. 16. FIG. 16 is a timing chart showing the output waveforms of the first laser beam and the second laser beam. In FIG. 16, waveform W1 shows the output waveform of the first laser beam emitted from the laser irradiation device LD, and waveform W1' shows the output waveform of the first laser beam absorbed by the irradiation target 99. Furthermore, waveform W2 shows the output waveform of the second laser beam emitted from the laser irradiation device LD, and waveform W2' shows the output waveform of the second laser beam absorbed by the irradiation target 99. As described above, the irradiation target 99 is, for example, the lead member 5.

[0095] As shown by waveforms W1 and W2 in FIG. 16, the outputs of the first laser beam and the second laser beam are both rectangular pulse waves.

[0096] The output P1 of the first laser beam emitted from the laser irradiation device LD (see waveform W1) is smaller than the output P2 of the second laser beam emitted from the laser irradiation device LD (see waveform W2) (P1 < P2). For example, the output P1 of the first laser beam is about 1.0 to 1.2 kW, and the output P2 of the second laser beam is about 1.5 to 2.5 kW. However, not all of the first laser beam irradiated from the laser irradiation device LD onto the irradiation target 99 is absorbed by the irradiation target 99, and a part of it is reflected by the irradiation target 99. Therefore, the output (intensity) P1' of the first laser beam absorbed by the irradiation target 99 decreases compared to the output P1 of the first laser beam (see waveform W1'). For example, when the irradiation target 99 is Cu, the first laser beam absorbed by the irradiation target 99 is about 45% of the first laser beam emitted from the laser irradiation device LD. Similarly, not all of the second laser beam irradiated from the laser irradiation device LD onto the irradiation target 99 is absorbed by the irradiation target 99, and a part of it is reflected by the irradiation target 99. Therefore, the output (intensity) P2' of the second laser beam absorbed by the irradiation target 99 decreases compared to the output P2 of the second laser beam (see waveform W2'). For example, when the irradiation target 99 is Cu, the second laser beam absorbed by the irradiation target 99 is about 10% of the second laser beam emitted from the laser irradiation device LD. In the present embodiment, as shown in FIG. 16, the output (intensity) P1' of the first laser beam absorbed by the irradiation target 99 is larger than the output (intensity) P2' of the second laser beam absorbed by the irradiation target 99 (P1' > P2').

[0097] The output time (irradiation time) T1 of the first laser beam is shorter than the output time (irradiation time) T2 of the second laser beam (T1 < T2). For example, the output time T1 of the first laser beam is about 1.0 to 1.3 ms, and the output time T2 of the second laser beam is about 5 to 15 ms.

[0098] The second laser beam is irradiated after the first laser beam. That is, the second laser beam is irradiated after a predetermined delay time Td has elapsed since the first laser beam was irradiated. For example, the delay time Td is about 0.1 to 0.6 ms.

[0099] The second laser beam is irradiated while the first laser beam is being irradiated (T1>Td). Therefore, there is a period during which the first laser beam and the second laser beam are irradiated simultaneously. Note that the second laser beam may be irradiated after the irradiation of the first laser beam has ended (T1<Td). In this case, unlike the waveform shown in FIG. 16, there is no period during which the first laser beam and the second laser beam are irradiated simultaneously.

[0100] As described above, when the first laser beam and the second laser beam of the output waveform shown in FIG. 16 are irradiated, first, the first laser beam is irradiated onto the lead member 5, and melting of the lead member 5 starts at the portion irradiated with the first laser beam. As a result, a molten pool in which a part of the lead member 5 is melted is formed. When the first laser beam is irradiated, a wavy pattern is formed on the surface of the molten pool. Subsequently, while the first laser beam is being irradiated, irradiation of the second laser beam is started, and the molten pool advances downward. As a result, the molten pool reaches the metal plate 31 from the lead member 5. At this time, the molten pool continues to melt downward while maintaining the wavy pattern formed on the surface. Subsequently, irradiation of the first laser beam is stopped. At this time, even when the irradiation of the first laser beam is stopped, melting continues due to the irradiation of the second laser beam. Thereafter, when the irradiation of the second laser beam is stopped, the molten pool is cooled and solidified, and melting ends. As a result, the lead member 5 is welded to the metal plate 31, and a weld mark 8 is formed at this welding portion (the portion irradiated with the laser beam). At this time, the wavy pattern formed on the surface of the molten pool appears as it is on the surface of the weld mark 8.

[0101] In the present embodiment, the first lead 51 (the second joint portion 512) and the conductive substrate 22B, and the second lead 52 (the second joint portion 522) and the input terminal 42 (the extended portion 421b) are also joined by the laser welding by the laser irradiation device LD.

[0102] The operation and effect of the semiconductor device A1 according to the first embodiment are as follows.

[0103] The semiconductor device A1 includes a semiconductor element 11, a metal plate 31, and a lead member 5. The semiconductor element 11 has a first region 111 (e.g., a source region) formed on the element principal surface 11a in the z direction. The metal plate 31 is disposed on the element principal surface 11a and is electrically connected to the first region 111. The lead member 5 is joined to the metal plate 31 by laser welding. With this configuration, the lead member 5 is electrically connected to the first region 111 of the semiconductor element 11 via the metal plate 31. Therefore, by laser welding the lead member 5 to the metal plate 31, the lead member 5 and the first region 111 of the semiconductor element 11 are electrically connected. In other words, the lead member 5 and the semiconductor element 11 (first region 111) can be electrically connected without ultrasonic bonding. As a result, pressure, vibration, and the like are not applied to the semiconductor element 11 during ultrasonic bonding, and damage to the semiconductor element 11 can be suppressed. This improves the reliability of the semiconductor device A1.

[0104] The semiconductor device A1 includes an element electrode 12. The element electrode 12 includes a first electrode layer 121 that is in ohmic contact with the first region 111 of the semiconductor element 11. The first electrode layer 121 is an electrode pad on the semiconductor chip 10, and a metal plate 31 is bonded to the first electrode layer 121 via a conductive bonding material 310. With this configuration, bonding the metal plate 31 to the first electrode layer 121 with the conductive bonding material 310 establishes electrical continuity between the metal plate 31 and the first electrode layer 121. In other words, electrical continuity between the metal plate 31 and the first electrode layer 121 can be established without ultrasonic bonding. This can prevent damage to the semiconductor element 11 even when the first electrode layer 121 and the metal plate 31 are bonded together. Therefore, the reliability of the semiconductor device A1 can be improved.

[0105] In the semiconductor device A1, the metal plate 31 and the first electrode layer 121 are bonded together with a conductive bonding material 310, which is a sintered metal (e.g., sintered silver). Bonding using sintered metal has higher durability in terms of heat resistance, pressure resistance, and impact resistance than bonding using solder. This configuration can prevent damage to the conductive bonding material 310 or peeling of the conductive bonding material 310. Therefore, the reliability of the semiconductor device A1 can be improved.

[0106] According to the semiconductor device A1, the first joint portion 511 of the first lead 51 (lead member 5) is laser-welded to the metal plate 31A, forming a weld mark 8. A lower end 82 of the weld mark 8 overlaps the metal plate 31A when viewed in a direction perpendicular to the z-direction. In other words, the weld mark 8 does not penetrate the metal plate 31A in the z-direction. The same applies to the first joint portion 521 of the second lead 52 (lead member 5). With this configuration, when the lead member 5 is laser-welded to the metal plate 31, a molten pool formed by the irradiation of the laser light does not penetrate the metal plate 31. Therefore, the heat generated during laser welding can be prevented from being transmitted to the semiconductor element 11. This prevents damage to the semiconductor element 11 due to the heat generated during laser welding, thereby improving the reliability of the semiconductor device A1.

[0107] According to the semiconductor device A1, a plurality of welding marks 8 are formed in the first joint portion 511 of the first lead 51 (lead member 5). Therefore, when the first lead 51 (first joint portion 511) is laser-welded to the metal plate 31A, laser light is irradiated at a plurality of locations. In a semiconductor device different from the semiconductor device A1, if a single welding mark 8 is formed in the first joint portion 511, when a force perpendicular to the z-direction is applied to the first lead 51, the first lead 51 may rotate around an axis in the z-direction passing through the single welding mark 8. On the other hand, according to the semiconductor device A1, since a plurality of welding marks 8 are formed in the first joint portion 511, the rotation can be suppressed. The same applies to the second joint portion 512 of the first lead 51 (lead member 5), the first joint portion 521 of the second lead 52 (lead member 5), and the second joint portion 522 of the second lead 52 (lead member 5).

[0108] According to the semiconductor device A1, the first lead 51 (lead member 5) includes a first bonding portion 511 and a second bonding portion 512. The first bonding portion 511 and the second bonding portion 512 each have a plurality of welding marks 8 formed thereon. Therefore, the first bonding portion 511 and the second bonding portion 512 are both bonded by laser welding. The same is true for the second lead 52 (lead member 5). With this configuration, there is no need to use different bonding methods for the first bonding portion 511 (521) and the second bonding portion 512 (522), thereby improving the manufacturing efficiency of the semiconductor device A1.

[0109] In semiconductor device A1, each weld mark 8 has an upper surface 81, and the upper surface 81 has a ripple pattern formed by peaks 811 and valleys 812. The upper surface 81 is in contact with the resin member 7. With this configuration, the unevenness on the upper surface 81 of each weld mark 8 can enhance the adhesiveness of the resin member 7 by an anchor effect.

[0110] In the semiconductor device A1, the lead member 5 and the metal plate 31 are joined by laser welding. In the laser welding, a first laser beam and a second laser beam having different wavelengths are irradiated. Therefore, according to the joining method of the present disclosure, by using these two laser beams, absorption, reflection, refraction, transmission, scattering, and the like can be appropriately adjusted depending on the material of the target (lead member 5) to be irradiated with the laser beam. This allows the z-direction dimension of the metal plate 31 to be smaller than the z-direction dimension of each semiconductor element 11. Therefore, even when the metal plate 31 is provided between the lead member 5 and the first electrode layer 121, an increase in the z-direction dimension of the semiconductor device A1 can be suppressed.

[0111] According to the joining method of the present disclosure, the wavelength of the first laser light is shorter than the wavelength of the second laser light. In the semiconductor device A1, for example, the first laser light is a green laser with a wavelength of approximately 532 nm, and the second laser light is an infrared laser with a wavelength of approximately 1064 nm. In the laser welding of this embodiment, the lead member 5 and the metal plate 31, which are the objects to be joined, are both made of, for example, copper. The shorter the wavelength of the laser light, the better the laser light absorption rate of copper. For example, the absorption rate of laser light (first laser light) with a wavelength of approximately 532 nm is approximately 45%, and the absorption rate of laser light (second laser light) with a wavelength of approximately 1064 nm is approximately 10%. Therefore, in the joining method of this embodiment, laser welding can be performed using two laser lights with different absorption rates for the objects to be joined.

[0112] According to the joining method of the present disclosure, the first laser beam and the second laser beam are irradiated by the laser irradiation device LD so as to have the output waveforms shown in FIG. 16 . That is, the output of the first laser beam is greater than the output of the second laser beam. The irradiation time of the first laser beam is shorter than the irradiation time of the second laser beam. After the start of irradiation of the first laser beam, irradiation of the second laser beam starts after a delay time Td. That is, the second laser beam is irradiated later than the first laser beam. Furthermore, while the first laser beam is being irradiated, the second laser beam is irradiated. The first laser beam has a better absorption rate in the joining target (copper) than the second laser beam, but output adjustment is difficult. Therefore, when laser welding is performed using only the first laser beam, it is possible to shorten the welding time, but there is a possibility that the weld mark 8 will penetrate the metal plate 31. Furthermore, the second laser beam has a lower absorption rate in the joining target (copper) than the first laser beam, but output adjustment is easier. Therefore, if laser welding is performed using only the second laser beam, it is possible to prevent the weld mark 8 from penetrating the metal plate 31, but the welding time may be longer. On the other hand, according to the joining method of the present disclosure, melting is initiated by the first laser beam, which has a high absorption rate in the joining target (copper), and the state of the molten pool is stabilized in a short time. Then, when the molten pool is in a stable state, irradiation of the second laser beam is initiated and irradiation of the first laser beam is stopped. In this way, the progress of the molten pool is adjusted by the second laser beam. Therefore, by irradiating the first and second laser beams having the output waveforms shown in FIG. 16, efficient laser welding can be achieved while suppressing damage to the semiconductor element 11. Furthermore, by irradiating the first laser beam before the second laser beam, deterioration of welding quality, such as spatter, can be suppressed.

[0113] A semiconductor device and a bonding method according to another embodiment of the present disclosure will be described below. In the following other embodiments, components that are the same as or similar to those in the first embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0114] Second Embodiment Fig. 17 shows a semiconductor device according to a second embodiment. The semiconductor device A2 of the second embodiment is different from the semiconductor device A1 in the shape of the resin member 7. Other than that, it is the same as the semiconductor device A1. Fig. 17 is a perspective view showing the semiconductor device A2.

[0115] In this embodiment, resin member 7 has edge portions in the y direction that extend in the x direction in plan view. The portions of resin member 7 that extend in the x2 direction cover portions of two input terminals 41 and 42 and insulating plate 49. Furthermore, the portion of resin member 7 that extends in the x1 direction covers portions of output terminal 43.

[0116] According to the semiconductor device A2, similar to the semiconductor device A1, the lead member 5 is laser-welded to the metal plate 31 to establish electrical continuity between the lead member 5 and the first region 111 of the semiconductor element 11. Therefore, similar to the semiconductor device A1, the semiconductor device A2 can suppress damage to the semiconductor element 11, thereby improving reliability.

[0117] According to the semiconductor device A2, for example, it is possible to protect each of the two input terminals 41 and 42, the output terminal 43, and a part of the insulating plate 49 that protrude from the resin member 7 in the semiconductor device A1.

[0118] Third Embodiment 18 to 22 show a semiconductor device according to a third embodiment. The semiconductor device A3 of the third embodiment includes a plurality of semiconductor chips 10, a support substrate 20, a plurality of metal plates 31, a plurality of terminals 40, a plurality of lead members 5, a plurality of wire members 6, and a resin member 7. In the semiconductor device A3, the plurality of terminals 40 include input terminals 41 and 42, an output terminal 43, a pair of gate terminals 44A and 44B, a pair of detection terminals 45A and 45B, a plurality of dummy terminals 46, and a pair of source signal terminals 48A and 48B.

[0119] FIG. 18 is a plan view showing the semiconductor device A3, with the resin member 7 indicated by an imaginary line (two-dot chain line). FIG. 19 is a partially enlarged view of a portion of FIG. 18. FIG. 20 is a front view showing the semiconductor device A3, with the resin member 7 indicated by an imaginary line (two-dot chain line). Note that the wire member 6 is not shown in FIG. 20. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 18. FIG. 22 is a partially enlarged view of a portion of FIG. 21.

[0120] 18 and 19, each semiconductor chip 10 in the semiconductor device A3 includes two first electrode layers 121 insulated by an insulating film 13. Each metal plate 31 is bonded across the two first electrode layers 121 by a conductive bonding material 310. Note that each semiconductor chip 10 may be configured to include one first electrode layer 121, similar to each semiconductor chip 10 in the semiconductor device A1.

[0121] The support substrate 20 of the semiconductor device A3 has a different configuration from the support substrate 20 of the semiconductor device A1. As shown in Figures 20, 21 and 22, it includes an insulating substrate 26, a main surface metal layer 27 and a back surface metal layer 28.

[0122] The insulating substrate 26 has electrical insulation properties. The constituent material of the insulating substrate 26 is ceramics, similar to the insulating substrate 21. However, the constituent material is not limited to ceramics, and may be an insulating resin sheet or the like.

[0123] 20 and 21, the insulating substrate 26 has a main surface 261 and a back surface 262. The main surface 261 and the back surface 262 are spaced apart in the z direction. The main surface 261 faces the z2 direction, and the back surface 262 faces the z1 direction.

[0124] The main surface metal layer 27 is formed on the main surface 261 of the insulating substrate 26. The main surface metal layer 27 is made of a metal containing copper, for example. The material may be aluminum instead of copper. The main surface metal layer 27 is covered with a resin member 7. The main surface metal layer 27 includes a plurality of conductor layers 271A, 271B, 271C, a pair of gate layers 272A, 272B, a pair of detection layers 273A, 273B, a pair of source signal layers 274A, 274B, and a plurality of dummy layers 275. These are arranged spaced apart from one another.

[0125] The conductive layer 271A has a plurality of semiconductor chips 10A mounted thereon and supports the plurality of semiconductor chips 10A. A part of the input terminal 41 (pad portion 411) is joined to the conductive layer 271A.

[0126] The conductive layer 271B is joined to a part (second joint portion 522) of the plurality of second leads 52. The conductive layer 271B is joined to a part (pad portion 421) of the input terminal .

[0127] The conductive layer 271C has a plurality of semiconductor chips 10B mounted thereon and supports the plurality of semiconductor chips 10B. Parts (second bonding portions 512) of the plurality of first leads 51 are bonded to the conductive layer 271C. Parts (pad portions 431) of the output terminals 43 are bonded to the conductive layer 271C.

[0128] The pair of gate layers 272A, 272B correspond to the pair of gate layers 24A, 24B. The gate layer 272A is electrically connected to the second electrode layer 122 (gate electrode) of each semiconductor chip 10A via a wire member 6 (gate wire 61). The gate layer 272B is electrically connected to the second electrode layer 122 (gate electrode) of each semiconductor chip 10B via a wire member 6 (gate wire 61). Each of the gate layers 272A, 272B has a strip-shaped portion extending in the x-direction. A plurality of gate wires 61 are bonded to each of the strip-shaped portions. A portion (pad portion 441) of the gate terminal 44A is directly bonded to the gate layer 272A. A portion (pad portion 441) of the gate terminal 44B is directly bonded to the gate layer 272B.

[0129] The pair of detection layers 273A, 273B correspond to the pair of detection layers 25A, 25B. The detection layer 273A is electrically connected to the first electrode layer 121 (source electrode) of each semiconductor chip 10A via the wire member 6 (detection wire 62). The detection layer 273B is electrically connected to the first electrode layer 121 (source electrode) of each semiconductor chip 10B via the wire member 6 (detection wire 62). Each of the detection layers 273A, 273B has a strip-shaped portion extending in the x-direction. A plurality of detection wires 62 are bonded to each of the strip-shaped portions. A portion (pad portion 451) of the detection terminal 45A is directly bonded to the detection layer 273A. A portion (pad portion 451) of the detection terminal 45B is directly bonded to the detection layer 273B.

[0130] The pair of source signal layers 274A, 274B are each electrically connected to the first electrode layer 121 of each semiconductor chip 10. The source signal layer 274A is electrically connected to the first electrode layer 121 (source electrode) of each semiconductor chip 10A via a wire member 6 (a source signal wire 65 described later). The source signal layer 274B is electrically connected to the first electrode layer 121 (source electrode) of each semiconductor chip 10B via a wire member 6 (a source signal wire 65 described later). A portion (pad portion 481) of the source signal terminal 48A is directly bonded to the source signal layer 274A. A portion (pad portion 481) of the source signal terminal 48B is directly bonded to the source signal layer 274B.

[0131] The plurality of dummy layers 275 are not electrically connected to any of the semiconductor chips 10. To each dummy layer 275, a part (pad portion 461) of the dummy terminal 46 is directly bonded.

[0132] The back surface metal layer 28 is formed on the back surface 262 of the insulating substrate 26. The constituent material of the back surface metal layer 28 is the same as the constituent material of the main surface metal layer 27. The surface of the back surface metal layer 28 facing the z1 direction may be exposed from the resin member 7. The surface facing the z1 direction may be covered by the resin member 7.

[0133] As shown in Fig. 18, the pad portion 411 of the input terminal 41 is joined to the conductive layer 271A. In the embodiment shown in Fig. 18, the input terminal 41 is partially bent in the portion covered with the resin member 7. The conductive layer 271A is electrically connected to the third electrode layer 123 of each semiconductor chip 10A. Therefore, the input terminal 41 is electrically connected to the third electrode layer 123 of each semiconductor chip 10A.

[0134] 18, the pad portion 421 of the input terminal 42 is joined to the conductive layer 271B. In the embodiment shown in FIG. 18, the input terminal 42 is partially bent in the portion covered with the resin member 7. The conductive layer 271B is electrically connected to the first electrode layer 121 of each semiconductor chip 10B via the second lead 52. Therefore, the input terminal 42 is electrically connected to the first electrode layer 121 of each semiconductor chip 10B.

[0135] 18, the pad portion 431 of the output terminal 43 is joined to the conductive layer 271C. In the embodiment shown in FIG. 18, the output terminal 43 is partially bent in the portion covered with the resin member 7. The conductive layer 271C is electrically connected to the first electrode layer 121 of each semiconductor chip 10A via the first lead 51, and is also electrically connected to the third electrode layer 123 of each semiconductor chip 10B. Therefore, the output terminal 43 is electrically connected to the first electrode layer 121 of each semiconductor chip 10A and the third electrode layer 123 of each semiconductor chip 10B.

[0136] The gate terminal 44A has a pad portion 441 bonded to the gate layer 272A. The gate layer 272A is electrically connected to the second electrode layer 122 of each semiconductor chip 10A via the gate wire 61. Therefore, the gate terminal 44A is electrically connected to the second electrode layer 122 of each semiconductor chip 10A. The gate terminal 44B has a pad portion 441 bonded to the gate layer 272B. The gate layer 272B is electrically connected to the second electrode layer 122 of each semiconductor chip 10B via the gate wire 61. Therefore, the gate terminal 44B is electrically connected to the second electrode layer 122 of each semiconductor chip 10B. As shown in FIG. 19 , the gate terminals 44A and 44B are arranged symmetrically with respect to the center of the insulating substrate 26 in a plan view.

[0137] The detection terminal 45A has a pad portion 451 bonded to the detection layer 273A. The detection layer 273A is electrically connected to the first electrode layer 121 of each semiconductor chip 10A via the detection wire 62. Therefore, the detection terminal 45A is electrically connected to the first electrode layer 121 of each semiconductor chip 10A. The detection terminal 45B has a pad portion 451 bonded to the detection layer 273B. The detection layer 273B is electrically connected to the first electrode layer 121 of each semiconductor chip 10B via the detection wire 62. Therefore, the detection terminal 45B is electrically connected to the first electrode layer 121 of each semiconductor chip 10B. As shown in FIG. 19 , the detection terminals 45A and 45B are arranged symmetrically with respect to the center of the insulating substrate 26 in a plan view.

[0138] The pad portion 461 of the dummy terminal 46 is bonded to the dummy layer 275. Since the dummy layer 275 is not electrically connected to any of the plurality of semiconductor chips 10A, 10B, the dummy terminal 46 is not electrically connected to any of the plurality of semiconductor chips 10A, 10B.

[0139] Each of the pair of source signal terminals 48A, 48B includes a pad portion 481 and a terminal portion 482. In each of the source signal terminals 48A, 48B, the pad portion 481 is covered with the resin member 7. The terminal portion 482 is connected to the pad portion 481 and is exposed from the resin member 7.

[0140] The source signal terminal 48A has a pad portion 481 bonded to the source signal layer 274A. The source signal layer 274A is electrically connected to the first electrode layer 121 of each semiconductor chip 10A via the wire member 6 (the source signal wire 65 described later). Therefore, the source signal terminal 48A is electrically connected to the first electrode layer 121 of each semiconductor chip 10A. The source signal terminal 48B has a pad portion 481 bonded to the source signal layer 274B. The source signal layer 274B is electrically connected to the first electrode layer 121 of each semiconductor chip 10B via the wire member 6 (the source signal wire 65 described later). Therefore, the source signal terminal 48B is electrically connected to the first electrode layer 121 of each semiconductor chip 10B. As shown in FIG. 19 , the source signal terminals 48A and 48B are arranged symmetrically with respect to the center of the insulating substrate 26 in a plan view.

[0141] Of the multiple terminals 40, the gate terminal 44A, the detection terminal 45A, some of the dummy terminals 46, and the source signal terminal 48A protrude from the resin side surface 734. These terminals overlap each other when viewed in the x direction, and are partially bent at the portions covered by the resin member 7 and the portions exposed from the resin member 7. Furthermore, the gate terminal 44B, the detection terminal 45B, some of the dummy terminals 46, and the source signal terminal 48B protrude from the resin side surface 733. These terminals overlap each other when viewed in the x direction, and are partially bent at the portions covered by the resin member 7 and the portions exposed from the resin member 7. The shapes of the pair of gate terminals 44A, 44B, the pair of detection terminals 45A, 45B, the multiple dummy terminals 46, and the pair of source signal terminals 48A, 48B are not limited, and may, for example, each protrude from the resin main surface 71.

[0142] As shown in FIGS. 18, 19, and 21, each of the multiple first leads 51 connects a corresponding semiconductor chip 10A to the conductive layer 271C. In each first lead 51, the first joint portion 511 is joined to the metal plate 31A. In this embodiment, the first joint portion 511 is also joined to the metal plate 31A by laser welding, and multiple weld marks 8 are formed in a planar view. In each first lead 51, the second joint portion 512 is also joined to the conductive layer 271C. In this embodiment, the second joint portion 512 is also joined to the conductive layer 271C by laser welding, and multiple weld marks 8 are formed in a planar view, as shown in FIGS. 18 and 19. The multiple weld marks 8 are arranged in a matrix pattern in a planar view.

[0143] In this embodiment, the first lead 51 corresponds to the "connection member" in the claims. In this case, the semiconductor element 11 of the semiconductor chip 10A corresponds to the "semiconductor element" in the claims, the metal plate 31A corresponds to the "electrode member" in the claims, the conductive layer 271A corresponds to the "first conductive member" in the claims, and the conductive layer 271C corresponds to the "second conductive member" in the claims.

[0144] As shown in FIGS. 18 and 21 , each of the multiple second leads 52 connects a corresponding semiconductor chip 10B to the conductive layer 271B. In each second lead 52, the first joint portion 521 is joined to the metal plate 31B. In this embodiment, the first joint portion 521 is also joined to the metal plate 31B by laser welding, and multiple weld marks 8 are formed in a plan view. In each second lead 52, the second joint portion 522 is also joined to the conductive layer 271B. In this embodiment, the second joint portion 522 is also joined to the conductive layer 271B by laser welding, and multiple weld marks 8 are formed in a plan view, as shown in FIG. 18 . The multiple weld marks 8 are arranged in a matrix pattern in a plan view.

[0145] In this embodiment, the second lead 52 also corresponds to the "connection member" in the claims. In this case, the semiconductor element 11 of the semiconductor chip 10B corresponds to the "semiconductor element" in the claims, the metal plate 31B corresponds to the "electrode member" in the claims, the conductive layer 271C corresponds to the "first conductive member" in the claims, and the conductive layer 271B corresponds to the "second conductive member" in the claims.

[0146] In the semiconductor device A3, the plurality of wire members 6 include a plurality of gate wires 61, a plurality of detection wires 62, and a plurality of source signal wires 65.

[0147] One end of each gate wire 61 is joined to the second electrode layer 122 (gate electrode) of each semiconductor chip 10, and the other end is joined to one of the pair of gate layers 272A, 272B. The multiple gate wires 61 include those that connect the second electrode layer 122 (gate electrode) of each semiconductor chip 10A to the gate layer 272A, and those that connect the second electrode layer 122 (gate electrode) of each semiconductor chip 10B to the gate layer 272B.

[0148] One end of each detection wire 62 is joined to the first electrode layer 121 (source electrode) of each semiconductor chip 10, and the other end is joined to one of the pair of detection layers 273A, 273B. The multiple detection wires 62 include one that connects the first electrode layer 121 (source electrode) of each semiconductor chip 10A to the detection layer 273A, and one that connects the first electrode layer 121 (source electrode) of each semiconductor chip 10B to the detection layer 273B.

[0149] One end of each of the plurality of source signal wires 65 is joined to the first electrode layer 121 (source electrode) of one of the plurality of semiconductor chips 10A, 10B, and the other end is joined to one of the pair of source signal layers 274A, 274B. The plurality of source signal wires 65 include one that connects the first electrode layer 121 (source electrode) of one of the semiconductor chips 10A to the source signal layer 274A, and one that connects the first electrode layer 121 (source electrode) of one of the semiconductor chips 10B to the source signal layer 274B.

[0150] According to the semiconductor device A3, similar to the semiconductor device A1, the lead member 5 is laser-welded to the metal plate 31 to establish electrical continuity between the lead member 5 and the first region 111 of the semiconductor element 11. Therefore, similar to the semiconductor device A1, the semiconductor device A3 can suppress damage to the semiconductor element 11, thereby improving reliability.

[0151] The semiconductor device A3 can achieve the same effects as the semiconductor device A1 in the parts configured in the same way as the semiconductor device A1.

[0152] <Fourth embodiment> Fig. 23 shows a semiconductor device according to the fourth embodiment. The semiconductor device A4 of the fourth embodiment differs from the semiconductor device A1 mainly in that it is a discrete component including one semiconductor chip 10. Fig. 23 is a perspective view showing the semiconductor device A4, with the resin member 7 indicated by imaginary lines.

[0153] The semiconductor device A4 includes a semiconductor chip 10, a metal plate 31, a lead frame 39, a lead member 5, a wire member 6, and a resin member 7. The semiconductor device A4 has a so-called lead frame structure.

[0154] The lead frame 39 supports the semiconductor chip 10 and is electrically connected to the semiconductor chip 10. A portion of the lead frame 39 is exposed from the resin member 7, and the exposed portion functions as a terminal of the semiconductor device A4. The lead frame 39 includes a first portion 391 and a second portion 392.

[0155] The first portion 391 supports the semiconductor chip 10. The semiconductor chip 10 is bonded to the first portion 391 via the conductive bonding material 100. The first portion 391 faces the back surface 11b of the semiconductor element 11. The first portion 391 is electrically connected to the third electrode layer 123 of the semiconductor chip 10. In this embodiment, the first portion 391 corresponds to a "first conductive member" recited in the claims.

[0156] The second part 392 is spaced apart from the first part 391. A part of the lead member 5 is joined to the second part 392. The second part 392 and the lead member 5 are joined by laser welding using a laser irradiation device LD. Therefore, a plurality of weld marks 8 are formed at the joint. In this embodiment, the second part 392 corresponds to the "second conductive member" recited in the claims.

[0157] According to the semiconductor device A4, similar to the semiconductor device A1, the lead member 5 is laser-welded to the metal plate 31 to establish electrical continuity between the lead member 5 and the first region 111 of the semiconductor element 11. Therefore, similar to the semiconductor device A1, the semiconductor device A4 can suppress damage to the semiconductor element 11, thereby improving reliability.

[0158] Although the semiconductor device A4 is shown as a discrete component, it is not limited to this. The semiconductor device A4 may also be an IC such as an LSI using a lead frame structure. The shape of the lead frame 39 is not limited to that shown in FIG. 23 and can be variously modified according to well-known semiconductor package types.

[0159] Fifth Embodiment Fig. 24 shows a semiconductor device according to the fifth embodiment. The semiconductor device A5 of the fifth embodiment differs from the semiconductor device A1 in that it does not include multiple metal plates 31, and the lead member 5 is directly bonded to the first electrode layer 121. The lead member 5 and the first electrode layer 121 are bonded by laser welding. Fig. 24 is an enlarged cross-sectional view of a main part of the semiconductor device A5. Fig. 24 corresponds to the partially enlarged view of the semiconductor device A1 shown in Fig. 12.

[0160] In the semiconductor device A5, the z-direction dimension of the first electrode layer 121 is larger than that of the first electrode layer 121 of the semiconductor device A1. Both the first electrode layer 121 and the second electrode layer 122 are in contact with the element main surface 11a, and the z-direction dimension of the first electrode layer 121 is larger than the z-direction dimension of the second electrode layer 122. Therefore, the first electrode layer 121 protrudes in the z-direction beyond the second electrode layer 122. The z-direction dimension of the first electrode layer 121 is smaller than the z-direction dimension of the semiconductor element 11. The z-direction dimension of the first electrode layer 121 is, for example, approximately 0.05 to 0.2 mm.

[0161] The semiconductor device A5 includes a semiconductor element 11, a first electrode layer 121, and a lead member 5. The semiconductor element 11 has a first region 111 (e.g., a source region) formed on the element principal surface 11a side in the z direction. The first electrode layer 121 is disposed on the element principal surface 11a and is electrically connected to the first region 111. The lead member 5 is joined to the first electrode layer 121 by laser welding according to the present disclosure. With this configuration, the lead member 5 is electrically connected to the first region 111 of the semiconductor element 11 via the first electrode layer 121. Therefore, by laser welding the lead member 5 to the first electrode layer 121, electrical conduction is established between the lead member 5 and the first region 111 of the semiconductor element 11. In other words, electrical conduction can be established between the lead member 5 and the semiconductor element 11 (first region 111) without ultrasonic bonding. As a result, pressure, vibration, and the like are not applied to the semiconductor element 11 during ultrasonic bonding, thereby suppressing damage to the semiconductor element 11. Therefore, the reliability of the semiconductor device A5 can be improved.

[0162] According to the semiconductor device A5, the first electrode layer 121 protrudes in the z-direction more than the second electrode layer 122. In this embodiment, the thickness of the first electrode layer 121 is made larger than the thickness of the second electrode layer 122. This makes it possible to suppress damage to the semiconductor element 11 due to heat generated during laser welding, even when the lead member 5 is laser-welded to the first electrode layer 121, thereby improving the reliability of the semiconductor device A5.

[0163] In the fifth embodiment, a semiconductor device A5 is shown in which the thickness of the first electrode layer 121 is increased without using the metal plate 31 in the semiconductor device A1, and the lead member 5 is directly laser-welded to this first electrode layer 121, but the present invention is not limited to this. The second to fourth embodiments, i.e., the semiconductor devices A2 to A4, may also be configured in a similar manner.

[0164] The semiconductor device and bonding method according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the bonding method according to the present disclosure can be freely designed in various ways.

[0165] The semiconductor device and bonding method according to the present disclosure include embodiments relating to the following supplementary notes. [Appendix 1] a semiconductor element having a main surface and a back surface spaced apart from each other in a first direction, and a first region disposed on the main surface side; an electrode member that is electrically connected to the first region and that is disposed on the main surface of the element; a first conductive member facing the back surface of the element and to which the semiconductor element is bonded; a second conductive member disposed spaced apart from the first conductive member; a connecting member that electrically connects the electrode member and the second conductive member; It is equipped with The semiconductor device, wherein the connection member is joined to the electrode member by laser welding. [Appendix 2] the electrode member is a first electrode layer in ohmic contact with the first region; 2. The semiconductor device according to claim 1. [Appendix 3] a second electrode layer disposed on the element main surface and different from the first electrode layer; The semiconductor element further includes a second region formed on the element main surface side, the second electrode layer is in ohmic contact with the second region; The first electrode layer protrudes in the first direction more than the second electrode layer. 3. The semiconductor device according to claim 2. [Appendix 4] a first electrode layer in ohmic contact with the first region; the electrode member is a metal plate joined to the first electrode layer via a conductive bonding material; 2. The semiconductor device according to claim 1. [Appendix 5] The conductive bonding material is a sintered metal. 5. The semiconductor device according to claim 4. [Appendix 6] The semiconductor element is a MOSFET. The semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 5. [Appendix 7] the first region is a source region; The first electrode layer is a source electrode. 7. The semiconductor device according to claim 6. [Appendix 8] the connecting member includes a first bonding portion bonded to the electrode member, A circular welding mark is formed in the first joint portion when viewed in the first direction. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film. [Appendix 9] A plurality of the welding marks are formed, The plurality of welding marks are arranged in a matrix when viewed in the first direction. 9. The semiconductor device according to claim 8. [Appendix 10] the electrode member has a dimension in the first direction smaller than that of the semiconductor element; 10. The semiconductor device according to claim 1. [Appendix 11] The connecting member is made of a metal containing copper. The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 10. [Appendix 12] The semiconductor device further includes an insulating member having a main surface of an insulating member facing in the same direction as the main surface of the element, the insulating member supporting the first conductive member and the second conductive member on the side of the main surface of the insulating member facing in the direction. 12. The semiconductor device according to claim 1. [Appendix 13] The semiconductor device further includes a resin member that covers the semiconductor element, the electrode member, the connection member, the first conductive member, and the second conductive member. 13. The semiconductor device according to claim 1. [Appendix 14] A bonding method for bonding a conductive connecting member to a semiconductor element having an element main surface and an element back surface spaced apart from each other in a first direction, comprising: the semiconductor element includes a first region disposed on the element main surface side, a first step of placing a conductive member on the element main surface and electrically connecting the conductive member to the first region; a second step of overlapping the connection member on the conductive member and laser welding the connection member and the conductive member in an area where the connection member and the conductive member overlap when viewed in the first direction, In the laser welding, a first laser beam and a second laser beam having different wavelengths are used. [Appendix 15] the wavelength of the first laser beam is shorter than the wavelength of the second laser beam; 15. The joining method according to claim 14. [Appendix 16] The output of the first laser beam is greater than the output of the second laser beam. 16. The joining method according to claim 14 or 15. [Appendix 17] the irradiation time of the first laser beam is shorter than the irradiation time of the second laser beam; 17. The joining method according to any one of claims 14 to 16. [Appendix 18] In the laser welding, the second laser beam is irradiated later than the first laser beam. 18. The joining method according to any one of claims 14 to 17. [Appendix 19] In the laser welding, the irradiation of the second laser light is started while the first laser light is being irradiated. 19. The joining method of claim 18.

Claims

1. a main surface and a rear surface of the element spaced apart from each other in a first direction; a semiconductor element having a first region disposed on the element main surface side; an electrode member electrically connected to the first region and disposed on the main surface of the element; a first conductive member disposed opposite the back surface of the element and to which the semiconductor element is bonded; a first connection member joined to the electrode member; It is equipped with the first connection member is partially welded to the electrode member, the electrode member is a metal plate, the semiconductor device further includes a resin member that covers at least a portion of the semiconductor element, the electrode member, the first connection member, and the first conductive member, The upper surface of the weld mark by the welding joint has an uneven surface and is in contact with the resin member. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein said first region constitutes a part of a transistor.

3. 3. The semiconductor device according to claim 2, further comprising a first electrode layer electrically connected to said first region and conducting to said electrode member.

4. a second conductive member disposed spaced apart from the first conductive member; The semiconductor device according to claim 3 , wherein the resin member covers at least a portion of the second conductive member.

5. The semiconductor device according to claim 4 , wherein said first connection member is partially welded and joined to said electrode member by laser welding.

6. The semiconductor device according to claim 4 , wherein the upper surface of the welding mark has a plurality of peaks and a plurality of valleys formed concentrically and alternately when viewed in the first direction.

7. 7. The semiconductor device according to claim 4, wherein the semiconductor element is made of a semiconductor material mainly containing SiC.

8. 8. The semiconductor device according to claim 4, wherein the electrode member has a thickness in the first direction smaller than that of the semiconductor element.

9. 9. The semiconductor device according to claim 4, wherein the electrode member has a thickness of 0.03 to 0.2 mm.

10. a detection wire connected to the first electrode layer and spaced apart from the electrode member; 10. The semiconductor device according to claim 4.

11. The semiconductor element has a MOSFET formed therein, the first region is a source region; the first electrode layer is a source electrode, The semiconductor element has a drain electrode arranged on a back surface side of the element.

11. The semiconductor device according to claim 4.

12. an insulating member having a main surface facing the same direction as the element main surface, and further including an insulating member supporting the first conductive member and the second conductive member on the side in the direction in which the insulating member main surface faces; 12. The semiconductor device according to claim 4.

13. an insulating layer bonded onto the first conductive member; and a wiring layer disposed on the insulating layer; the wiring layer is electrically connected to a second electrode layer formed on the element main surface of the semiconductor element; The semiconductor device according to claim 3 , wherein the electrode member is smaller than the semiconductor element when viewed in the first direction and is spaced apart from the second electrode layer.

14. 14. The semiconductor device according to claim 4, wherein the weld marks formed by the welding reach a depth partway through the electrode member in the first direction and do not penetrate the electrode member.

15. 15. The semiconductor device according to claim 4, wherein said electrode member contains copper.

16. the first connection member has a first joint portion joined to the electrode member, A plurality of the welding marks are formed in the first joint portion, The semiconductor device according to claim 4 , wherein the plurality of welding marks are arranged in a matrix when viewed in the first direction.

17. a plurality of the semiconductor elements; 17. The semiconductor device according to claim 4, wherein said plurality of semiconductor elements form a half-bridge circuit including an upper arm circuit and a lower arm circuit.

18. 18. The semiconductor device according to claim 17, wherein the plurality of semiconductor elements constituting each of the upper arm circuit and the lower arm circuit are connected in parallel.

19. Two input terminals to which power is input in the half-bridge circuit; an insulating plate overlapping at least a portion of each of the two input terminals; the resin member covers at least a portion of each of the two input terminals; 19. The semiconductor device according to claim 17, wherein the two input terminals have portions protruding from the resin member and are laminated with the insulating plate interposed therebetween.

20. 20. The semiconductor device according to claim 19, wherein an outer periphery of the portion of the insulating plate protruding from the resin member is located outside an outer periphery of the portion of the two input terminals protruding from the resin member when viewed in the first direction.

Images