Semiconductor device

Abstract

To provide a semiconductor device capable of forming routing wiring while suppressing a decrease in the number of semiconductor devices obtainable from one wafer.SOLUTION: The semiconductor device includes a semiconductor substrate, a seal ring, and at least one routing wiring. The semiconductor substrate has an outer peripheral portion in plan view. The seal ring is formed on the outer peripheral portion. The seal ring includes a plurality of conductors and a plurality of first plugs. Each of the plurality of conductors is stacked along a thickness direction of the semiconductor substrate and extends along the outer peripheral portion in plan view. Each of the plurality of conductors has a first outer peripheral edge and a first inner peripheral edge in plan view. The plurality of conductors include a first conductor located in an uppermost layer and a plurality of second conductors located in a layer lower than the first conductor. The first outer peripheral edge of the first conductor is located outside the respective first outer peripheral edges of the plurality of second conductors.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] The semiconductor device described in JP 2019-114673 A (Patent Document 1) has a semiconductor substrate and a seal ring formed on the outer periphery of the semiconductor substrate. The seal ring has a plurality of conductors and a plurality of plugs. The plurality of conductors are stacked. Each of the plurality of plugs connects two adjacent conductors. However, one of the plurality of plugs connects the conductor located in the bottom layer to the semiconductor substrate. A passivation film covers the conductor located in the top layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-114673 Summary of the Invention [Problem to be solved by the invention]

[0004] Inspection pads are sometimes formed at positions that overlap with scribe lines in a plan view. If wiring connected to these pads is formed at a position that overlaps with the scribe lines in a plan view, the width of the scribe lines increases, reducing the number of semiconductor devices that can be obtained from one wafer. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, a seal ring, and at least one routing wiring. The semiconductor substrate has an outer periphery in plan view. The seal ring is formed on the outer periphery. The seal ring has a plurality of conductors and a plurality of first plugs. Each of the plurality of conductors is stacked along the thickness direction of the semiconductor substrate and extends along the outer periphery in plan view. Each of the plurality of conductors has a first outer periphery edge and a first inner periphery edge in plan view. The plurality of conductors includes a first conductor located in an uppermost layer and a plurality of second conductors located in a layer below the first conductor. The first outer periphery edge of the first conductor is located outside each of the first outer peripheries of the plurality of second conductors. Each of the plurality of first plugs connects between the first conductor and one of the plurality of second conductors adjacent to the first conductor, between two adjacent second conductors, or between the outer periphery and one of the plurality of second conductors adjacent to the outer periphery, and extends along the outer periphery in plan view. Each of the at least one routing wiring is located between a first outer periphery of the first conductor and a first outer periphery of each of the plurality of second conductors in a plan view. Each of the at least one routing wiring is formed on or within the outer periphery so as to be located in a layer lower than the first conductor. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, it is possible to form lead wiring while suppressing a decrease in the number of semiconductor devices that can be obtained from one wafer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a plan view of the semiconductor device DEV1. [Figure 2] FIG. 2 is a partially enlarged view of FIG. [Figure 3] FIG. 3 is a cross-sectional view of the semiconductor device DEV1 taken along line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor device DEV1 taken along line IV-IV in FIG. [Figure 5A] FIG. 10 is a cross-sectional view of a semiconductor device DEV1 according to a first modification. [Figure 5B] FIG. 11 is a plan view of a semiconductor device DEV1 according to a second modification. [Figure 6] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 7] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S3. [Figure 8] FIG. 10 is a cross-sectional view illustrating a plug forming step S4. [Figure 9] FIG. 10 is a cross-sectional view illustrating a wiring formation step S5. [Figure 10] FIG. 10 is a cross-sectional view illustrating a passivation film forming step S6. [Figure 11] FIG. 10 is an enlarged plan view of the semiconductor device DEV1 along the scribe line SCL before the dicing step S7 is performed. [Figure 12] FIG. 2 is an enlarged plan view of the semiconductor device DEV2. [Figure 13] FIG. 13 is a cross-sectional view of the semiconductor device DEV2 taken along the line XIII-XIII in FIG. [Figure 14] FIG. 10 is an enlarged plan view of the semiconductor device DEV2 along the scribe line SCL before the dicing step S7 is performed. [Figure 15] FIG. 10 is an enlarged plan view of a semiconductor device DEV2 according to a modified example. [Figure 16] FIG. 2 is an enlarged plan view of the semiconductor device DEV3. [Figure 17] FIG. 17 is a cross-sectional view of the semiconductor device DEV3 taken along the line XVII-XVII in FIG. [Figure 18] FIG. 10 is an enlarged plan view of the semiconductor device DEV3 along the scribe line SCL before the dicing step S7 is performed. [Figure 19] 10 is an enlarged plan view of a semiconductor device DEV3 according to a first modification. FIG. [Figure 20] FIG. 10 is a cross-sectional view of a semiconductor device DEV3 according to a second modification. [Figure 21] FIG. 11 is a cross-sectional view of a semiconductor device DEV3 according to a third modification. [Figure 22] FIG. 11 is a cross-sectional view of a semiconductor device DEV3 according to a fourth modification. [Figure 23]FIG. 11 is a cross-sectional view of a semiconductor device DEV3 according to a fifth modification. [Figure 24] 10 is an enlarged plan view of a semiconductor device DEV3 according to a fifth modified example along a scribe line SCL before a dicing step S7 is performed. FIG. [Figure 25] FIG. 13 is a cross-sectional view of a semiconductor device DEV3 according to a sixth modification. [Figure 26] FIG. 13 is a cross-sectional view of a semiconductor device DEV3 according to a seventh modification. [Figure 27] FIG. 13 is a cross-sectional view of a semiconductor device DEV3 according to an eighth modification. [Figure 28] FIG. 13 is a cross-sectional view of a semiconductor device DEV3 according to a ninth modification. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of semiconductor device DEV1> 1 to 4, the semiconductor device DEV1 includes a semiconductor substrate SUB. The semiconductor substrate SUB has a peripheral portion PER in a plan view. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 located on the opposite side of the upper surface F1. The semiconductor substrate SUB is formed of, for example, single crystal silicon.

[0011] Although not shown, a source layer, a drain layer, and a well layer are formed in the semiconductor substrate SUB. Also, although not shown, the semiconductor device DEV1 has a gate insulating film and a gate electrode. The source layer and the drain layer are formed on the upper surface F1 so as to be spaced apart from each other. The well layer is formed on the upper surface F1 so as to surround the source layer and the drain layer. The gate insulating film is formed on the upper surface F1 between the source layer and the drain layer. The gate electrode is formed on the gate insulating film.

[0012] The semiconductor device DEV1 has an element isolation film ISL. A trench TR is formed in the upper surface F1 toward the lower surface F2. The element isolation film ISL is formed in the trench TR. The element isolation film ISL is formed of, for example, silicon oxide. Although not shown, the element isolation film ISL surrounds the transistor in a plan view. This electrically isolates the transistor from other elements located around it.

[0013] The semiconductor device DEV1 has a plurality of interlayer insulating films ILD. The plurality of interlayer insulating films ILD are stacked on the upper surface F1 along the thickness direction of the semiconductor substrate SUB. The interlayer insulating films ILD are made of, for example, silicon oxide. The semiconductor device DEV1 has a seal ring SR. The seal ring SR is formed on the outer periphery PER over the entire periphery of the outer periphery PER. The seal ring SR has a plurality of conductors CN and a plurality of plugs PG1.

[0014] The plurality of conductors CN are stacked along the thickness direction of the semiconductor substrate SUB. Each of the plurality of conductors CN extends along the outer periphery PER in a plan view. The plurality of conductors CN includes a conductor CN1 located in the uppermost layer and a plurality of conductors CN2 located in a layer below the conductor CN1. The conductor CN1 is formed on one of the plurality of interlayer insulating films ILD located in the uppermost layer. One of the plurality of conductors CN2 is formed on one of the plurality of interlayer insulating films ILD and is covered by another of the plurality of interlayer insulating films ILD. Each of the plurality of conductors CN has an outer periphery OE1 and an inner periphery IE1 in a plan view. The outer periphery OE1 of the conductor CN1 is located outside each of the outer peripheries OE1 of the plurality of conductors CN2 in a plan view. The thickness of the conductor CN1 is, for example, greater than each of the thicknesses of each of the plurality of conductors CN2. The plurality of conductors CN are formed of, for example, aluminum or an aluminum alloy.

[0015] Each of the plurality of plugs PG1 is formed in the interlayer insulating film ILD and connects between the conductor CN1 and one of the plurality of conductors CN2 adjacent to the conductor CN1, between two adjacent ones of the plurality of conductors CN2, or between the outer periphery portion PER and one of the plurality of conductors CN2 adjacent to the outer periphery portion PER. Each of the plurality of plugs PG1 extends along the outer periphery portion PER in a plan view. The plurality of plugs PG1 are formed of, for example, tungsten.

[0016] The semiconductor device DEV1 further includes a lead wiring RW. In plan view, the lead wiring RW is located between the outer periphery OE1 of the conductor CN1 and the outer periphery OE1 of each of the plurality of conductors CN2. That is, the lead wiring RW overlaps with the conductor CN1 in plan view. The lead wiring RW has an outer periphery OE2 and an inner periphery IE2 in plan view. As long as the inner periphery IE2 is located between the outer periphery OE1 of the conductor CN1 and the outer periphery OE1 of each of the plurality of conductors CN2 in plan view, the outer periphery OE2 may be located outside the outer periphery OE1 of the conductor CN1 in plan view. From another perspective, it is sufficient that the lead wiring RW at least partially overlaps with the conductor CN1 in plan view.

[0017] The lead wiring RW has a plurality of wires WL1, a plurality of wires WL2, a plurality of plugs PG2, and a plurality of plugs PG3. The lead wiring RW is located in a layer lower than the conductor CN1. The lead wiring RW is formed on the outer periphery portion PER over the entire periphery of the outer periphery portion PER in a plan view, for example.

[0018] The plurality of wirings WL1 are formed in a first layer located below the conductor CN1. The plurality of wirings WL2 are formed in a second layer located below the first layer. More specifically, the plurality of wirings WL2 are formed on one of the plurality of interlayer insulating films ILD (interlayer insulating film ILD1) and covered by one of the plurality of interlayer insulating films ILD formed on the interlayer insulating film ILD1 (interlayer insulating film ILD2). The plurality of wirings WL2 are formed on the interlayer insulating film ILD2 and covered by one of the plurality of interlayer insulating films ILD formed on the interlayer insulating film ILD2 (interlayer insulating film ILD3). From another perspective, the plurality of wirings WL1 are formed in the same layer as one of the plurality of conductors CN2, and the plurality of wirings WL2 are formed in the same layer as another one of the plurality of conductors CN2.

[0019] In a plan view, the multiple wirings WL1 are arranged along the outer periphery PER with a gap between two adjacent ones of the multiple wirings WL1. Each of the multiple wirings WL1 extends along the outer periphery PER in a plan view. Each of the multiple wirings WL1 has an end WL1a and an end WL1b. In a plan view, the multiple wirings WL2 are arranged along the outer periphery PER with a gap between two adjacent ones of the multiple wirings WL2. Each of the multiple wirings WL2 extends along the outer periphery PER in a plan view. Each of the multiple wirings WL2 has an end WL2a and an end WL2b.

[0020] In a plan view, one end WL1a of two adjacent ones of the plurality of wirings WL1 and the other end WL1b of two adjacent ones of the plurality of wirings WL1 overlap with an end WL2a and an end WL2b of one wiring WL2, respectively. Each of the plurality of plugs PG2 connects the overlapping ends WL1a and WL2a in a plan view. Each of the plurality of plugs PG3 connects the overlapping ends WL1b and WL2b in a plan view. The plurality of wirings WL1 and the plurality of wirings WL2 are formed of, for example, aluminum or an aluminum alloy. The plurality of plugs PG2 and the plurality of plugs PG3 are formed of, for example, tungsten.

[0021] The semiconductor device DEV1 further includes a passivation film PV. The passivation film PV is formed on the uppermost interlayer insulating film ILD so as to cover the conductor CN1. The passivation film PV is made of, for example, silicon nitride.

[0022] <Modification> As shown in FIGS. 5A and 5B, the semiconductor device DEV1 may have a plurality of routing wirings RW. In the example shown in FIGS. 5A and 5B, the semiconductor device DEV1 has two routing wirings RW (routing wiring RW1 and routing wiring RW2). As shown in FIG. 5A, the routing wirings RW1 and RW2 are formed to overlap each other in a plan view, for example. As shown in FIG. 5B, each of the routing wirings RW1 and RW2 may be formed on the outer periphery PER over a quarter or more of the entire circumference of the outer periphery PER in a plan view. Although not shown, the routing wirings RW may be formed on the outer periphery PER over a half or more of the entire circumference of the outer periphery PER in a plan view.

[0023] <Method of Manufacturing Semiconductor Device DEV1> As shown in Figure 6, the semiconductor device DEV1 includes a preparation process S1, a front-end process S2, an interlayer insulating film formation process S3, a plug formation process S4, a wiring formation process S5, a passivation film formation process S6, and a dicing process S7.

[0024] In the preparation step S1, a semiconductor substrate SUB is prepared. In the front-end step S2, a source layer, a drain layer, a well layer, a gate insulating film, and a gate electrode of the above-mentioned transistor are formed. Also, in the front-end step S2, a trench TR is formed in the upper surface F1, and an element isolation film ISL is formed in the trench TR.

[0025] 7, in the interlayer insulating film formation step S3, the lowermost interlayer insulating film ILD (interlayer insulating film ILD1) is formed on the upper surface F1 so as to cover the transistor. In the interlayer insulating film formation step S3, first, a constituent material of the interlayer insulating film ILD is formed on the upper surface F1 by, for example, a CVD (Chemical Vapor Deposition) method. Second, the constituent material of the interlayer insulating film ILD is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. In this manner, the interlayer insulating film ILD is formed.

[0026] As shown in FIG. 8, in the plug formation step S4, a plug PG1 is formed in the interlayer insulating film ILD1. In the plug formation step S4, first, a resist pattern is formed on the interlayer insulating film ILD1. The resist pattern is formed by applying photoresist to the interlayer insulating film ILD1, and then exposing and developing the photoresist. Second, a through-hole is formed in the interlayer insulating film ILD1 by dry etching the interlayer insulating film ILD using the resist pattern as a mask. Third, a constituent material for the plug PG1 is embedded in the through-hole by, for example, a CVD method, and the constituent material for the plug PG1 is formed on the interlayer insulating film ILD. Fourth, the constituent material for the plug PG1 formed outside the through-hole is removed by, for example, a CMP method. In this manner, the plug PG1 is formed.

[0027] As shown in FIG. 9, in the wiring formation step S5, a plurality of wirings WL2 are formed on the interlayer insulating film ILD1. In the wiring formation step S5, first, a constituent material of the wirings WL2 is formed on the interlayer insulating film ILD1 by, for example, sputtering. Second, a resist pattern is formed on the constituent material of the wirings WL2. The resist pattern is formed by applying photoresist to the constituent material of the wirings WL2 and then exposing and developing the photoresist. Third, the constituent material of the wirings WL2 is patterned by dry etching using the resist pattern as a mask, thereby forming a plurality of wirings WL2. The patterning of the constituent material of the wirings WL2 also forms the bottom-most conductor CN (conductor CN2).

[0028] By repeatedly performing the interlayer insulating film forming step S3, the plug forming step S4, and the wiring forming step S5, an interlayer insulating film ILD2 is formed, a plug PG1, a plurality of plugs PG2, and a plurality of plugs PG3 are formed in the interlayer insulating film ILD2, a plurality of wirings WL1 are formed on the interlayer insulating film ILD2, an interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2, and a plurality of interlayer insulating films ILD are formed on the interlayer insulating film ILD3. Furthermore, by repeatedly performing the interlayer insulating film forming step S3, the plug forming step S4, and the wiring forming step S5, a plurality of conductors CN2 and CN1 located in layers other than the bottommost layer are also formed.

[0029] 10, in a passivation film formation step S6, a passivation film PV is formed on the uppermost interlayer insulating film ILD so as to cover the conductor CN1, for example, by a CVD method. In a dicing step S7, the semiconductor substrate SUB and the multiple interlayer insulating films ILD are cut along scribe lines SCL (see FIG. 11). This forms the structure of the semiconductor device DEV1 shown in FIGS. 1 to 4.

[0030] 11, before the dicing step S7 is performed, pads PD1 and PD2 are formed on the uppermost interlayer insulating film ILD located on the scribe line SCL. One end of the lead-out wiring RW is electrically connected to the pad PD1, and the other end of the lead-out wiring RW is electrically connected to the pad PD2. By applying a voltage between the pads PD1 and PD2 and measuring the electrical resistance value of the lead-out wiring RW, it is possible to evaluate the quality of the wiring and plugs formed inside the outer periphery PER in plan view, for example.

[0031] <Effects of semiconductor device DEV1> If the routing wiring RW is formed so as to overlap the scribe line SCL in a plan view, the width of the scribe line SCL increases, reducing the number of semiconductor devices DEV1 that can be obtained from a single wafer. In particular, if a large current is to be passed through the semiconductor device DEV1, the thickness of the wiring formed on the top interlayer insulating film ILD (i.e., the wiring formed in the same layer as the conductor CN1) must be increased, which increases the width of the wiring and the conductor CN1. Therefore, there is an empty space below the conductor CN1.

[0032] In the semiconductor device DEV1, the routing wiring RW is formed on the outer peripheral portion PER so as to overlap the conductor CN1 in a plan view. Therefore, in the semiconductor device DEV1, the above-mentioned free space can be effectively utilized and the width of the scribe line SCL can be reduced, which makes it possible to increase the number of semiconductor devices DEV1 that can be obtained from one wafer.

[0033] (Second embodiment) A semiconductor device DEV2 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0034] <Configuration of semiconductor device DEV2> 12 and 13, in the semiconductor device DEV2, the lead-out wiring RW has a plurality of wirings WL3 and a plurality of plugs PG4. The plurality of wirings WL3 are located in a layer lower than the conductor CN1 and are stacked along the thickness direction of the semiconductor substrate SUB. That is, each of the plurality of wirings WL3 is formed on one of the plurality of interlayer insulating films ILD and is covered with another of the plurality of interlayer insulating films. Each of the plurality of wirings WL3 extends along the outer periphery PER in a plan view.

[0035] Each of the plurality of plugs PG4 connects two adjacent ones of the plurality of wirings WL3. From another perspective, the plurality of wirings WL3 are not electrically connected to the conductor CN1 and are not electrically connected to the outer periphery PER (semiconductor substrate SUB). Each of the plurality of plugs PG4 extends along the outer periphery PER in plan view.

[0036] 14, in the semiconductor device DEV2, before the dicing step S7 is performed, pads PD3, PD4, and PD5 are formed on the uppermost interlayer insulating film ILD located on the scribe line SCL. In addition, in the semiconductor device DEV2, a transistor Tr is formed at a position overlapping the scribe line SCL in a plan view.

[0037] The routing wiring RW is electrically connected at one end to the pad PD3 and at the other end to the gate electrode of the transistor Tr. The pads PD4 and PD5 are electrically connected to the source layer and drain layer of the transistor Tr, respectively. The characteristics of the transistor Tr can be measured by applying a voltage between the pads PD4 and PD5 and also to the pad PD3. Based on the characteristics of the transistor Tr, the characteristics of the transistor formed inside the outer peripheral portion PER in a plan view, and therefore the quality of the transistor, can be evaluated.

[0038] <Modification> As shown in FIG. 15, the semiconductor device DEV2 may have a plurality of lead-out wirings RW. In the example shown in FIG. 15, the semiconductor device DEV2 has a plurality of lead-out wirings RW3 and a plurality of lead-out wirings RW4 as the lead-out wirings RW. In a plan view, each of the plurality of lead-out wirings RW3 is arranged along the outer periphery PER with a gap between two adjacent ones of the plurality of lead-out wirings RW3. In a plan view, each of the plurality of lead-out wirings RW4 is located more inward than each of the plurality of lead-out wirings RW3. Furthermore, each of the plurality of lead-out wirings RW4 is arranged so as to face a gap between two adjacent ones of the plurality of lead-out wirings RW3.

[0039] <Effects of semiconductor device DEV2> In the semiconductor device DEV2, the routing wiring RW is formed so as to overlap the conductor CN1 in a plan view. Therefore, similar to the semiconductor device DEV1, the width of the scribe line SCL can be reduced, and the number of semiconductor devices DEV1 that can be obtained from one wafer can be increased. In the semiconductor device DEV2, the routing wiring RW has a structure similar to that of the seal ring SR. Therefore, the routing wiring RW not only provides electrical connection, but also serves as a seal ring that prevents the propagation of cracks that occur during dicing. As a result, the semiconductor device DEV2 can further prevent the propagation of cracks that occur during dicing.

[0040] Furthermore, when the semiconductor device DEV2 has a plurality of routing wirings RW3 and a plurality of routing wirings RW4, cracks that attempt to propagate from the gaps between the plurality of routing wirings RW3 can be stopped by the routing wiring RW4, thereby further suppressing the propagation of cracks that occur during dicing.

[0041] (Third embodiment) A semiconductor device DEV3 according to the third embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV2, and overlapping descriptions will not be repeated.

[0042] 16 and 17, in the semiconductor device DEV3, the lead wiring RW has a wiring WL4. The wiring WL4 is formed on one of the plurality of interlayer insulating films ILD and is covered by another of the plurality of interlayer insulating films ILD. The wiring WL4 extends along the outer periphery PER in a plan view.

[0043] In the semiconductor device DEV3, the seal ring SR may further include a plurality of plugs PG5. Furthermore, in the semiconductor device DEV3, the plurality of conductors CN may further include a plurality of conductors CN3. The plurality of conductors CN3 are located in a layer lower than the conductor CN1. The plurality of conductors CN3 are located between the inner peripheral edge IE1 of the conductor CN1 and the inner peripheral edges IE1 of each of the plurality of conductors CN2 in a plan view. Each of the plurality of plugs PG5 connects the conductor CN1 to one of the plurality of conductors CN3 adjacent to the conductor CN1, between two adjacent ones of the plurality of conductors CN3, and between the outer peripheral portion PER and one of the plurality of conductors CN3 adjacent to the outer peripheral portion PER.

[0044] 18, in the semiconductor device DEV3, before the dicing step S7 is performed, pads PD3, PD4, and PD5 are formed on the uppermost interlayer insulating film ILD located on the scribe line SCL. In the semiconductor device DEV3, a transistor Tr is formed at a position overlapping the scribe line SCL in a plan view. One end of the lead-out wiring RW is electrically connected to the pad PD3, and the other end is electrically connected to the gate electrode of the transistor Tr. The pads PD4 and PD5 are electrically connected to the source layer and drain layer of the transistor Tr, respectively.

[0045] <Modification> 19, in the semiconductor device DEV3, the conductors CN3 do not have to be formed around the entire periphery of the outer periphery portion PER in a plan view. For example, the conductors CN3 may be formed only at positions facing the lead wiring RW (wiring WL4) in a plan view.

[0046] As shown in FIG. 20, the thickness of the conductor CN1 is defined as thickness T. The distance between the outer periphery OE2 (the outer periphery of the wiring WL4) and the outer periphery OE1 in plan view is defined as distance DIS. The distance DIS may be, for example, 0.5 times or more the thickness T. Note that the outer periphery OE2 may be located outside the outer periphery OE1 in plan view, or may be located inside the outer periphery OE1.

[0047] 21, in the semiconductor device DEV3, the lead-out wiring RW may have a plurality of wirings WL4. The plurality of wirings WL4 are stacked along the thickness direction of the semiconductor substrate SUB. As shown in FIG. 22, the lead-out wiring RW may have a plurality of plugs PG6. Each of the plurality of plugs PG5 connects two adjacent ones of the plurality of wirings WL4.

[0048] As shown in Fig. 23, the semiconductor device DEV3 may have a plurality of lead-out wirings RW. In the example shown in Fig. 23, the semiconductor device DEV3 has two lead-out wirings RW (lead-out wirings RW5 and lead-out wirings RW6). The lead-out wirings RW5 has a wiring WL4a, and the lead-out wirings RW6 has a wiring WL4b. The wirings WL4a and WL4b are formed in different layers. In the example shown in Fig. 23, the wiring WL4a is formed on the interlayer insulating film ILD1, and the wiring WL4b is formed on the interlayer insulating film ILD2.

[0049] As shown in FIG. 24, in the semiconductor device DEV3, before the dicing step S7 is performed, pads PD6, PD7, and PD8 are formed on the uppermost interlayer insulating film ILD located on the scribe line SCL in addition to pads PD3, PD4, and PD5. In the semiconductor device DEV3, transistors Tr1 and Tr2 are formed at positions overlapping the scribe line SCL in a planar view. One end of the lead-out wiring RW5 is electrically connected to pad PD3, and the other end is electrically connected to the gate electrode of transistor Tr1. Pads PD4 and PD5 are electrically connected to the source layer and drain layer of transistor Tr1, respectively. One end of the lead-out wiring RW6 is electrically connected to pad PD6, and the other end is electrically connected to the gate electrode of transistor Tr2. Pads PD7 and PD8 are electrically connected to the source layer and drain layer of transistor Tr2, respectively.

[0050] As shown in FIG. 25, the wiring WL4a may be formed on the element isolation film ISL. In this case, the wiring WL4a is formed of, for example, polycrystalline silicon containing a dopant. As shown in FIGS. 26 to 28, the wiring WL4a may be formed in the semiconductor substrate SUB. In the example shown in FIG. 26, the wiring WL4a is an impurity diffusion layer formed on the upper surface F1. In the example shown in FIG. 27, the wiring WL4a is formed of polycrystalline silicon containing a dopant. In this case, a first trench is formed in the semiconductor substrate SUB and the element isolation film ISL, and an insulating film IF is buried in the first trench. A second trench is formed in the insulating film IF, and the wiring WL4a is buried in the second trench. As shown in FIG. 28, the wiring WL4a may be buried in the second trench by the insulating film IF. That is, the wiring WL4a and the wiring WL4b may be formed in different layers below the conductor CN1.

[0051] <Effects of semiconductor device DEV3> In the semiconductor device DEV3, the seal ring SR further includes a plurality of conductors CN2 and a plurality of plugs PG5. That is, in the semiconductor device DEV3, the seal ring SR has a double structure. Therefore, the semiconductor device DEV3 can further suppress the propagation of cracks that occur during dicing.

[0052] To pass a large current through the semiconductor device DEV3, it is necessary to increase the thickness of the wiring formed on the uppermost interlayer insulating film ILD (i.e., the wiring formed in the same layer as the conductor CN1), which increases the thickness T accordingly. As the thickness T increases, stress tends to act on the position overlapping with the outer periphery OE1 in plan view. When the distance DIS is 0.5 times the thickness T or more, the routing wiring RW is arranged so as to avoid the position overlapping with the outer periphery OE1 in plan view, thereby reducing the stress acting on the routing wiring RW.

[0053] When the lead wiring RW has a plurality of wirings WL4, the cross-sectional area of ​​the lead wiring RW becomes large, and the electrical resistance value of the lead wiring RW can be reduced. Furthermore, when the semiconductor device DEV3 has a plurality of lead wirings RW, and each of the plurality of lead wirings RW has a wiring WL4 formed in a different layer, the degree of freedom in arranging the lead wirings RW is increased.

[0054] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0055] CN, CN1, CN2, CN3 conductors, DEV1, DEV2, DEV3 semiconductor device, DIS distance, F1 top surface, F2 bottom surface, IE1, IE2 inner periphery, IF insulating film, ILD interlayer insulating film, ILD1, ILD2, ILD3 interlayer insulating film, ISL element isolation film, OE1, OE2 outer periphery, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8 pad, PER outer periphery, PG1, PG2, PG3, PG4, PG5, PG6 plug, PV passivation film, RW routing wiring, RW1, RW2, RW3, RW4, RW5, RW6 routing wiring, S1 preparation process, S2 front-end process, S3 interlayer insulating film formation process, S4 plug formation process, S5 wiring formation process, S6 passivation film formation process, S7 dicing process, SCL Scribe line, SR seal ring, SUB semiconductor substrate, T thickness, TR trench, Tr, Tr1, Tr2 transistors, WL1 wiring, WL1b, WL1a ends, WL2 wiring, WL2b, WL2a ends, WL3, WL4, WL4a, WL4b wiring.

Claims

1. a semiconductor substrate; A seal ring and at least one routing wiring; the semiconductor substrate has an outer periphery in a plan view, The seal ring is formed on the outer periphery, the seal ring has a plurality of conductors and a plurality of first plugs; each of the plurality of conductors is stacked along a thickness direction of the semiconductor substrate and extends along the outer periphery in a plan view; Each of the plurality of conductors has a first outer circumferential edge and a first inner circumferential edge in a plan view, the plurality of conductors include a first conductor located in an uppermost layer and a plurality of second conductors located in a layer below the first conductor; the first outer periphery of the first conductor is located outside any of the first outer peripheries of the plurality of second conductors, each of the plurality of first plugs connects between the first conductor and one of the plurality of second conductors adjacent to the first conductor, between two adjacent ones of the plurality of second conductors, or between the outer circumferential portion and one of the plurality of second conductors adjacent to the outer circumferential portion, and extends along the outer circumferential portion in a plan view; each of the at least one lead-out wiring is located between the first outer periphery of the first conductor and the first outer periphery of each of the plurality of second conductors in a plan view; The semiconductor device, wherein each of the at least one lead-out wiring is formed on or within the outer periphery so as to be located in a layer below the first conductor.

2. each of the at least one lead-out wirings includes a plurality of first wirings, a plurality of second wirings, a plurality of second plugs, and a plurality of third plugs; the plurality of first wirings are formed in a first layer located below the first conductor, and are arranged at intervals along the outer periphery in a plan view; the plurality of second wirings are formed in a second layer located below the first layer, and are arranged at intervals along the outer periphery in a plan view; Each of the plurality of first wirings has a first end and a second end, each of the plurality of second wirings has a third end and a fourth end; the first end portion of one of two adjacent ones of the plurality of first wirings and the second end portion of the other of two adjacent ones of the plurality of first wirings overlap with the third end portion and the fourth end portion of one of the plurality of second conductors in a plan view, each of the plurality of second plugs connects between the first end and the third end that overlap each other in a plan view; 2 . The semiconductor device according to claim 1 , wherein each of said plurality of third plugs connects between said second end and said fourth end that overlap each other in a plan view.

3. 3. The semiconductor device according to claim 2, wherein one of said at least one lead-out wiring is formed on said outer periphery over the entire periphery of said outer periphery in a plan view.

4. 3. The semiconductor device according to claim 2, wherein one of said at least one lead-out wiring is formed on said outer periphery over at least half of the entire periphery of said outer periphery in plan view.

5. 3. The semiconductor device according to claim 2, wherein one of said at least one lead-out wiring is formed on said outer periphery over at least one-fourth of the entire periphery of said outer periphery in plan view.

6. 2. The semiconductor device according to claim 1, wherein the at least one lead-out wiring comprises a first lead-out wiring and a second lead-out wiring formed so as to overlap the first lead-out wiring in a plan view.

7. each of the at least one lead-out wirings includes a plurality of third wirings and a plurality of fourth plugs; each of the plurality of third wirings is stacked along the thickness direction and extends along the outer periphery in a plan view; 2 . The semiconductor device according to claim 1 , wherein each of said plurality of fourth plugs connects two adjacent ones of said plurality of third interconnects and extends along said outer periphery in a plan view.

8. 8. The semiconductor device according to claim 7, wherein the at least one lead-out wiring includes a third lead-out wiring and a fourth lead-out wiring positioned more inward than the third lead-out wiring in a plan view.

9. the at least one lead-out wiring includes a plurality of third lead-out wirings and a plurality of fourth lead-out wirings; the third lead-out wirings are arranged at intervals along the outer periphery in a plan view, 8. The semiconductor device according to claim 7, wherein each of the plurality of fourth routing lines faces a gap between two adjacent ones of the plurality of third routing lines and is located more inward than each of the plurality of third routing lines in a plan view.

10. the seal ring further includes a plurality of fifth plugs; the plurality of conductors further include a plurality of third conductors located in a layer below the first conductors, each of the plurality of third conductors is located between the first inner peripheral edge of the first conductor and the first inner peripheral edge of each of the plurality of second conductors in a plan view; 2. The semiconductor device according to claim 1, wherein each of the plurality of fifth plugs connects between the first conductor and one of the plurality of third conductors adjacent to the first conductor, between two adjacent ones of the plurality of third conductors, or between the outer periphery and one of the plurality of third conductors adjacent to the outer periphery, and extends along the outer periphery in a planar view.

11. Each of the at least one lead-out wiring has a second outer periphery in a plan view, 2. The semiconductor device according to claim 1, wherein a distance between the second outer edge of one of the at least one routing wirings located outermost in a plan view and the first outer edge of the first conductor is 0.5 times or more the thickness of the first conductor.

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