Electronic module

Abstract

To provide an electronic module capable of achieving both reduction in power supply impedance and miniaturization.SOLUTION: The electronic module includes a printed wiring board, a semiconductor component mounted on the printed wiring board and having a first lead and a second lead each soldered to the printed wiring board, and a chip component, wherein the chip component is disposed between the printed wiring board and at least one of the first lead and the second lead.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present disclosure relates to electronic modules. [Background technology]

[0002] In recent years, with the increasing speed of circuit operation and the decrease in power supply voltage, there has been a tendency for semiconductor devices to malfunction. The cause of semiconductor device malfunction is fluctuations in the power supply potential of the semiconductor device due to external noise propagating through the power supply wiring of a printed circuit board and so-called self-noise caused by the operation of the semiconductor device itself. To suppress fluctuations in the power supply potential due to such noise, semiconductor device manufacturers recommend placing capacitors near the power supply terminals of the semiconductor device. For example, a method of avoiding malfunctions by adding capacitors to suppress increases in power supply impedance is used.

[0003] Patent Document 1 discloses that elements are arranged around a semiconductor device on which leads are provided. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-109411 Summary of the Invention [Problem to be solved by the invention]

[0005] The area around a semiconductor device is crowded with numerous wiring and electrical components for signal input / output with other surrounding components and for power supply, leaving little space for capacitor placement. Adding a capacitor far from the semiconductor device not only increases the size of the printed circuit board, but also may reduce the effectiveness of reducing power supply impedance.

[0006] As such, it is necessary to ensure functionality to reduce power supply impedance and suppress noise radiation or intrusion. It is also necessary to prevent the size of printed circuit boards from increasing. Improvements in packaging technology are necessary to reduce the size of printed circuit boards and improve their functionality.

[0007] An object of the present invention is to provide a technique that is advantageous in realizing an improved mounting structure in an electronic module. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided an electronic module comprising: a printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead respectively soldered to the printed wiring board; and a chip component, wherein the chip component is disposed between the printed wiring board and at least one of the first lead and the second lead. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an advantageous technique for realizing an improved mounting structure in an electronic module. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 is a front view illustrating an example of an electronic device according to a first embodiment. [Figure 1B] 1 is a side view illustrating an example of an electronic device according to a first embodiment. [Figure 2] 1 is a schematic diagram showing an electronic module according to a first embodiment. [Figure 3A] 1 is a perspective view showing an electronic module according to a first embodiment. [Figure 3B] 1 is a cross-sectional view showing an electronic module according to a first embodiment. [Figure 3C] 1 is a plan view showing a first main surface and a second main surface of the electronic module according to the first embodiment as viewed from above. [Figure 4A] 4 is a graph showing the relationship between frequency and power supply impedance in the electronic modules according to the first embodiment and a comparative configuration. [Figure 4B] 3 is a cross-sectional view showing the mounting positions of chip components in the electronic module according to the first embodiment. FIG. [Figure 4C] FIG. 2 is a diagram showing an equivalent circuit of the electronic module according to the first embodiment. [Figure 5A] FIG. 10 is a perspective view showing an electronic module according to a third embodiment. [Figure 5B] FIG. 10 is a cross-sectional view showing an electronic module according to a third embodiment. [Figure 5C] FIG. 11 is a plan view of a first main surface of an electronic module according to a third embodiment, as viewed from above. [Figure 6] 10 is a graph showing the relationship between frequency and power supply impedance in the electronic modules according to the comparative example and the second and third embodiments. [Figure 7A] FIG. 10 is a perspective view showing an electronic module according to a fourth embodiment. [Figure 7B] FIG. 10 is a plan view of a first main surface of an electronic module according to a fourth embodiment, as viewed from above. [Figure 7C] 10 is a graph showing the relationship between frequency and power supply impedance in the electronic module according to the fourth embodiment. [Figure 8A] FIG. 10 is a perspective view showing an electronic module according to a fifth embodiment. [Figure 8B] FIG. 11 is a plan view of a first main surface of an electronic module according to a fifth embodiment, as viewed from above. [Figure 9] FIG. 10 is a perspective view showing an electronic module according to another embodiment. [Figure 10] FIG. 10 is a perspective view showing an electronic module according to another embodiment. [Figure 11] FIG. 10 is a perspective view showing an electronic module according to another embodiment. [Figure 12] FIG. 10 is a perspective view showing an electronic module according to another embodiment. [Figure 13] FIG. 10 is a perspective view showing an electronic module according to another embodiment. [Figure 14] FIG. 10 is a perspective view showing an electronic module according to another embodiment. [Figure 15A] FIG. 10 is a perspective view showing an electronic module according to a comparative configuration. [Figure 15B] FIG. 10 is a cross-sectional view showing an electronic module according to a comparative configuration. [Figure 15C] FIG. 10 is a plan view of a first main surface of an electronic module according to a comparative configuration, as viewed from above. [Figure 15D] FIG. 10 is a plan view of a second main surface of an electronic module according to a comparative configuration, as viewed from above. [Figure 15E] 10 is a plan view showing an example of a wiring structure on a first main surface of an electronic module according to a comparative configuration, as viewed from above. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the embodiments described below are merely some embodiments of the invention, and the present invention is not limited to these. Common configurations will be described with mutual reference to multiple drawings, and descriptions of configurations with common reference numerals will be omitted as appropriate.

[0012] [First embodiment] An electronic device and an electronic module according to a first embodiment of the present invention will be described with reference to Figures 1A to 4C. In this embodiment, an electronic device (printing device) equipped with an image forming device will be described as an example of the electronic device. However, electronic devices to which the present invention can be applied are not limited to printing devices, and examples include imaging devices such as cameras, medical devices such as CT and MRI, industrial devices such as robots and electronic component manufacturing devices, and transportation devices such as automobiles, aircraft, and ships.

[0013] Fig. 1A is a front view of an electronic device 1 according to this embodiment. Fig. 1B is a side view of the electronic device according to this embodiment. The electronic device 1 is, for example, an electrophotographic printing device such as a printer, copier, fax machine, or multifunction device, but may also be an inkjet printing device.

[0014] As shown in FIGS. 1A and 1B, the electronic device 1 has an image forming device 2 that forms an image on a sheet, and an electronic module 3 that controls the image forming device 2. The electronic module 3 that controls the image forming device 2 can be referred to as a control module. The electronic device 1 has a housing. The electronic module 3 is disposed inside the housing of the electronic device 1. The image forming device 2 is also disposed inside the housing of the electronic device 1. The image forming device 2 includes an image forming unit that forms an image on a sheet, and a conveying mechanism that conveys the sheet. The image forming unit includes components necessary for forming an image on a sheet, such as a photosensitive drum, a charging unit, a developing unit, a transfer unit, and a fixing unit, all of which are not shown.

[0015] The electronic module 3 is an electronic module configured as a printed circuit board. The electronic module 3 receives image data from an external device via an interface such as a LAN (Local Area Network) or a USB (Universal Serial Bus) (registered trademark). The electronic module 3 then processes the received image data, transmits the image data to the image forming apparatus 2, and controls the image forming apparatus 2 to form an image on a sheet.

[0016] Fig. 2 is a schematic diagram showing an electronic module 3 according to this embodiment. As shown in Fig. 2, the electronic module 3 includes an integrated circuit device 4, which is an example of a semiconductor component, and an integrated circuit device 10, which is also an example of a semiconductor component. The electronic module 3 also includes connectors 5, 6, and 7, and a printed wiring board 30. In the electronic module 3 configured as a printed circuit board, the integrated circuit device 4, the connectors 5, 6, and 7, and the integrated circuit device 10 are mounted on the printed wiring board 30. The printed wiring board 30 is, for example, a rigid substrate.

[0017] A communication cable 8 such as a LAN (Local Area Network) cable is attached to the connector 5, and image data is received from an external device via the communication cable 8. The integrated circuit device 4 processes the image data received at the connector 5, stores it in a memory controller and memory device (not shown), reads the image data from the memory device, and outputs it to the integrated circuit device 10. The integrated circuit device 10 outputs the image data to connectors 6 and 7, and transmits the image data to an image forming unit connected to the connectors 6 and 7 via a communication cable (not shown). In the electronic module 3 of this example, the integrated circuit device 4 is used as a conversion chip, and the integrated circuit device 10 is used as a communication device, but the electronic module 3 to which the present invention can be applied is not limited to this.

[0018] 3A is a perspective view showing a printed wiring board 30 constituting the electronic module 3 according to this embodiment. Fig. 3A shows a portion of the printed wiring board 30 on which the integrated circuit device 10 is mounted. In the following description, the mutually orthogonal directions along a first main surface 35 of the printed wiring board 30 on which the integrated circuit device 10 is mounted are referred to as the X direction and the Y direction, and the direction perpendicular to the first main surface 35 is referred to as the Z direction.

[0019] As shown in FIG. 3A , the integrated circuit device 10 is a semiconductor component, and has, for example, a QFP (Quad Flat Package) package structure, including a package body 11 and multiple leads 12. This embodiment is suitable for integrated circuit devices 10 with eight or more leads, and also suitable for devices with sixteen or more leads. The multiple leads 12, including leads 12a and 12b, are outer leads constituting a lead frame and protrude from the side surfaces of the package body 11 on four sides along the X and Y directions. The electronic module 3 further includes a chip component 20. The integrated circuit device 10 and the chip component 20 are mounted on a first main surface 35 of a printed wiring board 30. The chip component 20 is mounted between the leads 12a and 12b of the integrated circuit device 10 and the first main surface 35 of the printed wiring board 30. That is, the chip component 20 is disposed between the printed wiring board 30 and portions of the leads 12a and 12b that are distant from the printed wiring board 30. The chip component 20 is a capacitor component, such as a multilayer ceramic capacitor.

[0020] The printed wiring board 30 is a substrate on whose surface and inside there are formed wiring for electrically connecting components mounted on the printed wiring board 30, such as the integrated circuit device 10. Note that instead of the printed wiring board 30, a substrate capable of providing electrical connection to the mounted components, such as the integrated circuit device 10, can be used.

[0021] Fig. 3B is a cross-sectional view showing a cross section along the X direction indicated by region 39 in Fig. 3A. The cross section shown in Fig. 3B includes lead 12a as a power supply lead, which is one of leads 12 along the X direction to which a power supply potential to be supplied to integrated circuit device 10 is supplied in electronic module 3 according to this embodiment.

[0022] The printed wiring board 30 has an insulating substrate and conductive conductors that form the wiring. The substrate is made of, for example, epoxy resin. The conductor is made of, for example, copper. As shown in FIG. 3B , the printed wiring board 30 is a four-layer laminate substrate having, for example, four conductor layers 31, 32, 33, and 34. The conductor layers 31, 32, 33, and 34 are spaced apart from one another in the Z direction perpendicular to the first main surface 35. A substrate, i.e., an insulating layer, is provided between the conductor layer 31 and the conductor layer 32, between the conductor layer 32 and the conductor layer 33, and between the conductor layer 33 and the conductor layer 34. The conductor layers 31, 32, 33, and 34 are stacked in this order from the first main surface 35 to the second main surface 36, with the insulating layer interposed between them.

[0023] Conductor layer 31 is a first surface layer having a first main surface 35 which is a mounting surface on which integrated circuit devices 10, chip components 20, etc. are mounted. Conductor layer 34 is a second surface layer having a second main surface 36 which is a main surface opposite to the first main surface. Conductor layer 32 located between conductor layer 31 and conductor layer 34 is a first inner layer, and conductor layer 33 located between conductor layer 32 and conductor layer 34 is a second inner layer.

[0024] A solder resist (not shown) may be disposed on the conductor layers 31 and 34. Conductor patterns constituting wiring are provided on the conductor layers 31, 32, 33, and 34. Furthermore, the printed wiring board 30 is provided with a through-hole 62 that is a through-hole constituting wiring, spanning from the conductor layer 31 to the conductor layer 34.

[0025] Component pads 41 and 51 and wiring 61a and 61b are provided on the conductor layer 31. Lead 12a, which is one of the leads 12 of the integrated circuit device 10, is soldered and joined to the component pad 41. One terminal of the chip component 20 is soldered and joined to the component pad 51. The component pads 41 and 51 are connected by wiring 61a. Furthermore, wiring 61b is connected to the component pad 41. In this way, one terminal of the chip component 20 joined to the component pad 51 is electrically connected to the lead 12a joined to the component pad 41.

[0026] The chip component 20 is disposed and mounted between the package body 11 of the integrated circuit device 10, the lead 12a, and the conductor layer 31 of the printed wiring board 30. The chip component 20 may be disposed between the printed wiring board 30 and at least one of the leads 12a and 12b. The chip component 20 is disposed so as not to overlap the package body 11 in a direction perpendicular to the main surface of the printed wiring board 30. By preventing the chip component 20 from overlapping the package body 11, it is possible to avoid difficulties in the mounting process (which may result in reduced productivity (mounting speed) and yield) and / or difficulties in the visual or image processing inspection process. The wiring 61a and 61b are power supply wirings that supply a power supply potential to the integrated circuit device 10. The wiring 61b is connected to the through via 62. A chip component 70 is mounted on the second main surface 36 of the conductor layer 34. The conductor layer 34 is provided with a wiring 64. The wiring 64 is connected to the chip component 70. The wiring 61b is connected to the chip component 70 through the through via 62 and the wiring 64, and is further electrically connected to a power supply circuit (not shown).

[0027] Note that a part of the package body 11 may be located at a position lower than the height of the chip component 20. Even in such a case, a space for mounting the chip component 20 can be secured between the first main surface 35 of the printed wiring board 30 and the leads 12.

[0028] 3C is a plan view of first main surface 35 of conductor layer 31 in printed wiring board 30, viewed from above in the Z direction. As shown in FIG. 3C, component pads 40, 41, and 42 are provided on conductor layer 31. Component pads 40, 41, and 42 are arranged side by side around integrated circuit device 10 to correspond to multiple leads 12.

[0029] The multiple leads 12 of the integrated circuit device 10 are soldered and joined to component pads 40, 41, and 42. Lead 12a, which is one of the leads 12 to which a power supply potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 41. Lead 12b, which is one of the leads 12 to which a ground potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 42. Component pad 41 and component pad 42 are arranged adjacent to each other. Component pad 41 is supplied with a power supply potential. Component pad 42 is supplied with a ground potential.

[0030] Component pads 51 and 52, wirings 61a and 61b, and wirings 63a and 63b are provided on the conductor layer 31. The wirings 61a and 61b are power supply wirings, and the wirings 63a and 63b are ground wirings.

[0031] The chip component 20 has two terminals, one of which is soldered to a component pad 51 and the other of which is soldered to a component pad 52. The component pad 41, which supplies a power supply potential, is connected to the component pad 51 via a wiring 61a, which is a power supply wiring. Furthermore, the component pad 41 is electrically connected to a power supply circuit (not shown) via a wiring 61b, which is a power supply wiring connected to the component pad 41. One terminal of the chip component 20 is electrically connected to a lead 12a via the component pad 51, the wiring 61a, and the component pad 41. The component pad 42, which supplies a ground potential, is electrically connected to the component pad 52 via a wiring 63a, which is a ground wiring. Furthermore, the component pad 42 is electrically connected to a power supply circuit (not shown) via a wiring 63b, which is a power supply wiring connected to the component pad 42. The other terminal of the chip component 20 is electrically connected to a lead 12b via the component pad 52, the wiring 63a, and the component pad 42.

[0032] Thus, in the electronic module 3 according to this embodiment, the chip component 20 is mounted between the first main surface 35 of the printed wiring board 30 and the leads 12a, 12b. In this embodiment, the chip component 20 can reduce the power supply impedance, as will be described in detail below. Furthermore, because the chip component 20 is mounted between the first main surface 35 of the printed wiring board 30 and the leads 12, the chip component 20 does not prevent the electronic module 3 from being made smaller.

[0033] Details of the electronic module 3 according to this embodiment will be described below, comparing it with a comparative configuration shown in Figures 15A to 15E. The comparative configuration shown in Figures 15A to 15E differs from the configuration of this embodiment shown in Figures 3A to 3C in that the chip components 20 are not mounted. Note that in Figures 15A to 15E, elements common to this embodiment shown in Figures 3A to 3C are assigned the same reference numerals as those in this embodiment or reference numerals that are 200 larger than those in this embodiment, and descriptions thereof will be omitted or simplified.

[0034] 15A is a perspective view showing a printed wiring board 230 according to a comparative configuration. As shown in FIG. 15A, an integrated circuit device 10 is mounted on a first main surface 235 of a conductor layer 231 of the printed wiring board 230. A chip component 270 is mounted on a second main surface 236 of a conductor layer 234 of the printed wiring board 230.

[0035] The multiple leads 12 include leads 12a and 12b. The lead 12a is a power lead, which is one of the leads 12 to which a power supply potential to be supplied to the integrated circuit device 10 is supplied. The lead 12a is connected to one terminal of the chip component 270 via a wiring 261 provided in the conductor layer 231, a through via 262, and a wiring 263 provided in the conductor layer 234. The wiring 261 and 263 are power wirings. The lead 12b is a ground lead, which is one of the leads 12 to which a ground potential to be supplied to the integrated circuit device 10 is supplied. The lead 12b is connected to the other terminal of the chip component 270 via a wiring 264 provided in the conductor layer 231, a through via 265, and a wiring 266 provided in the conductor layer 234. The wiring 264 and 266 are ground wirings.

[0036] 15B is a cross-sectional view showing a cross section along the X direction indicated by region 239 in FIG. 15A. The cross section shown in FIG. 15B includes lead 12a, which is one of leads 12 in electronic module 203 to which a power supply potential to be supplied to integrated circuit device 10 is supplied. A ground wiring that supplies a ground potential is formed on conductor layer 232, which is a first inner layer of printed wiring board 230. A power supply wiring that supplies a power supply potential is formed on conductor layer 233, which is a second inner layer of printed wiring board 230. The ground wiring and power supply wiring are electrically connected to a power supply circuit (not shown). Chip component 270 is a capacitor component such as a multilayer ceramic capacitor.

[0037] FIG. 15C is a plan view of conductor layer 231 having first main surface 235 of printed wiring board 230, as viewed from above. FIG. 15D is a plan view of conductor layer 234, which is second main surface 236 of printed wiring board 230, as viewed from above. Both FIGS. 15C and 15D are views of integrated circuit device 10 viewed from above in the Z direction. Multiple leads 12 of integrated circuit device 10 are soldered and joined to component pads 240, 241, and 242 provided on conductor layer 231. Lead 12a, to which a power supply potential is supplied, is soldered and joined to component pad 241. Lead 12b, to which a ground potential to be supplied to integrated circuit device 10 is supplied, is soldered and joined to component pad 242. Component pad 241 is connected to through-hole via 262 via wiring 261. Component pad 242 is connected to through-hole via 265 via wiring 264. The through via 262 is connected to a component pad 250 provided on the conductor layer 234 via a wiring 263 provided on the conductor layer 234. The through via 265 is connected to a component pad 251 provided on the conductor layer 234 via a wiring 266 provided on the conductor layer 234.

[0038] 15E is a plan view showing an example of a wiring structure near component pads 240 for mounting integrated circuit devices 10 on printed wiring board 230 according to a comparative configuration. In FIG. 15E, the area of ​​conductor layer 231 on which integrated circuit devices 10 are mounted is viewed from above in the Z direction.

[0039] As shown in FIG. 15E , in the comparative configuration, a conductor layer 231 has numerous wirings and numerous through-hole vias near or around component pads 240 connected to the integrated circuit device 10. The numerous through-hole vias include through-hole vias 281, 282, 283, and 284. The through-hole vias 281, 282, and 283 are connected to component pads 240, including component pads 241 and 242, and are provided to supply different power supply potentials to the integrated circuit device 10. The through-hole via 284 is provided to supply a ground potential to the integrated circuit device 10. As described above, the conductor layer 231 near or around the component pads 240 has a high wiring density and cannot accommodate capacitor components to suppress fluctuations in each power supply potential. Therefore, in the comparative configurations shown in FIGS. 15A to 15E , the component pads that supply power supply potentials and ground potentials are connected to a chip component 270 mounted on the conductor layer 234 via through-hole vias 281, 282, 283, and 284. The chip component 270 is a capacitor component such as a multilayer ceramic capacitor.

[0040] 15A to 15E, the path for supplying a power supply potential to the integrated circuit device 10 is made up of a lead 12a, a wiring 261, a through via 262, and a wiring 263. The path for supplying a ground potential to the integrated circuit device 10 is made up of a lead 12b, a wiring 264, a through via 265, and a wiring 266. The path connecting the integrated circuit device 10 and a chip component 270, which is a capacitor component, includes thin, long leads, thin wiring on the substrate, and a through via. Therefore, the parasitic inductance components of each element constituting the path increase the power supply impedance, especially in the high frequency band, and increase fluctuations in the power supply potential.

[0041] In contrast to this, the electronic module 3 according to this embodiment can reduce the power supply impedance without increasing the size. The effects of the configuration according to this embodiment will now be described with reference to Figures 4A to 4C.

[0042] 4A is a graph showing the simulation results of power supply impedance inside integrated circuit device 10 for the configuration according to this embodiment shown in FIGS. 3A to 3D and the comparative configuration shown in FIGS. 15A to 15E. The horizontal axis of the graph represents frequency, and the vertical axis represents the power supply impedance characteristics as seen from inside integrated circuit device 10. In the graph, solid line 92 represents the simulation results for the configuration according to this embodiment, and dashed line 91 represents the simulation results for the comparative configuration.

[0043] FIG. 4B is a cross-sectional view showing the mounting position of the capacitor component in the configuration according to this embodiment shown in FIG. 4A. In the configuration according to this embodiment, a chip component 20 is mounted on the first main surface 35 of the conductor layer 31 on which the integrated circuit device 10 is mounted, between the leads 12a and 12b of the integrated circuit device 10 and the first main surface 35. In addition, in the configuration according to this embodiment, a chip component 70 is mounted on the second main surface 36 of the conductor layer 34. The chip components 20 and 70 are capacitor components such as multilayer ceramic capacitors. The chip component 20 is a chip component mounted at a position from the edge of the semiconductor package that provides the minimum inductance. The leads 12a and 12b of the integrated circuit device 10 are connected to the chip component 70, which is a capacitor component, via component pads, wiring, and through vias on the printed wiring board 30. The chip component 70 is located closer to the chip component 20 than the chip component 20.

[0044] The configuration according to this embodiment is equipped with chip components 20 and 70, whereas the comparative configuration is not equipped with chip component 20, but with only chip component 270 corresponding to chip component 70. The capacitor components constituting chip components 20, 70, and 270 each have the same capacitance of 0.01 μF.

[0045] FIG. 4C is a circuit diagram showing an equivalent circuit from which the power supply impedance shown in FIG. 4A is derived. FIG. 4C is a model of the physical structure shown in FIG. 4B in an equivalent circuit. Leads 12a and 12b of integrated circuit device 10 electrically connect the inside of its semiconductor package to component pads 41 and 42 provided on printed wiring board 30. Leads 12a and 12b are also electrically connected to chip components 20 and 70, which are capacitor components, via wiring provided on printed wiring board 30. This wiring structure is divided into three circuit elements corresponding to distances p1, p2, and p3 shown in FIG. 4B, respectively.

[0046] 4B is the portion where leads 12a and 12b are surrounded by air, from the end of package body 11 of the semiconductor package of integrated circuit device 10 to component pads 41 and 42 provided on printed wiring board 30. The inductance components on the power supply potential side and ground potential side of the portion corresponding to distance p1 are LleadV1 and LleadG1, respectively.

[0047] 4B is the portion of leads 12a and 12b that is soldered to component pads 41 and 42 of printed wiring board 30. The inductance components on the power supply potential side and ground potential side of the portion that corresponds to distance p2 are LleadV2 and LleadG2, respectively.

[0048] 4B is the portion from the ends of component pads 41 and 42 of the wiring path to chip component 70 mounted on second main surface 36 of printed wiring board 30. The inductance components on the power supply potential side and ground potential side of the portion corresponding to distance p3 are Lpcb1 and LpcbG, respectively.

[0049] The inductance components on the power supply potential side and the ground potential side of the portions that become the leads and wiring paths provided inside the semiconductor package of the integrated circuit device 10 are LpkgV and LpkgG, respectively.

[0050] 4A is observed on the power supply potential side of Cdie inside the integrated circuit device 10.

[0051] In a structure that supplies power supply potential, the parasitic inductance characteristics at the connection from the end of the semiconductor package to the chip component 70 mounted on the printed wiring board 30 can be expressed by the following equation for the comparative configuration and the configuration according to this embodiment. Comparison configuration: LleadV1+LleadV2+Lpcb1 Configuration according to this embodiment: LleadV1

[0052] In a structure that supplies ground potential, the parasitic inductance characteristics at the connection from the end of the semiconductor package to the chip component 70 mounted on the printed wiring board 30 can be expressed by the following equation for the comparative configuration and the configuration according to this embodiment. Comparison configuration: LleadG1+LleadG2+LpcbG Configuration according to this embodiment: LleadG1

[0053] In the integrated circuit device 10, the distance p1 between the leads 12a and 12b and the air is equal to or less than the distance p2 between the leads 12a and 12b and the component pads 41 and 42 on the printed wiring board 30.

[0054] Therefore, in the configuration according to this embodiment, the inductance component parasitic on the leads 12a and 12b that form the path connecting the end of the semiconductor package to the chip component 70 is reduced to roughly half that of the comparative configuration.

[0055] Furthermore, the configuration according to this embodiment reduces the parasitic inductance components Lpcb1 and LpcbG in the portion corresponding to the distance p3, which is the wiring path of the printed wiring board 30. Therefore, the configuration according to this embodiment can enhance the effect of reducing the power supply impedance when the chip component 70, which is a capacitor component, is mounted. Here, a configuration in which the effect of reducing the power supply impedance is particularly significant has been described, but the chip component 70 may be mounted on the first main surface 35 instead of the second main surface 36. Furthermore, the chip component 70 may be omitted, or the chip component 20 may replace the chip component 70, or multiple chip components 20 may replace the chip component 70.

[0056] In the configuration according to this embodiment, component pad 41 of printed wiring board 30 connected to integrated circuit device 10 is integrated with component pad 51 on which chip component 20 is mounted. Also, in the configuration according to this embodiment, component pad 42 of printed wiring board 30 connected to integrated circuit device 10 is integrated with component pad 52 on which chip component 20 is mounted.

[0057] Note that component pads 41 and 51 may be separate, independent pads, and component pads 42 and 52 may also be separate, independent pads. Component pads 41 and 51, which are provided as separate, independent pads, can be connected by wiring provided on conductor layer 31 of printed wiring board 30. Component pads 42 and 52, which are provided as separate, independent pads, can also be connected by wiring provided on conductor layer 31. Connecting component pads by wiring in this manner eliminates the need to match the size of chip component 20 with the pitch of adjacent leads 12a and 12b, enabling various mounting structures to be employed in electronic module 3. However, the wiring connecting component pads 41 and 51 and the wiring connecting component pads 42 and 52 are preferably thick and short to reduce parasitic inductance.

[0058] 4A compares the configuration of this embodiment and the comparative configuration under the condition that a capacitor that is a chip component 70 of the same structure and the same capacitance is mounted, but the present invention is not limited to this. By changing the chip component 70 to a component with a larger capacitance, it is possible to increase the frequency band in which the power impedance is reduced and the amount of reduction in power impedance.

[0059] Furthermore, component pad 41 connected to lead 12a supplied with power supply potential and component pad 42 connected to lead 12b supplied with ground potential do not necessarily need to be adjacent to each other. In this case, the component size of chip component 20 can be selected in accordance with the pitch of leads 12 including leads 12a and 12b of integrated circuit device 10.

[0060] Furthermore, printed wiring board 30 is not limited to a four-layer board, but may be a through-hole board having two or more layers of through-hole vias. Furthermore, the package structure of integrated circuit device 10 is not limited to a QFP having terminals on four sides of the package body, but may be an SOP (Small Outline Package) having terminals on only two sides.

[0061] Furthermore, the leads 12, 12a, 12b and the component pads 40, 41, 42 of the integrated circuit device 10 are not necessarily joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive. Similarly, the terminals of the chip component 20 and the component pads 51, 52 are not necessarily joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive.

[0062] As described above, according to this embodiment, it is possible to achieve both a reduction in power supply impedance and a reduction in size in the electronic module 3. In this way, according to this embodiment, it is possible to realize an improved mounting structure that is effective for reducing the size of the printed wiring board 30 and improving functionality.

[0063] [Second embodiment] An electronic device and an electronic module according to a second embodiment of the present invention will be described with reference to Figures 3B and 6. The basic configuration of the electronic device and the electronic module according to this embodiment is the same as that of the electronic device and the electronic module according to the first embodiment. In the electronic module 3 according to this embodiment, too, the chip component 20 mounted on the first main surface 35 of the printed wiring board 30 is soldered and joined to component pads 51 and 52 provided on the first main surface 35 of the printed wiring board 30, as in the first embodiment.

[0064] Furthermore, in this embodiment, one terminal of the chip component 20 and the lead 12a are also soldered and joined in an area 21 shown by a dashed ellipse in Fig. 3B where the lead 12a of the integrated circuit device 10 is surrounded by air. That is, one terminal of the chip component 20 is soldered and joined to a portion of the lead 12a away from the first main surface 35.

[0065] 3B, the other terminal of the chip component 20 is also soldered to the lead 12b in a region corresponding to the region 21 shown by the dashed oval in Fig. 3B, where the lead 12b is surrounded by air. That is, the other terminal of the chip component 20 is soldered to a portion of the lead 12b that is away from the first main surface 35.

[0066] Here, the terminals of the chip component 20 and the leads 12a, 12b are not limited to being joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive.

[0067] The method for connecting the terminals of the chip component 20 to the leads 12a, 12b in the region 21 is not particularly limited, but examples thereof include the following methods. Examples include a method of printing solder on the portions of the terminals of the chip component 20 facing the leads 12 and then soldering them together, and a method of providing a conductor between the chip component 20 and the leads 12 to connect them. Another example is a method of connecting the chip component 20 to the leads 12 using a printed wiring board other than the printed wiring board 30 on the mounting surface of the chip component 20 opposite the mounting surface that is connected to the printed wiring board 30. In this case, the terminals of the chip component 20 are joined to a printed wiring board (not shown) on the opposite mounting surface of the chip component 20 by soldering or the like, and the printed wiring board (not shown) is joined to the leads 12a, 12b in the region 21 by soldering or the like.

[0068] 6 is a graph showing the simulation results of the power supply impedance inside the integrated circuit device 10 having the configuration according to this embodiment, together with the simulation results of the comparative configuration described above and the configuration according to the third embodiment described below. The horizontal axis of the graph represents frequency, and the vertical axis represents the power supply impedance characteristics as seen from inside the integrated circuit device 10. In the graph, dashed line 91 represents the simulation results of the comparative configuration described above, solid line 93 represents the simulation results of the configuration according to this embodiment, and solid line 94 represents the simulation results of the configuration according to the third embodiment.

[0069] In this embodiment, component pad 41 provided on first main surface 35 of printed wiring board 30 on which integrated circuit device 10 is mounted and component pad 51 to which chip component 20 is connected are connected by wiring 61a with a parasitic inductance of 0.1 nH. Chip component 20 is a multilayer ceramic capacitor, and is the same component with a capacitance of 0.01 μF as in the comparative configuration and the first embodiment. In chip component 20, a terminal for supplying a power supply potential and a terminal for supplying a ground potential are connected to leads 12a and 12b of integrated circuit device 10, respectively, in region 21. On the other hand, the comparative configuration is the configuration shown in FIGS. 15A to 15E described above, and is run under the same conditions as the simulation shown in FIG. 4A.

[0070] In the configuration according to the present embodiment, the terminal of the chip component 20 is joined to the lead 12a in the region 21, and the terminal of the chip component 20 is joined to the lead 12b in the region corresponding to the region 21. In the configuration according to the present embodiment, in the equivalent circuit shown in Fig. 4C, LleadV1 corresponding to the lead 12a to which the power supply potential is supplied and LleadG1 corresponding to the lead 12b to which the ground potential is supplied can both be reduced compared to the configuration according to the first embodiment.

[0071] As a result, in the power supply impedance characteristics shown in FIG. 6, in the frequency band from 4 MHz to 85 MHz, the configuration according to this embodiment, shown by the solid line 93, is able to significantly reduce the power supply impedance compared to the comparative configuration, shown by the dashed line 91.

[0072] It should be noted that the chip component 20 does not necessarily need to have terminals bonded to both the leads 12a and 12b as described above. The chip component 20 only needs to have a terminal connected to at least one of the lead 12a to which the power supply potential to be supplied to the integrated circuit device 10 is supplied and the lead 12b to which the ground potential is supplied. However, it is preferable that terminals be connected to both the leads 12a and 12b, since this can reduce both LleadV1 and LleadG1 as described above.

[0073] [Third embodiment] An electronic device and an electronic module according to a third embodiment of the present invention will be described with reference to Figures 5A to 6. The basic configuration of the electronic device and the electronic module according to this embodiment is the same as that of the electronic device and the electronic module according to the first embodiment. In the electronic module 3 according to this embodiment, chip components 120 and 122 are mounted on a printed wiring board 30 instead of the chip component 20.

[0074] Fig. 5A is a perspective view showing a printed wiring board 30 constituting the electronic module 3 according to this embodiment. Fig. 5A shows a portion of the printed wiring board 30 on which the integrated circuit device 10 is mounted.

[0075] 5A, an integrated circuit device 10 and a chip component 120 are mounted on a first main surface 35 of a printed wiring board 30. The chip component 120 is mounted between the leads 12a of the integrated circuit device 10 and the first main surface 35 of the printed wiring board 30. In other words, the chip component 120 is disposed between the printed wiring board 30 and a portion of the leads 12a that is distant from the printed wiring board 30. The chip component 120 is a capacitor component such as a multilayer ceramic capacitor.

[0076] Fig. 5B is a cross-sectional view showing a cross section along the X direction indicated by region 39 in Fig. 5A. The cross section shown in Fig. 5B includes lead 12a as a power supply lead, which is one of leads 12 along the X direction to which a power supply potential to be supplied to integrated circuit device 10 is supplied in electronic module 3 according to this embodiment.

[0077] 5B, similar to the first embodiment, the printed wiring board 30 is a four-layer laminated board in which four conductor layers 31, 32, 33, and 34 are provided at a distance from each other in the Z direction from the first main surface 35 to the second main surface 36. A solder resist (not shown) may be disposed on the conductor layers 31 and 34. Each of the conductor layers 31, 32, 33, and 34 is provided with a conductor pattern that forms wiring. Furthermore, the printed wiring board 30 is provided with a through-hole 62 that forms wiring and extends from the conductor layer 31 to the conductor layer 34.

[0078] A lead 12a, which is one of the leads 12 of the integrated circuit device 10, is soldered and joined to a component pad 41 provided on the conductor layer 31 of the printed wiring board 30. One terminal of the chip component 120 is soldered and joined to a component pad 152 provided on the conductor layer 31. The other terminal of the chip component 120 is soldered and joined to the lead 12a of the integrated circuit device 10 in a region 121. The region 121 is located midway between the end of the package body 11 of the integrated circuit device 10 and the point where the lead 12 is connected to the component pad 41 of the printed wiring board 30. The other terminal of the chip component 120 is soldered and joined to a portion of the lead 12a in the region 121 that is away from the first main surface 35. The chip component 120, whose two terminals are connected in this manner, is mounted in a direction substantially parallel to the Z direction of the printed wiring board 30.

[0079] 5C is a plan view of first main surface 35 of conductor layer 31 in printed wiring board 30, viewed from above in the Z direction. As shown in FIG. 5C, component pads 40, 41, 42, and 43 are provided on conductor layer 31. Component pads 40, 41, 42, and 43 are arranged side by side around integrated circuit device 10 to correspond to multiple leads 12.

[0080] The multiple leads 12 of the integrated circuit device 10 are soldered and joined to component pads 40, 41, 42, and 43. Lead 12a, which is one of the leads 12 to which a power supply potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 41. Lead 12b, which is one of the leads 12 to which a ground potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 42.

[0081] Furthermore, a component pad 152 and a wiring 63a are provided on the conductor layer 31. The component pad 152 is provided in a position close to or adjacent to the component pad 41 having the power supply potential.

[0082] One terminal of chip component 120 is soldered and bonded to component pad 152. Component pad 152 is electrically connected to component pad 42, which has ground potential, via wiring 63a. In this way, one terminal of chip component 120 bonded to component pad 152 is electrically connected to lead 12b bonded to component pad 42.

[0083] Component pads 41, 42 may be electrically connected to chip components such as capacitor components (not shown) mounted in an area of ​​first main surface 35 other than the area onto which integrated circuit device 10 is projected, via wiring (not shown) provided on conductor layer 31. Component pads 41, 42 are also electrically connected to a power supply circuit (not shown) for supplying power to integrated circuit device 10, via wiring (not shown) provided on conductor layer 31.

[0084] In this embodiment, lead 12a, to which the power supply potential to be supplied to integrated circuit device 10 is supplied, can be connected to the other terminal of chip component 120 before being connected to component pad 41. Furthermore, one terminal of chip component 120 can be connected to lead 12b, to which ground potential is supplied, via component pad 152, wiring 63a, and component pad 42.

[0085] This configuration makes it possible to shorten the distance connecting the leads 12a, 12b of the integrated circuit device 10 to the chip component 120. As a result, in this embodiment, it becomes possible to reduce LleadV1 or LleadG1 shown in Fig. 4C. In order to reduce LleadG1, it is preferable that the wiring 63a be thick and short.

[0086] In the graph of FIG. 6 described above, solid line 94 indicates the results of a simulation of the power supply impedance characteristics of the configuration according to this embodiment. In the simulation, LleadG1 shown in FIG. 4C , which is the inductance component corresponding to wiring 63a connecting component pad 42 provided on first main surface 35 of printed wiring board 30 to chip component 120, is set to 0.1 nH. Chip component 120 is a multilayer ceramic capacitor, and is the same component with a capacitance of 0.01 μF as chip components 20 of the comparative configuration and the first and second embodiments. In this case, solid line 93 for the configuration according to the second embodiment and solid line 94 for the configuration according to this embodiment show approximately the same power supply impedance.

[0087] It is preferable that the region 121 where the chip component 120 and the lead 12a are connected is as close as possible to the end of the package body 11 of the integrated circuit device 10. The closer the region 121 is to the end of the package body 11, the greater the effect of reducing the power supply impedance.

[0088] 5C , component pad 43 having a power supply potential different from that of component pad 41 may be provided on conductor layer 31 in a position close to or adjacent to component pad 41, which connects lead 12a to which the power supply potential to be supplied to integrated circuit device 10 is supplied. Lead 12c, which serves as a power supply lead and is one of leads 12 of integrated circuit device 10, is soldered and joined to component pad 43. Even in such a configuration, by using the mounting structure according to this embodiment, it is possible to reduce the power supply impedance of both paths supplying power supply potentials that are close to or adjacent to each other.

[0089] In order to reduce the power supply impedances of both paths that supply power supply potentials close to or adjacent to each other, specifically, a configuration can be adopted in which a chip component 122 is mounted between the lead 12c and the first main surface 35 of the printed wiring board 30, as follows. That is, the chip component 122 can be disposed between the printed wiring board 30 and a portion of the lead 12c that is distant from the printed wiring board 30.

[0090] Specifically, as shown in FIG. 5C , a component pad 153 having ground potential is provided on the conductor layer 31 in a position close to or adjacent to the component pad 43. The component pad 153 is electrically connected to the component pad 152 via a wiring 63b provided on the conductor layer 31. The component pad 152 is electrically connected to the component pad 42 via a wiring 63a. One terminal of the chip component 122 is soldered and bonded to the component pad 153. The one terminal of the chip component 122 bonded to the component pad 153 is electrically connected to the lead 12b bonded to the component pad 42 via the wiring 63b, the component pad 152, and the wiring 63a. The other terminal of the chip component 122 is soldered and bonded in a region corresponding to the region 121 of the lead 12c connected to the component pad 43. That is, the other terminal of the chip component 122 is soldered and bonded to a portion of the region corresponding to the region 121 of the lead 12c, away from the first main surface 35. The chip component 122 having two terminals connected in this manner is mounted in a direction substantially parallel to the Z direction of the printed wiring board 30. The chip component 122 is a capacitor component such as a multilayer ceramic capacitor.

[0091] Between component pad 43 that supplies a power supply potential and component pad 42 that supplies a ground potential, component pad 41 that supplies another power supply potential is interposed. In this way, component pad 43 that supplies the power supply potential and component pad 42 that supplies the ground potential may be separated from each other. In this case, by mounting chip component 122 in an orientation that is approximately parallel to the Z direction of printed wiring board 30, integrated circuit device 10 and chip component 122 can be electrically connected with low impedance.

[0092] Although the configuration in which the leads 12a and 12c of the integrated circuit device 10 having a power supply potential are respectively connected to the chip components 120 and 122 has been described, the present invention is not limited to this. One terminal of the chip component 120 may be soldered and connected to the lead 12 having a ground potential. In this case, the other terminal of the chip component 120 may be soldered and connected to a component pad having a power supply potential provided on the conductor layer 31 of the printed wiring board 30. One terminal of the chip component 122 may also be soldered and connected to the lead 12 having a ground potential. In this case, the other terminal of the chip component 122 may be soldered and connected to the lead 12 having a ground potential. In this case, the other terminal of the chip component 122 may be soldered and connected to a component pad having a power supply potential provided on the conductor layer 31 of the printed wiring board 30.

[0093] Furthermore, a portion of the package body 11 of the integrated circuit device 10 may be located at a position lower than the height of the chip components 120, 122. Even in such a case, a space for mounting the chip components 120, 122 can be secured between the first main surface 35 of the printed wiring board 30 and the leads 12.

[0094] Furthermore, the leads 12, 12a, and 12c of the integrated circuit device 10 and the terminals of the chip components 120 and 122 are not necessarily joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive. Furthermore, the terminals of the chip components 120 and 122 and the component pads 152 and 153 are not necessarily joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive.

[0095] As described above, according to this embodiment, the electronic module 3 can achieve both a reduction in power supply impedance and a reduction in size.

[0096] [Fourth embodiment] An electronic device and an electronic module according to a fourth embodiment of the present invention will be described with reference to Figures 7A to 7C. The basic configuration of the electronic device and the electronic module according to this embodiment is the same as that of the electronic device and the electronic module according to the first embodiment. In the electronic module 3 according to this embodiment, chip components 130 and 131 are mounted on a printed wiring board 30 instead of the chip component 20.

[0097] Fig. 7A is a perspective view showing a printed wiring board 30 constituting the electronic module 3 according to this embodiment. Fig. 7A shows a portion of the printed wiring board 30 on which the integrated circuit device 10 is mounted.

[0098] As shown in Fig. 7A, an integrated circuit device 10 and chip components 130 and 131 are mounted on a first main surface 35 of a printed wiring board 30. As in the third embodiment shown in Fig. 5A, the chip component 131 is mounted between the lead 12a of the integrated circuit device 10 and the first main surface 35 of the printed wiring board 30. The chip component 130 is mounted between the lead 12b of the integrated circuit device 10 and the first main surface 35 of the printed wiring board 30. The chip component 131 is a resistor component, and the chip component 130 is a capacitor component such as a multilayer ceramic capacitor.

[0099] Chip component 131 is mounted between lead 12a having a power supply potential and first main surface 35 of printed wiring board 30. That is, chip component 131 is disposed between the printed wiring board 30 and a portion of lead 12a that is distant from printed wiring board 30. Chip component 130 is mounted between lead 12b having a ground potential and first main surface 35 of printed wiring board 30. That is, chip component 130 is disposed between the printed wiring board 30 and a portion of lead 12b that is distant from printed wiring board 30.

[0100] 7B is a plan view of first main surface 35 of printed wiring board 30 viewed from above in the Z direction. As shown in Fig. 7B, component pads 40, 41, and 42 are provided on conductor layer 31. Component pads 40, 41, and 42 are arranged side by side around integrated circuit device 10 to correspond to multiple leads 12.

[0101] The multiple leads 12 of the integrated circuit device 10 are soldered and joined to component pads 40, 41, and 42. Lead 12a, which is one of the leads 12 to which a power supply potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 41. Lead 12b, which is one of the leads 12 to which a ground potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 42.

[0102] Conductor layer 31 also has component pads 152 and 154 and wiring 63a and 161. Component pad 152 is located close to or adjacent to component pad 42, which has ground potential. Component pad 154 is located close to or adjacent to component pad 41, which has power supply potential.

[0103] One terminal of chip component 131 is soldered and joined to component pad 154. The other terminal of chip component 131 is soldered and joined to the middle of lead 12a having the power supply potential. In other words, the other terminal of chip component 131 is soldered and joined to a portion of lead 12a away from first main surface 35.

[0104] One terminal of the chip component 130 is soldered and joined to the component pad 152. The other terminal of the chip component 130 is soldered and joined to the middle of the lead 12b having the ground potential. In other words, the other terminal of the chip component 130 is soldered and joined to a portion of the lead 12b away from the first main surface 35.

[0105] Component pad 152 is electrically connected to component pad 42, which has ground potential, via wiring 63a. Component pad 154 is electrically connected to component pad 152 via wiring 161. One terminal of chip component 130 bonded to component pad 152 is electrically connected to lead 12b bonded to component pad 42 via wiring 63a. One terminal of chip component 131 bonded to component pad 154 is electrically connected to lead 12b bonded to component pad 42 via wiring 161, component pad 152, and wiring 63a.

[0106] With this configuration, a resistor and a capacitor can be connected in series between the power supply potential and ground potential of the integrated circuit device 10. Note that the chip component 131 may be a capacitor component, and the chip component 130 may be a resistor component.

[0107] The component pads 41, 42 are electrically connected to a power supply circuit (not shown) via wiring (not shown) provided on the conductor layer 31 in an area other than the area on the first main surface 35 where the integrated circuit device 10 is projected. A filter component, such as a ferrite bead, may be connected between the component pads 41, 42 and the power supply circuit (not shown).

[0108] 7C is a graph showing the simulation results of the power supply impedance characteristics inside integrated circuit device 10 for the configuration according to the comparative configuration, the configuration according to the third embodiment, and the configuration according to this embodiment. The horizontal axis of the graph represents frequency, and the vertical axis represents the power supply impedance characteristics as seen from inside integrated circuit device 10. In the graph, dashed line 91 represents the simulation results for the comparative configuration, solid line 94 represents the simulation results for the configuration according to the third embodiment, and solid line 95 represents the simulation results for the configuration according to this embodiment.

[0109] The chip component 130 is a multilayer ceramic capacitor, and is the same component with a resistance of 0.01 μF as in the comparative configuration and the third embodiment. The chip component 131 is a chip resistor component with a resistance of 1.1 Ω. The wirings 63 a and 161 each have a parasitic inductance of 0.1 nH.

[0110] With this configuration, in this embodiment, it is possible to reduce the power supply impedance that increases in the 100 MHz band in the configuration according to the third embodiment.

[0111] Note that a portion of the package body 11 of the integrated circuit device 10 may be located at a position lower than the height of the chip components 130, 131. Even in such a case, a space for mounting the chip components 130, 131 can be secured between the first main surface 35 of the printed wiring board 30 and the leads 12.

[0112] Furthermore, the leads 12a, 12b of the integrated circuit device 10 and the terminals of the chip components 131, 130 are not necessarily joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive. Furthermore, the terminals of the chip components 131, 130 and the component pads 154, 152 are not necessarily joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive.

[0113] As described above, according to this embodiment, the electronic module 3 can achieve both a reduction in power supply impedance and a reduction in size.

[0114] [Fifth embodiment] An electronic device and an electronic module according to a fifth embodiment of the present invention will be described with reference to Figures 8A and 8B. The basic configuration of the electronic device and the electronic module according to this embodiment is the same as that of the electronic device and the electronic module according to the first embodiment. In the electronic module 3 according to this embodiment, chip components 140 and 141 are mounted on a printed wiring board 30 instead of the chip component 20.

[0115] Fig. 8A is a perspective view showing a printed wiring board 30 constituting the electronic module 3 according to this embodiment. Fig. 8A shows a portion of the printed wiring board 30 on which the integrated circuit device 10 is mounted.

[0116] As shown in FIG. 8A , an integrated circuit device 10 and chip components 140 and 141 are mounted on a first main surface 35 of a printed wiring board 30. The chip component 140 is mounted between the leads 12 a and 12 b of the integrated circuit device 10 and the first main surface 35 of the printed wiring board 30. That is, the chip component 140 is disposed between the printed wiring board 30 and portions of the leads 12 a and 12 b that are distant from the printed wiring board 30. The chip component 141 is mounted between the lead 12 c of the integrated circuit device 10 and the first main surface 35 of the printed wiring board 30. That is, the chip component 141 is disposed between the printed wiring board 30 and portions of the lead 12 c that are distant from the printed wiring board 30. The chip components 140 and 141 are capacitor components such as multilayer ceramic capacitors.

[0117] 8B is a plan view of first main surface 35 of conductor layer 31 in printed wiring board 30, viewed from above in the Z direction. As shown in Fig. 8B, component pads 40, 41, 42, and 43 are provided on conductor layer 31. Component pads 40, 41, 42, and 43 are arranged side by side around integrated circuit device 10 to correspond to multiple leads 12.

[0118] The multiple leads 12 of the integrated circuit device 10 are soldered and joined to component pads 40, 41, 42, and 43. Lead 12a, which is one of the leads 12 to which a power supply potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 41. Lead 12b, which is one of the leads 12 to which a ground potential to the integrated circuit device 10 is supplied, is soldered and joined to component pad 42. Lead 12c, which is one of the leads 12 to which a power supply potential to be supplied to the integrated circuit device 10 is supplied, is soldered and joined to component pad 43. A power supply potential different from the power supply potential supplied to lead 12a is supplied to lead 12c.

[0119] Component pads 51 and 52 and wirings 61a, 63a, and 63b are provided on conductor layer 31. Component pad 51 is provided in a position close to or adjacent to component pad 41, which has a power supply potential. Component pad 52 is provided in a position close to or adjacent to component pad 42, which has a ground potential.

[0120] One terminal of the chip component 140 is soldered and bonded to the component pad 51. The other terminal of the chip component 140 is soldered and bonded to the component pad 52. The component pad 51 is electrically connected to the component pad 41 via the wiring 61a. The component pad 52 is electrically connected to the component pad 42 via the wiring 63a. One terminal of the chip component 140 bonded to the component pad 51 is electrically connected to the lead 12a bonded to the component pad 41 via the wiring 61a. The other terminal of the chip component 140 bonded to the component pad 52 is electrically connected to the lead 12b bonded to the component pad 42 via the wiring 63a.

[0121] One terminal of chip component 141 is soldered and joined to component pad 155. Component pad 155 is electrically connected via wiring 162 to component pad 43 to which lead 12c, one of leads 12 of integrated circuit device 10, is connected. The other terminal of chip component 141 is soldered and joined to component pad 156. Component pad 156 is electrically connected via wiring 63b to component pad 52 to which the other terminal of chip component 140 is connected. Component pad 52 is soldered and joined via wiring 63a to component pad 42 to which lead 12b, one of leads 12 of integrated circuit device 10, is connected. One terminal of chip component 141 joined to component pad 155 is electrically connected via wiring 162 to lead 12c joined to component pad 43. The other terminal of the chip component 141 bonded to the component pad 156 is electrically connected to the lead 12b bonded to the component pad 42 via the wiring 63b, the component pad 52, and the wiring 63a.

[0122] Component pads 41, 42, and 43 are connected to chip components (not shown) provided on conductor layer 31 or conductor layer 34 of printed wiring board 30 via wiring (not shown) provided on conductor layer 31. Component pads 41, 42, and 43 are also electrically connected to a power supply circuit (not shown) via wiring (not shown) provided on conductor layer 31.

[0123] In addition, although Figures 8A and 8B show chip components 140 and 141 having different configurations in terms of component size and mounted orientation, the component size and mounted orientation do not necessarily have to be different from each other.

[0124] In this embodiment, it is possible to adjust the component size, mounting orientation, wiring structure connecting chip components 140, 141, etc. of chip components 140, 141 mounted between leads 12a, 12b, 12c and first main surface 35 of integrated circuit device 10. As a result, in this embodiment, it is possible to reduce the parasitic inductance in the path supplying power supply potential to integrated circuit device 10, and reduce power supply impedance.

[0125] As shown in the second to fourth embodiments, it is preferable that one terminal and the other terminal of the chip component 140 are respectively soldered and joined to the middle of the leads 12a and 12b of the integrated circuit device 10. It is also preferable that one terminal or the other terminal of the chip component 141 is respectively soldered and joined to the middle of the lead 12c of the integrated circuit device 10, as shown in the second to fourth embodiments.

[0126] Furthermore, the two terminals of chip component 140 are bonded to component pads 51 and 52, but this is not limiting. Of the two terminals of chip component 140, one terminal may be bonded to component pad 51 and the other terminal may be bonded to the middle of lead 12b, or one terminal may be bonded to the middle of lead 12a and the other terminal may be bonded to component pad 52.

[0127] Note that a portion of the package body 11 of the integrated circuit device 10 may be located at a position lower than the height of the chip components 140, 141. Even in such a case, a space for mounting the chip components 140, 141 can be secured between the first main surface 35 of the printed wiring board 30 and the leads 12.

[0128] Furthermore, the terminals of chip components 140 and 141 and component pads 51, 52, 155 and 156 are not limited to being joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive. Similarly, the leads 12a, 12b and 12c of integrated circuit device 10 and the terminals of chip components 131 and 130 are not limited to being joined by soldering, but may be physically and electrically connected by a conductive material such as a conductive adhesive.

[0129] As described above, according to this embodiment, the electronic module 3 can achieve both a reduction in power supply impedance and a reduction in size.

[0130] [Other embodiments] The present disclosure is not limited to the above-described embodiments and various modifications are possible. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present disclosure.

[0131] Furthermore, in the above embodiment, an example has been described in which the integrated circuit device 10 is mounted as a semiconductor component, but other semiconductor components may be mounted instead of the integrated circuit device 10.

[0132] Furthermore, the power supply potential and ground potential supplied to each of the leads 12a, 12b, component pads 41, 42, etc. in the electronic module 3 may be reversed from those in the above embodiment.

[0133] Furthermore, the chip component 20 may be soldered and joined to the leads 12a and 12b. For example, as shown in Fig. 9, one terminal of the chip component 20 may be soldered and joined to the lead 12a, and the other terminal of the chip component 20 may be soldered and joined to the lead 12b. In this manner, the chip component 20 may be soldered to the leads 12a and 12b and mounted between the main surface 35 of the printed wiring board 30 and the leads 12a and 12b.

[0134] The chip components 20 can also be stacked and mounted on the main surface 35 of the printed wiring board 30. For example, as shown in FIG. 10 , a plurality of chip components 20 may be stacked vertically on the printed wiring board 30 between the main surface 35 of the printed wiring board 30 and the leads 12a, 12b. In this case, one terminal of the lower chip component 20 is connected to a component pad 51. The other terminal of the lower chip component 20 is connected to a component pad 52. One terminal of the upper chip component 20 is connected to one terminal of the lower chip component 20. The other terminal of the upper chip component 20 is connected to the other terminal of the lower chip component 20.

[0135] Alternatively, the chip component 20 may be mounted on the main surface 35 of the printed wiring board 30 with terminals bonded to component pads 41, 42 to which the leads 12a, 12b are connected. For example, as shown in FIG. 11 , the leads 12a, 12b may be connected to the printed wiring board 30 via the chip component 20 mounted on the main surface 35 of the printed wiring board 30. In this case, the lead 12a is electrically connected to the component pad 41 via one terminal of the chip component 20. The lead 12b is electrically connected to the component pad 42 via the other terminal of the chip component 20. The one and other terminals of the chip component 20 are soldered and bonded to the component pads 41, 42, respectively. In this way, the leads 12a, 12b may be electrically connected to the component pads 41, 42 via the one and other terminals of the chip component, respectively.

[0136] The chip component 20 can also be mounted on the printed wiring board 30 so as to be located between two adjacent leads 12. For example, as shown in Fig. 12, the chip component 20 may be mounted on the main surface 35 of the printed wiring board 30 so as to be located between the leads 12a and 12b. The chip component 20 is arranged so as not to overlap the package body 11 in the direction perpendicular to the main surface of the printed wiring board 30.

[0137] The chip component 20 can also be mounted on the leads 12. For example, as shown in FIG. 13, the chip component 20 may be mounted on the leads 12a and 12b connected to the printed wiring board 30 via the chip component 20 shown in FIG. 11. In this case, one terminal of the chip component 20 mounted on the leads 12a and 12b is connected to the lead 12a. The other terminal of the chip component 20 is connected to the lead 12b. The chip component 20 is soldered to the leads 12a and 12b so as not to overlap the package body 11 in the direction perpendicular to the main surface of the printed wiring board 30.

[0138] 12 mounted on the printed wiring board 30 so as to be positioned between two adjacent leads 12 can also be mounted on the printed wiring board 30 together with other chip components 20. For example, as shown in FIG. 14, in addition to the chip component 20 mounted on the first main surface 35 of the printed wiring board 30 as described in the first embodiment, another chip component 20 may be mounted on the first main surface 35 so as to be positioned between the lead 12a and the lead 12b.

[0139] In the above embodiment, the chip components 20, 70, 120, 122, 130, 140, and 141 are capacitor components, but this is not limiting. The chip components 20, 70, 120, 122, 130, 140, and 141 may be resistor components, inductor components, diode components, etc., in addition to capacitor components. In this case, the leads 12a, 12b, and 12c may be power supply leads or ground leads, or signal leads for inputting or outputting signals. Chip components such as capacitor components, resistor components, inductor components, and diode components may be arranged under the signal leads in the same manner as described above.

[0140] Furthermore, the second part soldered to the first part may be further soldered to a third part separate from the first part. Here, the first part, second part, and third part are each a terminal, a lead, or a pad. For example, a terminal soldered to a lead may also be soldered to a pad.

[0141] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present disclosure, and the technical scope of the present disclosure should not be interpreted as being limited by these embodiments. In other words, the present disclosure can be carried out in various forms without departing from its technical idea or main features.

[0142] The disclosure of this embodiment includes the following configurations and methods. (Configuration 1) A printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead each soldered to the printed wiring board; a chip component, The chip component is disposed between the printed wiring board and at least one of the first lead and the second lead. 1. An electronic module comprising: (Configuration 2) The chip component is arranged so as not to overlap the package body of the semiconductor component in a direction perpendicular to the main surface of the printed wiring board. 2. The electronic module according to claim 1, (Configuration 3) A printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead each soldered to the printed wiring board; a chip component, The chip component is disposed between the first lead and the second lead so as not to overlap the package body of the semiconductor component in a direction perpendicular to the main surface of the printed wiring board. 1. An electronic module comprising: (Configuration 4) A printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead each soldered to the printed wiring board; a chip component, The chip component is soldered to the first lead and the second lead so as not to overlap the package body of the semiconductor component in a direction perpendicular to the main surface of the printed wiring board. 1. An electronic module comprising: (Configuration 5) the chip component has a first terminal and a second terminal, The first terminal is electrically connected to the first lead. 5. The electronic module according to any one of configurations 1 to 4. (Configuration 6) The second terminal is electrically connected to the second lead. 6. The electronic module according to configuration 5. (Configuration 7) The first terminal is soldered to the first lead. 7. The electronic module according to configuration 5 or 6. (Configuration 8) The second terminal is soldered to the second lead. 8. The electronic module according to any one of configurations 5 to 7. (Configuration 9) The first terminal is soldered to the printed wiring board. 9. The electronic module according to any one of configurations 5 to 8. (Configuration 10) The second terminal is soldered to the second lead. 10. The electronic module according to any one of configurations 5 to 9. (Configuration 11) the printed wiring board has a first pad to which the first terminal is soldered; The first pad is electrically connected to the first lead. 11. The electronic module according to any one of configurations 5 to 10. (Configuration 12) The second terminal is soldered to the printed wiring board. 12. The electronic module according to any one of configurations 5 to 11. (Configuration 13) the printed wiring board has a first pad to which the first terminal is soldered; The first pad is electrically connected to the first lead. 13. The electronic module according to any one of configurations 5 to 12. (Configuration 14) the printed wiring board has a second pad to which the second terminal is soldered; The second pad is electrically connected to the second lead. 14. The electronic module according to any one of configurations 5 to 13. (Configuration 15) A part of the package body of the semiconductor component is located at a position lower than the height of the chip component. 15. The electronic module according to any one of configurations 1 to 14. (Configuration 16) The chip component includes a plurality of stacked chip components. 16. The electronic module according to any one of configurations 1 to 15. (Configuration 17) The first lead is connected to the printed wiring board via the chip component. 17. The electronic module according to any one of configurations 1 to 16. (Configuration 18) Another chip component is mounted on the first lead. 18. An electronic module according to any one of configurations 1 to 17. (Configuration 19) the first lead and the second lead are adjacent to each other; and a second chip positioned between the first lead and the second lead. 19. An electronic module according to any one of configurations 1 to 18. (Configuration 20) The chip component is a capacitor component. 20. An electronic module according to any one of configurations 1 to 19. (Configuration 21) The housing and an electronic module according to any one of configurations 1 to 20 disposed inside the housing; An electronic device comprising: [Explanation of symbols]

[0143] 1 Electronic equipment 3 Electronic Module 10 Integrated Circuit Devices 12, 12a, 12b, 12c leads 20, 70, 120, 122, 130, 131, 140, 141 Chip parts 30 Printed wiring board 40, 41, 42 component pads 51, 52, 152, 153, 154, 155, 156 Component pads 31, 32, 33, 34 Conductor layers 61a, 61b, 63a, 63b, 64, 161, 162 wiring 62 Penetrating Via

Claims

1. A printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead each soldered to the printed wiring board; a chip component; The chip component is disposed between the printed wiring board and at least one of the first lead and the second lead.

1. An electronic module comprising:

2. The chip component is arranged so as not to overlap the package body of the semiconductor component in a direction perpendicular to the main surface of the printed wiring board.

2. The electronic module of claim 1.

3. A printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead each soldered to the printed wiring board; a chip component; The chip component is disposed between the first lead and the second lead so as not to overlap the package body of the semiconductor component in a direction perpendicular to the main surface of the printed wiring board.

1. An electronic module comprising:

4. A printed wiring board; a semiconductor component mounted on the printed wiring board and having a first lead and a second lead each soldered to the printed wiring board; a chip component; The chip component is soldered to the first lead and the second lead so as not to overlap the package body of the semiconductor component in a direction perpendicular to the main surface of the printed wiring board.

1. An electronic module comprising:

5. the chip component has a first terminal and a second terminal, The first terminal is electrically connected to the first lead.

5. An electronic module according to any one of claims 1 to 4.

6. The second terminal is electrically connected to the second lead.

6. The electronic module according to claim 5.

7. The first terminal is soldered to the first lead.

6. The electronic module according to claim 5.

8. The second terminal is soldered to the second lead.

8. The electronic module according to claim 7.

9. The first terminal is soldered to the printed wiring board.

6. The electronic module according to claim 5.

10. The second terminal is soldered to the second lead.

10. The electronic module of claim 9.

11. the printed wiring board has a first pad to which the first terminal is soldered; The first pad is electrically connected to the first lead.

10. The electronic module of claim 9.

12. The second terminal is soldered to the printed wiring board.

10. The electronic module of claim 9.

13. the printed wiring board has a first pad to which the first terminal is soldered; The first pad is electrically connected to the first lead.

13. The electronic module of claim 12.

14. the printed wiring board has a second pad to which the second terminal is soldered; The second pad is electrically connected to the second lead.

13. The electronic module of claim 12.

15. A part of the package body of the semiconductor component is located at a position lower than the height of the chip component.

5. An electronic module according to any one of claims 1 to 4.

16. The chip component includes a plurality of stacked chip components.

5. An electronic module according to any one of claims 1 to 4.

17. The first lead is connected to the printed wiring board via the chip component.

5. An electronic module according to any one of claims 1 to 4.

18. Another chip component is mounted on the first lead.

5. An electronic module according to any one of claims 1 to 4.

19. the first lead and the second lead are adjacent to each other; and a second chip positioned between the first lead and the second lead.

5. An electronic module according to any one of claims 1 to 4.

20. The chip component is a capacitor component.

5. An electronic module according to any one of claims 1 to 4.

21. The housing and an electronic module according to any one of claims 1 to 4 disposed inside the housing; An electronic device comprising:

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