Electronic component

Abstract

To provide an electronic component which can be reduced in size and thickness while achieving desired characteristics.SOLUTION: The electronic component 1 includes a first input / output port 11, a second input / output port 12, a third input / output port 13, a first circuit 21, and a second circuit 22. The first circuit 21 has a first end 21a connected to the first input / output port 11 and a second end 21b connected to the second input / output port 12. The second circuit 22 has a first end 21b connected to the second input / output port 12 and the second end 22a of the first circuit 21, and a second end 21c connected to the third input / output port 13 and the third end 22b of the first circuit 21. Each of the first circuit 21 and the second circuit 22 includes at least one inductor and at least one capacitor. The second circuit 22 has a circuit configuration having a complex conjugate relationship with the circuit configuration of the first circuit 21.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to electronic components used in communication devices. [Background technology]

[0002] In recent years, wireless communication functions have been implemented in a variety of devices, including not only portable wireless communication devices such as mobile phones, portable information terminals, and body-worn terminals, but also automobiles, flying objects, and other transportation devices, as well as traffic signal devices, household electrical appliances, industrial devices, and measuring devices. The widespread use of such devices has led to a variety of devices, such as instruments, devices, and sensors, being connected via wireless communication. Some of these devices also have broadcast reception capabilities.

[0003] Some communication devices with wireless communication and broadcast reception functions are equipped with multiple antennas to stabilize the wireless communication and broadcast reception. A distributor / combiner is one of the electronic components used in communication devices equipped with multiple antennas. The distributor / combiner is used to distribute signals to multiple antennas or to combine multiple signals received by multiple antennas. For example, Patent Document 1 describes a high-frequency branch / divider composed of a low-pass filter and an impedance conversion filter connected to the low-pass filter. Each of the low-pass filter and the impedance conversion filter includes a capacitor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-16063 Summary of the Invention [Problem to be solved by the invention]

[0005] For communication devices with wireless communication and broadcast reception functions, there is a strong demand for faster and more sophisticated wireless communication and broadcasting, and the electronic components used in communication devices are also required to have higher performance. In addition, as communication devices have become increasingly miniaturized in recent years, there is a demand for smaller and thinner electronic components as well.

[0006] As described in Patent Document 1, a divider and combiner uses multiple elements such as inductors and capacitors. Generally, the number of elements increases as performance improves. Furthermore, depending on the frequency of the signals to which the divider and combiner is applied, the size of the elements increases. Therefore, in order to achieve a compact size while achieving the desired characteristics, it is necessary to devise a way to reduce the number of elements.

[0007] One of the objects of the present disclosure is to provide an electronic component that can be miniaturized while achieving desired characteristics. [Means for solving the problem]

[0008] The electronic component of the present disclosure includes a first circuit having a first input / output port, a second input / output port, a third input / output port, a first end connected to the first input / output port, a second end connected to the second input / output port, and a third end connected to the third input / output port, and a second circuit having a fourth end connected to the second input / output port and the second end, and a fifth end connected to the third input / output port and the third end. Each of the first circuit and the second circuit includes at least one inductor and at least one capacitor. The second circuit has a circuit configuration that is a complex conjugate of the circuit configuration of the first circuit. [Effects of the Invention]

[0009] In the electronic component of the present disclosure, the second circuit has a circuit configuration that is a complex conjugate of the circuit configuration of the first circuit, thereby enabling the present disclosure to realize a relatively small electronic component while achieving desired characteristics. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of an electronic component according to an embodiment of the present disclosure. [Figure 2] 1 is a block diagram showing a configuration of an electronic component according to an embodiment of the present disclosure. [Figure 3] 1 is a circuit diagram illustrating a circuit configuration of an electronic component according to an embodiment of the present disclosure. [Figure 4] 1 is a perspective view illustrating an electronic component according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a perspective view showing the inside of the laminate of the electronic component shown in FIG. [Figure 6] 6 is a perspective view showing the dielectric layers, conductor layers, and through-holes of the laminate of the electronic component shown in FIG. 5. [Figure 7] 7 is a plan view showing a pattern-forming surface of the first dielectric layer of the laminate of the electronic component shown in FIG. 6. FIG. [Figure 8] 7 is a plan view showing a pattern-forming surface of a second dielectric layer of the laminate of the electronic component shown in FIG. 6. FIG. [Figure 9] 7 is a plan view showing a pattern-forming surface of a third dielectric layer of the laminate of the electronic component shown in FIG. 6. FIG. [Figure 10] 7 is a plan view showing a pattern-forming surface of a fourth dielectric layer of the laminate of the electronic component shown in FIG. 6. FIG. [Figure 11] 7 is a plan view showing a terminal-forming surface of a fourth dielectric layer of the laminate of the electronic component shown in FIG. 6. FIG. [Figure 12] FIG. 10 is a characteristic diagram showing frequency characteristics of isolation of the model of the embodiment. [Figure 13] FIG. 10 is a characteristic diagram showing frequency characteristics of insertion loss of the model of the example. [Figure 14] FIG. 10 is a characteristic diagram showing the frequency characteristics of the return loss of the model of the example. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. First, the configuration of an electronic component according to an embodiment of the present disclosure will be described with reference to Figs. 1 to 3. Figs. 1 and 2 are block diagrams showing the configuration of the electronic component according to this embodiment. Fig. 3 is a circuit diagram showing the circuit configuration of the electronic component according to this embodiment.

[0012] The electronic component 1 according to this embodiment is a distributor / combiner that distributes or combines multiple signals. The electronic component 1 includes a first input / output port 11, a second input / output port 12, a third input / output port 13, a first circuit 21, and a second circuit 22.

[0013] In terms of the circuit configuration, the first circuit 21 is provided between the first input / output port 11 and the second and third input / output ports 12 and 13. In this application, the expression "in terms of the circuit configuration" refers to the arrangement on a circuit diagram, not the arrangement in a physical configuration. The second circuit 22 is connected to the first circuit 21.

[0014] As shown in FIG. 2, the electronic component 1 may further include a third circuit 23 and a matching circuit 24. The third circuit 23 is connected to the second circuit 22. The matching circuit 24 is provided between the first input / output port 11 and the first circuit 21 in terms of the circuit configuration. The third circuit 23 and the matching circuit 24 are not essential components of the electronic component 1 and may not be provided. The third circuit 23 and the matching circuit 24 are provided as appropriate depending on the specifications and characteristics required of the electronic component 1. Hereinafter, this embodiment will be described taking as an example a case where the electronic component 1 includes the third circuit 23 and the matching circuit 24 as shown in FIG. 2.

[0015] 3, the first circuit 21 has a first end 21a connected to the first input / output port 11, a second end 21b connected to the second input / output port 12, and a third end 21c connected to the third input / output port 13. In this embodiment, particularly, the first end 21a of the first circuit 21 is indirectly connected to the first input / output port 11 via a matching circuit 24. The second end 21b of the first circuit 21 is directly connected to the second input / output port 12. The third end 21c of the first circuit 21 is directly connected to the third input / output port 13.

[0016] The second circuit 22 has a first end 22a connected to the second end 21b of the first circuit 21, a second end 22b connected to the third end 21c of the first circuit 21, a third end 22c, and a fourth end 22d. The third circuit 23 has a first end 23a connected to the third end 22c of the second circuit 22 and a second end 23b connected to the fourth end 22d of the second circuit 22. The first end 22a of the second circuit 22 is further directly connected to the second input / output port 12. The second end 22b of the second circuit 22 is further directly connected to the third input / output port 13.

[0017] The second circuit 22 has a circuit configuration that is a complex conjugate of the first circuit 21. The circuit configuration that is a complex conjugate of the first circuit 21 is a circuit configuration in which the sign of the imaginary part of the impedance is opposite to that of the first circuit 21.

[0018] Each of the first and second circuits 21 and 22 includes at least one inductor and at least one capacitor. The inductor and the capacitor are elements whose imaginary parts of impedances have opposite signs. At least one inductor of the second circuit 22 is provided in the second circuit 22 so as to have a complex conjugate relationship with at least one capacitor of the first circuit 21. At least one capacitor of the second circuit 22 is provided in the second circuit 22 so as to have a complex conjugate relationship with at least one inductor of the first circuit 21.

[0019] Here, the path connecting the first terminal 21a and the second terminal 21b is referred to as path P11, and the path connecting the first terminal 21a and the third terminal 21c is referred to as path P12. Furthermore, the element of the first circuit 21 provided on path P11 is referred to as the first series element of the first circuit 21, and the element of the first circuit 21 provided on path P12 is referred to as the second series element of the first circuit 21. Furthermore, the element of the first circuit 21 provided between path P11 and path P12 is referred to as the parallel element of the first circuit 21.

[0020] In this embodiment, the elements constituting the second circuit 22 are provided in the second circuit 22 so as to have a complex conjugate relationship with the elements constituting the first circuit 21, as described below. In the second circuit 22, an element (first element) whose imaginary part of impedance has an opposite sign to that of the first series element of the first circuit 21 is connected in series to the first series element of the first circuit 21. Also, an element (second element) whose imaginary part of impedance has an opposite sign to that of the second series element of the first circuit 21 is connected in series to the second series element of the first circuit 21. Also, an element whose imaginary part of impedance has an opposite sign to that of the parallel element of the first circuit 21 is provided between the first element and the second element.

[0021] In particular, in this embodiment, the first circuit 21 includes a first inductor L11 provided on the path P11, a second inductor L12 provided on the path P12, and a first capacitor C11 provided between the paths P11 and P12. The circuit configuration of the first circuit 21 is symmetrical with respect to the first capacitor C11.

[0022] The path P11 is part of a path (first path) connecting the first input / output port 11 and the second input / output port 12. Therefore, it can be said that the first inductor L11 is provided in the first path. Similarly, the path P12 is part of a path (second path) connecting the first input / output port 11 and the third input / output port 13. Therefore, it can be said that the second inductor L12 is provided in the second path.

[0023] The second circuit 22 includes a second capacitor C21 connected in series to the first inductor L11, a third capacitor C22 connected in series to the second inductor L12, and a third inductor L21. Here, a path connecting the first terminal 22a and the third terminal 22c is referred to as a path P21, and a path connecting the second terminal 22b and the fourth terminal 22d is referred to as a path P22. The second capacitor C21 is provided on the path P21. The third capacitor C22 is provided on the path P22.

[0024] The second circuit 22 further includes a resistive element R21. The third inductor L21 and the resistive element R21 are provided between the path P21 and the path P22. The circuit configuration of the second circuit 22 is symmetrical with respect to the third inductor L21 and the resistive element R21.

[0025] The second input / output port 12 is connected to a path connecting the first inductor L11 of the first circuit 21 and the second capacitor C21 of the second circuit 22. The third input / output port 13 is connected to a path connecting the second inductor L12 of the first circuit 21 and the third capacitor C22 of the second circuit 22.

[0026] The third circuit 23 includes a capacitor C31 provided in a path connecting the first terminal 23a and the second terminal 23b.

[0027] In this embodiment, a low-pass filter circuit is used as the matching circuit 24. That is, the matching circuit 24 includes an inductor L41 provided on a path P4 connecting the first input / output port 11 and the first end 21a of the first circuit 21, and capacitors C41 and C42 provided between the path P4 and ground.

[0028] The number of inductors provided in the first circuit 21 may be the same as the number of capacitors provided in the second circuit 22. In the example shown in Fig. 3, the number of inductors provided in the first circuit 21 and the number of capacitors provided in the second circuit 22 are two.

[0029] The number of capacitors provided in the first circuit 21 may be the same as the number of inductors provided in the second circuit 22. In this embodiment, the number of inductors provided in the first circuit 21 and the number of capacitors provided in the second circuit 22 are one.

[0030] The inductance of the first inductor L11 and the inductance of the second inductor L12 may be smaller than the inductance of the third inductor L21. Also, the inductance of the first inductor L11 and the inductance of the second inductor L12 may be smaller than the inductance of the inductor L41.

[0031] Next, the connection relationship of the components of the electronic component 1 according to this embodiment will be described with reference to Fig. 3. One end of the inductor L41 of the matching circuit 24 is connected to the first input / output port 11. One end of the capacitor C41 of the matching circuit 24 is connected to one end of the inductor L41. One end of the capacitor C42 of the matching circuit 24 is connected to the other end of the inductor L41. The other ends of the capacitors C41 and C42 are connected to ground.

[0032] One end of the first inductor L11 of the first circuit 21 and one end of the second inductor L12 of the first circuit 21 are connected to a node ND. The node ND is connected to the other end of the inductor L41 of the matching circuit 24.

[0033] The other end of the first inductor L11 is connected to the second input / output port 12. The other end of the second inductor L12 is connected to the third input / output port 13. One end of the first capacitor C11 of the first circuit 21 is connected to the other end of the first inductor L11. The other end of the first capacitor C11 of the first circuit 21 is connected to the other end of the second inductor L12.

[0034] One end of the second capacitor C21 of the second circuit 22 is connected to the other end of the first inductor L11 of the first circuit 21 and the second input / output port 12. One end of the third capacitor C22 of the second circuit 22 is connected to the other end of the second inductor L12 of the first circuit 21 and the third input / output port 13.

[0035] One end of each of the third inductor L21 and the resistor R21 of the second circuit 22 is connected to the other end of the second capacitor C21. The other ends of each of the third inductor L21 and the resistor R21 are connected to the other end of the third capacitor C22.

[0036] One end of the capacitor C31 of the third circuit 23 is connected to the other end of the second capacitor C21 of the second circuit 22. The other end of the capacitor C31 is connected to the other end of the third capacitor C22 of the second circuit 22.

[0037] 3, the first circuit 21 and the second circuit 22 are not connected to ground, and the third circuit 23 is also not connected to ground. The matching circuit 24 is connected to ground.

[0038] Next, an example of the structure of the electronic component 1 will be described with reference to Figs. 4 to 6. Fig. 4 is a perspective view of the electronic component 1. Fig. 5 is a perspective view showing the inside of the laminate of the electronic component 1. Fig. 6 is a perspective view showing the dielectric layers, conductor layers, and through-holes of the laminate of the electronic component 1. The electronic component 1 further includes a laminate 30 for integrating the first to third input / output ports 11 to 13, the first to third circuits 21 to 23, and the matching circuit 24. As will be described in detail later, the laminate 30 includes a plurality of laminated dielectric layers and a plurality of conductor layers.

[0039] The laminate 30 has a rectangular parallelepiped shape. The laminate 30 has a top surface 30a, a bottom surface 30b, and four side surfaces 30c to 30f that form the outer periphery of the laminate 30. The top surface 30a and the bottom surface 30b face in opposite directions, the side surfaces 30c and 30d also face in opposite directions, and the side surfaces 30e and 30f also face in opposite directions. The side surfaces 30c to 30f are perpendicular or nearly perpendicular to the top surface 30a and the bottom surface 30b. In the laminate 30, the direction perpendicular to the top surface 30a and the bottom surface 30b is the stacking direction of the multiple dielectric layers and multiple conductor layers. In Figures 5 and 6, this stacking direction is indicated by an arrow with the symbol T. The top surface 30a and the bottom surface 30b are located at both ends of the stacking direction T.

[0040] The electronic component 1 further includes a first terminal 41, a second terminal 42, a third terminal 43, and a fourth terminal 44 provided on the laminate 30. As shown in FIG. 4, the first to fourth terminals 41 to 44 are arranged on the bottom surface 30b of the laminate 30. The first terminal 41 corresponds to the first input / output port 11. The second terminal 42 corresponds to the second input / output port 12. The third terminal 43 corresponds to the third input / output port 13. The fourth terminal 44 is connected to ground.

[0041] Next, the laminate 30 will be described in detail with reference to Fig. 6 to Fig. 11. The laminate 30 includes four laminated dielectric layers. Hereinafter, these four dielectric layers will be referred to as the first dielectric layer 31, the second dielectric layer 32, the third dielectric layer 33, and the fourth dielectric layer 34, in that order from the top surface side of the laminate 30. In Fig. 6, the first to fourth dielectric layers 31 to 34 are drawn spaced apart from one another along the lamination direction T (see Figs. 4 and 5).

[0042] Each of the first to fourth dielectric layers 31 to 34 has a pattern formation surface. The fourth dielectric layer 34 has a terminal formation surface located on the opposite side to the pattern formation surface. Fig. 7 shows the pattern formation surface of the first dielectric layer 31. Fig. 8 shows the pattern formation surface of the second dielectric layer 32. Fig. 9 shows the pattern formation surface of the third dielectric layer 33. Fig. 10 shows the pattern formation surface of the fourth dielectric layer 34. Fig. 11 shows the terminal formation surface of the fourth dielectric layer 34.

[0043] As shown in Figure 7, conductor layers 101, 102, 103, and 104, conductor layers 111, 112, 113, 114, 115, 116, and 117 for the first circuit 21, conductor layers 121, 122, 123, and 124 for the second circuit 22, and conductor layers 141, 142, 143, and 144 for the matching circuit 24 are formed on the pattern forming surface of the first dielectric layer 31.

[0044] Each of the conductor layers 111, 112, 121, and 143 has a first end and a second end located opposite to each other. The first end of the conductor layer 111, the first end of the conductor layer 112, and the first end of the conductor layer 143 are connected to the conductor layer 117. The first end of the conductor layer 121 is connected to the conductor layer 122. In FIG. 7, the boundary between two conductor layers is indicated by a dotted line.

[0045] The conductor layer 123 is connected to the conductor layer 103. The conductor layer 141 is connected to the conductor layer 101. The conductor layer 142 is connected to the conductor layer 107.

[0046] Furthermore, through holes T101, T102, T103, T104, T105, T106, T107, T108, T109, T110, T111, and T112 are formed in the dielectric layer 31. The through holes T101 to T104 are connected to the conductor layers 101 to 104, respectively.

[0047] The through hole T105 is connected to a portion of the conductor layer 111 near its second end. The through hole T106 is connected to a portion of the conductor layer 112 near its second end. The through hole T107 is connected to the conductor layer 115. The through hole T108 is connected to the conductor layer 122. The through hole T109 is connected to the conductor layer 121 near its second end. The through hole T111 is connected to the conductor layer 143 near its second end.

[0048] 8, conductor layers 201, 202, 203, and 204, conductor layers 211, 212, 213, 214, 215, and 216 for the first circuit 21, conductor layers 221, 222, 223, 224, and 225 for the second circuit 22, conductor layer 231 for the third circuit 23, and conductor layers 241, 242, 243, and 244 for the matching circuit 24 are formed on the pattern formation surface of the second dielectric layer 32. Each of the conductor layers 211, 212, 221, and 243 has a first end and a second end located opposite to each other.

[0049] Conductive layer 222 is connected to conductive layer 202. Conductive layer 231 is connected to conductive layer 223. Conductive layers 241 and 242 are connected to conductive layer 204. In FIG. 8, the boundary between the two conductive layers is indicated by a dotted line.

[0050] The through holes T101 to T104 formed in the first dielectric layer 31 are connected to the conductor layers 201 to 204, respectively.

[0051] In FIG. 8, dashed lines indicate the connection positions of through holes T105 to T112 formed in the first dielectric layer 31. The through hole T105 is connected to a portion of the conductor layer 211 near the first end. The through hole T106 is connected to a portion of the conductor layer 212 near the first end. The through hole T107 is connected to the conductor layer 215. The through holes T108 and T112 are connected to the conductor layer 225. The through hole T109 is connected to a portion of the conductor layer 221 near the first end. The through hole T110 is connected to the conductor layer 223. The through hole T111 is connected to a portion of the conductor layer 243 near the first end.

[0052] Furthermore, through holes T201, T202, T203, T204, T205, T206, T207, T208, T209, T210, and T211 are formed in the dielectric layer 32. The through holes T201 to T204 are connected to the conductor layers 201 to 204, respectively.

[0053] The through hole T205 is connected to a portion of the conductor layer 211 near its second end. The through hole T206 is connected to a portion of the conductor layer 212 near its second end. The through hole T207 is connected to the conductor layer 215. The through hole T208 is connected to the conductor layer 216. The through hole T209 is connected to a portion of the conductor layer 221 near its second end. The through hole T210 is connected to the conductor layer 223. The through hole T211 is connected to a portion of the conductor layer 243 near its second end.

[0054] 9, conductor layers 301, 302, 303, and 304, conductor layers 311, 312, 313, and 314 for the first circuit 21, conductor layers 321 and 322 for the second circuit 22, and a conductor layer 343 for the matching circuit 24 are formed on the pattern formation surface of the third dielectric layer 33. Each of the conductor layers 311, 312, 321, and 343 has a first end and a second end located opposite to each other.

[0055] The through holes T201 to T204 formed in the second dielectric layer 32 are connected to the conductor layers 301 to 304, respectively.

[0056] In FIG. 9, dashed lines indicate the connection positions of through holes T205 to T211 formed in the second dielectric layer 32. The through hole T205 is connected to a portion of the conductor layer 311 near its first end. The through hole T206 is connected to a portion of the conductor layer 312 near its first end. The through hole T207 is connected to the conductor layer 313. The through hole T208 is connected to the conductor layer 314. The through hole T209 is connected to a portion of the conductor layer 321 near its first end. The through hole T210 is connected to the conductor layer 322. The through hole T211 is connected to a portion of the conductor layer 343 near its first end.

[0057] Furthermore, through holes T301, T302, T303, T304, T305, T306, T307, T308, T309, T310, and T311 are formed in the dielectric layer 33. The through holes T301 to T304 are connected to the conductor layers 301 to 304, respectively.

[0058] The through hole T305 is connected to a portion of the conductor layer 311 near its second end. The through hole T306 is connected to a portion of the conductor layer 312 near its second end. The through hole T307 is connected to the conductor layer 313. The through hole T308 is connected to the conductor layer 314. The through hole T309 is connected to a portion of the conductor layer 321 near its second end. The through hole T310 is connected to the conductor layer 322. The through hole T311 is connected to a portion of the conductor layer 343 near its second end.

[0059] 10, conductor layers 401, 402, 403, and 404, conductor layers 411, 412, 413, and 414 for the first circuit 21, a conductor layer 421 for the second circuit 22, and a conductor layer 443 for the matching circuit 24 are formed on the pattern formation surface of the fourth dielectric layer 34. Each of the conductor layers 411 to 414, 421, and 443 has a first end and a second end located opposite to each other.

[0060] A first end of conductor layer 413 is connected to conductor layer 402. A second end of conductor layer 413 is connected to a first end of conductor layer 411. A first end of conductor layer 414 is connected to conductor layer 403. A second end of conductor layer 414 is connected to a first end of conductor layer 412. A first end of conductor layer 443 is connected to conductor layer 401. In FIG. 10, the boundary between the two conductor layers is indicated by a dotted line.

[0061] Through holes T301 to T304 formed in the third dielectric layer 33 are connected to the conductor layers 401 to 404, respectively.

[0062] In FIG. 10, dashed lines indicate the connection positions of through holes T305 to T311 formed in the third dielectric layer 33. The through hole T305 is connected to a portion of the conductor layer 411 near the second end. The through hole T306 is connected to a portion of the conductor layer 412 near the second end. The through hole T307 is connected to a portion of the conductor layer 413 near the second end. The through hole T308 is connected to a portion of the conductor layer 414 near the second end. The through hole T309 is connected to a portion of the conductor layer 421 near the first end. The through hole T310 is connected to a portion of the conductor layer 421 near the second end. The through hole T311 is connected to a portion of the conductor layer 443 near the second end.

[0063] Furthermore, through holes T401, T402, T403, and T404 are formed in the dielectric layer 34. The through holes T401 to T404 are connected to the conductor layers 401 to 404, respectively.

[0064] As shown in Fig. 11, first to fourth terminals 41 to 44 are formed on the terminal formation surface of the fourth dielectric layer 34. In Fig. 11, the dashed lines indicate the connection positions of through holes T401 to T404. The through holes T401 to T404 are connected to the first to fourth terminals 41 to 44, respectively.

[0065] The laminate 30 shown in FIG. 4 is configured by stacking the first to fourth dielectric layers 31 to 34 such that the terminal-forming surface of the fourth dielectric layer 34 is the bottom surface 30b of the laminate 30. The electronic component 1 may also include a support substrate (not shown) that supports the laminate 30. The laminate 30 and the support substrate are aligned in the stacking direction T. The support substrate has a top surface, a bottom surface, and four side surfaces that form the outer periphery of the support substrate. The top surface of the laminate 30 and the bottom surface of the support substrate face each other. The electronic component 1 may also include an insulating layer (not shown) interposed between the first dielectric layer 31 of the laminate 30 and the support substrate.

[0066] The following describes the correspondence between the components of the electronic component 1 and the internal components of the laminate 30 shown in Figures 6 to 11. First, the first circuit 21 will be described. The first inductor L11 is composed of conductor layers 111, 211, 311, and 411 and through holes T105, T205, and T305. The second inductor L12 is composed of conductor layers 112, 212, 312, and 412 and through holes T106, T206, and T306.

[0067] The first capacitor C11 is formed by the conductor layers 115 and 216 and the dielectric layer 31 between the conductor layers 115 and 216.

[0068] Next, a description will be given of the second circuit 22. The third inductor L21 is composed of conductor layers 121, 221, 321, and 421, and through holes T109, T209, and T309.

[0069] The second capacitor C21 is formed by conductor layers 122 and 222 and a dielectric layer 31 between the conductor layers 122 and 222. The third capacitor C22 is formed by conductor layers 123 and 223 and a dielectric layer 31 between the conductor layers 123 and 223. Although not shown, the resistive element R21 is connected to through holes T110 and T112.

[0070] Next, a description will be given of the third circuit 23. The capacitor C31 is composed of conductor layers 122 and 231 and a dielectric layer 31 between the conductor layers 122 and 231.

[0071] Next, we will explain the matching circuit 24. The inductor L41 is composed of conductor layers 143, 243, 343, and 443, and through holes T111, T211, and T311.

[0072] The capacitor C41 is formed by conductor layers 141 and 241 and a dielectric layer 31 between the conductor layers 141 and 241. The capacitor C42 is formed by conductor layers 142 and 242 and a dielectric layer 31 between the conductor layers 142 and 242.

[0073] Next, the operation and effect of the electronic component 1 according to this embodiment will be described. The electronic component 1 according to this embodiment is a divider and combiner. Isolation is one of the main parameters that represent the characteristics of a divider and combiner. The isolation of the electronic component 1 is defined as follows: When a high-frequency signal with power p20 is input to the second input / output port 12, the power of the signal output from the third input / output port 13 is set to P23. The isolation I is defined by the following equation (1). It is preferable that the isolation I be, for example, -20 dB or less.

[0074] I=10log(P23 / P20) …(1)

[0075] The effects of this embodiment will be described below with reference to the results of simulations. First, an example model used in the simulations will be described. The example model is a model of the electronic component 1 according to this embodiment. In the example model, the parameters of each of the multiple components of the electronic component 1 are designed so that the frequency band used by the electronic component 1 is 1.2 to 1.6 GHz.

[0076] In the simulation, the isolation, insertion loss, reflection loss at the first input / output port 11, and reflection loss at the second input / output port 12 were calculated for the model of the example. The definitions of the insertion loss and reflection loss of the electronic component 1 are as follows: When power p10 is input to the first input / output port 11, the power of the signal reflected at the first input / output port 11 is defined as p11, the power of the signal output from the second input / output port 12 is defined as p12, and the power of the signal output from the third input / output port 13 is defined as p13. Furthermore, when a high-frequency signal with power p20 is input to the second input / output port 12, the power of the signal reflected at the second input / output port 12 is defined as p22, and the power of the signal output from the first input / output port 11 is defined as p21. The insertion loss IL1 between the first input / output port 11 and the second input / output port 12, the insertion loss IL2 between the first input / output port 11 and the third input / output port 13, the return loss RL1 of the first input / output port 11, and the return loss RL2 of the second input / output port 12 are defined by the following equations (2) to (5), respectively.

[0077] IL1=10log(p12 / p10) …(2) IL2=10log(p13 / P10) …(3) RL1=10log(p11 / p10) …(4) RL2=10log(p22 / p20) …(5)

[0078] Fig. 12 is a characteristic diagram showing the frequency characteristics of isolation in the model of the example. In Fig. 12, the horizontal axis represents frequency and the vertical axis represents isolation. In the model of the example, the isolation is -20 dB or less when the frequency is in the range of 1.2 to 1.6 GHz.

[0079] FIG. 13 is a characteristic diagram showing the frequency characteristics of insertion loss in the model of the embodiment. FIG. 14 is a characteristic diagram showing the frequency characteristics of return loss at the second input / output port 12 in the model of the embodiment. In FIG. 13, the horizontal axis represents frequency, and the vertical axis represents insertion loss. Also in FIG. 13, the solid curve represents insertion loss IL1 between the first input / output port 11 and the second input / output port 12, and the dashed curve represents insertion loss IL2 between the first input / output port 11 and the third input / output port 13. In FIG. 14, the horizontal axis represents frequency, and the vertical axis represents return loss. Note that in FIG. 14, the return loss RL1 at the first input / output port 11 and the return loss RL2 at the second input / output port 12 almost overlap. From FIGS. 13 and 14, it can be seen that the electronic component 1 has sufficient characteristics for practical use as a distributor and combiner.

[0080] The model of the embodiment is designed so that a relatively low frequency band is used. Generally, the lower the frequency band used, the larger the area of ​​the elements. Therefore, when a relatively low frequency band is used, it is necessary to devise a way to reduce the number and area of ​​elements in order to make the electronic component 1 smaller and thinner.

[0081] In this embodiment, a low-pass filter circuit is used as matching circuit 24. In electronic component 1, a high-pass filter circuit can also be used as matching circuit 24. However, in this case, the number of inductors increases and the inductance of the inductors needs to be increased to a certain extent. Therefore, according to this embodiment, by using a low-pass filter circuit as matching circuit 24, the number of inductors can be reduced and the inductance of the inductors can be made smaller. As a result, according to this embodiment, the area occupied by matching circuit 24 can be reduced, allowing the electronic component 1 to be made smaller and thinner.

[0082] In this embodiment, the first capacitor C11 of the first circuit 21 is provided between the path P11 and the path P12. Instead of the first capacitor C11, the electronic component 1 may also include a capacitor provided between the path P11 and the ground and a capacitor provided between the path P12 and the ground. However, this would increase the number of capacitors and require a terminal connected to the ground. Therefore, in this embodiment, the first capacitor C11 can reduce the number of capacitors and the number of terminals connected to the ground. As a result, this embodiment allows the electronic component 1 to be made smaller and thinner.

[0083] In this embodiment, the first circuit 21 and the second circuit 22 are not connected to the ground, which makes it possible to reduce the number of terminals connected to the ground.

[0084] In this embodiment, the third circuit 23 includes a capacitor C31 provided in a path connecting the first terminal 23a and the second terminal 23b. In the electronic component 1, instead of the capacitor C31, a capacitor connected in series with the second capacitor C21 of the second circuit 22 and a capacitor connected in series with the third capacitor C22 of the second circuit 22 can be provided. However, in this case, the number of capacitors increases and the capacitance of the capacitors needs to be increased to a certain extent. Therefore, according to this embodiment, the capacitor C31 can reduce the number of capacitors and the capacitance of the capacitors. As a result, according to this embodiment, the area occupied by the third circuit 23 can be reduced, thereby enabling the electronic component 1 to be made smaller and thinner.

[0085] In this embodiment, only one first inductor L11 is provided in the path P11 of the first circuit 21, and only one second inductor L12 is provided in the path P12 of the first circuit 21. In the electronic component 1, it is also possible to provide two first inductors in the path P11 and two second inductors in the path P12, connect one end of the first capacitor C11 to the junction of the two first inductors, and connect the other end of the first capacitor C11 to the junction of the two second inductors. However, this would require a large number of inductors and a relatively large inductance for each inductor. Therefore, according to this embodiment, by using one first inductor L11 and one second inductor L12, the number of inductors can be reduced and the inductance of each inductor can be reduced. As a result, according to this embodiment, the area occupied by the first circuit 21 can be reduced, thereby enabling the electronic component 1 to be made smaller and thinner.

[0086] Furthermore, in this embodiment, the inductance of the first inductor L11 and the inductance of the second inductor L12 are smaller than the inductance of the third inductor L21. That is, in this embodiment, the inductances of the inductors (first and second inductors L11, L12) included in the first circuit 21, which has a larger number of inductors than the second circuit 22, are made smaller. As a result, according to this embodiment, the inductances of the inductors (first and second inductors L11, L12) included in the first circuit 21 are made smaller than in the case where the inductance of the inductor (third inductor L21) included in the second circuit 22, which has a smaller number of inductors than the first circuit 21, is made smaller, thereby making it possible to reduce the area occupied by the inductors and make the electronic component 1 smaller and thinner.

[0087] Furthermore, in this embodiment, the inductance of the first inductor L11 and the inductance of the second inductor L12 are smaller than the inductance of the inductor L41 of the matching circuit 24. That is, in this embodiment, the inductances of the inductors (first and second inductors L11, L12) included in the first circuit 21, which has a larger number of inductors than the matching circuit 24, are made smaller. As a result, according to this embodiment, the inductances of the inductors (first and second inductors L11, L12) included in the first circuit 21 are made smaller than in a case where the inductance of the inductor (inductor L41) included in the matching circuit 24, which has a smaller number of inductors than the first circuit 21, is made smaller, thereby making it possible to reduce the area occupied by the inductors and make the electronic component 1 smaller and thinner.

[0088] The present disclosure is not limited to the above-described embodiments and may be modified in various ways. For example, as long as the requirements of the claims are met, the number of input / output ports on the branch side and the number and arrangement of inductors and capacitors in each circuit are not limited to the examples shown in the embodiments and may be arbitrary. The number of input / output ports on the branch side is not limited to two or three, but may be four or more. Each of the first and second circuits may further include additional circuit elements, such as parasitic capacitance components between two or more conductor layers and inductance components of the conductor layers themselves.

[0089] Furthermore, the first to third circuits of the present disclosure are not limited to distributors and combiners, but can also be applied to electronic components having various functions such as branchers, shunts, mixers, splitters, dividers, combiners, and 3 dB hybrids.

[0090] Furthermore, as long as the electronic component of the present disclosure has a circuit configuration that satisfies the scope of the claims, it can be configured using a low-temperature co-fired ceramic (LTCC) multilayer substrate, or discrete elements, i.e., chip capacitors, chip inductors, and chip resistors, rather than being limited to the laminate 30 described with reference to Figures 6 to 12.

[0091] As described above, the electronic component of the present disclosure includes a first circuit having a first input / output port, a second input / output port, a third input / output port, a first end connected to the first input / output port, a second end connected to the second input / output port, and a third end connected to the third input / output port, and a second circuit having a fourth end connected to the second input / output port and the second end, and a fifth end connected to the third input / output port and the third end. Each of the first circuit and the second circuit includes at least one inductor and at least one capacitor. The second circuit has a circuit configuration that is a complex conjugate of the circuit configuration of the first circuit.

[0092] In the electronic component of the present disclosure, at least one inductor of the second circuit may be provided in the second circuit so as to have a complex conjugate relationship with at least one capacitor of the first circuit, and at least one capacitor of the second circuit may be provided in the second circuit so as to have a complex conjugate relationship with at least one inductor of the first circuit.

[0093] In the electronic component of the present disclosure, the number of the at least one inductor provided in the first circuit may be the same as the number of the at least one capacitor provided in the second circuit.The number of the at least one capacitor provided in the first circuit may be the same as the number of the at least one inductor provided in the second circuit.

[0094] Furthermore, in the electronic component of the present disclosure, the first circuit may include a first inductor, a second inductor, and a first capacitor as the at least one inductor and at least one capacitor. The first inductor may be provided in a first path connecting the first input / output port and the second input / output port. The second inductor may be provided in a second path connecting the first input / output port and the third input / output port. The first capacitor may have one end connected to the first path and the other end connected to the second path. The second circuit may include a third inductor, a second capacitor, and a third capacitor as the at least one inductor and at least one capacitor. The second capacitor may be connected in series with the first inductor. The third capacitor may be connected in series with the second inductor. The third inductor may have one end connected to the second capacitor and the other end connected to the third capacitor. The second input / output port may be connected to the path connecting the first inductor and the second capacitor. The third input / output port may be connected to a path connecting the second inductor and the third capacitor.

[0095] The circuit configuration of the first circuit may be symmetrical about the first capacitor. The second circuit may further include a resistive element connected in parallel with the third inductor. The circuit configuration of the second circuit may be symmetrical about the third inductor and the resistive element. The inductance of the first inductor and the inductance of the second inductor may be smaller than the inductance of the third inductor.

[0096] The electronic component of the present disclosure may further include a matching circuit provided between the first input / output port and the first circuit. The matching circuit may include a fourth inductor provided in a third path connecting the first input / output port and the first end of the first circuit, and a fourth capacitor provided between the third path and ground. The inductance of the first inductor and the inductance of the second inductor may be smaller than the inductance of the fourth inductor.

[0097] In the electronic component of the present disclosure, the first circuit and the second circuit do not have to be connected to ground.

[0098] The electronic component of the present disclosure may further include a third circuit. The second circuit may further have a sixth terminal and a seventh terminal. The third circuit may have an eighth terminal connected to the sixth terminal and a ninth terminal connected to the seventh terminal, and may include a capacitor.

[0099] The electronic components of the present disclosure may also be distributors and combiners. [Explanation of symbols]

[0100] 1...electronic component, 11...first input / output port, 12...second input / output port, 13...third input / output port, 21...first circuit, 22...second circuit, 23...third circuit, 24...matching circuit, 30...laminated body, 31-34...dielectric layers, 41...first terminal, 42...second terminal, 43...third terminal, 44...fourth terminal, C11...first capacitor, C21...second capacitor, C22...third capacitor, C31, C41, C42...capacitors, L11...first inductor, L12...second inductor, L21...third inductor, L41...inductor, R21...resistive element.

Claims

1. a first input / output port; a second input / output port; a third input / output port; a first circuit having a first end connected to the first input / output port, a second end connected to the second input / output port, and a third end connected to the third input / output port; a second circuit having a fourth end connected to the second input / output port and the second end, and a fifth end connected to the third input / output port and the third end; each of the first circuit and the second circuit includes at least one inductor and at least one capacitor; The electronic component, wherein the second circuit has a circuit configuration that is a complex conjugate of the circuit configuration of the first circuit.

2. the at least one inductor of the second circuit is provided in the second circuit so as to have a complex conjugate relationship with the at least one capacitor of the first circuit; 2. The electronic component according to claim 1, wherein the at least one capacitor of the second circuit is provided in the second circuit so as to have a complex conjugate relationship with the at least one inductor of the first circuit.

3. the number of the at least one inductor provided in the first circuit is equal to the number of the at least one capacitor provided in the second circuit; 2. The electronic component according to claim 1, wherein the number of the at least one capacitor provided in the first circuit is the same as the number of the at least one inductor provided in the second circuit.

4. the first circuit includes a first inductor, a second inductor, and a first capacitor as the at least one inductor and the at least one capacitor; the first inductor is provided in a first path connecting the first input / output port and the second input / output port; the second inductor is provided in a second path connecting the first input / output port and the third input / output port; the first capacitor has one end connected to the first path and the other end connected to the second path; the second circuit includes a third inductor, a second capacitor, and a third capacitor as the at least one inductor and the at least one capacitor; the second capacitor is connected in series with the first inductor; the third capacitor is connected in series with the second inductor; 2. The electronic component according to claim 1, wherein one end of the third inductor is connected to the second capacitor and the other end is connected to the third capacitor.

5. the second input / output port is connected to a path connecting the first inductor and the second capacitor; 5. The electronic component according to claim 4, wherein the third input / output port is connected to a path connecting the second inductor and the third capacitor.

6. 5. The electronic component according to claim 4, wherein the circuit configuration of the first circuit is symmetrical with respect to the first capacitor.

7. 5. The electronic component according to claim 4, wherein the second circuit further includes a resistive element connected in parallel to the third inductor.

8. 8. The electronic component according to claim 7, wherein the circuit configuration of the second circuit is symmetrical with respect to the third inductor and the resistive element.

9. 5. The electronic component according to claim 4, wherein the inductance of the first inductor and the inductance of the second inductor are smaller than the inductance of the third inductor.

10. further comprising a matching circuit provided between the first input / output port and the first circuit; 5. The electronic component according to claim 4, wherein the matching circuit includes a fourth inductor provided in a third path connecting the first input / output port and the first end of the first circuit, and a fourth capacitor provided between the third path and ground.

11. 11. The electronic component according to claim 10, wherein the inductance of the first inductor and the inductance of the second inductor are smaller than the inductance of the fourth inductor.

12. 2. The electronic component according to claim 1, wherein the first circuit and the second circuit are not connected to ground.

13. further comprising a third circuit, the second circuit further has a sixth terminal and a seventh terminal; 2. The electronic component according to claim 1, wherein the third circuit has an eighth terminal connected to the sixth terminal and a ninth terminal connected to the seventh terminal, and includes a capacitor.

14. 14. The electronic component according to claim 1, wherein the electronic component is a distributor and combiner.

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