Power loss protection controller circuit, power loss protection circuit, and data storage device

Abstract

To provide a power supply circuit which is more robust against power loss.SOLUTION: The feedback circuit 242 generates the feedback control signal C2 so that the voltage VSTR of the backup capacitor CTL1 approaches the first target level VSTR (REF) in the step-up mode, and generates the feedback control signal CTL1 so that the voltage VBUS approaches the second target level VBUS (REF) in the step-down mode. The logic circuit 244 controls the high-side driver 232 and the low-side driver 234 based on the feedback control signal CTL1. When switching from the step-up mode to the step-down mode, the high-side forced-on circuit 246 controls the logic circuit 244 so as to forcibly fix the high-side transistor M1 to the on-state during a high-side forced-on period of a predetermined length.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power loss protection circuit. [Background technology]

[0002] A stable supply of power voltage is essential for electronic components. A momentary power interruption in storage devices such as solid-state drives and hard disks can result in the destruction or loss of stored data. Even after the input voltage is cut off, the power supply voltage must be maintained long enough for the load to perform necessary protection processes, such as data verification. This type of function is known as power loss protection or power interruption protection, and is also known in English as PLP (Power Loss Protection), PLI (Power Loss Imminent), or PFP (Power Failure Protection).

[0003] 1 is a block diagram of a system with a PLP function. The system 2 includes a power supply 10, a load 20, and a power loss protection (PLP) circuit 30. The power supply 10 receives an input voltage V of about 12 V. IN The load 20 includes a PMIC (power management circuit) 22 and a plurality of electronic components 24_1 to 24_n. The PMIC 22 generates a 12V power supply voltage V BUS The power supply circuit 24 receives the power, boosts or lowers the voltage, and supplies the voltage to the electronic components 24_1 to 24_n.

[0004] The PLP circuit 30 is provided between the power supply 10 and the load 20. The PLP circuit 30 includes a switch 32, a backup capacitor 34, and a bidirectional converter 36.

[0005] The switch 32 is provided on a power supply line 38 connecting the power supply 10 and the load 20. The available input voltage V IN is supplied, switch 32 is on, and the input voltage V IN is the power supply voltage V BUSThe input terminal IN of the bidirectional converter 36 is connected to the power supply line 38, and the output terminal OUT is connected to the backup capacitor 34. The bidirectional converter 36 converts the input voltage V IN While the input voltage V IN is boosted and the backup capacitor 34 is charged (boost mode). The capacitance of the backup capacitor 34 is C, and the voltage generated in the backup capacitor 34 is V STR Then, the charge Q and energy E stored in the backup capacitor 34 are expressed by the following equations: Q=C·V STR E=C·V STR 2 / 2

[0006] The PLP circuit 30 receives an input voltage V IN When the interruption (loss) of the power supply is detected, the switch 32 is turned off. The bidirectional converter 36 then operates in the reverse direction as a step-down converter with the OUT side as the input and the IN side as the output, and the capacitor voltage V STR , the power supply voltage V BUS and supplies it to the load 20 (step-down mode). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2021-5924 Summary of the Invention [Problem to be solved by the invention]

[0008] 1, there is a delay in switching between the normal step-up operation of the bidirectional converter 36 and the step-down operation when power is lost. If this delay is long, the voltage V BUS will drop, and the load 20 will become inoperable.

[0009] [overview] The present disclosure has been made in this context, and one exemplary purpose of an embodiment thereof is to provide a PLP circuit that is more robust against power loss.

[0010] A power loss protection controller circuit according to an embodiment of the present disclosure receives an input voltage and supplies an output voltage to a load. The power loss protection controller circuit includes a bidirectional converter that, in a step-up mode, boosts the input voltage to charge a backup capacitor and, in a step-down mode, steps down the voltage of the backup capacitor to generate an output voltage, and a converter controller that operates the bidirectional converter in the step-up mode in a normal state when the input voltage is higher than a predetermined threshold voltage and operates the bidirectional converter in the step-down mode in a power loss state when the input voltage is lower than the threshold voltage. The bidirectional converter includes a bootstrap circuit, a high-side transistor and a low-side transistor, a high-side driver that drives the high-side transistor, a low-side driver that drives the low-side transistor, and a voltage maintenance circuit that is provided separately from the bootstrap circuit and that maintains the voltage of the bootstrap line of the bidirectional converter at a voltage that is higher by a predetermined voltage step than the switching voltage. The converter controller includes: a feedback circuit that generates a feedback control signal in a step-up mode so that the voltage of the backup capacitor approaches a first target level; and that generates a feedback control signal in a step-down mode so that the output voltage approaches a second target level; a logic circuit that controls the high-side driver and the low-side driver based on the feedback control signal; and a high-side forced-on circuit that controls the logic circuit to forcibly fix the high-side transistor to on during a high-side forced-on interval of a predetermined length when switching from the step-up mode to the step-down mode. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of a system with PLP functionality. [Figure 2] FIG. 2 is a circuit diagram of a PLP circuit according to a comparative technique. [Figure 3] FIG. 3 is a waveform diagram illustrating the operation of the PLP controller of FIG. [Figure 4] FIG. 4 is a circuit diagram of a PLP circuit according to an embodiment. [Figure 5] FIG. 5 is a circuit diagram of a voltage maintenance circuit according to an embodiment. [Figure 6] FIG. 6 is a waveform diagram illustrating the operation of the PLP circuit of FIG. [Figure 7] FIG. 7 is a circuit diagram of a PLP circuit according to the first modification. [Figure 8] FIG. 8 is a circuit diagram of a PLP circuit according to the second modification. [Figure 9] FIG. 9 is a diagram illustrating the first control example. [Figure 10] FIG. 10 is a diagram illustrating the second control example. [Figure 11] FIG. 11 is a diagram illustrating the third control example. [Figure 12] FIG. 12 is a diagram illustrating another problem that occurs in basic control. [Figure 13] FIG. 13 is a diagram illustrating the fourth control example. [Figure 14] FIG. 14 is a circuit diagram of a PLP circuit according to the third modification. [Figure 15] FIG. 15 is a waveform diagram illustrating the operation of the PLP circuit of FIG. [Figure 16] FIG. 16 is a block diagram of a data storage device with a PLP function.

[0012] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] According to one embodiment, a power loss protection controller circuit receives an input voltage and supplies an output voltage to a load. The power loss protection controller circuit includes a bidirectional converter that, in a step-up mode, boosts the input voltage to charge a backup capacitor and, in a step-down mode, steps down the voltage of the backup capacitor to generate an output voltage. The bidirectional converter also includes a converter controller that operates the bidirectional converter in the step-up mode in a normal state when the input voltage is higher than a predetermined threshold voltage and operates the bidirectional converter in the step-down mode in a power loss state when the input voltage is lower than the threshold voltage. The bidirectional converter includes a bootstrap circuit, a high-side transistor and a low-side transistor, a high-side driver that drives the high-side transistor, a low-side driver that drives the low-side transistor, and a voltage maintenance circuit that is provided separately from the bootstrap circuit and that maintains the voltage of the bootstrap line of the bidirectional converter at a voltage that is higher than a switching voltage by a predetermined voltage step. The converter controller includes: a feedback circuit that generates a feedback control signal in a step-up mode so that the voltage of the backup capacitor approaches a first target level; and that generates a feedback control signal in a step-down mode so that the output voltage approaches a second target level; a logic circuit that controls the high-side driver and the low-side driver based on the feedback control signal; and a high-side forced-on circuit that controls the logic circuit to forcibly fix the high-side transistor to on during a high-side forced-on interval of a predetermined length when switching from the step-up mode to the step-down mode.

[0014] With this configuration, immediately after switching from step-up mode to step-down mode due to a power loss, the high-side transistor can be fixed on immediately based on the output of the high-side forced-on circuit without being affected by delays in the analog feedback circuit, thereby suppressing a drop in output voltage.

[0015] In one embodiment, the voltage maintenance circuit may include a charge pump circuit.

[0016] In one embodiment, the voltage maintenance circuit may include a charging circuit that charges the bootstrap line based on the voltage of the backup capacitor.

[0017] In one embodiment, the converter controller may control the bidirectional converter so that the on-period of the low-side transistor immediately after the high-side forced on-period is not narrower than a predetermined minimum width, thereby protecting the high-side transistor and the low-side transistor.

[0018] In one embodiment, the converter controller may disable the forcing on of the high-side transistor when the target level of the output voltage of the bidirectional converter in buck mode is lower than a threshold voltage, thereby preventing the output voltage from changing in a direction opposite to the target level.

[0019] In one embodiment, when the converter controller disables the forced on of the high-side transistor, the converter controller may temporarily shift the target level of the output voltage of the bidirectional converter to a voltage level higher than normal immediately after switching to the buck mode, thereby enabling the output voltage to be stabilized at the target level in a short time.

[0020] In one embodiment, the converter controller includes an overcurrent protection function that limits the current flowing through the inductor of the bidirectional converter so that it does not exceed an overcurrent threshold, and may increase the overcurrent threshold over time after switching from boost mode to buck mode, thereby suppressing overshoot of the output voltage.

[0021] In one embodiment, the converter controller may further include a low-side force-on circuit that controls the logic circuit to forcibly fix the low-side transistor to on during a low-side force-on interval of a predetermined length when switching from the buck mode to the boost mode, thereby suppressing undershoot of the voltage of the backup capacitor.

[0022] In one embodiment, the converter controller may terminate the low-side forced-on interval when the inductor current commutates and reaches a predetermined peak current.

[0023] In one embodiment, the bidirectional converter may operate in a synchronous rectification mode in boost mode. In one embodiment, the bidirectional converter may operate in a diode rectification mode in boost mode.

[0024] In one embodiment, the power loss protection controller circuitry may be integrated onto a single semiconductor substrate.

[0025] A power loss protection circuit according to one embodiment may include a backup capacitor and any of the power loss protection controller circuits described above coupled to the backup capacitor.

[0026] A data storage device according to one embodiment may include the power loss protection circuit described above.

[0027] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are merely examples and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0028] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected, but also a case in which component A and component B are indirectly connected via another component that does not affect the electrical connection or impair function. Also, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which component C is indirectly connected via another component that does not affect the electrical connection or impair function.

[0029] The technical significance of the PLP circuit according to the embodiment will become clear when compared with a comparative technique, so the comparative technique will be described first.

[0030] (Comparative Technology) 2 is a circuit diagram of a PLP circuit 100R according to a comparative technique. The PLP circuit 100R receives an input voltage V IN and outputs an output voltage (called a bus voltage) V BUS supply.

[0031] The PLP circuit 100R includes a PLP controller 200R and its peripheral circuits, which may include an output capacitor C1, a backup capacitor C2, a bootstrap capacitor C3, an inductor L1, and the like.

[0032] The PLP controller 200R is a functional IC (Integrated Circuit) in which the PLP circuit 100R is integrated on a semiconductor substrate.

[0033] The input terminal VIN of the PLP controller 200R is connected to the input line 104, and the input voltage V IN The output terminal VBUS of the PLP controller 200R is connected to a load via an output line 108. The storage terminal VSTR of the PLP controller 200R is connected to a backup capacitor C2 via a backup line 106.

[0034] An inductor L1 is connected between the switching terminal SW of the PLP controller 200R and the output line 108. A bootstrap capacitor C3 is connected between the switching terminal SW of the PLP controller 200R and the bootstrap terminal BST.

[0035] The PLP controller 200R includes a switch 210, a switch controller 220, a bidirectional converter 230R, and a converter controller 240R.

[0036] The switch 210, also called an electronic fuse, is connected between the input terminal VIN and the output terminal VBUS. The switch 210 may be a bidirectional switch.

[0037] The switch controller 220 is connected to the input voltage V IN Or the output voltage V BUS Voltage V is either DET For example, the switch controller 220 may monitor the voltage V DET , the PLP threshold V TH(PLP) The switch controller 220 may include a voltage comparator that compares V DET >V TH(PLP) When V is in normal condition, DET <V TH(PLP) The switch controller 220 turns on the switch 210 in a normal state and turns off the switch 210 in a power loss state.

[0038] The bidirectional converter 230R includes a high-side transistor M1, a low-side transistor M2, a diode D1, a high-side driver 232, and a low-side driver 234. The high-side transistor M1 is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is connected between a storage terminal VSTR and a switching terminal SW. The low-side transistor M2 is also an N-channel MOSFET and is connected between the switching terminal SW and a ground terminal PGND.

[0039] The high-side driver 232 drives the high-side transistor M1 based on a high-side control signal S1, and the low-side driver 234 drives the low-side transistor M2 based on a low-side control signal S2.

[0040] The diode D1 forms a bootstrap circuit together with the bootstrap capacitor C3. The cathode of the diode D1 is connected to the bootstrap terminal BST via the bootstrap line 204. A constant voltage V REG The bootstrap circuit generates a bootstrap voltage V BST is V SW +V REG -Vf. Bootstrap voltage V BST is supplied to the high-side driver 232 as a gate high voltage of the high-side transistor M1. Vf is the forward voltage of the diode D1. Note that instead of the diode D1, a synchronous switch that is controlled in synchronization with the switching of the bidirectional converter 230R may be provided.

[0041] In a normal state, the converter controller 240R operates the bidirectional converter 230R in a boost mode. Specifically, the voltage V of the backup capacitor C2 (referred to as a capacitor voltage) STR is the predetermined target voltage V STR(REF) The high-side transistor M1 and the low-side transistor M2 are feedback-controlled so that the output voltage V BUS is boosted and the power is stored in the backup capacitor C2. Note that in boost mode, the high-side transistor M1 and the low-side transistor M2 may operate in synchronous rectification mode, where they switch complementarily. Alternatively, the high-side transistor M1 may operate in diode rectification mode, where it is fixed to the off position.

[0042] In a power loss state, the converter controller 240R operates the bidirectional converter 230R in buck mode. This reduces the voltage V of the backup capacitor C2. STR is stepped down and the output voltage V BUS Specifically, the output voltage V BUS is the predetermined target voltage VBUS(REF) The high-side transistor M1 and the low-side transistor M2 are feedback-controlled so that the voltage is stabilized to a certain voltage (for example, 12V).

[0043] The converter controller 240R includes a feedback circuit 242 configured as an analog circuit, and a logic circuit 244.

[0044] The feedback circuit 242 receives the bus voltage V BUS Feedback voltage V according to BUS_FB and the feedback voltage V according to the capacitor voltage VSTR STR_FB is entered.

[0045] In the boost mode, the feedback circuit 242 STR is the first target level V STR(REF) In buck mode, the feedback control signal CTL1 is generated so that the output voltage V BUS is the second target level V BUS(REF) The feedback circuit 242 generates a feedback control signal CTL1 so that the high-side transistor M1 and the low-side transistor M2 are close to each other. The feedback circuit 242 includes analog circuits such as an error amplifier and a voltage comparator. The feedback control signal CTL1 may include a timing signal that triggers turning on or off the high-side transistor M1 and the low-side transistor M2, a pulse signal that defines the on time or off time, or the like.

[0046] The circuit configuration of the feedback circuit 242 is not particularly limited, and can be configured using known technology.

[0047] The logic circuit 244 generates a high-side control signal S1 and a low-side control signal S2 based on the feedback control signal CTL1, and controls the high-side driver 232 and the low-side driver 234.

[0048] The above is the configuration of the PLP controller 200R.

[0049] Next, the operation will be explained.

[0050] 3 is a waveform diagram illustrating the operation of the PLP controller 200R of FIG. 2. Before time t0, the state is normal, and the threshold voltage V TH(PLP) Input voltage higher than V IN is being supplied.

[0051] Input voltage V IN In a normal state, the bidirectional converter 230R operates in boost mode. FIG. 3 shows a state in which the backup capacitor C2 is fully charged, and the capacitor voltage V STR is V STR(REF) =30V. In this state, the bidirectional converter 230R is in a light load state and operates in pulse frequency modulation (PFM) mode. That is, the bidirectional converter 230R repeats a period T1 in which the low-side transistor M2 is on and the high-side transistor M1 is off, a period T2 in which the low-side transistor M2 is off and the high-side transistor M1 is on, and a high-impedance period T3 in which both the high-side transistor M1 and the low-side transistor M2 are off. In period T1, the switching voltage V SW is 0V, and in section T2, the switching voltage V SW is the voltage V of the backup capacitor C2 STR In section T3, the switching voltage V SW is the input voltage V IN =12V.

[0052] At time t0, the input voltage V IN is the threshold voltage V TH(PLP) Ideally, switching control in the buck mode should start immediately at time t0. However, since the feedback circuit 242 of the converter controller 240 has a delay due to an error amplifier and the like, switching in the buck mode occurs at time t1, which is a certain time τ1 later than time t0. During this delay time τ1, the output voltage V BUS will decrease, and the threshold voltage V TH(PLP)It will be lower than that.

[0053] At time t1, switching in the buck mode begins. In the buck mode, a period T4 in which the low-side transistor M2 is on and the high-side transistor M1 is off and a period T5 in which the low-side transistor M2 is off and the high-side transistor M1 is on occur alternately.

[0054] In the section T4 (indicated by τ2 in FIG. 2) immediately after time t1, the coil current I L is negative. This means that the charge is discharged from the output capacitor C1, and the output voltage V BUS will decrease further.

[0055] In other words, in the comparison technique, the output voltage V BUS is the threshold voltage of PLP, V TH(PLP) After falling below , it continues to decrease in the two sections τ1 and τ2. As a result, the output voltage V BUS This may result in unstable operation of the load being supplied with the

[0056] The above is the operation of the PLP controller 200R. Next, the PLP controller 200 according to the embodiment will be described.

[0057] (Embodiment) 4 is a circuit diagram of an embodiment of a PLP circuit 100. The switch 210 is a bidirectional switch and may include two N-channel MOSFETs connected in anti-series.

[0058] In this embodiment, the bidirectional converter 230 is provided with a voltage maintenance circuit 236. The bootstrap circuit does not operate unless the bidirectional converter 230 is switching, and therefore cannot appropriately maintain the potential difference between the bootstrap line 204 and the switching line 202 when switching is stopped.

[0059] The voltage maintenance circuit 236 is provided separately from the bootstrap circuit. The voltage maintenance circuit 236 maintains the voltage V BST , the switching voltage V SW Voltage V is higher by a certain voltage step ΔV than SW In other words, the potential difference between the bootstrap line 204 and the switching line 202 is kept at a constant value ΔV.

[0060] The voltage maintenance circuit 236 maintains the switching voltage V SW A constant voltage V REG The charge pump circuit may be a charge pump circuit that adds

[0061] 5 is a circuit diagram of a voltage maintenance circuit 236A according to one embodiment. The voltage maintenance circuit 236A is a charge pump circuit. The type of the charge pump circuit is not particularly limited, but may include, for example, a flying capacitor Cf, rectifying elements D11 and D12, and a driver circuit DR1. The driver circuit DR1 receives a clock signal CLK and outputs a constant voltage V REG A pulse signal with an amplitude of is supplied to one end of the flying capacitor Cf. The other end of the flying capacitor Cf is supplied with the switching voltage V, which is the input voltage, via a rectifier element D11. SW The other end of the flying capacitor Cf is connected to the output capacitor Co via a rectifying element D12. The output capacitor Co may be a bootstrap capacitor C3.

[0062] In this example, the rectifying elements D11 and D12 are diodes, but they may be configured with transistors instead. The topology of the charge pump circuit is not limited to that shown in Figure 5, and can be configured using known or future available technologies.

[0063] Returning to FIG. 4, the addition of the voltage maintenance circuit 236 reduces the bootstrap voltage V BST is always equal to the switching voltage V SWThis maintains the voltage higher than the gate threshold voltage V between the gate and source of the high-side transistor M1. GS(th) Therefore, a higher gate high voltage can be applied.

[0064] The converter controller 240 is provided with a high-side forced-on circuit 246 in addition to a feedback circuit 242 and a logic circuit 244 .

[0065] When switching from the step-up mode to the step-down mode, the high-side forcible-on circuit 246 generates a high-side forcible-on signal CTL2 and controls the logic circuit 244 to forcibly fix the high-side transistor M1 to on during a high-side forcible-on interval of a predetermined length. Note that during the forcible-on interval, the logic circuit 244 fixes the low-side transistor M2 to off.

[0066] The above is the configuration of the PLP circuit 100. Next, its operation will be explained.

[0067] 6 is a waveform diagram illustrating the operation of the PLP circuit 100 of FIG. 4. Before time t0, the state is normal, and the threshold voltage V TH(PLP) Input voltage higher than V IN is being supplied.

[0068] In a normal state, the bidirectional converter 230 operates in a pulse frequency modulation (PFM) mode, and repeats a period T1 in which the low-side transistor M2 is on and the high-side transistor M1 is off, a period T2 in which the low-side transistor M2 is off and the high-side transistor M1 is on, and a high-impedance period T3 in which both the high-side transistor M1 and the low-side transistor M2 are off.

[0069] At time t0, the input voltage V IN is the threshold voltage V TH(PLP)If it goes lower, a power loss protection state is triggered, turning off switch 210 and switching bidirectional converter 230 from boost mode to buck mode.

[0070] When switching from the step-up mode to the step-down mode, regardless of the feedback signal CTL1 generated by the feedback circuit 242, the logic circuit 244 responds to the high-side forcible-on signal CTL2 generated by the high-side forcible-on circuit 246 to forcibly fix the high-side transistor M1 to on and forcibly fix the low-side transistor M2 to off during a high-side forcible-on interval T6 of a predetermined length.

[0071] The voltage V of the bootstrap line 204 BST is maintained by the voltage maintenance circuit 236 at the switching voltage V SW At time t0, high-side driver 232 can turn on high-side transistor M1 because VOUT is maintained at a voltage level higher than VOUT.

[0072] After the high-side forced-on interval T6 ends, the logic circuit 244 operates the bidirectional converter 230 in the step-down mode based on the feedback signal CTL1 generated by the feedback circuit 242. In the step-down mode, intervals T4 and T5 are alternately repeated.

[0073] The operation of the PLP circuit 100 is as described above.

[0074] In this PLP circuit 100, when a voltage loss state is detected at time t0, the high-side forced-on circuit 246 digitally controls the high-side transistor M1 to be turned on and the low-side transistor M2 to be turned off at time t0, regardless of the state of the feedback circuit 242 of the converter controller 240. This reduces the effect of the delay (τ1 in FIG. 3) of the analog circuit, and the output voltage V BUS This can suppress the decline in

[0075] Also, during the high-side forced-on section T6 immediately after switching from the step-up mode to the step-down mode, the high-side transistor M1 is on and the low-side transistor M2 is off, so the coil current I L flows in the direction of charging the output capacitor C1. This causes the output voltage V BUS can be increased compared to the conventional technology, BUS This can suppress the decline in

[0076] Next, a modification of the PLP circuit 100 will be described.

[0077] (Variation 1) 7 is a circuit diagram of a PLP circuit 100A according to Modification 1. In this modification, a voltage maintenance circuit 236A maintains the voltage V of the backup capacitor C2. STR The charging circuit includes a charging circuit that receives the reference voltage V as an input voltage. The charging circuit is, for example, a linear regulator circuit (LDO: Low Drop Output), and supplies the reference voltage to the switching voltage V SW The capacitor voltage V STR is the output voltage V BUS , the voltage V of the bootstrap line 204 can be reduced without using a charge pump circuit. BST The switching voltage V SW The voltage can be stabilized to an appropriate voltage level that is a predetermined voltage higher than the reference voltage.

[0078] (Variation 2) 8 is a circuit diagram of a PLP circuit 100B according to Modification 2. In this modification, the PLP controller 200B further includes a blocking transistor (FET) 250. A blocking input terminal VBBIN of the PLP controller 200B is connected to an inductor L1. The blocking transistor 250 is provided between the blocking input terminal VBBIN and the output terminal VBUS.

[0079] In the configuration of FIG. 4, when the PLP controller 200B starts up, the input voltage V INWhen power is turned on, the backlap line 106 is charged through a charging path that includes the switch 210, the inductor L1, and the high-side transistor M1. If the impedance of this charging path is too low, an inrush current may flow.

[0080] Blocking transistor 250 is inserted to prevent inrush current from flowing through backup capacitor C2. At startup, switch controller 220B gradually reduces the on-resistance of blocking transistor 250 over time.

[0081] The switch 210 may have the function of the blocking transistor 250. That is, the switch controller 220 may gradually reduce the on-resistance of the switch 210 over time at startup. In this case, at startup, the output voltage V BUS Although the rise speed of the signal is slower, the blocking transistor 250 is not required.

[0082] Next, a more preferable control of the bidirectional converter 230 by the converter controller 240 will be described.

[0083] Control example 1 9 is a diagram illustrating Control Example 1. Depending on the operating state of the PLP circuit 100, the on-period T4 of the low-side transistor M2 immediately after the high-side forced on interval T6 may become very short. If the on-period T4 of the low-side transistor M2 is too short, stress may be applied to the high-side transistor M1 and the low-side transistor M2, potentially reducing their reliability.

[0084] Therefore, the converter controller 240 determines whether the on-period T4 immediately after the high-side forced on-period T6 has a predetermined minimum width T MIN Generate control signals S1 and S2 so that they do not become narrower than the minimum width T MIN can be set to, for example, several hundred ns, specifically, about 100 ns to 500 ns, and more specifically, about 250 ns.

[0085] This makes it possible to prevent the reliability of the high-side transistor M1 and the low-side transistor M2 from decreasing.

[0086] Control example 2 FIG. 10 is a diagram illustrating Control Example 2. In the above description, the bus voltage V BUS Target Level V BUS(REF) is the threshold voltage of PLP, V TH(PLP) (V BUS(REF) >V TH(PLP) ) This is called basic control.

[0087] PLP threshold voltage V TH(PLP) and the output voltage V in buck mode BUS Target Level V BUS(REF) If the user can freely set V BUS(REF) <V TH(PLP) It is also possible that this may occur.

[0088] V BUS(REF) <V TH(PLP) In this situation, if a high-side forced-on section T6 is provided when transitioning from step-up mode to step-down mode, the bus voltage V BUS will rise, and the target level V BUS(REF) It is far from the target level V BUS(REF) convergence to

[0089] In control example 2, V BUS(REF) <V TH(PLP) In this case, the logic circuit 244 disables the forced on of the high-side transistor M1 and operates in the step-down mode based on the output CTL1 of the feedback circuit 242. As a result, the bus voltage V BUS to the target level V in a short time. BUS(REF) can be approached.

[0090] Control example 3 FIG. 11 is a diagram illustrating Control Example 3. Control Example 3 is an improvement of Control Example 2. FIG. 11 shows a comparison between the operation of Control Example 2 and the operation of Control Example 3. In Control Example 2, V BUS(REF) <V TH(PLP) The forced on of the high-side transistor M1 is disabled when the target level V of the bidirectional converter 230 in the buck mode BUS(REF) is at a constant level V0. In this case, the bus voltage V BUS But the target level is V BUS(REF) There is a possibility of undershoot occurring, where the output voltage is lower than the reference voltage.

[0091] In the control example 3, immediately after the transition to the buck mode, the target level V BUS(REF) is temporarily shifted to a level V1 slightly higher than the true level V0, and then to the target level V BUS(REF) This returns the bus voltage V BUS But the target level is V BUS(REF) This can suppress undershoot, which becomes lower than the true level V0.

[0092] Control example 4 12 is a diagram illustrating another problem that occurs in basic control. The feedback circuit 242 has an overcurrent protection function, and in the step-down mode, the coil current I L is the overcurrent protection threshold I OCP The switching of the bidirectional converter 230 is controlled so as not to exceed

[0093] In this case, the threshold I OCP If the level of the coil current I is constant, immediately after the high side forced on section T6, L is the threshold I OCP =I0, which supplies a large current to the output capacitor C1. As a result, the bus voltage V BUS Target level V BUS(REF) There is a risk of overshoot exceeding this.

[0094] 13 is a diagram illustrating control example 4. In control example 4, after transitioning from the voltage step-up mode to the voltage step-down mode, the feedback circuit 242 adjusts the overcurrent threshold I OCP As a result, immediately after the high side forced on section T6, the coil current I L A small threshold I OCP This clamps the current supplied to the output capacitor C1, reducing the bus voltage V BUS The amount of overshoot can be reduced.

[0095] Next, further modifications of the PLP circuit 100 will be described.

[0096] (Variation 3) 14 is a circuit diagram of a PLP circuit 100C according to Modification 3. A low-side forced-on circuit 248 is provided in a converter controller 240C.

[0097] When switching from the step-down mode to the step-up mode, the low-side forcibly-on circuit 248 generates a low-side forcibly-on signal CTL3 and controls the logic circuit 244 to forcibly fix the low-side transistor M2 to on. During this low-side forcibly-on interval, the logic circuit 244 fixes the high-side transistor M1 to off.

[0098] FIG. 15 is a waveform diagram illustrating the operation of the PLP circuit 100C of FIG.

[0099] Before time t0, the PLP circuit 100 is operating in the step-down mode, and the bidirectional converter 230 alternates between a period T4 in which the low-side transistor M2 is on and the high-side transistor M1 is off and a period T5 in which the low-side transistor M2 is off and the high-side transistor M1 is on.

[0100] At time t0, the low-side forced-on signal CTL3 is generated, and immediately after switching to the boost mode, a low-side forced-on interval T7 is inserted. During this low-side forced-on interval T7, the low-side transistor M2 is forcibly fixed to on, regardless of the control signal CTL1 generated by the feedback circuit 242 in the converter controller 240.

[0101] And the coil current I L is commutated and the predetermined peak I PEAK When the coil current I L and Peak I PEAK The circuit for comparing the coil current I L and Peak I PEAK A signal indicating the comparison result is included in the feedback signal CTL1.

[0102] If the low-side forced-on section T7 is not provided, the start of operation in the boost mode is delayed due to the delay of the feedback circuit 242, so that the backup capacitor C2 is discharged by the load current, and the capacitor voltage V STR decreases as shown by the dashed line (i).

[0103] In addition, in the control based on the feedback signal CTL1 generated by the feedback 242, immediately after switching to the boost mode, the high-side transistor M1 is turned on and the low-side transistor M2 is turned off. Therefore, the backup capacitor C2 is discharged, and the capacitor voltage V STR decreases as shown by the dashed line (i).

[0104] By providing the low-side forced-on section T7, the influence of the delay of the feedback circuit 242 can be eliminated, and the boost operation can be started from the charging cycle of the backup capacitor C2. As a result, as shown by the solid line (i), the capacitor voltage V STR This can suppress the decline in

[0105] (Application) PLP circuits 100, 100A, 100B, and 100C (hereinafter collectively referred to as 100) according to the embodiments can be used in a data storage device 300. Fig. 16 is a block diagram of a data storage device 300 with a PLP function. The data storage device 300 is, for example, an SSD (Solid State Drive), and includes the PLP circuit 100, a PMIC 302, a controller 304, a NAND memory 306, a cache memory 308, and an interface 310.

[0106] The data storage device 300 may be for a server, may be built into a computer, or may be a portable SSD.

[0107] The PLP circuit 100 receives a DC input voltage V from an AC / DC converter or a USB bus (the power supply 10 described above, not shown in FIG. 16). DC The PMIC302 receives the power supply voltage V DD The PMIC 302 supplies power supply voltage to the controller 304, the NAND memory 306, the cache memory 308, and the interface 310.

[0108] The use of the PLP circuit 100 is not limited to the data storage device 300, but can be used in any application where the power supply voltage must be maintained for a certain period of time even after the power is cut off.

[0109] The embodiments described using specific terms merely illustrate the principles and applications of the present disclosure, and many modifications and arrangements are possible within the scope of the present invention as defined in the claims.

[0110] [Note] One aspect of the technology disclosed in this specification can be understood as follows.

[0111] (Item 1) 1. A power loss protection controller circuit that receives an input voltage and provides an output voltage to a load, comprising: a bidirectional converter that, in a step-up mode, steps up the input voltage to charge a backup capacitor, and, in a step-down mode, steps down the voltage of the backup capacitor to generate the output voltage; a converter controller that operates the bidirectional converter in the step-up mode in a normal state where the input voltage is higher than a predetermined threshold voltage, and operates the bidirectional converter in the step-down mode in a power loss state where the input voltage is lower than the threshold voltage; Equipped with The bidirectional converter includes: A bootstrap circuit; a high-side transistor and a low-side transistor; a high-side driver that drives the high-side transistor; a low-side driver that drives the low-side transistor; a voltage maintaining circuit provided separately from the bootstrap circuit, which maintains a voltage of a bootstrap line of the bidirectional converter at a voltage higher than a switching voltage by a predetermined voltage step; Equipped with The converter controller a feedback circuit that generates a feedback control signal in the step-up mode so that the voltage of the backup capacitor approaches a first target level, and generates a feedback control signal in the step-down mode so that the output voltage approaches a second target level; a logic circuit that controls the high-side driver and the low-side driver based on the feedback control signal; a high-side forced-on circuit that controls the logic circuit so as to forcibly fix the high-side transistor to on during a high-side forced-on section of a predetermined length when switching from the step-up mode to the step-down mode; a power loss protection controller circuit,

[0112] (Item 2) Item 1. The power loss protection controller circuit of item 1, wherein the voltage maintenance circuit includes a charge pump circuit.

[0113] (Item 3) 2. The power loss protection controller circuit of item 1, wherein the voltage maintenance circuit includes a charging circuit that charges the bootstrap line based on the voltage of the backup capacitor.

[0114] (Item 4) 4. The power loss protection controller circuit according to any one of items 1 to 3, wherein the converter controller controls the bidirectional converter so that an on-period of the low-side transistor immediately after the high-side forced on-period does not become narrower than a predetermined minimum width.

[0115] (Item 5) 5. The power loss protection controller circuit according to any one of items 1 to 4, wherein the converter controller disables forcing on of the high-side transistor when a target level of the output voltage of the bidirectional converter in the step-down mode is lower than the threshold voltage.

[0116] (Item 6) 6. The power loss protection controller circuit according to item 5, wherein the converter controller, when disabling forced on of the high-side transistor, temporarily shifts the target level of the output voltage of the bidirectional converter to a voltage level higher than normal immediately after transitioning to the step-down mode.

[0117] (Item 7) 7. The power loss protection controller circuit according to any one of items 1 to 6, wherein the converter controller has an overcurrent protection function that limits a current flowing through an inductor of the bidirectional converter so as not to exceed an overcurrent threshold, and increases the overcurrent threshold over time after switching from the step-up mode to the step-down mode.

[0118] (Item 8) The converter controller 8. The power loss protection controller circuit according to claim 1, further comprising a low-side forced-on circuit that controls the logic circuit to forcibly fix the low-side transistor to on during a low-side forced-on interval of a predetermined length when switching from the step-down mode to the step-up mode.

[0119] (Item 9) 9. The power loss protection controller circuit according to item 8, wherein the converter controller ends the low side forced on interval when the coil current commutates and reaches a predetermined peak current.

[0120] (Item 10) 10. The power loss protection controller circuit of any one of items 1 to 9, wherein the bidirectional converter operates in a synchronous rectification mode in the boost mode.

[0121] (Item 11) 10. The power loss protection controller circuit of any one of items 1 to 9, wherein the bidirectional converter operates in diode rectification mode in the boost mode.

[0122] (Item 12) 12. The power loss protection controller circuit according to any one of items 1 to 11, which is integrated on a single semiconductor substrate.

[0123] (Item 13) A backup capacitor; 13. A power loss protection controller circuit according to any one of items 1 to 12, connected to the backup capacitor; A power loss protection circuit comprising:

[0124] (Item 14) Item 14. A data storage device comprising the power loss protection circuit according to item 13. [Explanation of symbols]

[0125] 2. System 10 Power supply 20 Load 22 PMIC 24 Electronic Components 30 PLP circuit 32 Switch 34 Backup capacitor 36 Bidirectional Converter 100 PLP circuits 104 input lines 106 Backlap Line 108 output lines C1 Output capacitor C2 backup capacitor C3 Bootstrap capacitor L1 inductor 200 PLP Controller 210 Switch 220 Switch Controller 230 Bidirectional Converter M1 High-side transistor M2 Low-side transistor 232 High Side Driver 234 Low Side Driver 240 Converter Controller 242 Feedback Circuit 244 Logic Circuits 246 High-side forced-on circuit 248 Low-side forced-on circuit 300 Data storage device 302 PMIC 304 Controller 306 NAND memory 308 Cache Memory 310 Interface 204 Bootstrap Line

Claims

1. 1. A power loss protection controller circuit that receives an input voltage and provides an output voltage to a load, comprising: a bidirectional converter that, in a step-up mode, steps up the input voltage to charge a backup capacitor, and, in a step-down mode, steps down the voltage of the backup capacitor to generate the output voltage; a converter controller that operates the bidirectional converter in the step-up mode in a normal state where the input voltage is higher than a predetermined threshold voltage, and operates the bidirectional converter in the step-down mode in a power loss state where the input voltage is lower than the threshold voltage; Equipped with The bidirectional converter includes: A bootstrap circuit; a high-side transistor and a low-side transistor; a high-side driver that drives the high-side transistor; a low-side driver that drives the low-side transistor; a voltage maintaining circuit provided separately from the bootstrap circuit, which maintains a voltage of a bootstrap line of the bidirectional converter at a voltage higher than a switching voltage by a predetermined voltage step; Equipped with The converter controller a feedback circuit that generates a feedback control signal in the voltage step-up mode so that the voltage of the backup capacitor approaches a first target level, and generates a feedback control signal in the voltage step-down mode so that the output voltage approaches a second target level; a logic circuit that controls the high-side driver and the low-side driver based on the feedback control signal; a high-side forced-on circuit that controls the logic circuit so as to forcibly fix the high-side transistor to on during a high-side forced-on section of a predetermined length when switching from the step-up mode to the step-down mode; a power loss protection controller circuit,

2. 2. The power loss protection controller circuit of claim 1, wherein the voltage maintenance circuit includes a charge pump circuit.

3. 2. The power loss protection controller circuit of claim 1, wherein the voltage maintenance circuit includes a charging circuit that charges the bootstrap line based on the voltage of the backup capacitor.

4. 4. The power loss protection controller circuit according to claim 1, wherein the converter controller controls the bidirectional converter so that an on-period of the low-side transistor immediately after the high-side forced on-period does not become narrower than a predetermined minimum width.

5. 4. The power loss protection controller circuit according to claim 1, wherein the converter controller disables forcing on of the high-side transistor when a target level of the output voltage of the bidirectional converter in the step-down mode is lower than the threshold voltage.

6. 6. The power loss protection controller circuit of claim 5, wherein the converter controller, when disabling forced on of the high-side transistor, temporarily shifts the target level of the output voltage of the bidirectional converter to a voltage level higher than normal immediately after transitioning to the step-down mode.

7. 4. The power loss protection controller circuit according to claim 1, wherein the converter controller has an overcurrent protection function that limits a current flowing through an inductor of the bidirectional converter so as not to exceed an overcurrent threshold, and increases the overcurrent threshold over time after switching from the voltage step-up mode to the voltage step-down mode.

8. The converter controller 4. The power loss protection controller circuit according to claim 1, further comprising: a low-side forced-on circuit that controls the logic circuit so as to forcibly fix the low-side transistor to on during a low-side forced-on interval of a predetermined length when switching from the step-down mode to the step-up mode.

9. 9. The power loss protection controller circuit of claim 8, wherein the converter controller ends the low side forced on interval when the coil current commutates and reaches a predetermined peak current.

10. 4. The power loss protection controller circuit of claim 1, wherein the bidirectional converter operates in a synchronous rectification mode in the boost mode.

11. 4. The power loss protection controller circuit of claim 1, wherein the bidirectional converter operates in a diode rectification mode in the boost mode.

12. 4. The power loss protection controller circuit according to claim 1, which is integrated on a single semiconductor substrate.

13. A backup capacitor; a power loss protection controller circuit according to any one of claims 1 to 3, connected to the backup capacitor; A power loss protection circuit comprising:

14. A data storage device comprising the power loss protection circuit of claim 13.

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